Commit 76c7473f authored by Bartosz Golaszewski's avatar Bartosz Golaszewski Committed by Sekhar Nori

ARM: davinci: da850: switch to using the clocksource driver

We now have a proper clocksource driver for davinci. Switch the da850
platform to using it.
Signed-off-by: default avatarBartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: default avatarDavid Lechner <david@lechnology.com>
Signed-off-by: default avatarSekhar Nori <nsekhar@ti.com>
parent d470df3b
...@@ -35,7 +35,8 @@ ...@@ -35,7 +35,8 @@
#include <mach/cputype.h> #include <mach/cputype.h>
#include <mach/da8xx.h> #include <mach/da8xx.h>
#include <mach/pm.h> #include <mach/pm.h>
#include <mach/time.h>
#include <clocksource/timer-davinci.h>
#include "irqs.h" #include "irqs.h"
#include "mux.h" #include "mux.h"
...@@ -333,38 +334,16 @@ static struct davinci_id da850_ids[] = { ...@@ -333,38 +334,16 @@ static struct davinci_id da850_ids[] = {
}, },
}; };
static struct davinci_timer_instance da850_timer_instance[4] = {
{
.base = DA8XX_TIMER64P0_BASE,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0),
},
{
.base = DA8XX_TIMER64P1_BASE,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_1),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_1),
},
{
.base = DA850_TIMER64P2_BASE,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_2),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_2),
},
{
.base = DA850_TIMER64P3_BASE,
.bottom_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT12_3),
.top_irq = DAVINCI_INTC_IRQ(IRQ_DA850_TINT34_3),
},
};
/* /*
* T0_BOT: Timer 0, bottom : Used for clock_event * Bottom half of timer 0 is used for clock_event, top half for
* T0_TOP: Timer 0, top : Used for clocksource * clocksource.
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
*/ */
static struct davinci_timer_info da850_timer_info = { static const struct davinci_timer_cfg da850_timer_cfg = {
.timers = da850_timer_instance, .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K),
.clockevent_id = T0_BOT, .irq = {
.clocksource_id = T0_TOP, DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)),
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0)),
},
}; };
#ifdef CONFIG_CPU_FREQ #ifdef CONFIG_CPU_FREQ
...@@ -635,7 +614,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = { ...@@ -635,7 +614,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = {
.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
.pinmux_pins = da850_pins, .pinmux_pins = da850_pins,
.pinmux_pins_num = ARRAY_SIZE(da850_pins), .pinmux_pins_num = ARRAY_SIZE(da850_pins),
.timer_info = &da850_timer_info,
.emac_pdata = &da8xx_emac_pdata, .emac_pdata = &da8xx_emac_pdata,
.sram_dma = DA8XX_SHARED_RAM_BASE, .sram_dma = DA8XX_SHARED_RAM_BASE,
.sram_len = SZ_128K, .sram_len = SZ_128K,
...@@ -672,6 +650,7 @@ void __init da850_init_time(void) ...@@ -672,6 +650,7 @@ void __init da850_init_time(void)
void __iomem *pll0; void __iomem *pll0;
struct regmap *cfgchip; struct regmap *cfgchip;
struct clk *clk; struct clk *clk;
int rv;
clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ); clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ);
...@@ -686,7 +665,8 @@ void __init da850_init_time(void) ...@@ -686,7 +665,8 @@ void __init da850_init_time(void)
return; return;
} }
davinci_timer_init(clk); rv = davinci_timer_register(clk, &da850_timer_cfg);
WARN(rv, "Unable to register the timer: %d\n", rv);
} }
static struct resource da850_pll1_resources[] = { static struct resource da850_pll1_resources[] = {
......
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