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Commit 798bcf73 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
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drm/radeon/kms: move clock/pcie setting callbacks into pm struct 

tidy up radeon_asic struct.
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König<christian.koenig@amd.com>
Reviewed-by: default avatarMichel Dänzer <michel.daenzer@amd.com>
Reviewed-by: default avatarJerome Glisse <jglisse@redhat.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent c79a49ca
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Showing with 145 additions and 143 deletions
drivers/gpu/drm/radeon/r100.c
View file @ 798bcf73
...@@ -450,7 +450,7 @@ void r100_pm_misc(struct radeon_device *rdev) ...@@ -450,7 +450,7 @@ void r100_pm_misc(struct radeon_device *rdev)
/* set pcie lanes */ /* set pcie lanes */
if ((rdev->flags & RADEON_IS_PCIE) && if ((rdev->flags & RADEON_IS_PCIE) &&
!(rdev->flags & RADEON_IS_IGP) && !(rdev->flags & RADEON_IS_IGP) &&
rdev->asic->set_pcie_lanes && rdev->asic->pm.set_pcie_lanes &&
(ps->pcie_lanes != (ps->pcie_lanes !=
rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
radeon_set_pcie_lanes(rdev, radeon_set_pcie_lanes(rdev,
......
drivers/gpu/drm/radeon/radeon.h
View file @ 798bcf73
...@@ -1188,13 +1188,6 @@ struct radeon_asic { ...@@ -1188,13 +1188,6 @@ struct radeon_asic {
u32 copy_ring_index; u32 copy_ring_index;
} copy; } copy;
uint32_t (*get_engine_clock)(struct radeon_device *rdev);
void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
uint32_t (*get_memory_clock)(struct radeon_device *rdev);
void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
int (*get_pcie_lanes)(struct radeon_device *rdev);
void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
void (*set_clock_gating)(struct radeon_device *rdev, int enable);
int (*set_surface_reg)(struct radeon_device *rdev, int reg, int (*set_surface_reg)(struct radeon_device *rdev, int reg,
uint32_t tiling_flags, uint32_t pitch, uint32_t tiling_flags, uint32_t pitch,
uint32_t offset, uint32_t obj_size); uint32_t offset, uint32_t obj_size);
...@@ -1223,6 +1216,13 @@ struct radeon_asic { ...@@ -1223,6 +1216,13 @@ struct radeon_asic {
void (*finish)(struct radeon_device *rdev); void (*finish)(struct radeon_device *rdev);
void (*init_profile)(struct radeon_device *rdev); void (*init_profile)(struct radeon_device *rdev);
void (*get_dynpm_state)(struct radeon_device *rdev); void (*get_dynpm_state)(struct radeon_device *rdev);
uint32_t (*get_engine_clock)(struct radeon_device *rdev);
void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
uint32_t (*get_memory_clock)(struct radeon_device *rdev);
void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
int (*get_pcie_lanes)(struct radeon_device *rdev);
void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
void (*set_clock_gating)(struct radeon_device *rdev, int enable);
} pm; } pm;
/* pageflipping */ /* pageflipping */
struct { struct {
...@@ -1700,13 +1700,13 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v); ...@@ -1700,13 +1700,13 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev)) #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
......
drivers/gpu/drm/radeon/radeon_asic.c
View file @ 798bcf73
...@@ -168,13 +168,6 @@ static struct radeon_asic r100_asic = { ...@@ -168,13 +168,6 @@ static struct radeon_asic r100_asic = {
.copy = &r100_copy_blit, .copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.get_engine_clock = &radeon_legacy_get_engine_clock,
.set_engine_clock = &radeon_legacy_set_engine_clock,
.get_memory_clock = &radeon_legacy_get_memory_clock,
.set_memory_clock = NULL,
.get_pcie_lanes = NULL,
.set_pcie_lanes = NULL,
.set_clock_gating = &radeon_legacy_set_clock_gating,
.set_surface_reg = r100_set_surface_reg, .set_surface_reg = r100_set_surface_reg,
.clear_surface_reg = r100_clear_surface_reg, .clear_surface_reg = r100_clear_surface_reg,
.hpd = { .hpd = {
...@@ -191,6 +184,13 @@ static struct radeon_asic r100_asic = { ...@@ -191,6 +184,13 @@ static struct radeon_asic r100_asic = {
.finish = &r100_pm_finish, .finish = &r100_pm_finish,
.init_profile = &r100_pm_init_profile, .init_profile = &r100_pm_init_profile,
.get_dynpm_state = &r100_pm_get_dynpm_state, .get_dynpm_state = &r100_pm_get_dynpm_state,
.get_engine_clock = &radeon_legacy_get_engine_clock,
.set_engine_clock = &radeon_legacy_set_engine_clock,
.get_memory_clock = &radeon_legacy_get_memory_clock,
.set_memory_clock = NULL,
.get_pcie_lanes = NULL,
.set_pcie_lanes = NULL,
.set_clock_gating = &radeon_legacy_set_clock_gating,
}, },
.pflip = { .pflip = {
.pre_page_flip = &r100_pre_page_flip, .pre_page_flip = &r100_pre_page_flip,
...@@ -240,12 +240,6 @@ static struct radeon_asic r200_asic = { ...@@ -240,12 +240,6 @@ static struct radeon_asic r200_asic = {
.copy = &r100_copy_blit, .copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.get_engine_clock = &radeon_legacy_get_engine_clock,
.set_engine_clock = &radeon_legacy_set_engine_clock,
.get_memory_clock = &radeon_legacy_get_memory_clock,
.set_memory_clock = NULL,
.set_pcie_lanes = NULL,
.set_clock_gating = &radeon_legacy_set_clock_gating,
.set_surface_reg = r100_set_surface_reg, .set_surface_reg = r100_set_surface_reg,
.clear_surface_reg = r100_clear_surface_reg, .clear_surface_reg = r100_clear_surface_reg,
.hpd = { .hpd = {
...@@ -262,6 +256,13 @@ static struct radeon_asic r200_asic = { ...@@ -262,6 +256,13 @@ static struct radeon_asic r200_asic = {
.finish = &r100_pm_finish, .finish = &r100_pm_finish,
.init_profile = &r100_pm_init_profile, .init_profile = &r100_pm_init_profile,
.get_dynpm_state = &r100_pm_get_dynpm_state, .get_dynpm_state = &r100_pm_get_dynpm_state,
.get_engine_clock = &radeon_legacy_get_engine_clock,
.set_engine_clock = &radeon_legacy_set_engine_clock,
.get_memory_clock = &radeon_legacy_get_memory_clock,
.set_memory_clock = NULL,
.get_pcie_lanes = NULL,
.set_pcie_lanes = NULL,
.set_clock_gating = &radeon_legacy_set_clock_gating,
}, },
.pflip = { .pflip = {
.pre_page_flip = &r100_pre_page_flip, .pre_page_flip = &r100_pre_page_flip,
...@@ -311,13 +312,6 @@ static struct radeon_asic r300_asic = { ...@@ -311,13 +312,6 @@ static struct radeon_asic r300_asic = {
.copy = &r100_copy_blit, .copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.get_engine_clock = &radeon_legacy_get_engine_clock,
.set_engine_clock = &radeon_legacy_set_engine_clock,
.get_memory_clock = &radeon_legacy_get_memory_clock,
.set_memory_clock = NULL,
.get_pcie_lanes = &rv370_get_pcie_lanes,
.set_pcie_lanes = &rv370_set_pcie_lanes,
.set_clock_gating = &radeon_legacy_set_clock_gating,
.set_surface_reg = r100_set_surface_reg, .set_surface_reg = r100_set_surface_reg,
.clear_surface_reg = r100_clear_surface_reg, .clear_surface_reg = r100_clear_surface_reg,
.hpd = { .hpd = {
...@@ -334,6 +328,13 @@ static struct radeon_asic r300_asic = { ...@@ -334,6 +328,13 @@ static struct radeon_asic r300_asic = {
.finish = &r100_pm_finish, .finish = &r100_pm_finish,
.init_profile = &r100_pm_init_profile, .init_profile = &r100_pm_init_profile,
.get_dynpm_state = &r100_pm_get_dynpm_state, .get_dynpm_state = &r100_pm_get_dynpm_state,
.get_engine_clock = &radeon_legacy_get_engine_clock,
.set_engine_clock = &radeon_legacy_set_engine_clock,
.get_memory_clock = &radeon_legacy_get_memory_clock,
.set_memory_clock = NULL,
.get_pcie_lanes = &rv370_get_pcie_lanes,
.set_pcie_lanes = &rv370_set_pcie_lanes,
.set_clock_gating = &radeon_legacy_set_clock_gating,
}, },
.pflip = { .pflip = {
.pre_page_flip = &r100_pre_page_flip, .pre_page_flip = &r100_pre_page_flip,
...@@ -383,12 +384,6 @@ static struct radeon_asic r300_asic_pcie = { ...@@ -383,12 +384,6 @@ static struct radeon_asic r300_asic_pcie = {
.copy = &r100_copy_blit, .copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.get_engine_clock = &radeon_legacy_get_engine_clock,
.set_engine_clock = &radeon_legacy_set_engine_clock,
.get_memory_clock = &radeon_legacy_get_memory_clock,
.set_memory_clock = NULL,
.set_pcie_lanes = &rv370_set_pcie_lanes,
.set_clock_gating = &radeon_legacy_set_clock_gating,
.set_surface_reg = r100_set_surface_reg, .set_surface_reg = r100_set_surface_reg,
.clear_surface_reg = r100_clear_surface_reg, .clear_surface_reg = r100_clear_surface_reg,
.hpd = { .hpd = {
...@@ -405,6 +400,13 @@ static struct radeon_asic r300_asic_pcie = { ...@@ -405,6 +400,13 @@ static struct radeon_asic r300_asic_pcie = {
.finish = &r100_pm_finish, .finish = &r100_pm_finish,
.init_profile = &r100_pm_init_profile, .init_profile = &r100_pm_init_profile,
.get_dynpm_state = &r100_pm_get_dynpm_state, .get_dynpm_state = &r100_pm_get_dynpm_state,
.get_engine_clock = &radeon_legacy_get_engine_clock,
.set_engine_clock = &radeon_legacy_set_engine_clock,
.get_memory_clock = &radeon_legacy_get_memory_clock,
.set_memory_clock = NULL,
.get_pcie_lanes = &rv370_get_pcie_lanes,
.set_pcie_lanes = &rv370_set_pcie_lanes,
.set_clock_gating = &radeon_legacy_set_clock_gating,
}, },
.pflip = { .pflip = {
.pre_page_flip = &r100_pre_page_flip, .pre_page_flip = &r100_pre_page_flip,
...@@ -454,13 +456,6 @@ static struct radeon_asic r420_asic = { ...@@ -454,13 +456,6 @@ static struct radeon_asic r420_asic = {
.copy = &r100_copy_blit, .copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = &radeon_atom_get_memory_clock,
.set_memory_clock = &radeon_atom_set_memory_clock,
.get_pcie_lanes = &rv370_get_pcie_lanes,
.set_pcie_lanes = &rv370_set_pcie_lanes,
.set_clock_gating = &radeon_atom_set_clock_gating,
.set_surface_reg = r100_set_surface_reg, .set_surface_reg = r100_set_surface_reg,
.clear_surface_reg = r100_clear_surface_reg, .clear_surface_reg = r100_clear_surface_reg,
...@@ -478,6 +473,13 @@ static struct radeon_asic r420_asic = { ...@@ -478,6 +473,13 @@ static struct radeon_asic r420_asic = {
.finish = &r100_pm_finish, .finish = &r100_pm_finish,
.init_profile = &r420_pm_init_profile, .init_profile = &r420_pm_init_profile,
.get_dynpm_state = &r100_pm_get_dynpm_state, .get_dynpm_state = &r100_pm_get_dynpm_state,
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = &radeon_atom_get_memory_clock,
.set_memory_clock = &radeon_atom_set_memory_clock,
.get_pcie_lanes = &rv370_get_pcie_lanes,
.set_pcie_lanes = &rv370_set_pcie_lanes,
.set_clock_gating = &radeon_atom_set_clock_gating,
}, },
.pflip = { .pflip = {
.pre_page_flip = &r100_pre_page_flip, .pre_page_flip = &r100_pre_page_flip,
...@@ -527,13 +529,6 @@ static struct radeon_asic rs400_asic = { ...@@ -527,13 +529,6 @@ static struct radeon_asic rs400_asic = {
.copy = &r100_copy_blit, .copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.get_engine_clock = &radeon_legacy_get_engine_clock,
.set_engine_clock = &radeon_legacy_set_engine_clock,
.get_memory_clock = &radeon_legacy_get_memory_clock,
.set_memory_clock = NULL,
.get_pcie_lanes = NULL,
.set_pcie_lanes = NULL,
.set_clock_gating = &radeon_legacy_set_clock_gating,
.set_surface_reg = r100_set_surface_reg, .set_surface_reg = r100_set_surface_reg,
.clear_surface_reg = r100_clear_surface_reg, .clear_surface_reg = r100_clear_surface_reg,
.hpd = { .hpd = {
...@@ -550,6 +545,13 @@ static struct radeon_asic rs400_asic = { ...@@ -550,6 +545,13 @@ static struct radeon_asic rs400_asic = {
.finish = &r100_pm_finish, .finish = &r100_pm_finish,
.init_profile = &r100_pm_init_profile, .init_profile = &r100_pm_init_profile,
.get_dynpm_state = &r100_pm_get_dynpm_state, .get_dynpm_state = &r100_pm_get_dynpm_state,
.get_engine_clock = &radeon_legacy_get_engine_clock,
.set_engine_clock = &radeon_legacy_set_engine_clock,
.get_memory_clock = &radeon_legacy_get_memory_clock,
.set_memory_clock = NULL,
.get_pcie_lanes = NULL,
.set_pcie_lanes = NULL,
.set_clock_gating = &radeon_legacy_set_clock_gating,
}, },
.pflip = { .pflip = {
.pre_page_flip = &r100_pre_page_flip, .pre_page_flip = &r100_pre_page_flip,
...@@ -599,13 +601,6 @@ static struct radeon_asic rs600_asic = { ...@@ -599,13 +601,6 @@ static struct radeon_asic rs600_asic = {
.copy = &r100_copy_blit, .copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = &radeon_atom_get_memory_clock,
.set_memory_clock = &radeon_atom_set_memory_clock,
.get_pcie_lanes = NULL,
.set_pcie_lanes = NULL,
.set_clock_gating = &radeon_atom_set_clock_gating,
.set_surface_reg = r100_set_surface_reg, .set_surface_reg = r100_set_surface_reg,
.clear_surface_reg = r100_clear_surface_reg, .clear_surface_reg = r100_clear_surface_reg,
.hpd = { .hpd = {
...@@ -622,6 +617,13 @@ static struct radeon_asic rs600_asic = { ...@@ -622,6 +617,13 @@ static struct radeon_asic rs600_asic = {
.finish = &rs600_pm_finish, .finish = &rs600_pm_finish,
.init_profile = &r420_pm_init_profile, .init_profile = &r420_pm_init_profile,
.get_dynpm_state = &r100_pm_get_dynpm_state, .get_dynpm_state = &r100_pm_get_dynpm_state,
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = &radeon_atom_get_memory_clock,
.set_memory_clock = &radeon_atom_set_memory_clock,
.get_pcie_lanes = NULL,
.set_pcie_lanes = NULL,
.set_clock_gating = &radeon_atom_set_clock_gating,
}, },
.pflip = { .pflip = {
.pre_page_flip = &rs600_pre_page_flip, .pre_page_flip = &rs600_pre_page_flip,
...@@ -671,13 +673,6 @@ static struct radeon_asic rs690_asic = { ...@@ -671,13 +673,6 @@ static struct radeon_asic rs690_asic = {
.copy = &r200_copy_dma, .copy = &r200_copy_dma,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = &radeon_atom_get_memory_clock,
.set_memory_clock = &radeon_atom_set_memory_clock,
.get_pcie_lanes = NULL,
.set_pcie_lanes = NULL,
.set_clock_gating = &radeon_atom_set_clock_gating,
.set_surface_reg = r100_set_surface_reg, .set_surface_reg = r100_set_surface_reg,
.clear_surface_reg = r100_clear_surface_reg, .clear_surface_reg = r100_clear_surface_reg,
.hpd = { .hpd = {
...@@ -694,6 +689,13 @@ static struct radeon_asic rs690_asic = { ...@@ -694,6 +689,13 @@ static struct radeon_asic rs690_asic = {
.finish = &rs600_pm_finish, .finish = &rs600_pm_finish,
.init_profile = &r420_pm_init_profile, .init_profile = &r420_pm_init_profile,
.get_dynpm_state = &r100_pm_get_dynpm_state, .get_dynpm_state = &r100_pm_get_dynpm_state,
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = &radeon_atom_get_memory_clock,
.set_memory_clock = &radeon_atom_set_memory_clock,
.get_pcie_lanes = NULL,
.set_pcie_lanes = NULL,
.set_clock_gating = &radeon_atom_set_clock_gating,
}, },
.pflip = { .pflip = {
.pre_page_flip = &rs600_pre_page_flip, .pre_page_flip = &rs600_pre_page_flip,
...@@ -743,13 +745,6 @@ static struct radeon_asic rv515_asic = { ...@@ -743,13 +745,6 @@ static struct radeon_asic rv515_asic = {
.copy = &r100_copy_blit, .copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = &radeon_atom_get_memory_clock,
.set_memory_clock = &radeon_atom_set_memory_clock,
.get_pcie_lanes = &rv370_get_pcie_lanes,
.set_pcie_lanes = &rv370_set_pcie_lanes,
.set_clock_gating = &radeon_atom_set_clock_gating,
.set_surface_reg = r100_set_surface_reg, .set_surface_reg = r100_set_surface_reg,
.clear_surface_reg = r100_clear_surface_reg, .clear_surface_reg = r100_clear_surface_reg,
.hpd = { .hpd = {
...@@ -766,6 +761,13 @@ static struct radeon_asic rv515_asic = { ...@@ -766,6 +761,13 @@ static struct radeon_asic rv515_asic = {
.finish = &rs600_pm_finish, .finish = &rs600_pm_finish,
.init_profile = &r420_pm_init_profile, .init_profile = &r420_pm_init_profile,
.get_dynpm_state = &r100_pm_get_dynpm_state, .get_dynpm_state = &r100_pm_get_dynpm_state,
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = &radeon_atom_get_memory_clock,
.set_memory_clock = &radeon_atom_set_memory_clock,
.get_pcie_lanes = &rv370_get_pcie_lanes,
.set_pcie_lanes = &rv370_set_pcie_lanes,
.set_clock_gating = &radeon_atom_set_clock_gating,
}, },
.pflip = { .pflip = {
.pre_page_flip = &rs600_pre_page_flip, .pre_page_flip = &rs600_pre_page_flip,
...@@ -815,13 +817,6 @@ static struct radeon_asic r520_asic = { ...@@ -815,13 +817,6 @@ static struct radeon_asic r520_asic = {
.copy = &r100_copy_blit, .copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = &radeon_atom_get_memory_clock,
.set_memory_clock = &radeon_atom_set_memory_clock,
.get_pcie_lanes = &rv370_get_pcie_lanes,
.set_pcie_lanes = &rv370_set_pcie_lanes,
.set_clock_gating = &radeon_atom_set_clock_gating,
.set_surface_reg = r100_set_surface_reg, .set_surface_reg = r100_set_surface_reg,
.clear_surface_reg = r100_clear_surface_reg, .clear_surface_reg = r100_clear_surface_reg,
.hpd = { .hpd = {
...@@ -838,6 +833,13 @@ static struct radeon_asic r520_asic = { ...@@ -838,6 +833,13 @@ static struct radeon_asic r520_asic = {
.finish = &rs600_pm_finish, .finish = &rs600_pm_finish,
.init_profile = &r420_pm_init_profile, .init_profile = &r420_pm_init_profile,
.get_dynpm_state = &r100_pm_get_dynpm_state, .get_dynpm_state = &r100_pm_get_dynpm_state,
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = &radeon_atom_get_memory_clock,
.set_memory_clock = &radeon_atom_set_memory_clock,
.get_pcie_lanes = &rv370_get_pcie_lanes,
.set_pcie_lanes = &rv370_set_pcie_lanes,
.set_clock_gating = &radeon_atom_set_clock_gating,
}, },
.pflip = { .pflip = {
.pre_page_flip = &rs600_pre_page_flip, .pre_page_flip = &rs600_pre_page_flip,
...@@ -886,13 +888,6 @@ static struct radeon_asic r600_asic = { ...@@ -886,13 +888,6 @@ static struct radeon_asic r600_asic = {
.copy = &r600_copy_blit, .copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = &radeon_atom_get_memory_clock,
.set_memory_clock = &radeon_atom_set_memory_clock,
.get_pcie_lanes = &r600_get_pcie_lanes,
.set_pcie_lanes = &r600_set_pcie_lanes,
.set_clock_gating = NULL,
.set_surface_reg = r600_set_surface_reg, .set_surface_reg = r600_set_surface_reg,
.clear_surface_reg = r600_clear_surface_reg, .clear_surface_reg = r600_clear_surface_reg,
.hpd = { .hpd = {
...@@ -909,6 +904,13 @@ static struct radeon_asic r600_asic = { ...@@ -909,6 +904,13 @@ static struct radeon_asic r600_asic = {
.finish = &rs600_pm_finish, .finish = &rs600_pm_finish,
.init_profile = &r600_pm_init_profile, .init_profile = &r600_pm_init_profile,
.get_dynpm_state = &r600_pm_get_dynpm_state, .get_dynpm_state = &r600_pm_get_dynpm_state,
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = &radeon_atom_get_memory_clock,
.set_memory_clock = &radeon_atom_set_memory_clock,
.get_pcie_lanes = &r600_get_pcie_lanes,
.set_pcie_lanes = &r600_set_pcie_lanes,
.set_clock_gating = NULL,
}, },
.pflip = { .pflip = {
.pre_page_flip = &rs600_pre_page_flip, .pre_page_flip = &rs600_pre_page_flip,
...@@ -957,13 +959,6 @@ static struct radeon_asic rs780_asic = { ...@@ -957,13 +959,6 @@ static struct radeon_asic rs780_asic = {
.copy = &r600_copy_blit, .copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = NULL,
.set_memory_clock = NULL,
.get_pcie_lanes = NULL,
.set_pcie_lanes = NULL,
.set_clock_gating = NULL,
.set_surface_reg = r600_set_surface_reg, .set_surface_reg = r600_set_surface_reg,
.clear_surface_reg = r600_clear_surface_reg, .clear_surface_reg = r600_clear_surface_reg,
.hpd = { .hpd = {
...@@ -980,6 +975,13 @@ static struct radeon_asic rs780_asic = { ...@@ -980,6 +975,13 @@ static struct radeon_asic rs780_asic = {
.finish = &rs600_pm_finish, .finish = &rs600_pm_finish,
.init_profile = &rs780_pm_init_profile, .init_profile = &rs780_pm_init_profile,
.get_dynpm_state = &r600_pm_get_dynpm_state, .get_dynpm_state = &r600_pm_get_dynpm_state,
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = NULL,
.set_memory_clock = NULL,
.get_pcie_lanes = NULL,
.set_pcie_lanes = NULL,
.set_clock_gating = NULL,
}, },
.pflip = { .pflip = {
.pre_page_flip = &rs600_pre_page_flip, .pre_page_flip = &rs600_pre_page_flip,
...@@ -1028,13 +1030,6 @@ static struct radeon_asic rv770_asic = { ...@@ -1028,13 +1030,6 @@ static struct radeon_asic rv770_asic = {
.copy = &r600_copy_blit, .copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = &radeon_atom_get_memory_clock,
.set_memory_clock = &radeon_atom_set_memory_clock,
.get_pcie_lanes = &r600_get_pcie_lanes,
.set_pcie_lanes = &r600_set_pcie_lanes,
.set_clock_gating = &radeon_atom_set_clock_gating,
.set_surface_reg = r600_set_surface_reg, .set_surface_reg = r600_set_surface_reg,
.clear_surface_reg = r600_clear_surface_reg, .clear_surface_reg = r600_clear_surface_reg,
.hpd = { .hpd = {
...@@ -1051,6 +1046,13 @@ static struct radeon_asic rv770_asic = { ...@@ -1051,6 +1046,13 @@ static struct radeon_asic rv770_asic = {
.finish = &rs600_pm_finish, .finish = &rs600_pm_finish,
.init_profile = &r600_pm_init_profile, .init_profile = &r600_pm_init_profile,
.get_dynpm_state = &r600_pm_get_dynpm_state, .get_dynpm_state = &r600_pm_get_dynpm_state,
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = &radeon_atom_get_memory_clock,
.set_memory_clock = &radeon_atom_set_memory_clock,
.get_pcie_lanes = &r600_get_pcie_lanes,
.set_pcie_lanes = &r600_set_pcie_lanes,
.set_clock_gating = &radeon_atom_set_clock_gating,
}, },
.pflip = { .pflip = {
.pre_page_flip = &rs600_pre_page_flip, .pre_page_flip = &rs600_pre_page_flip,
...@@ -1099,13 +1101,6 @@ static struct radeon_asic evergreen_asic = { ...@@ -1099,13 +1101,6 @@ static struct radeon_asic evergreen_asic = {
.copy = &r600_copy_blit, .copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = &radeon_atom_get_memory_clock,
.set_memory_clock = &radeon_atom_set_memory_clock,
.get_pcie_lanes = &r600_get_pcie_lanes,
.set_pcie_lanes = &r600_set_pcie_lanes,
.set_clock_gating = NULL,
.set_surface_reg = r600_set_surface_reg, .set_surface_reg = r600_set_surface_reg,
.clear_surface_reg = r600_clear_surface_reg, .clear_surface_reg = r600_clear_surface_reg,
.hpd = { .hpd = {
...@@ -1122,6 +1117,13 @@ static struct radeon_asic evergreen_asic = { ...@@ -1122,6 +1117,13 @@ static struct radeon_asic evergreen_asic = {
.finish = &evergreen_pm_finish, .finish = &evergreen_pm_finish,
.init_profile = &r600_pm_init_profile, .init_profile = &r600_pm_init_profile,
.get_dynpm_state = &r600_pm_get_dynpm_state, .get_dynpm_state = &r600_pm_get_dynpm_state,
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = &radeon_atom_get_memory_clock,
.set_memory_clock = &radeon_atom_set_memory_clock,
.get_pcie_lanes = &r600_get_pcie_lanes,
.set_pcie_lanes = &r600_set_pcie_lanes,
.set_clock_gating = NULL,
}, },
.pflip = { .pflip = {
.pre_page_flip = &evergreen_pre_page_flip, .pre_page_flip = &evergreen_pre_page_flip,
...@@ -1170,13 +1172,6 @@ static struct radeon_asic sumo_asic = { ...@@ -1170,13 +1172,6 @@ static struct radeon_asic sumo_asic = {
.copy = &r600_copy_blit, .copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = NULL,
.set_memory_clock = NULL,
.get_pcie_lanes = NULL,
.set_pcie_lanes = NULL,
.set_clock_gating = NULL,
.set_surface_reg = r600_set_surface_reg, .set_surface_reg = r600_set_surface_reg,
.clear_surface_reg = r600_clear_surface_reg, .clear_surface_reg = r600_clear_surface_reg,
.hpd = { .hpd = {
...@@ -1193,6 +1188,13 @@ static struct radeon_asic sumo_asic = { ...@@ -1193,6 +1188,13 @@ static struct radeon_asic sumo_asic = {
.finish = &evergreen_pm_finish, .finish = &evergreen_pm_finish,
.init_profile = &sumo_pm_init_profile, .init_profile = &sumo_pm_init_profile,
.get_dynpm_state = &r600_pm_get_dynpm_state, .get_dynpm_state = &r600_pm_get_dynpm_state,
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = NULL,
.set_memory_clock = NULL,
.get_pcie_lanes = NULL,
.set_pcie_lanes = NULL,
.set_clock_gating = NULL,
}, },
.pflip = { .pflip = {
.pre_page_flip = &evergreen_pre_page_flip, .pre_page_flip = &evergreen_pre_page_flip,
...@@ -1241,13 +1243,6 @@ static struct radeon_asic btc_asic = { ...@@ -1241,13 +1243,6 @@ static struct radeon_asic btc_asic = {
.copy = &r600_copy_blit, .copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = &radeon_atom_get_memory_clock,
.set_memory_clock = &radeon_atom_set_memory_clock,
.get_pcie_lanes = NULL,
.set_pcie_lanes = NULL,
.set_clock_gating = NULL,
.set_surface_reg = r600_set_surface_reg, .set_surface_reg = r600_set_surface_reg,
.clear_surface_reg = r600_clear_surface_reg, .clear_surface_reg = r600_clear_surface_reg,
.hpd = { .hpd = {
...@@ -1264,6 +1259,13 @@ static struct radeon_asic btc_asic = { ...@@ -1264,6 +1259,13 @@ static struct radeon_asic btc_asic = {
.finish = &evergreen_pm_finish, .finish = &evergreen_pm_finish,
.init_profile = &r600_pm_init_profile, .init_profile = &r600_pm_init_profile,
.get_dynpm_state = &r600_pm_get_dynpm_state, .get_dynpm_state = &r600_pm_get_dynpm_state,
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = &radeon_atom_get_memory_clock,
.set_memory_clock = &radeon_atom_set_memory_clock,
.get_pcie_lanes = NULL,
.set_pcie_lanes = NULL,
.set_clock_gating = NULL,
}, },
.pflip = { .pflip = {
.pre_page_flip = &evergreen_pre_page_flip, .pre_page_flip = &evergreen_pre_page_flip,
...@@ -1341,13 +1343,6 @@ static struct radeon_asic cayman_asic = { ...@@ -1341,13 +1343,6 @@ static struct radeon_asic cayman_asic = {
.copy = &r600_copy_blit, .copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
}, },
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = &radeon_atom_get_memory_clock,
.set_memory_clock = &radeon_atom_set_memory_clock,
.get_pcie_lanes = NULL,
.set_pcie_lanes = NULL,
.set_clock_gating = NULL,
.set_surface_reg = r600_set_surface_reg, .set_surface_reg = r600_set_surface_reg,
.clear_surface_reg = r600_clear_surface_reg, .clear_surface_reg = r600_clear_surface_reg,
.hpd = { .hpd = {
...@@ -1364,6 +1359,13 @@ static struct radeon_asic cayman_asic = { ...@@ -1364,6 +1359,13 @@ static struct radeon_asic cayman_asic = {
.finish = &evergreen_pm_finish, .finish = &evergreen_pm_finish,
.init_profile = &r600_pm_init_profile, .init_profile = &r600_pm_init_profile,
.get_dynpm_state = &r600_pm_get_dynpm_state, .get_dynpm_state = &r600_pm_get_dynpm_state,
.get_engine_clock = &radeon_atom_get_engine_clock,
.set_engine_clock = &radeon_atom_set_engine_clock,
.get_memory_clock = &radeon_atom_get_memory_clock,
.set_memory_clock = &radeon_atom_set_memory_clock,
.get_pcie_lanes = NULL,
.set_pcie_lanes = NULL,
.set_clock_gating = NULL,
}, },
.pflip = { .pflip = {
.pre_page_flip = &evergreen_pre_page_flip, .pre_page_flip = &evergreen_pre_page_flip,
...@@ -1412,10 +1414,10 @@ int radeon_asic_init(struct radeon_device *rdev) ...@@ -1412,10 +1414,10 @@ int radeon_asic_init(struct radeon_device *rdev)
rdev->asic = &r420_asic; rdev->asic = &r420_asic;
/* handle macs */ /* handle macs */
if (rdev->bios == NULL) { if (rdev->bios == NULL) {
rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock; rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock; rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock; rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
rdev->asic->set_memory_clock = NULL; rdev->asic->pm.set_memory_clock = NULL;
} }
break; break;
case CHIP_RS400: case CHIP_RS400:
...@@ -1496,8 +1498,8 @@ int radeon_asic_init(struct radeon_device *rdev) ...@@ -1496,8 +1498,8 @@ int radeon_asic_init(struct radeon_device *rdev)
} }
if (rdev->flags & RADEON_IS_IGP) { if (rdev->flags & RADEON_IS_IGP) {
rdev->asic->get_memory_clock = NULL; rdev->asic->pm.get_memory_clock = NULL;
rdev->asic->set_memory_clock = NULL; rdev->asic->pm.set_memory_clock = NULL;
} }
return 0; return 0;
......
drivers/gpu/drm/radeon/radeon_clocks.c
View file @ 798bcf73
...@@ -334,7 +334,7 @@ void radeon_get_clock_info(struct drm_device *dev) ...@@ -334,7 +334,7 @@ void radeon_get_clock_info(struct drm_device *dev)
if (!rdev->clock.default_sclk) if (!rdev->clock.default_sclk)
rdev->clock.default_sclk = radeon_get_engine_clock(rdev); rdev->clock.default_sclk = radeon_get_engine_clock(rdev);
if ((!rdev->clock.default_mclk) && rdev->asic->get_memory_clock) if ((!rdev->clock.default_mclk) && rdev->asic->pm.get_memory_clock)
rdev->clock.default_mclk = radeon_get_memory_clock(rdev); rdev->clock.default_mclk = radeon_get_memory_clock(rdev);
rdev->pm.current_sclk = rdev->clock.default_sclk; rdev->pm.current_sclk = rdev->clock.default_sclk;
......
drivers/gpu/drm/radeon/radeon_pm.c
View file @ 798bcf73
...@@ -221,7 +221,7 @@ static void radeon_set_power_state(struct radeon_device *rdev) ...@@ -221,7 +221,7 @@ static void radeon_set_power_state(struct radeon_device *rdev)
} }
/* set memory clock */ /* set memory clock */
if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) { if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
radeon_pm_debug_check_in_vbl(rdev, false); radeon_pm_debug_check_in_vbl(rdev, false);
radeon_set_memory_clock(rdev, mclk); radeon_set_memory_clock(rdev, mclk);
radeon_pm_debug_check_in_vbl(rdev, true); radeon_pm_debug_check_in_vbl(rdev, true);
...@@ -863,11 +863,11 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data) ...@@ -863,11 +863,11 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
if (rdev->asic->get_memory_clock) if (rdev->asic->pm.get_memory_clock)
seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
if (rdev->pm.current_vddc) if (rdev->pm.current_vddc)
seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
if (rdev->asic->get_pcie_lanes) if (rdev->asic->pm.get_pcie_lanes)
seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
return 0; return 0;
......
drivers/gpu/drm/radeon/rs600.c
View file @ 798bcf73
...@@ -194,7 +194,7 @@ void rs600_pm_misc(struct radeon_device *rdev) ...@@ -194,7 +194,7 @@ void rs600_pm_misc(struct radeon_device *rdev)
/* set pcie lanes */ /* set pcie lanes */
if ((rdev->flags & RADEON_IS_PCIE) && if ((rdev->flags & RADEON_IS_PCIE) &&
!(rdev->flags & RADEON_IS_IGP) && !(rdev->flags & RADEON_IS_IGP) &&
rdev->asic->set_pcie_lanes && rdev->asic->pm.set_pcie_lanes &&
(ps->pcie_lanes != (ps->pcie_lanes !=
rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
radeon_set_pcie_lanes(rdev, radeon_set_pcie_lanes(rdev,
......
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