Commit 79dbddaf authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'powerpc-4.4-4' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux

Pull powerpc fixes from Michael Ellerman:
 - opal-irqchip: Fix double endian conversion from Alistair Popple
 - cxl: Set endianess of kernel contexts from Frederic Barrat
 - sbc8641: drop bogus PHY IRQ entries from DTS file from Paul Gortmaker
 - Revert "powerpc/eeh: Don't unfreeze PHB PE after reset" from Andrew
   Donnellan

* tag 'powerpc-4.4-4' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
  Revert "powerpc/eeh: Don't unfreeze PHB PE after reset"
  powerpc/sbc8641: drop bogus PHY IRQ entries from DTS file
  cxl: Set endianess of kernel contexts
  powerpc/opal-irqchip: Fix double endian conversion
parents 800f1ac4 dc9c41bd
...@@ -227,23 +227,15 @@ mdio@520 { ...@@ -227,23 +227,15 @@ mdio@520 {
reg = <0x520 0x20>; reg = <0x520 0x20>;
phy0: ethernet-phy@1f { phy0: ethernet-phy@1f {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <0x1f>; reg = <0x1f>;
}; };
phy1: ethernet-phy@0 { phy1: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <0>; reg = <0>;
}; };
phy2: ethernet-phy@1 { phy2: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <1>; reg = <1>;
}; };
phy3: ethernet-phy@2 { phy3: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <2>; reg = <2>;
}; };
tbi0: tbi-phy@11 { tbi0: tbi-phy@11 {
......
...@@ -590,16 +590,10 @@ static int eeh_reset_device(struct eeh_pe *pe, struct pci_bus *bus) ...@@ -590,16 +590,10 @@ static int eeh_reset_device(struct eeh_pe *pe, struct pci_bus *bus)
eeh_ops->configure_bridge(pe); eeh_ops->configure_bridge(pe);
eeh_pe_restore_bars(pe); eeh_pe_restore_bars(pe);
/* /* Clear frozen state */
* If it's PHB PE, the frozen state on all available PEs should have
* been cleared by the PHB reset. Otherwise, we unfreeze the PE and its
* child PEs because they might be in frozen state.
*/
if (!(pe->type & EEH_PE_PHB)) {
rc = eeh_clear_pe_frozen_state(pe, false); rc = eeh_clear_pe_frozen_state(pe, false);
if (rc) if (rc)
return rc; return rc;
}
/* Give the system 5 seconds to finish running the user-space /* Give the system 5 seconds to finish running the user-space
* hotplug shutdown scripts, e.g. ifdown for ethernet. Yes, * hotplug shutdown scripts, e.g. ifdown for ethernet. Yes,
......
...@@ -43,11 +43,34 @@ static unsigned int opal_irq_count; ...@@ -43,11 +43,34 @@ static unsigned int opal_irq_count;
static unsigned int *opal_irqs; static unsigned int *opal_irqs;
static void opal_handle_irq_work(struct irq_work *work); static void opal_handle_irq_work(struct irq_work *work);
static __be64 last_outstanding_events; static u64 last_outstanding_events;
static struct irq_work opal_event_irq_work = { static struct irq_work opal_event_irq_work = {
.func = opal_handle_irq_work, .func = opal_handle_irq_work,
}; };
void opal_handle_events(uint64_t events)
{
int virq, hwirq = 0;
u64 mask = opal_event_irqchip.mask;
if (!in_irq() && (events & mask)) {
last_outstanding_events = events;
irq_work_queue(&opal_event_irq_work);
return;
}
while (events & mask) {
hwirq = fls64(events) - 1;
if (BIT_ULL(hwirq) & mask) {
virq = irq_find_mapping(opal_event_irqchip.domain,
hwirq);
if (virq)
generic_handle_irq(virq);
}
events &= ~BIT_ULL(hwirq);
}
}
static void opal_event_mask(struct irq_data *d) static void opal_event_mask(struct irq_data *d)
{ {
clear_bit(d->hwirq, &opal_event_irqchip.mask); clear_bit(d->hwirq, &opal_event_irqchip.mask);
...@@ -55,12 +78,12 @@ static void opal_event_mask(struct irq_data *d) ...@@ -55,12 +78,12 @@ static void opal_event_mask(struct irq_data *d)
static void opal_event_unmask(struct irq_data *d) static void opal_event_unmask(struct irq_data *d)
{ {
__be64 events;
set_bit(d->hwirq, &opal_event_irqchip.mask); set_bit(d->hwirq, &opal_event_irqchip.mask);
opal_poll_events(&last_outstanding_events); opal_poll_events(&events);
if (last_outstanding_events & opal_event_irqchip.mask) opal_handle_events(be64_to_cpu(events));
/* Need to retrigger the interrupt */
irq_work_queue(&opal_event_irq_work);
} }
static int opal_event_set_type(struct irq_data *d, unsigned int flow_type) static int opal_event_set_type(struct irq_data *d, unsigned int flow_type)
...@@ -96,29 +119,6 @@ static int opal_event_map(struct irq_domain *d, unsigned int irq, ...@@ -96,29 +119,6 @@ static int opal_event_map(struct irq_domain *d, unsigned int irq,
return 0; return 0;
} }
void opal_handle_events(uint64_t events)
{
int virq, hwirq = 0;
u64 mask = opal_event_irqchip.mask;
if (!in_irq() && (events & mask)) {
last_outstanding_events = events;
irq_work_queue(&opal_event_irq_work);
return;
}
while (events & mask) {
hwirq = fls64(events) - 1;
if (BIT_ULL(hwirq) & mask) {
virq = irq_find_mapping(opal_event_irqchip.domain,
hwirq);
if (virq)
generic_handle_irq(virq);
}
events &= ~BIT_ULL(hwirq);
}
}
static irqreturn_t opal_interrupt(int irq, void *data) static irqreturn_t opal_interrupt(int irq, void *data)
{ {
__be64 events; __be64 events;
...@@ -131,7 +131,7 @@ static irqreturn_t opal_interrupt(int irq, void *data) ...@@ -131,7 +131,7 @@ static irqreturn_t opal_interrupt(int irq, void *data)
static void opal_handle_irq_work(struct irq_work *work) static void opal_handle_irq_work(struct irq_work *work)
{ {
opal_handle_events(be64_to_cpu(last_outstanding_events)); opal_handle_events(last_outstanding_events);
} }
static int opal_event_match(struct irq_domain *h, struct device_node *node, static int opal_event_match(struct irq_domain *h, struct device_node *node,
......
...@@ -497,6 +497,7 @@ static u64 calculate_sr(struct cxl_context *ctx) ...@@ -497,6 +497,7 @@ static u64 calculate_sr(struct cxl_context *ctx)
{ {
u64 sr = 0; u64 sr = 0;
set_endian(sr);
if (ctx->master) if (ctx->master)
sr |= CXL_PSL_SR_An_MP; sr |= CXL_PSL_SR_An_MP;
if (mfspr(SPRN_LPCR) & LPCR_TC) if (mfspr(SPRN_LPCR) & LPCR_TC)
...@@ -506,7 +507,6 @@ static u64 calculate_sr(struct cxl_context *ctx) ...@@ -506,7 +507,6 @@ static u64 calculate_sr(struct cxl_context *ctx)
sr |= CXL_PSL_SR_An_HV; sr |= CXL_PSL_SR_An_HV;
} else { } else {
sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R; sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
set_endian(sr);
sr &= ~(CXL_PSL_SR_An_HV); sr &= ~(CXL_PSL_SR_An_HV);
if (!test_tsk_thread_flag(current, TIF_32BIT)) if (!test_tsk_thread_flag(current, TIF_32BIT))
sr |= CXL_PSL_SR_An_SF; sr |= CXL_PSL_SR_An_SF;
......
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