ppc64: fix up set_tb and SPRN_TB* defines as well as some misc cleanups.

arch/ppc64/kernel/bitops.c

@@ -45,17 +45,6 @@ unsigned long find_next_zero_bit(unsigned long *addr, unsigned long size,
 	return result + ffz(tmp);
 }
 
-static __inline__ unsigned long ___ffs(unsigned long word)
-{
-        unsigned long result = 0;
-
-        while (!(word & 1UL)) {
-                result++;
-                word >>= 1;
-        }
-        return result;
-}
-
 unsigned long find_next_bit(unsigned long *addr, unsigned long size, unsigned long offset)
 {
 	unsigned long *p = addr + (offset >> 6);
@@ -91,7 +80,7 @@ unsigned long find_next_bit(unsigned long *addr, unsigned long size, unsigned lo
 	if (tmp == 0UL)        /* Are any bits set? */
 		return result + size; /* Nope. */
 found_middle:
-	return result + ___ffs(tmp);
+	return result + __ffs(tmp);
 }
 
 static __inline__ unsigned int ext2_ilog2(unsigned int x) 

arch/ppc64/kernel/ppc_ksyms.c

@@ -54,12 +54,6 @@
 /* Tell string.h we don't want memcpy etc. as cpp defines */
 #define EXPORT_SYMTAB_STROPS
 
-extern void do_IRQ(struct pt_regs *regs, int isfake);
-extern void SystemResetException(struct pt_regs *regs);
-extern void MachineCheckException(struct pt_regs *regs);
-extern void AlignmentException(struct pt_regs *regs);
-extern void ProgramCheckException(struct pt_regs *regs);
-extern void SingleStepException(struct pt_regs *regs);
 extern int sys_sigreturn(struct pt_regs *regs);
 extern int do_signal(sigset_t *, struct pt_regs *);
 extern int register_ioctl32_conversion(unsigned int cmd, int (*handler)(unsigned int, unsigned int, unsigned long, struct file *));
@@ -74,17 +68,12 @@ extern struct pci_dev * iSeries_veth_dev;
 extern struct pci_dev * iSeries_vio_dev;
 
 EXPORT_SYMBOL(do_signal);
-EXPORT_SYMBOL(do_IRQ);
-EXPORT_SYMBOL(SystemResetException);
-EXPORT_SYMBOL(MachineCheckException);
-EXPORT_SYMBOL(AlignmentException);
-EXPORT_SYMBOL(ProgramCheckException);
-EXPORT_SYMBOL(SingleStepException);
 EXPORT_SYMBOL(sys_sigreturn);
 EXPORT_SYMBOL(enable_irq);
 EXPORT_SYMBOL(disable_irq);
 EXPORT_SYMBOL(disable_irq_nosync);
 #ifdef CONFIG_SMP
+EXPORT_SYMBOL(synchronize_irq);
 EXPORT_SYMBOL(kernel_flag);
 #endif /* CONFIG_SMP */
 
@@ -126,15 +115,6 @@ EXPORT_SYMBOL(__clear_user);
 EXPORT_SYMBOL(__strncpy_from_user);
 EXPORT_SYMBOL(__strnlen_user);
 
-/*
-EXPORT_SYMBOL(inb);
-EXPORT_SYMBOL(inw);
-EXPORT_SYMBOL(inl);
-EXPORT_SYMBOL(outb);
-EXPORT_SYMBOL(outw);
-EXPORT_SYMBOL(outl);
-EXPORT_SYMBOL(outsl);*/
-
 #ifdef CONFIG_MSCHUNKS
 EXPORT_SYMBOL(msChunks);
 #endif
@@ -243,8 +223,6 @@ EXPORT_SYMBOL(abs);
 
 EXPORT_SYMBOL(timer_interrupt);
 EXPORT_SYMBOL(irq_desc);
-void ppc_irq_dispatch_handler(struct pt_regs *, int);
-EXPORT_SYMBOL(ppc_irq_dispatch_handler);
 EXPORT_SYMBOL(get_wchan);
 EXPORT_SYMBOL(console_drivers);
 #ifdef CONFIG_XMON

arch/ppc64/kernel/smp.c

@@ -85,9 +85,9 @@ struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
 
 static inline void set_tb(unsigned int upper, unsigned int lower)
 {
-	mtspr(SPRN_TBWL, 0);
-	mtspr(SPRN_TBWU, upper);
-	mtspr(SPRN_TBWL, lower);
+	mttbl(0);
+	mttbu(upper);
+	mttbl(lower);
 }
 
 void iSeries_smp_message_recv( struct pt_regs * regs )
@@ -181,12 +181,12 @@ static void smp_iSeries_kick_cpu(int nr)
 	paca[nr].xProcStart = 1;
 }
 
-static void smp_iSeries_setup_cpu(int nr)
+static void __devinit smp_iSeries_setup_cpu(int nr)
 {
 }
 
 /* This is called very early. */
-void smp_init_iSeries(void)
+void __init smp_init_iSeries(void)
 {
 	smp_ops = &ppc_md.smp_ops;
 	smp_ops->message_pass = smp_iSeries_message_pass;
@@ -224,7 +224,7 @@ smp_openpic_message_pass(int target, int msg, unsigned long data, int wait)
 	}
 }
 
-static int smp_chrp_probe(void)
+static int __init smp_chrp_probe(void)
 {
 	int i;
 	int nr_cpus = 0;
@@ -262,7 +262,7 @@ smp_kick_cpu(int nr)
 	paca[nr].xProcStart = 1;
 }
 
-static void smp_space_timers(unsigned int max_cpus)
+static void __init smp_space_timers(unsigned int max_cpus)
 {
 	int i;
 	unsigned long offset = tb_ticks_per_jiffy / max_cpus;
@@ -306,7 +306,7 @@ smp_xics_message_pass(int target, int msg, unsigned long data, int wait)
 	}
 }
 
-static int smp_xics_probe(void)
+static int __init smp_xics_probe(void)
 {
 	int i;
 	int nr_cpus = 0;
@@ -339,7 +339,7 @@ static void __devinit pSeries_take_timebase(void)
 	while (!timebase)
 		barrier();
 	spin_lock(&timebase_lock);
-	set_tb(timebase, timebase >> 32);
+	set_tb(timebase >> 32, timebase & 0xffffffff);
 	timebase = 0;
 	spin_unlock(&timebase_lock);
 }
@@ -608,7 +608,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 	smp_space_timers(max_cpus);
 }
 
-int __cpu_up(unsigned int cpu)
+int __devinit __cpu_up(unsigned int cpu)
 {
 	struct pt_regs regs;
 	struct task_struct *p;
@@ -667,7 +667,6 @@ int __devinit start_secondary(void *unused)
 	if (smp_ops->take_timebase)
 		smp_ops->take_timebase();
 
-	/* XXX required? */
 	local_irq_enable();
 
 	return cpu_idle(NULL);
@@ -678,7 +677,7 @@ int setup_profiling_timer(unsigned int multiplier)
 	return 0;
 }
 
-void smp_cpus_done(unsigned int max_cpus)
+void __init smp_cpus_done(unsigned int max_cpus)
 {
 	smp_ops->setup_cpu(boot_cpuid);
 

include/asm-ppc64/processor.h

@@ -274,16 +274,10 @@
 #define	SPRN_SPRG3	0x113	/* Special Purpose Register General 3 */
 #define	SPRN_SRR0	0x01A	/* Save/Restore Register 0 */
 #define	SPRN_SRR1	0x01B	/* Save/Restore Register 1 */
-#define	SPRN_SRR2	0x3DE	/* Save/Restore Register 2 */
-#define	SPRN_SRR3 	0x3DF	/* Save/Restore Register 3 */
-#define	SPRN_TBHI	0x3DC	/* Time Base High */
-#define	SPRN_TBHU	0x3CC	/* Time Base High User-mode */
-#define	SPRN_TBLO	0x3DD	/* Time Base Low */
-#define	SPRN_TBLU	0x3CD	/* Time Base Low User-mode */
-#define	SPRN_TBRL	0x10D	/* Time Base Read Lower Register */
-#define	SPRN_TBRU	0x10C	/* Time Base Read Upper Register */
-#define	SPRN_TBWL	0x11D	/* Time Base Write Lower Register */
-#define	SPRN_TBWU	0x11C	/* Time Base Write Upper Register */
+#define	SPRN_TBRL	0x10C	/* Time Base Read Lower Register (user, R/O) */
+#define	SPRN_TBRU	0x10D	/* Time Base Read Upper Register (user, R/O) */
+#define	SPRN_TBWL	0x11C	/* Time Base Lower Register (super, W/O) */
+#define	SPRN_TBWU	0x11D	/* Time Base Write Upper Register (super, W/O) */
 #define	SPRN_TCR	0x3DA	/* Timer Control Register */
 #define	  TCR_WP(x)		(((x)&0x3)<<30)	/* WDT Period */
 #define	    WP_2_17		0		/* 2^17 clocks */
@@ -585,6 +579,9 @@ GLUE(GLUE(.LT,NAME),_procname_end):
 #define mftb()		({unsigned long rval;	\
 			asm volatile("mftb %0" : "=r" (rval)); rval;})
 
+#define mttbl(v)	asm volatile("mttbl %0":: "r"(v))
+#define mttbu(v)	asm volatile("mttbu %0":: "r"(v))
+
 /* iSeries CTRL register (for runlatch) */
 
 #define CTRLT		0x098

include/asm-ppc64/smp.h

@@ -56,9 +56,7 @@ extern volatile unsigned long cpu_callin_map[NR_CPUS];
 
 #define smp_processor_id() (get_paca()->xPacaIndex)
 
-/* remove when the boot sequence gets rewritten to use hotplug interface */
 extern int boot_cpuid;
-extern int ppc64_is_smp;
 
 /* Since OpenPIC has only 4 IPIs, we use slightly different message numbers.
  *