net: phy: mscc: configure both RX and TX internal delays for RGMII

The driver appears to be secretly enabling the RX clock skew
irrespective of PHY interface type, which is generally considered a big
no-no.

Make them configurable instead, and add TX internal delays when
necessary too.

While at it, configure a more canonical clock skew of 2.0 nanoseconds
than the current default of 1.1 ns.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

drivers/net/phy/mscc/mscc.h

@@ -178,6 +178,8 @@ enum rgmii_clock_delay {
 #define MSCC_PHY_RGMII_CNTL		  20
 #define RGMII_RX_CLK_DELAY_MASK		  0x0070
 #define RGMII_RX_CLK_DELAY_POS		  4
+#define RGMII_TX_CLK_DELAY_MASK		  0x0007
+#define RGMII_TX_CLK_DELAY_POS		  0
 
 #define MSCC_PHY_WOL_LOWER_MAC_ADDR	  21
 #define MSCC_PHY_WOL_MID_MAC_ADDR	  22

drivers/net/phy/mscc/mscc_main.c

@@ -522,16 +522,26 @@ static int vsc85xx_mac_if_set(struct phy_device *phydev,
 
 static int vsc85xx_default_config(struct phy_device *phydev)
 {
+	u16 reg_val = 0;
 	int rc;
-	u16 reg_val;
 
 	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
+
+	if (!phy_interface_mode_is_rgmii(phydev->interface))
+		return 0;
+
 	mutex_lock(&phydev->lock);
 
-	reg_val = RGMII_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS;
+	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
+	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+		reg_val |= RGMII_CLK_DELAY_2_0_NS << RGMII_RX_CLK_DELAY_POS;
+	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
+	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+		reg_val |= RGMII_CLK_DELAY_2_0_NS << RGMII_TX_CLK_DELAY_POS;
 
 	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
-			      MSCC_PHY_RGMII_CNTL, RGMII_RX_CLK_DELAY_MASK,
+			      MSCC_PHY_RGMII_CNTL,
+			      RGMII_RX_CLK_DELAY_MASK | RGMII_TX_CLK_DELAY_MASK,
 			      reg_val);
 
 	mutex_unlock(&phydev->lock);