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Commit 7b59c7e4 authored by Archit Taneja's avatar Archit Taneja Committed by Rob Clark
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drm/msm/mdp5: Use updated MDP5 register names 

Since MDSS registers were stuffed within the the MDP5 register
space, we had an __offset_MDP() macro to identify the offset
between the start of MDSS and MDP5 address spaces. This offset
macro expected a MDP index argument, which didn't make much
sense since we don't have multiple MDPs.

The offset is no longer needed now that we have devices for the 2
different register address spaces. Also, remove the "REG_MDP5_MDP_"
prefix to "REG_MDP5_".

Update the generated headers in mdp5.xml.h

We generally update headers as a separate patch, but we need to
do these together to prevent breaking build.
Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent 392ae6e0
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Showing with 143 additions and 160 deletions
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
View file @ 7b59c7e4
...@@ -8,19 +8,11 @@ This file was generated by the rules-ng-ng headergen tool in this git repository ...@@ -8,19 +8,11 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone https://github.com/freedreno/envytools.git git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are: The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) - /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-05-10 05:06:30)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) - /local/mnt/workspace/source_trees/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-05-09 06:32:54)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) - /local/mnt/workspace/source_trees/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2016-01-07 08:45:55)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) Copyright (C) 2013-2016 by the following authors:
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark) - Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
...@@ -198,118 +190,109 @@ static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val) ...@@ -198,118 +190,109 @@ static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val)
#define MDSS_HW_INTR_STATUS_INTR_HDMI 0x00000100 #define MDSS_HW_INTR_STATUS_INTR_HDMI 0x00000100
#define MDSS_HW_INTR_STATUS_INTR_EDP 0x00001000 #define MDSS_HW_INTR_STATUS_INTR_EDP 0x00001000
static inline uint32_t __offset_MDP(uint32_t idx) #define REG_MDP5_HW_VERSION 0x00000000
{ #define MDP5_HW_VERSION_STEP__MASK 0x0000ffff
switch (idx) { #define MDP5_HW_VERSION_STEP__SHIFT 0
case 0: return (mdp5_cfg->mdp.base[0]); static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val)
default: return INVALID_IDX(idx);
}
}
static inline uint32_t REG_MDP5_MDP(uint32_t i0) { return 0x00000000 + __offset_MDP(i0); }
static inline uint32_t REG_MDP5_MDP_HW_VERSION(uint32_t i0) { return 0x00000000 + __offset_MDP(i0); }
#define MDP5_MDP_HW_VERSION_STEP__MASK 0x0000ffff
#define MDP5_MDP_HW_VERSION_STEP__SHIFT 0
static inline uint32_t MDP5_MDP_HW_VERSION_STEP(uint32_t val)
{ {
return ((val) << MDP5_MDP_HW_VERSION_STEP__SHIFT) & MDP5_MDP_HW_VERSION_STEP__MASK; return ((val) << MDP5_HW_VERSION_STEP__SHIFT) & MDP5_HW_VERSION_STEP__MASK;
} }
#define MDP5_MDP_HW_VERSION_MINOR__MASK 0x0fff0000 #define MDP5_HW_VERSION_MINOR__MASK 0x0fff0000
#define MDP5_MDP_HW_VERSION_MINOR__SHIFT 16 #define MDP5_HW_VERSION_MINOR__SHIFT 16
static inline uint32_t MDP5_MDP_HW_VERSION_MINOR(uint32_t val) static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val)
{ {
return ((val) << MDP5_MDP_HW_VERSION_MINOR__SHIFT) & MDP5_MDP_HW_VERSION_MINOR__MASK; return ((val) << MDP5_HW_VERSION_MINOR__SHIFT) & MDP5_HW_VERSION_MINOR__MASK;
} }
#define MDP5_MDP_HW_VERSION_MAJOR__MASK 0xf0000000 #define MDP5_HW_VERSION_MAJOR__MASK 0xf0000000
#define MDP5_MDP_HW_VERSION_MAJOR__SHIFT 28 #define MDP5_HW_VERSION_MAJOR__SHIFT 28
static inline uint32_t MDP5_MDP_HW_VERSION_MAJOR(uint32_t val) static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val)
{ {
return ((val) << MDP5_MDP_HW_VERSION_MAJOR__SHIFT) & MDP5_MDP_HW_VERSION_MAJOR__MASK; return ((val) << MDP5_HW_VERSION_MAJOR__SHIFT) & MDP5_HW_VERSION_MAJOR__MASK;
} }
static inline uint32_t REG_MDP5_MDP_DISP_INTF_SEL(uint32_t i0) { return 0x00000004 + __offset_MDP(i0); } #define REG_MDP5_DISP_INTF_SEL 0x00000004
#define MDP5_MDP_DISP_INTF_SEL_INTF0__MASK 0x000000ff #define MDP5_DISP_INTF_SEL_INTF0__MASK 0x000000ff
#define MDP5_MDP_DISP_INTF_SEL_INTF0__SHIFT 0 #define MDP5_DISP_INTF_SEL_INTF0__SHIFT 0
static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val) static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val)
{ {
return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF0__MASK; return ((val) << MDP5_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_DISP_INTF_SEL_INTF0__MASK;
} }
#define MDP5_MDP_DISP_INTF_SEL_INTF1__MASK 0x0000ff00 #define MDP5_DISP_INTF_SEL_INTF1__MASK 0x0000ff00
#define MDP5_MDP_DISP_INTF_SEL_INTF1__SHIFT 8 #define MDP5_DISP_INTF_SEL_INTF1__SHIFT 8
static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val) static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val)
{ {
return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF1__MASK; return ((val) << MDP5_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_DISP_INTF_SEL_INTF1__MASK;
} }
#define MDP5_MDP_DISP_INTF_SEL_INTF2__MASK 0x00ff0000 #define MDP5_DISP_INTF_SEL_INTF2__MASK 0x00ff0000
#define MDP5_MDP_DISP_INTF_SEL_INTF2__SHIFT 16 #define MDP5_DISP_INTF_SEL_INTF2__SHIFT 16
static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val) static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val)
{ {
return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF2__MASK; return ((val) << MDP5_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_DISP_INTF_SEL_INTF2__MASK;
} }
#define MDP5_MDP_DISP_INTF_SEL_INTF3__MASK 0xff000000 #define MDP5_DISP_INTF_SEL_INTF3__MASK 0xff000000
#define MDP5_MDP_DISP_INTF_SEL_INTF3__SHIFT 24 #define MDP5_DISP_INTF_SEL_INTF3__SHIFT 24
static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val) static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val)
{ {
return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF3__MASK; return ((val) << MDP5_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_DISP_INTF_SEL_INTF3__MASK;
} }
static inline uint32_t REG_MDP5_MDP_INTR_EN(uint32_t i0) { return 0x00000010 + __offset_MDP(i0); } #define REG_MDP5_INTR_EN 0x00000010
static inline uint32_t REG_MDP5_MDP_INTR_STATUS(uint32_t i0) { return 0x00000014 + __offset_MDP(i0); } #define REG_MDP5_INTR_STATUS 0x00000014
static inline uint32_t REG_MDP5_MDP_INTR_CLEAR(uint32_t i0) { return 0x00000018 + __offset_MDP(i0); } #define REG_MDP5_INTR_CLEAR 0x00000018
static inline uint32_t REG_MDP5_MDP_HIST_INTR_EN(uint32_t i0) { return 0x0000001c + __offset_MDP(i0); } #define REG_MDP5_HIST_INTR_EN 0x0000001c
static inline uint32_t REG_MDP5_MDP_HIST_INTR_STATUS(uint32_t i0) { return 0x00000020 + __offset_MDP(i0); } #define REG_MDP5_HIST_INTR_STATUS 0x00000020
static inline uint32_t REG_MDP5_MDP_HIST_INTR_CLEAR(uint32_t i0) { return 0x00000024 + __offset_MDP(i0); } #define REG_MDP5_HIST_INTR_CLEAR 0x00000024
static inline uint32_t REG_MDP5_MDP_SPARE_0(uint32_t i0) { return 0x00000028 + __offset_MDP(i0); } #define REG_MDP5_SPARE_0 0x00000028
#define MDP5_MDP_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN 0x00000001 #define MDP5_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN 0x00000001
static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_MDP(i0) + 0x4*i1; } static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; }
static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W_REG(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_MDP(i0) + 0x4*i1; } static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; }
#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__MASK 0x000000ff #define MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK 0x000000ff
#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__SHIFT 0 #define MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT 0
static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0(uint32_t val) static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(uint32_t val)
{ {
return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__MASK; return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK;
} }
#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__MASK 0x0000ff00 #define MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK 0x0000ff00
#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__SHIFT 8 #define MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT 8
static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1(uint32_t val) static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(uint32_t val)
{ {
return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__MASK; return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK;
} }
#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff0000 #define MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff0000
#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__SHIFT 16 #define MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT 16
static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2(uint32_t val) static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(uint32_t val)
{ {
return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__MASK; return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK;
} }
static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_MDP(i0) + 0x4*i1; } static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; }
static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R_REG(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_MDP(i0) + 0x4*i1; } static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; }
#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__MASK 0x000000ff #define MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK 0x000000ff
#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__SHIFT 0 #define MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT 0
static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0(uint32_t val) static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(uint32_t val)
{ {
return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__MASK; return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK;
} }
#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__MASK 0x0000ff00 #define MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK 0x0000ff00
#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__SHIFT 8 #define MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT 8
static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1(uint32_t val) static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(uint32_t val)
{ {
return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__MASK; return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK;
} }
#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff0000 #define MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff0000
#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__SHIFT 16 #define MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT 16
static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2(uint32_t val) static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(uint32_t val)
{ {
return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__MASK; return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK;
} }
static inline uint32_t __offset_IGC(enum mdp5_igc_type idx) static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)
...@@ -322,35 +305,35 @@ static inline uint32_t __offset_IGC(enum mdp5_igc_type idx) ...@@ -322,35 +305,35 @@ static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)
default: return INVALID_IDX(idx); default: return INVALID_IDX(idx);
} }
} }
static inline uint32_t REG_MDP5_MDP_IGC(uint32_t i0, enum mdp5_igc_type i1) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1); } static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); }
static inline uint32_t REG_MDP5_MDP_IGC_LUT(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1) + 0x4*i2; } static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
static inline uint32_t REG_MDP5_MDP_IGC_LUT_REG(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1) + 0x4*i2; } static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
#define MDP5_MDP_IGC_LUT_REG_VAL__MASK 0x00000fff #define MDP5_IGC_LUT_REG_VAL__MASK 0x00000fff
#define MDP5_MDP_IGC_LUT_REG_VAL__SHIFT 0 #define MDP5_IGC_LUT_REG_VAL__SHIFT 0
static inline uint32_t MDP5_MDP_IGC_LUT_REG_VAL(uint32_t val) static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val)
{ {
return ((val) << MDP5_MDP_IGC_LUT_REG_VAL__SHIFT) & MDP5_MDP_IGC_LUT_REG_VAL__MASK; return ((val) << MDP5_IGC_LUT_REG_VAL__SHIFT) & MDP5_IGC_LUT_REG_VAL__MASK;
} }
#define MDP5_MDP_IGC_LUT_REG_INDEX_UPDATE 0x02000000 #define MDP5_IGC_LUT_REG_INDEX_UPDATE 0x02000000
#define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_0 0x10000000 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_0 0x10000000
#define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000
#define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000
static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_EN(uint32_t i0) { return 0x000002f4 + __offset_MDP(i0); } #define REG_MDP5_SPLIT_DPL_EN 0x000002f4
static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_UPPER(uint32_t i0) { return 0x000002f8 + __offset_MDP(i0); } #define REG_MDP5_SPLIT_DPL_UPPER 0x000002f8
#define MDP5_MDP_SPLIT_DPL_UPPER_SMART_PANEL 0x00000002 #define MDP5_SPLIT_DPL_UPPER_SMART_PANEL 0x00000002
#define MDP5_MDP_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN 0x00000004 #define MDP5_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN 0x00000004
#define MDP5_MDP_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX 0x00000010 #define MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX 0x00000010
#define MDP5_MDP_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX 0x00000100 #define MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX 0x00000100
static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_LOWER(uint32_t i0) { return 0x000003f0 + __offset_MDP(i0); } #define REG_MDP5_SPLIT_DPL_LOWER 0x000003f0
#define MDP5_MDP_SPLIT_DPL_LOWER_SMART_PANEL 0x00000002 #define MDP5_SPLIT_DPL_LOWER_SMART_PANEL 0x00000002
#define MDP5_MDP_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN 0x00000004 #define MDP5_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN 0x00000004
#define MDP5_MDP_SPLIT_DPL_LOWER_INTF1_TG_SYNC 0x00000010 #define MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC 0x00000010
#define MDP5_MDP_SPLIT_DPL_LOWER_INTF2_TG_SYNC 0x00000100 #define MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC 0x00000100
static inline uint32_t __offset_CTL(uint32_t idx) static inline uint32_t __offset_CTL(uint32_t idx)
{ {
......
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c
View file @ 7b59c7e4
...@@ -272,22 +272,22 @@ int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder, ...@@ -272,22 +272,22 @@ int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder,
* start signal for the slave encoder * start signal for the slave encoder
*/ */
if (intf_num == 1) if (intf_num == 1)
data |= MDP5_MDP_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX; data |= MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX;
else if (intf_num == 2) else if (intf_num == 2)
data |= MDP5_MDP_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX; data |= MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX;
else else
return -EINVAL; return -EINVAL;
/* Smart Panel, Sync mode */ /* Smart Panel, Sync mode */
data |= MDP5_MDP_SPLIT_DPL_UPPER_SMART_PANEL; data |= MDP5_SPLIT_DPL_UPPER_SMART_PANEL;
/* Make sure clocks are on when connectors calling this function. */ /* Make sure clocks are on when connectors calling this function. */
mdp5_enable(mdp5_kms); mdp5_enable(mdp5_kms);
mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_UPPER(0), data); mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, data);
mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_LOWER(0), mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER,
MDP5_MDP_SPLIT_DPL_LOWER_SMART_PANEL); MDP5_SPLIT_DPL_LOWER_SMART_PANEL);
mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_EN(0), 1); mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1);
mdp5_disable(mdp5_kms); mdp5_disable(mdp5_kms);
return 0; return 0;
......
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
View file @ 7b59c7e4
...@@ -118,31 +118,31 @@ static void set_display_intf(struct mdp5_kms *mdp5_kms, ...@@ -118,31 +118,31 @@ static void set_display_intf(struct mdp5_kms *mdp5_kms,
u32 intf_sel; u32 intf_sel;
spin_lock_irqsave(&mdp5_kms->resource_lock, flags); spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
intf_sel = mdp5_read(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0)); intf_sel = mdp5_read(mdp5_kms, REG_MDP5_DISP_INTF_SEL);
switch (intf->num) { switch (intf->num) {
case 0: case 0:
intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF0__MASK; intf_sel &= ~MDP5_DISP_INTF_SEL_INTF0__MASK;
intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF0(intf->type); intf_sel |= MDP5_DISP_INTF_SEL_INTF0(intf->type);
break; break;
case 1: case 1:
intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF1__MASK; intf_sel &= ~MDP5_DISP_INTF_SEL_INTF1__MASK;
intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF1(intf->type); intf_sel |= MDP5_DISP_INTF_SEL_INTF1(intf->type);
break; break;
case 2: case 2:
intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF2__MASK; intf_sel &= ~MDP5_DISP_INTF_SEL_INTF2__MASK;
intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF2(intf->type); intf_sel |= MDP5_DISP_INTF_SEL_INTF2(intf->type);
break; break;
case 3: case 3:
intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF3__MASK; intf_sel &= ~MDP5_DISP_INTF_SEL_INTF3__MASK;
intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF3(intf->type); intf_sel |= MDP5_DISP_INTF_SEL_INTF3(intf->type);
break; break;
default: default:
BUG(); BUG();
break; break;
} }
mdp5_write(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0), intf_sel); mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, intf_sel);
spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);
} }
...@@ -557,7 +557,7 @@ int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable) ...@@ -557,7 +557,7 @@ int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable)
if (!enable) { if (!enable) {
ctlx->pair = NULL; ctlx->pair = NULL;
ctly->pair = NULL; ctly->pair = NULL;
mdp5_write(mdp5_kms, REG_MDP5_MDP_SPARE_0(0), 0); mdp5_write(mdp5_kms, REG_MDP5_SPARE_0, 0);
return 0; return 0;
} else if ((ctlx->pair != NULL) || (ctly->pair != NULL)) { } else if ((ctlx->pair != NULL) || (ctly->pair != NULL)) {
dev_err(ctl_mgr->dev->dev, "CTLs already paired\n"); dev_err(ctl_mgr->dev->dev, "CTLs already paired\n");
...@@ -570,8 +570,8 @@ int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable) ...@@ -570,8 +570,8 @@ int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable)
ctlx->pair = ctly; ctlx->pair = ctly;
ctly->pair = ctlx; ctly->pair = ctlx;
mdp5_write(mdp5_kms, REG_MDP5_MDP_SPARE_0(0), mdp5_write(mdp5_kms, REG_MDP5_SPARE_0,
MDP5_MDP_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN); MDP5_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN);
return 0; return 0;
} }
......
drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
View file @ 7b59c7e4
...@@ -322,18 +322,18 @@ int mdp5_encoder_set_split_display(struct drm_encoder *encoder, ...@@ -322,18 +322,18 @@ int mdp5_encoder_set_split_display(struct drm_encoder *encoder,
* to use the master's enable signal for the slave encoder. * to use the master's enable signal for the slave encoder.
*/ */
if (intf_num == 1) if (intf_num == 1)
data |= MDP5_MDP_SPLIT_DPL_LOWER_INTF2_TG_SYNC; data |= MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC;
else if (intf_num == 2) else if (intf_num == 2)
data |= MDP5_MDP_SPLIT_DPL_LOWER_INTF1_TG_SYNC; data |= MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC;
else else
return -EINVAL; return -EINVAL;
/* Make sure clocks are on when connectors calling this function. */ /* Make sure clocks are on when connectors calling this function. */
mdp5_enable(mdp5_kms); mdp5_enable(mdp5_kms);
/* Dumb Panel, Sync mode */ /* Dumb Panel, Sync mode */
mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_UPPER(0), 0); mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, 0);
mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_LOWER(0), data); mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, data);
mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_EN(0), 1); mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1);
mdp5_ctl_pair(mdp5_encoder->ctl, mdp5_slave_enc->ctl, true); mdp5_ctl_pair(mdp5_encoder->ctl, mdp5_slave_enc->ctl, true);
......
drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
View file @ 7b59c7e4
...@@ -23,9 +23,9 @@ ...@@ -23,9 +23,9 @@
void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
uint32_t old_irqmask) uint32_t old_irqmask)
{ {
mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_MDP_INTR_CLEAR(0), mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_CLEAR,
irqmask ^ (irqmask & old_irqmask)); irqmask ^ (irqmask & old_irqmask));
mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_MDP_INTR_EN(0), irqmask); mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_EN, irqmask);
} }
static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus) static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus)
...@@ -37,8 +37,8 @@ void mdp5_irq_preinstall(struct msm_kms *kms) ...@@ -37,8 +37,8 @@ void mdp5_irq_preinstall(struct msm_kms *kms)
{ {
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
mdp5_enable(mdp5_kms); mdp5_enable(mdp5_kms);
mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_CLEAR(0), 0xffffffff); mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0xffffffff);
mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_EN(0), 0x00000000); mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000);
mdp5_disable(mdp5_kms); mdp5_disable(mdp5_kms);
} }
...@@ -63,7 +63,7 @@ void mdp5_irq_uninstall(struct msm_kms *kms) ...@@ -63,7 +63,7 @@ void mdp5_irq_uninstall(struct msm_kms *kms)
{ {
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
mdp5_enable(mdp5_kms); mdp5_enable(mdp5_kms);
mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_EN(0), 0x00000000); mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000);
mdp5_disable(mdp5_kms); mdp5_disable(mdp5_kms);
} }
...@@ -76,9 +76,9 @@ irqreturn_t mdp5_irq(struct msm_kms *kms) ...@@ -76,9 +76,9 @@ irqreturn_t mdp5_irq(struct msm_kms *kms)
unsigned int id; unsigned int id;
uint32_t status, enable; uint32_t status, enable;
enable = mdp5_read(mdp5_kms, REG_MDP5_MDP_INTR_EN(0)); enable = mdp5_read(mdp5_kms, REG_MDP5_INTR_EN);
status = mdp5_read(mdp5_kms, REG_MDP5_MDP_INTR_STATUS(0)) & enable; status = mdp5_read(mdp5_kms, REG_MDP5_INTR_STATUS) & enable;
mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_CLEAR(0), status); mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, status);
VERB("status=%08x", status); VERB("status=%08x", status);
......
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
View file @ 7b59c7e4
...@@ -59,7 +59,7 @@ static int mdp5_hw_init(struct msm_kms *kms) ...@@ -59,7 +59,7 @@ static int mdp5_hw_init(struct msm_kms *kms)
*/ */
spin_lock_irqsave(&mdp5_kms->resource_lock, flags); spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
mdp5_write(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0), 0); mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);
spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);
mdp5_ctlm_hw_reset(mdp5_kms->ctlm); mdp5_ctlm_hw_reset(mdp5_kms->ctlm);
...@@ -408,11 +408,11 @@ static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms, ...@@ -408,11 +408,11 @@ static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms,
u32 version; u32 version;
mdp5_enable(mdp5_kms); mdp5_enable(mdp5_kms);
version = mdp5_read(mdp5_kms, REG_MDP5_MDP_HW_VERSION(0)); version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION);
mdp5_disable(mdp5_kms); mdp5_disable(mdp5_kms);
*major = FIELD(version, MDP5_MDP_HW_VERSION_MAJOR); *major = FIELD(version, MDP5_HW_VERSION_MAJOR);
*minor = FIELD(version, MDP5_MDP_HW_VERSION_MINOR); *minor = FIELD(version, MDP5_HW_VERSION_MINOR);
DBG("MDP5 version v%d.%d", *major, *minor); DBG("MDP5 version v%d.%d", *major, *minor);
} }
......
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
View file @ 7b59c7e4
...@@ -55,7 +55,7 @@ struct mdp5_kms { ...@@ -55,7 +55,7 @@ struct mdp5_kms {
/* /*
* lock to protect access to global resources: ie., following register: * lock to protect access to global resources: ie., following register:
* - REG_MDP5_MDP_DISP_INTF_SEL * - REG_MDP5_DISP_INTF_SEL
*/ */
spinlock_t resource_lock; spinlock_t resource_lock;
......
drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
View file @ 7b59c7e4
...@@ -42,7 +42,7 @@ ...@@ -42,7 +42,7 @@
* *
* configured: * configured:
* The block is allocated to some client, and assigned to that * The block is allocated to some client, and assigned to that
* client in MDP5_MDP_SMP_ALLOC registers. * client in MDP5_SMP_ALLOC registers.
* *
* inuse: * inuse:
* The block is being actively used by a client. * The block is being actively used by a client.
...@@ -59,7 +59,7 @@ ...@@ -59,7 +59,7 @@
* mdp5_smp_commit. * mdp5_smp_commit.
* *
* 2) mdp5_smp_configure(): * 2) mdp5_smp_configure():
* As hw is programmed, before FLUSH, MDP5_MDP_SMP_ALLOC registers * As hw is programmed, before FLUSH, MDP5_SMP_ALLOC registers
* are configured for the union(pending, inuse) * are configured for the union(pending, inuse)
* Current pending is copied to configured. * Current pending is copied to configured.
* It is assumed that mdp5_smp_request and mdp5_smp_configure not run * It is assumed that mdp5_smp_request and mdp5_smp_configure not run
...@@ -311,25 +311,25 @@ static void update_smp_state(struct mdp5_smp *smp, ...@@ -311,25 +311,25 @@ static void update_smp_state(struct mdp5_smp *smp,
int idx = blk / 3; int idx = blk / 3;
int fld = blk % 3; int fld = blk % 3;
val = mdp5_read(mdp5_kms, REG_MDP5_MDP_SMP_ALLOC_W_REG(0, idx)); val = mdp5_read(mdp5_kms, REG_MDP5_SMP_ALLOC_W_REG(idx));
switch (fld) { switch (fld) {
case 0: case 0:
val &= ~MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__MASK; val &= ~MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK;
val |= MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0(cid); val |= MDP5_SMP_ALLOC_W_REG_CLIENT0(cid);
break; break;
case 1: case 1:
val &= ~MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__MASK; val &= ~MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK;
val |= MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1(cid); val |= MDP5_SMP_ALLOC_W_REG_CLIENT1(cid);
break; break;
case 2: case 2:
val &= ~MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__MASK; val &= ~MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK;
val |= MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2(cid); val |= MDP5_SMP_ALLOC_W_REG_CLIENT2(cid);
break; break;
} }
mdp5_write(mdp5_kms, REG_MDP5_MDP_SMP_ALLOC_W_REG(0, idx), val); mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_W_REG(idx), val);
mdp5_write(mdp5_kms, REG_MDP5_MDP_SMP_ALLOC_R_REG(0, idx), val); mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_R_REG(idx), val);
} }
} }
......
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