Commit 7d138d3a authored by J Keerthy's avatar J Keerthy Committed by Mike Turquette

ARM: dts: clk: Add apll related clocks

The patch adds a mux node to choose the parent of apll_pcie_ck node.
Signed-off-by: default avatarJ Keerthy <j-keerthy@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Tested-by: default avatarNishanth Menon <nm@ti.com>
Acked-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent ee6c7507
......@@ -1150,11 +1150,19 @@ dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
ti,invert-autoidle-bit;
};
apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
compatible = "ti,mux-clock";
clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
#clock-cells = <0>;
reg = <0x021c 0x4>;
ti,bit-shift = <7>;
};
apll_pcie_ck: apll_pcie_ck {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_ck>;
reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
compatible = "ti,dra7-apll-clock";
clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
reg = <0x021c>, <0x0220>;
};
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment