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Commit 7d738dbb authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'stm32-dt-for-v4.15-1' of... 

Merge tag 'stm32-dt-for-v4.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into next/soc

Pull "STM32 DT updates for v4.15, round 1" from Alexandre Torgue:

Highlights:
----------
 -Add I2C1 support on STM32F746 SoC
 -Enable I2C1 on STM32F746 eval board
 -Add Timers support on STM32F746 SoC
 -Add USB HS and FS supports on STM32F746 Soc
 -Enable USB HS on STM32F746 disco and eval boards
 -Enable USB FS en STM32F746 disco board
 -Add Vrefbuf to STM32H743 SoC
 -Add LPTIMERS support on STM32H743 SoC
 -Add DMAMUX support on STM32H743 SoC
 -Enable STM32H743 clock driver
 -Add MDMA support on STM32H743 SoC
 -Change pinctrl pinmux entries for all SoC.

* tag 'stm32-dt-for-v4.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
  ARM: dts: stm32: Add MDMA support for STM32H743 SoC
  ARM: dts: stm32: Enable USB FS on stm32f746-disco
  ARM: dts: stm32: Add USB FS support for STM32F746 MCU
  ARM: dts: stm32: Enable USB HS on stm32f746-disco
  ARM: dts: stm32: Enable USB HS on stm32746g-eval
  ARM: dts: stm32: Add USB HS support for STM32F746 MCU
  ARM: dts: stm32: change pinctrl bindings definition
  ARM: dts: stm32: Enable STM32H743 clock driver
  ARM: dts: stm32: fix hse clock frequency on STM32H743 Eval board
  ARM: dts: stm32: add Timers driver for stm32f746 MCU
  ARM: dts: stm32: Add DMAMUX support for STM32H743 SoC
  ARM: dts: stm32: Add lptimer definitions to stm32h743
  ARM: dts: stm32: add vrefbuf to stm32h743
  ARM: dts: stm32: Add I2C1 support for STM32F746 eval board
  ARM: dts: stm32: Add I2C1 support for STM32F746 SoC
parents 282e1cd1 4bd93eb3
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Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
View file @ 7d738dbb
......@@ -143,6 +143,24 @@ Required properties:
* 16 : Alternate Function 15
* 17 : Analog
To simplify the usage, macro is available to generate "pinmux" field.
This macro is available here:
- include/dt-bindings/pinctrl/stm32-pinfunc.h
Some examples of using macro:
/* GPIO A9 set as alernate function 2 */
... {
pinmux = <STM32_PINMUX('A', 9, AF2)>;
};
/* GPIO A9 set as GPIO */
... {
pinmux = <STM32_PINMUX('A', 9, GPIO)>;
};
/* GPIO A9 set as analog */
... {
pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
};
Optional properties:
- GENERIC_PINCONFIG: is the generic pinconfig options to use.
Available options are:
......@@ -165,13 +183,13 @@ pin-controller {
...
usart1_pins_a: usart1@0 {
pins1 {
pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
pinmux = <STM32_PINMUX('A', 9, AF7)>;
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
pinmux = <STM32_PINMUX('A', 10, AF7)>;
bias-disable;
};
};
......
arch/arm/boot/dts/stm32746g-eval.dts
View file @ 7d738dbb
......@@ -83,6 +83,13 @@ button@0 {
gpios = <&gpioc 13 0>;
};
};
usbotg_hs_phy: usb-phy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
clock-names = "main_clk";
};
};
&clk_hse {
......@@ -93,6 +100,14 @@ &crc {
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_pins_b>;
pinctrl-names = "default";
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
};
&rtc {
status = "okay";
};
......@@ -102,3 +117,12 @@ &usart1 {
pinctrl-names = "default";
status = "okay";
};
&usbotg_hs {
dr_mode = "host";
phys = <&usbotg_hs_phy>;
phy-names = "usb2-phy";
pinctrl-0 = <&usbotg_hs_pins_a>;
pinctrl-names = "default";
status = "okay";
};
arch/arm/boot/dts/stm32f4-pinctrl.dtsi
View file @ 7d738dbb
......@@ -40,7 +40,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include <dt-bindings/mfd/stm32f4-rcc.h>
/ {
......@@ -165,35 +165,35 @@ gpiok: gpio@40022800 {
usart1_pins_a: usart1@0 {
pins1 {
pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
bias-disable;
};
};
usart3_pins_a: usart3@0 {
pins1 {
pinmux = <STM32F429_PB10_FUNC_USART3_TX>;
pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32F429_PB11_FUNC_USART3_RX>;
pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
bias-disable;
};
};
usbotg_fs_pins_a: usbotg_fs@0 {
pins {
pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>,
<STM32F429_PA11_FUNC_OTG_FS_DM>,
<STM32F429_PA12_FUNC_OTG_FS_DP>;
pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
<STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
<STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
bias-disable;
drive-push-pull;
slew-rate = <2>;
......@@ -202,9 +202,9 @@ pins {
usbotg_fs_pins_b: usbotg_fs@1 {
pins {
pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>,
<STM32F429_PB14_FUNC_OTG_HS_DM>,
<STM32F429_PB15_FUNC_OTG_HS_DP>;
pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
<STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
<STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */
bias-disable;
drive-push-pull;
slew-rate = <2>;
......@@ -213,18 +213,18 @@ pins {
usbotg_hs_pins_a: usbotg_hs@0 {
pins {
pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
<STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
<STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
<STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
<STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
<STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
<STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
<STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
<STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
<STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
<STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
<STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/
<STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
bias-disable;
drive-push-pull;
slew-rate = <2>;
......@@ -233,49 +233,49 @@ pins {
ethernet_mii: mii@0 {
pins {
pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
<STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
<STM32F429_PC2_FUNC_ETH_MII_TXD2>,
<STM32F429_PB8_FUNC_ETH_MII_TXD3>,
<STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
<STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
<STM32F429_PA2_FUNC_ETH_MDIO>,
<STM32F429_PC1_FUNC_ETH_MDC>,
<STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
<STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
<STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
<STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
<STM32F429_PH6_FUNC_ETH_MII_RXD2>,
<STM32F429_PH7_FUNC_ETH_MII_RXD3>;
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
<STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */
<STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */
<STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */
<STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */
<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
<STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
<STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */
<STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */
<STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */
<STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */
<STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */
<STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */
slew-rate = <2>;
};
};
adc3_in8_pin: adc@200 {
pins {
pinmux = <STM32F429_PF10_FUNC_ANALOG>;
pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
};
};
pwm1_pins: pwm@1 {
pins {
pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
<STM32F429_PB13_FUNC_TIM1_CH1N>,
<STM32F429_PB12_FUNC_TIM1_BKIN>;
pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
<STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
<STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */
};
};
pwm3_pins: pwm@3 {
pins {
pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
<STM32F429_PB5_FUNC_TIM3_CH2>;
pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
<STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
};
};
i2c1_pins: i2c1@0 {
pins {
pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>,
<STM32F429_PB6_FUNC_I2C1_SCL>;
pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
<STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
bias-disable;
drive-open-drain;
slew-rate = <3>;
......@@ -284,55 +284,55 @@ pins {
ltdc_pins: ltdc@0 {
pins {
pinmux = <STM32F429_PI12_FUNC_LCD_HSYNC>,
<STM32F429_PI13_FUNC_LCD_VSYNC>,
<STM32F429_PI14_FUNC_LCD_CLK>,
<STM32F429_PI15_FUNC_LCD_R0>,
<STM32F429_PJ0_FUNC_LCD_R1>,
<STM32F429_PJ1_FUNC_LCD_R2>,
<STM32F429_PJ2_FUNC_LCD_R3>,
<STM32F429_PJ3_FUNC_LCD_R4>,
<STM32F429_PJ4_FUNC_LCD_R5>,
<STM32F429_PJ5_FUNC_LCD_R6>,
<STM32F429_PJ6_FUNC_LCD_R7>,
<STM32F429_PJ7_FUNC_LCD_G0>,
<STM32F429_PJ8_FUNC_LCD_G1>,
<STM32F429_PJ9_FUNC_LCD_G2>,
<STM32F429_PJ10_FUNC_LCD_G3>,
<STM32F429_PJ11_FUNC_LCD_G4>,
<STM32F429_PJ12_FUNC_LCD_B0>,
<STM32F429_PJ13_FUNC_LCD_B1>,
<STM32F429_PJ14_FUNC_LCD_B2>,
<STM32F429_PJ15_FUNC_LCD_B3>,
<STM32F429_PK0_FUNC_LCD_G5>,
<STM32F429_PK1_FUNC_LCD_G6>,
<STM32F429_PK2_FUNC_LCD_G7>,
<STM32F429_PK3_FUNC_LCD_B4>,
<STM32F429_PK4_FUNC_LCD_B5>,
<STM32F429_PK5_FUNC_LCD_B6>,
<STM32F429_PK6_FUNC_LCD_B7>,
<STM32F429_PK7_FUNC_LCD_DE>;
pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
<STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
<STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
<STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
<STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
<STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
<STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
<STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
<STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
<STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/
<STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
<STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
<STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
<STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
<STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
<STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
<STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
<STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
<STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
<STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/
<STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
<STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
<STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
<STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
<STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
<STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
<STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
<STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
slew-rate = <2>;
};
};
dcmi_pins: dcmi@0 {
pins {
pinmux = <STM32F429_PA4_FUNC_DCMI_HSYNC>,
<STM32F429_PB7_FUNC_DCMI_VSYNC>,
<STM32F429_PA6_FUNC_DCMI_PIXCLK>,
<STM32F429_PC6_FUNC_DCMI_D0>,
<STM32F429_PC7_FUNC_DCMI_D1>,
<STM32F429_PC8_FUNC_DCMI_D2>,
<STM32F429_PC9_FUNC_DCMI_D3>,
<STM32F429_PC11_FUNC_DCMI_D4>,
<STM32F429_PD3_FUNC_DCMI_D5>,
<STM32F429_PB8_FUNC_DCMI_D6>,
<STM32F429_PE6_FUNC_DCMI_D7>,
<STM32F429_PC10_FUNC_DCMI_D8>,
<STM32F429_PC12_FUNC_DCMI_D9>,
<STM32F429_PD6_FUNC_DCMI_D10>,
<STM32F429_PD2_FUNC_DCMI_D11>;
pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
<STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
<STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */
<STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */
<STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */
<STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */
<STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */
<STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */
<STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */
<STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */
<STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */
<STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */
<STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */
<STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */
<STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */
bias-disable;
drive-push-pull;
slew-rate = <3>;
......
arch/arm/boot/dts/stm32f746-disco.dts
View file @ 7d738dbb
......@@ -61,6 +61,20 @@ aliases {
serial0 = &usart1;
};
usbotg_hs_phy: usb-phy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
clock-names = "main_clk";
};
/* This turns on vbus for otg fs for host mode (dwc2) */
vcc5v_otg_fs: vcc5v-otg-fs-regulator {
compatible = "regulator-fixed";
gpio = <&gpiod 5 0>;
regulator-name = "vcc5_host1";
regulator-always-on;
};
};
&clk_hse {
......@@ -72,3 +86,19 @@ &usart1 {
pinctrl-names = "default";
status = "okay";
};
&usbotg_fs {
dr_mode = "host";
pinctrl-0 = <&usbotg_fs_pins_a>;
pinctrl-names = "default";
status = "okay";
};
&usbotg_hs {
dr_mode = "host";
phys = <&usbotg_hs_phy>;
phy-names = "usb2-phy";
pinctrl-0 = <&usbotg_hs_pins_b>;
pinctrl-names = "default";
status = "okay";
};
arch/arm/boot/dts/stm32f746.dtsi
View file @ 7d738dbb
This diff is collapsed.
arch/arm/boot/dts/stm32h743-pinctrl.dtsi
View file @ 7d738dbb
......@@ -40,7 +40,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/pinctrl/stm32h7-pinfunc.h>
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
/ {
soc {
......@@ -55,7 +55,7 @@ gpioa: gpio@58020000 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x0 0x400>;
clocks = <&timer_clk>;
clocks = <&rcc GPIOA_CK>;
st,bank-name = "GPIOA";
};
......@@ -63,7 +63,7 @@ gpiob: gpio@58020400 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x400 0x400>;
clocks = <&timer_clk>;
clocks = <&rcc GPIOB_CK>;
st,bank-name = "GPIOB";
};
......@@ -71,7 +71,7 @@ gpioc: gpio@58020800 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x800 0x400>;
clocks = <&timer_clk>;
clocks = <&rcc GPIOC_CK>;
st,bank-name = "GPIOC";
};
......@@ -79,7 +79,7 @@ gpiod: gpio@58020c00 {
gpio-controller;
#gpio-cells = <2>;
reg = <0xc00 0x400>;
clocks = <&timer_clk>;
clocks = <&rcc GPIOD_CK>;
st,bank-name = "GPIOD";
};
......@@ -87,7 +87,7 @@ gpioe: gpio@58021000 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x1000 0x400>;
clocks = <&timer_clk>;
clocks = <&rcc GPIOE_CK>;
st,bank-name = "GPIOE";
};
......@@ -95,7 +95,7 @@ gpiof: gpio@58021400 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x1400 0x400>;
clocks = <&timer_clk>;
clocks = <&rcc GPIOF_CK>;
st,bank-name = "GPIOF";
};
......@@ -103,7 +103,7 @@ gpiog: gpio@58021800 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x1800 0x400>;
clocks = <&timer_clk>;
clocks = <&rcc GPIOG_CK>;
st,bank-name = "GPIOG";
};
......@@ -111,7 +111,7 @@ gpioh: gpio@58021c00 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x1c00 0x400>;
clocks = <&timer_clk>;
clocks = <&rcc GPIOH_CK>;
st,bank-name = "GPIOH";
};
......@@ -119,7 +119,7 @@ gpioi: gpio@58022000 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x2000 0x400>;
clocks = <&timer_clk>;
clocks = <&rcc GPIOI_CK>;
st,bank-name = "GPIOI";
};
......@@ -127,7 +127,7 @@ gpioj: gpio@58022400 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x2400 0x400>;
clocks = <&timer_clk>;
clocks = <&rcc GPIOJ_CK>;
st,bank-name = "GPIOJ";
};
......@@ -135,32 +135,32 @@ gpiok: gpio@58022800 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x2800 0x400>;
clocks = <&timer_clk>;
clocks = <&rcc GPIOK_CK>;
st,bank-name = "GPIOK";
};
usart1_pins: usart1@0 {
pins1 {
pinmux = <STM32H7_PB14_FUNC_USART1_TX>;
pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32H7_PB15_FUNC_USART1_RX>;
pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
bias-disable;
};
};
usart2_pins: usart2@0 {
pins1 {
pinmux = <STM32H7_PD5_FUNC_USART2_TX>;
pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32H7_PD6_FUNC_USART2_RX>;
pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
bias-disable;
};
};
......
arch/arm/boot/dts/stm32h743.dtsi
View file @ 7d738dbb
......@@ -42,6 +42,8 @@
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include <dt-bindings/clock/stm32h7-clks.h>
#include <dt-bindings/mfd/stm32h7-rcc.h>
/ {
clocks {
......@@ -51,10 +53,16 @@ clk_hse: clk-hse {
clock-frequency = <0>;
};
timer_clk: timer-clk {
clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-frequency = <32768>;
};
clk_i2s: i2s_ckin {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
};
......@@ -63,7 +71,33 @@ timer5: timer@40000c00 {
compatible = "st,stm32-timer";
reg = <0x40000c00 0x400>;
interrupts = <50>;
clocks = <&timer_clk>;
clocks = <&rcc TIM5_CK>;
};
lptimer1: timer@40002400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x40002400 0x400>;
clocks = <&rcc LPTIM1_CK>;
clock-names = "mux";
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
status = "disabled";
};
trigger@0 {
compatible = "st,stm32-lptimer-trigger";
reg = <0>;
status = "disabled";
};
counter {
compatible = "st,stm32-lptimer-counter";
status = "disabled";
};
};
usart2: serial@40004400 {
......@@ -71,13 +105,13 @@ usart2: serial@40004400 {
reg = <0x40004400 0x400>;
interrupts = <38>;
status = "disabled";
clocks = <&timer_clk>;
clocks = <&rcc USART2_CK>;
};
dac: dac@40007400 {
compatible = "st,stm32h7-dac-core";
reg = <0x40007400 0x400>;
clocks = <&timer_clk>;
clocks = <&rcc DAC12_CK>;
clock-names = "pclk";
#address-cells = <1>;
#size-cells = <0>;
......@@ -103,8 +137,7 @@ usart1: serial@40011000 {
reg = <0x40011000 0x400>;
interrupts = <37>;
status = "disabled";
clocks = <&timer_clk>;
clocks = <&rcc USART1_CK>;
};
dma1: dma@40020000 {
......@@ -118,9 +151,10 @@ dma1: dma@40020000 {
<16>,
<17>,
<47>;
clocks = <&timer_clk>;
clocks = <&rcc DMA1_CK>;
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
status = "disabled";
};
......@@ -135,17 +169,28 @@ dma2: dma@40020400 {
<68>,
<69>,
<70>;
clocks = <&timer_clk>;
clocks = <&rcc DMA2_CK>;
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
status = "disabled";
};
dmamux1: dma-router@40020800 {
compatible = "st,stm32h7-dmamux";
reg = <0x40020800 0x1c>;
#dma-cells = <3>;
dma-channels = <16>;
dma-requests = <128>;
dma-masters = <&dma1 &dma2>;
clocks = <&rcc DMA1_CK>;
};
adc_12: adc@40022000 {
compatible = "st,stm32h7-adc-core";
reg = <0x40022000 0x400>;
interrupts = <18>;
clocks = <&timer_clk>;
clocks = <&rcc ADC12_CK>;
clock-names = "bus";
interrupt-controller;
#interrupt-cells = <1>;
......@@ -172,11 +217,121 @@ adc2: adc@100 {
};
};
mdma1: dma@52000000 {
compatible = "st,stm32h7-mdma";
reg = <0x52000000 0x1000>;
interrupts = <122>;
clocks = <&rcc MDMA_CK>;
#dma-cells = <5>;
dma-channels = <16>;
dma-requests = <32>;
};
lptimer2: timer@58002400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x58002400 0x400>;
clocks = <&rcc LPTIM2_CK>;
clock-names = "mux";
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
status = "disabled";
};
trigger@1 {
compatible = "st,stm32-lptimer-trigger";
reg = <1>;
status = "disabled";
};
counter {
compatible = "st,stm32-lptimer-counter";
status = "disabled";
};
};
lptimer3: timer@58002800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x58002800 0x400>;
clocks = <&rcc LPTIM3_CK>;
clock-names = "mux";
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
status = "disabled";
};
trigger@2 {
compatible = "st,stm32-lptimer-trigger";
reg = <2>;
status = "disabled";
};
};
lptimer4: timer@58002c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x58002c00 0x400>;
clocks = <&rcc LPTIM4_CK>;
clock-names = "mux";
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
status = "disabled";
};
};
lptimer5: timer@58003000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x58003000 0x400>;
clocks = <&rcc LPTIM5_CK>;
clock-names = "mux";
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
status = "disabled";
};
};
vrefbuf: regulator@58003C00 {
compatible = "st,stm32-vrefbuf";
reg = <0x58003C00 0x8>;
clocks = <&rcc VREF_CK>;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2500000>;
status = "disabled";
};
rcc: reset-clock-controller@58024400 {
compatible = "st,stm32h743-rcc", "st,stm32-rcc";
reg = <0x58024400 0x400>;
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
st,syscfg = <&pwrcfg>;
};
pwrcfg: power-config@58024800 {
compatible = "syscon";
reg = <0x58024800 0x400>;
};
adc_3: adc@58026000 {
compatible = "st,stm32h7-adc-core";
reg = <0x58026000 0x400>;
interrupts = <127>;
clocks = <&timer_clk>;
clocks = <&rcc ADC3_CK>;
clock-names = "bus";
interrupt-controller;
#interrupt-cells = <1>;
......
arch/arm/boot/dts/stm32h743i-eval.dts
View file @ 7d738dbb
......@@ -81,7 +81,7 @@ adc1: adc@0 {
};
&clk_hse {
clock-frequency = <125000000>;
clock-frequency = <25000000>;
};
&usart1 {
......
include/dt-bindings/pinctrl/stm32-pinfunc.h 0 → 100644
View file @ 7d738dbb
#ifndef _DT_BINDINGS_STM32_PINFUNC_H
#define _DT_BINDINGS_STM32_PINFUNC_H
/* define PIN modes */
#define GPIO 0x0
#define AF0 0x1
#define AF1 0x2
#define AF2 0x3
#define AF3 0x4
#define AF4 0x5
#define AF5 0x6
#define AF6 0x7
#define AF7 0x8
#define AF8 0x9
#define AF9 0xa
#define AF10 0xb
#define AF11 0xc
#define AF12 0xd
#define AF13 0xe
#define AF14 0xf
#define AF15 0x10
#define ANALOG 0x11
/* define Pins number*/
#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line))
#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode))
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
include/dt-bindings/pinctrl/stm32f429-pinfunc.h deleted 100644 → 0
View file @ 282e1cd1
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include/dt-bindings/pinctrl/stm32f746-pinfunc.h deleted 100644 → 0
View file @ 282e1cd1
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include/dt-bindings/pinctrl/stm32h7-pinfunc.h deleted 100644 → 0
View file @ 282e1cd1
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