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Commit 7f80850d authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'rmobile-fixes-for-linus' of git://github.com/pmundt/linux-sh 

* 'rmobile-fixes-for-linus' of git://github.com/pmundt/linux-sh:
  ARM: mach-shmobile: cpuidle single/global and last_state fixes
  ARM: mach-shmobile: move helper macro PORTCR to sh_pfc.h
  ARM: mach-shmobile: move helper macro PORT_xx to sh_pfc.h
  ARM: mach-shmobile: move helper macro PORT_DATA_xx to sh_pfc.h
  ARM: mach-shmobile: ap4evb: remove white space from end of line
  ARM: mach-shmobile: clock-sh7372: remove un-necessary index
  ARM: mach-shmobile: kota2: add comment out separator
  ARM: mach-shmobile: sh73a0: add MMC data pin pull-up
parents b93cd6a0 b73b5c49
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Showing with 400 additions and 523 deletions
arch/arm/mach-shmobile/board-ag5evm.c
View file @ 7f80850d
......@@ -515,14 +515,14 @@ static void __init ag5evm_init(void)
/* enable MMCIF */
gpio_request(GPIO_FN_MMCCLK0, NULL);
gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
gpio_request(GPIO_FN_MMCD0_0, NULL);
gpio_request(GPIO_FN_MMCD0_1, NULL);
gpio_request(GPIO_FN_MMCD0_2, NULL);
gpio_request(GPIO_FN_MMCD0_3, NULL);
gpio_request(GPIO_FN_MMCD0_4, NULL);
gpio_request(GPIO_FN_MMCD0_5, NULL);
gpio_request(GPIO_FN_MMCD0_6, NULL);
gpio_request(GPIO_FN_MMCD0_7, NULL);
gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
gpio_request(GPIO_PORT208, NULL); /* Reset */
gpio_direction_output(GPIO_PORT208, 1);
......
arch/arm/mach-shmobile/board-kota2.c
View file @ 7f80850d
......@@ -48,6 +48,7 @@
#include <asm/hardware/cache-l2x0.h>
#include <asm/traps.h>
/* SMSC 9220 */
static struct resource smsc9220_resources[] = {
[0] = {
.start = 0x14000000, /* CS5A */
......@@ -77,6 +78,7 @@ static struct platform_device eth_device = {
.num_resources = ARRAY_SIZE(smsc9220_resources),
};
/* KEYSC */
static struct sh_keysc_info keysc_platdata = {
.mode = SH_KEYSC_MODE_6,
.scan_timing = 3,
......@@ -120,6 +122,7 @@ static struct platform_device keysc_device = {
},
};
/* GPIO KEY */
#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
static struct gpio_keys_button gpio_buttons[] = {
......@@ -150,6 +153,7 @@ static struct platform_device gpio_keys_device = {
},
};
/* GPIO LED */
#define GPIO_LED(n, g) { .name = n, .gpio = g }
static struct gpio_led gpio_leds[] = {
......@@ -175,6 +179,7 @@ static struct platform_device gpio_leds_device = {
},
};
/* MMCIF */
static struct resource mmcif_resources[] = {
[0] = {
.name = "MMCIF",
......@@ -207,6 +212,7 @@ static struct platform_device mmcif_device = {
.resource = mmcif_resources,
};
/* SDHI0 */
static struct sh_mobile_sdhi_info sdhi0_info = {
.tmio_caps = MMC_CAP_SD_HIGHSPEED,
.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
......@@ -243,6 +249,7 @@ static struct platform_device sdhi0_device = {
},
};
/* SDHI1 */
static struct sh_mobile_sdhi_info sdhi1_info = {
.tmio_caps = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ,
.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
......
arch/arm/mach-shmobile/clock-sh7372.c
View file @ 7f80850d
......@@ -476,7 +476,7 @@ static struct clk_ops fsidiv_clk_ops = {
.disable = fsidiv_disable,
};
static struct clk_mapping sh7372_fsidiva_clk_mapping = {
static struct clk_mapping fsidiva_clk_mapping = {
.phys = FSIDIVA,
.len = 8,
};
......@@ -484,10 +484,10 @@ static struct clk_mapping sh7372_fsidiva_clk_mapping = {
struct clk sh7372_fsidiva_clk = {
.ops = &fsidiv_clk_ops,
.parent = &div6_reparent_clks[DIV6_FSIA], /* late install */
.mapping = &sh7372_fsidiva_clk_mapping,
.mapping = &fsidiva_clk_mapping,
};
static struct clk_mapping sh7372_fsidivb_clk_mapping = {
static struct clk_mapping fsidivb_clk_mapping = {
.phys = FSIDIVB,
.len = 8,
};
......@@ -495,7 +495,7 @@ static struct clk_mapping sh7372_fsidivb_clk_mapping = {
struct clk sh7372_fsidivb_clk = {
.ops = &fsidiv_clk_ops,
.parent = &div6_reparent_clks[DIV6_FSIB], /* late install */
.mapping = &sh7372_fsidivb_clk_mapping,
.mapping = &fsidivb_clk_mapping,
};
static struct clk *late_main_clks[] = {
......
arch/arm/mach-shmobile/cpuidle.c
View file @ 7f80850d
......@@ -26,65 +26,59 @@ void (*shmobile_cpuidle_modes[CPUIDLE_STATE_MAX])(void) = {
};
static int shmobile_cpuidle_enter(struct cpuidle_device *dev,
struct cpuidle_state *state)
struct cpuidle_driver *drv,
int index)
{
ktime_t before, after;
int requested_state = state - &dev->states[0];
dev->last_state = &dev->states[requested_state];
before = ktime_get();
local_irq_disable();
local_fiq_disable();
shmobile_cpuidle_modes[requested_state]();
shmobile_cpuidle_modes[index]();
local_irq_enable();
local_fiq_enable();
after = ktime_get();
return ktime_to_ns(ktime_sub(after, before)) >> 10;
dev->last_residency = ktime_to_ns(ktime_sub(after, before)) >> 10;
return index;
}
static struct cpuidle_device shmobile_cpuidle_dev;
static struct cpuidle_driver shmobile_cpuidle_driver = {
.name = "shmobile_cpuidle",
.owner = THIS_MODULE,
.states[0] = {
.name = "C1",
.desc = "WFI",
.exit_latency = 1,
.target_residency = 1 * 2,
.flags = CPUIDLE_FLAG_TIME_VALID,
},
.safe_state_index = 0, /* C1 */
.state_count = 1,
};
void (*shmobile_cpuidle_setup)(struct cpuidle_device *dev);
void (*shmobile_cpuidle_setup)(struct cpuidle_driver *drv);
static int shmobile_cpuidle_init(void)
{
struct cpuidle_device *dev = &shmobile_cpuidle_dev;
struct cpuidle_state *state;
struct cpuidle_driver *drv = &shmobile_cpuidle_driver;
int i;
cpuidle_register_driver(&shmobile_cpuidle_driver);
for (i = 0; i < CPUIDLE_STATE_MAX; i++) {
dev->states[i].name[0] = '\0';
dev->states[i].desc[0] = '\0';
dev->states[i].enter = shmobile_cpuidle_enter;
}
i = CPUIDLE_DRIVER_STATE_START;
state = &dev->states[i++];
snprintf(state->name, CPUIDLE_NAME_LEN, "C1");
strncpy(state->desc, "WFI", CPUIDLE_DESC_LEN);
state->exit_latency = 1;
state->target_residency = 1 * 2;
state->power_usage = 3;
state->flags = 0;
state->flags |= CPUIDLE_FLAG_TIME_VALID;
dev->safe_state = state;
dev->state_count = i;
for (i = 0; i < CPUIDLE_STATE_MAX; i++)
drv->states[i].enter = shmobile_cpuidle_enter;
if (shmobile_cpuidle_setup)
shmobile_cpuidle_setup(dev);
shmobile_cpuidle_setup(drv);
cpuidle_register_driver(drv);
dev->state_count = drv->state_count;
cpuidle_register_device(dev);
return 0;
......
arch/arm/mach-shmobile/include/mach/common.h
View file @ 7f80850d
......@@ -9,9 +9,9 @@ extern int clk_init(void);
extern void shmobile_handle_irq_intc(struct pt_regs *);
extern void shmobile_handle_irq_gic(struct pt_regs *);
extern struct platform_suspend_ops shmobile_suspend_ops;
struct cpuidle_device;
struct cpuidle_driver;
extern void (*shmobile_cpuidle_modes[])(void);
extern void (*shmobile_cpuidle_setup)(struct cpuidle_device *dev);
extern void (*shmobile_cpuidle_setup)(struct cpuidle_driver *drv);
extern void sh7367_init_irq(void);
extern void sh7367_add_early_devices(void);
......
arch/arm/mach-shmobile/include/mach/sh73a0.h
View file @ 7f80850d
......@@ -470,6 +470,14 @@ enum {
GPIO_FN_SDHICMD2_PU,
GPIO_FN_MMCCMD0_PU,
GPIO_FN_MMCCMD1_PU,
GPIO_FN_MMCD0_0_PU,
GPIO_FN_MMCD0_1_PU,
GPIO_FN_MMCD0_2_PU,
GPIO_FN_MMCD0_3_PU,
GPIO_FN_MMCD0_4_PU,
GPIO_FN_MMCD0_5_PU,
GPIO_FN_MMCD0_6_PU,
GPIO_FN_MMCD0_7_PU,
GPIO_FN_FSIACK_PU,
GPIO_FN_FSIAILR_PU,
GPIO_FN_FSIAIBT_PU,
......
arch/arm/mach-shmobile/pfc-sh7367.c
View file @ 7f80850d
......@@ -21,68 +21,49 @@
#include <linux/gpio.h>
#include <mach/sh7367.h>
#define _1(fn, pfx, sfx) fn(pfx, sfx)
#define _10(fn, pfx, sfx) \
_1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \
_1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \
_1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \
_1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \
_1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx)
#define _90(fn, pfx, sfx) \
_10(fn, pfx##1, sfx), _10(fn, pfx##2, sfx), \
_10(fn, pfx##3, sfx), _10(fn, pfx##4, sfx), \
_10(fn, pfx##5, sfx), _10(fn, pfx##6, sfx), \
_10(fn, pfx##7, sfx), _10(fn, pfx##8, sfx), \
_10(fn, pfx##9, sfx)
#define _273(fn, pfx, sfx) \
_10(fn, pfx, sfx), _90(fn, pfx, sfx), \
_10(fn, pfx##10, sfx), _90(fn, pfx##1, sfx), \
_10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx), \
_10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx), \
_10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx), \
_10(fn, pfx##26, sfx), _1(fn, pfx##270, sfx), \
_1(fn, pfx##271, sfx), _1(fn, pfx##272, sfx)
#define _PORT(pfx, sfx) pfx##_##sfx
#define PORT_273(str) _273(_PORT, PORT, str)
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
PORT_10(fn, pfx##26, sfx), PORT_1(fn, pfx##270, sfx), \
PORT_1(fn, pfx##271, sfx), PORT_1(fn, pfx##272, sfx)
enum {
PINMUX_RESERVED = 0,
PINMUX_DATA_BEGIN,
PORT_273(DATA), /* PORT0_DATA -> PORT272_DATA */
PORT_ALL(DATA), /* PORT0_DATA -> PORT272_DATA */
PINMUX_DATA_END,
PINMUX_INPUT_BEGIN,
PORT_273(IN), /* PORT0_IN -> PORT272_IN */
PORT_ALL(IN), /* PORT0_IN -> PORT272_IN */
PINMUX_INPUT_END,
PINMUX_INPUT_PULLUP_BEGIN,
PORT_273(IN_PU), /* PORT0_IN_PU -> PORT272_IN_PU */
PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT272_IN_PU */
PINMUX_INPUT_PULLUP_END,
PINMUX_INPUT_PULLDOWN_BEGIN,
PORT_273(IN_PD), /* PORT0_IN_PD -> PORT272_IN_PD */
PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT272_IN_PD */
PINMUX_INPUT_PULLDOWN_END,
PINMUX_OUTPUT_BEGIN,
PORT_273(OUT), /* PORT0_OUT -> PORT272_OUT */
PORT_ALL(OUT), /* PORT0_OUT -> PORT272_OUT */
PINMUX_OUTPUT_END,
PINMUX_FUNCTION_BEGIN,
PORT_273(FN_IN), /* PORT0_FN_IN -> PORT272_FN_IN */
PORT_273(FN_OUT), /* PORT0_FN_OUT -> PORT272_FN_OUT */
PORT_273(FN0), /* PORT0_FN0 -> PORT272_FN0 */
PORT_273(FN1), /* PORT0_FN1 -> PORT272_FN1 */
PORT_273(FN2), /* PORT0_FN2 -> PORT272_FN2 */
PORT_273(FN3), /* PORT0_FN3 -> PORT272_FN3 */
PORT_273(FN4), /* PORT0_FN4 -> PORT272_FN4 */
PORT_273(FN5), /* PORT0_FN5 -> PORT272_FN5 */
PORT_273(FN6), /* PORT0_FN6 -> PORT272_FN6 */
PORT_273(FN7), /* PORT0_FN7 -> PORT272_FN7 */
PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT272_FN_IN */
PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT272_FN_OUT */
PORT_ALL(FN0), /* PORT0_FN0 -> PORT272_FN0 */
PORT_ALL(FN1), /* PORT0_FN1 -> PORT272_FN1 */
PORT_ALL(FN2), /* PORT0_FN2 -> PORT272_FN2 */
PORT_ALL(FN3), /* PORT0_FN3 -> PORT272_FN3 */
PORT_ALL(FN4), /* PORT0_FN4 -> PORT272_FN4 */
PORT_ALL(FN5), /* PORT0_FN5 -> PORT272_FN5 */
PORT_ALL(FN6), /* PORT0_FN6 -> PORT272_FN6 */
PORT_ALL(FN7), /* PORT0_FN7 -> PORT272_FN7 */
MSELBCR_MSEL2_1, MSELBCR_MSEL2_0,
PINMUX_FUNCTION_END,
......@@ -327,41 +308,6 @@ enum {
PINMUX_MARK_END,
};
#define PORT_DATA_I(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
#define PORT_DATA_I_PD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_IN, PORT##nr##_IN_PD)
#define PORT_DATA_I_PU(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_IN, PORT##nr##_IN_PU)
#define PORT_DATA_I_PU_PD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
#define PORT_DATA_O(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
#define PORT_DATA_IO(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
PORT##nr##_IN)
#define PORT_DATA_IO_PD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
PORT##nr##_IN, PORT##nr##_IN_PD)
#define PORT_DATA_IO_PU(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
PORT##nr##_IN, PORT##nr##_IN_PU)
#define PORT_DATA_IO_PU_PD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
static pinmux_enum_t pinmux_data[] = {
/* specify valid pin states for each pin in GPIO mode */
......@@ -1098,13 +1044,9 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(DIVLOCK_MARK, PORT272_FN1),
};
#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
#define GPIO_PORT_273() _273(_GPIO_PORT, , unused)
#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
static struct pinmux_gpio pinmux_gpios[] = {
/* 49-1 -> 49-6 (GPIO) */
GPIO_PORT_273(),
GPIO_PORT_ALL(),
/* Special Pull-up / Pull-down Functions */
GPIO_FN(PORT48_KEYIN0_PU), GPIO_FN(PORT49_KEYIN1_PU),
......@@ -1345,22 +1287,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(DIVLOCK),
};
/* helper for top 4 bits in PORTnCR */
#define PCRH(in, in_pd, in_pu, out) \
0, (out), (in), 0, \
0, 0, 0, 0, \
0, 0, (in_pd), 0, \
0, 0, (in_pu), 0
#define PORTCR(nr, reg) \
{ PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \
PORT##nr##_IN_PU, PORT##nr##_OUT), \
PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \
PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \
PORT##nr##_FN6, PORT##nr##_FN7 } \
}
static struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(0, 0xe6050000), /* PORT0CR */
PORTCR(1, 0xe6050001), /* PORT1CR */
......
arch/arm/mach-shmobile/pfc-sh7372.c
View file @ 7f80850d
......@@ -25,27 +25,13 @@
#include <linux/gpio.h>
#include <mach/sh7372.h>
#define _1(fn, pfx, sfx) fn(pfx, sfx)
#define _10(fn, pfx, sfx) \
_1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \
_1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \
_1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \
_1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \
_1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx)
#define _80(fn, pfx, sfx) \
_10(fn, pfx##1, sfx), _10(fn, pfx##2, sfx), \
_10(fn, pfx##3, sfx), _10(fn, pfx##4, sfx), \
_10(fn, pfx##5, sfx), _10(fn, pfx##6, sfx), \
_10(fn, pfx##7, sfx), _10(fn, pfx##8, sfx)
#define _190(fn, pfx, sfx) \
_10(fn, pfx, sfx), _80(fn, pfx, sfx), _10(fn, pfx##9, sfx), \
_10(fn, pfx##10, sfx), _80(fn, pfx##1, sfx), _1(fn, pfx##190, sfx)
#define _PORT(pfx, sfx) pfx##_##sfx
#define PORT_ALL(str) _190(_PORT, PORT, str)
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
PORT_10(fn, pfx##10, sfx), PORT_10(fn, pfx##11, sfx), \
PORT_10(fn, pfx##12, sfx), PORT_10(fn, pfx##13, sfx), \
PORT_10(fn, pfx##14, sfx), PORT_10(fn, pfx##15, sfx), \
PORT_10(fn, pfx##16, sfx), PORT_10(fn, pfx##17, sfx), \
PORT_10(fn, pfx##18, sfx), PORT_1(fn, pfx##190, sfx)
enum {
PINMUX_RESERVED = 0,
......@@ -381,108 +367,124 @@ enum {
PINMUX_MARK_END,
};
/* PORT_DATA_I_PD(nr) */
#define _I___D(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_IN, PORT##nr##_IN_PD)
/* PORT_DATA_I_PU(nr) */
#define _I__U_(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_IN, PORT##nr##_IN_PU)
/* PORT_DATA_I_PU_PD(nr) */
#define _I__UD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
/* PORT_DATA_O(nr) */
#define __O___(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
/* PORT_DATA_IO(nr) */
#define _IO___(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
PORT##nr##_IN)
/* PORT_DATA_IO_PD(nr) */
#define _IO__D(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
PORT##nr##_IN, PORT##nr##_IN_PD)
/* PORT_DATA_IO_PU(nr) */
#define _IO_U_(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
PORT##nr##_IN, PORT##nr##_IN_PU)
/* PORT_DATA_IO_PU_PD(nr) */
#define _IO_UD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
static pinmux_enum_t pinmux_data[] = {
/* specify valid pin states for each pin in GPIO mode */
_IO__D(0), _IO__D(1), __O___(2), _I___D(3), _I___D(4),
_I___D(5), _IO_UD(6), _I___D(7), _IO__D(8), __O___(9),
__O___(10), __O___(11), _IO_UD(12), _IO__D(13), _IO__D(14),
__O___(15), _IO__D(16), _IO__D(17), _I___D(18), _IO___(19),
_IO___(20), _IO___(21), _IO___(22), _IO___(23), _IO___(24),
_IO___(25), _IO___(26), _IO___(27), _IO___(28), _IO___(29),
_IO___(30), _IO___(31), _IO___(32), _IO___(33), _IO___(34),
_IO___(35), _IO___(36), _IO___(37), _IO___(38), _IO___(39),
_IO___(40), _IO___(41), _IO___(42), _IO___(43), _IO___(44),
_IO___(45), _IO_U_(46), _IO_U_(47), _IO_U_(48), _IO_U_(49),
_IO_U_(50), _IO_U_(51), _IO_U_(52), _IO_U_(53), _IO_U_(54),
_IO_U_(55), _IO_U_(56), _IO_U_(57), _IO_U_(58), _IO_U_(59),
_IO_U_(60), _IO_U_(61), _IO___(62), __O___(63), __O___(64),
_IO_U_(65), __O___(66), _IO_U_(67), __O___(68), _IO___(69), /*66?*/
_IO___(70), _IO___(71), __O___(72), _I__U_(73), _I__UD(74),
_IO_UD(75), _IO_UD(76), _IO_UD(77), _IO_UD(78), _IO_UD(79),
_IO_UD(80), _IO_UD(81), _IO_UD(82), _IO_UD(83), _IO_UD(84),
_IO_UD(85), _IO_UD(86), _IO_UD(87), _IO_UD(88), _IO_UD(89),
_IO_UD(90), _IO_UD(91), _IO_UD(92), _IO_UD(93), _IO_UD(94),
_IO_UD(95), _IO_U_(96), _IO_UD(97), _IO_UD(98), __O___(99), /*99?*/
_IO__D(100), _IO__D(101), _IO__D(102), _IO__D(103), _IO__D(104),
_IO__D(105), _IO_U_(106), _IO_U_(107), _IO_U_(108), _IO_U_(109),
_IO_U_(110), _IO_U_(111), _IO__D(112), _IO__D(113), _IO_U_(114),
_IO_U_(115), _IO_U_(116), _IO_U_(117), _IO_U_(118), _IO_U_(119),
_IO_U_(120), _IO__D(121), _IO__D(122), _IO__D(123), _IO__D(124),
_IO__D(125), _IO__D(126), _IO__D(127), _IO__D(128), _IO_UD(129),
_IO_UD(130), _IO_UD(131), _IO_UD(132), _IO_UD(133), _IO_UD(134),
_IO_UD(135), _IO__D(136), _IO__D(137), _IO__D(138), _IO__D(139),
_IO__D(140), _IO__D(141), _IO__D(142), _IO_UD(143), _IO__D(144),
_IO__D(145), _IO__D(146), _IO__D(147), _IO__D(148), _IO__D(149),
_IO__D(150), _IO__D(151), _IO_UD(152), _I___D(153), _IO_UD(154),
_I___D(155), _IO__D(156), _IO__D(157), _I___D(158), _IO__D(159),
__O___(160), _IO__D(161), _IO__D(162), _IO__D(163), _I___D(164),
_IO__D(165), _I___D(166), _I___D(167), _I___D(168), _I___D(169),
_I___D(170), __O___(171), _IO_UD(172), _IO_UD(173), _IO_UD(174),
_IO_UD(175), _IO_UD(176), _IO_UD(177), _IO_UD(178), __O___(179),
_IO_UD(180), _IO_UD(181), _IO_UD(182), _IO_UD(183), _IO_UD(184),
__O___(185), _IO_UD(186), _IO_UD(187), _IO_UD(188), _IO_UD(189),
_IO_UD(190),
PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
PORT_DATA_O(2), PORT_DATA_I_PD(3),
PORT_DATA_I_PD(4), PORT_DATA_I_PD(5),
PORT_DATA_IO_PU_PD(6), PORT_DATA_I_PD(7),
PORT_DATA_IO_PD(8), PORT_DATA_O(9),
PORT_DATA_O(10), PORT_DATA_O(11),
PORT_DATA_IO_PU_PD(12), PORT_DATA_IO_PD(13),
PORT_DATA_IO_PD(14), PORT_DATA_O(15),
PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17),
PORT_DATA_I_PD(18), PORT_DATA_IO(19),
PORT_DATA_IO(20), PORT_DATA_IO(21),
PORT_DATA_IO(22), PORT_DATA_IO(23),
PORT_DATA_IO(24), PORT_DATA_IO(25),
PORT_DATA_IO(26), PORT_DATA_IO(27),
PORT_DATA_IO(28), PORT_DATA_IO(29),
PORT_DATA_IO(30), PORT_DATA_IO(31),
PORT_DATA_IO(32), PORT_DATA_IO(33),
PORT_DATA_IO(34), PORT_DATA_IO(35),
PORT_DATA_IO(36), PORT_DATA_IO(37),
PORT_DATA_IO(38), PORT_DATA_IO(39),
PORT_DATA_IO(40), PORT_DATA_IO(41),
PORT_DATA_IO(42), PORT_DATA_IO(43),
PORT_DATA_IO(44), PORT_DATA_IO(45),
PORT_DATA_IO_PU(46), PORT_DATA_IO_PU(47),
PORT_DATA_IO_PU(48), PORT_DATA_IO_PU(49),
PORT_DATA_IO_PU(50), PORT_DATA_IO_PU(51),
PORT_DATA_IO_PU(52), PORT_DATA_IO_PU(53),
PORT_DATA_IO_PU(54), PORT_DATA_IO_PU(55),
PORT_DATA_IO_PU(56), PORT_DATA_IO_PU(57),
PORT_DATA_IO_PU(58), PORT_DATA_IO_PU(59),
PORT_DATA_IO_PU(60), PORT_DATA_IO_PU(61),
PORT_DATA_IO(62), PORT_DATA_O(63),
PORT_DATA_O(64), PORT_DATA_IO_PU(65),
PORT_DATA_O(66), PORT_DATA_IO_PU(67), /*66?*/
PORT_DATA_O(68), PORT_DATA_IO(69),
PORT_DATA_IO(70), PORT_DATA_IO(71),
PORT_DATA_O(72), PORT_DATA_I_PU(73),
PORT_DATA_I_PU_PD(74), PORT_DATA_IO_PU_PD(75),
PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
PORT_DATA_IO_PU_PD(82), PORT_DATA_IO_PU_PD(83),
PORT_DATA_IO_PU_PD(84), PORT_DATA_IO_PU_PD(85),
PORT_DATA_IO_PU_PD(86), PORT_DATA_IO_PU_PD(87),
PORT_DATA_IO_PU_PD(88), PORT_DATA_IO_PU_PD(89),
PORT_DATA_IO_PU_PD(90), PORT_DATA_IO_PU_PD(91),
PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93),
PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95),
PORT_DATA_IO_PU(96), PORT_DATA_IO_PU_PD(97),
PORT_DATA_IO_PU_PD(98), PORT_DATA_O(99), /*99?*/
PORT_DATA_IO_PD(100), PORT_DATA_IO_PD(101),
PORT_DATA_IO_PD(102), PORT_DATA_IO_PD(103),
PORT_DATA_IO_PD(104), PORT_DATA_IO_PD(105),
PORT_DATA_IO_PU(106), PORT_DATA_IO_PU(107),
PORT_DATA_IO_PU(108), PORT_DATA_IO_PU(109),
PORT_DATA_IO_PU(110), PORT_DATA_IO_PU(111),
PORT_DATA_IO_PD(112), PORT_DATA_IO_PD(113),
PORT_DATA_IO_PU(114), PORT_DATA_IO_PU(115),
PORT_DATA_IO_PU(116), PORT_DATA_IO_PU(117),
PORT_DATA_IO_PU(118), PORT_DATA_IO_PU(119),
PORT_DATA_IO_PU(120), PORT_DATA_IO_PD(121),
PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123),
PORT_DATA_IO_PD(124), PORT_DATA_IO_PD(125),
PORT_DATA_IO_PD(126), PORT_DATA_IO_PD(127),
PORT_DATA_IO_PD(128), PORT_DATA_IO_PU_PD(129),
PORT_DATA_IO_PU_PD(130), PORT_DATA_IO_PU_PD(131),
PORT_DATA_IO_PU_PD(132), PORT_DATA_IO_PU_PD(133),
PORT_DATA_IO_PU_PD(134), PORT_DATA_IO_PU_PD(135),
PORT_DATA_IO_PD(136), PORT_DATA_IO_PD(137),
PORT_DATA_IO_PD(138), PORT_DATA_IO_PD(139),
PORT_DATA_IO_PD(140), PORT_DATA_IO_PD(141),
PORT_DATA_IO_PD(142), PORT_DATA_IO_PU_PD(143),
PORT_DATA_IO_PD(144), PORT_DATA_IO_PD(145),
PORT_DATA_IO_PD(146), PORT_DATA_IO_PD(147),
PORT_DATA_IO_PD(148), PORT_DATA_IO_PD(149),
PORT_DATA_IO_PD(150), PORT_DATA_IO_PD(151),
PORT_DATA_IO_PU_PD(152), PORT_DATA_I_PD(153),
PORT_DATA_IO_PU_PD(154), PORT_DATA_I_PD(155),
PORT_DATA_IO_PD(156), PORT_DATA_IO_PD(157),
PORT_DATA_I_PD(158), PORT_DATA_IO_PD(159),
PORT_DATA_O(160), PORT_DATA_IO_PD(161),
PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163),
PORT_DATA_I_PD(164), PORT_DATA_IO_PD(165),
PORT_DATA_I_PD(166), PORT_DATA_I_PD(167),
PORT_DATA_I_PD(168), PORT_DATA_I_PD(169),
PORT_DATA_I_PD(170), PORT_DATA_O(171),
PORT_DATA_IO_PU_PD(172), PORT_DATA_IO_PU_PD(173),
PORT_DATA_IO_PU_PD(174), PORT_DATA_IO_PU_PD(175),
PORT_DATA_IO_PU_PD(176), PORT_DATA_IO_PU_PD(177),
PORT_DATA_IO_PU_PD(178), PORT_DATA_O(179),
PORT_DATA_IO_PU_PD(180), PORT_DATA_IO_PU_PD(181),
PORT_DATA_IO_PU_PD(182), PORT_DATA_IO_PU_PD(183),
PORT_DATA_IO_PU_PD(184), PORT_DATA_O(185),
PORT_DATA_IO_PU_PD(186), PORT_DATA_IO_PU_PD(187),
PORT_DATA_IO_PU_PD(188), PORT_DATA_IO_PU_PD(189),
PORT_DATA_IO_PU_PD(190),
/* IRQ */
PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0),
......@@ -926,10 +928,6 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1),
};
#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
#define GPIO_PORT_ALL() _190(_GPIO_PORT, , unused)
#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
static struct pinmux_gpio pinmux_gpios[] = {
/* PORT */
......@@ -1201,22 +1199,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(SDENC_DV_CLKI),
};
/* helper for top 4 bits in PORTnCR */
#define PCRH(in, in_pd, in_pu, out) \
0, (out), (in), 0, \
0, 0, 0, 0, \
0, 0, (in_pd), 0, \
0, 0, (in_pu), 0
#define PORTCR(nr, reg) \
{ PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \
PORT##nr##_IN_PU, PORT##nr##_OUT), \
PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \
PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \
PORT##nr##_FN6, PORT##nr##_FN7 } \
}
static struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(0, 0xE6051000), /* PORT0CR */
PORTCR(1, 0xE6051001), /* PORT1CR */
......
arch/arm/mach-shmobile/pfc-sh7377.c
View file @ 7f80850d
......@@ -22,84 +22,65 @@
#include <linux/gpio.h>
#include <mach/sh7377.h>
#define _1(fn, pfx, sfx) fn(pfx, sfx)
#define _10(fn, pfx, sfx) \
_1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \
_1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \
_1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \
_1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \
_1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx)
#define _90(fn, pfx, sfx) \
_10(fn, pfx##1, sfx), _10(fn, pfx##2, sfx), \
_10(fn, pfx##3, sfx), _10(fn, pfx##4, sfx), \
_10(fn, pfx##5, sfx), _10(fn, pfx##6, sfx), \
_10(fn, pfx##7, sfx), _10(fn, pfx##8, sfx), \
_10(fn, pfx##9, sfx)
#define _265(fn, pfx, sfx) \
_10(fn, pfx, sfx), _90(fn, pfx, sfx), \
_10(fn, pfx##10, sfx), \
_1(fn, pfx##110, sfx), _1(fn, pfx##111, sfx), \
_1(fn, pfx##112, sfx), _1(fn, pfx##113, sfx), \
_1(fn, pfx##114, sfx), _1(fn, pfx##115, sfx), \
_1(fn, pfx##116, sfx), _1(fn, pfx##117, sfx), \
_1(fn, pfx##118, sfx), \
_1(fn, pfx##128, sfx), _1(fn, pfx##129, sfx), \
_10(fn, pfx##13, sfx), _10(fn, pfx##14, sfx), \
_10(fn, pfx##15, sfx), \
_1(fn, pfx##160, sfx), _1(fn, pfx##161, sfx), \
_1(fn, pfx##162, sfx), _1(fn, pfx##163, sfx), \
_1(fn, pfx##164, sfx), \
_1(fn, pfx##192, sfx), _1(fn, pfx##193, sfx), \
_1(fn, pfx##194, sfx), _1(fn, pfx##195, sfx), \
_1(fn, pfx##196, sfx), _1(fn, pfx##197, sfx), \
_1(fn, pfx##198, sfx), _1(fn, pfx##199, sfx), \
_10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx), \
_10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx), \
_10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx), \
_1(fn, pfx##260, sfx), _1(fn, pfx##261, sfx), \
_1(fn, pfx##262, sfx), _1(fn, pfx##263, sfx), \
_1(fn, pfx##264, sfx)
#define _PORT(pfx, sfx) pfx##_##sfx
#define PORT_265(str) _265(_PORT, PORT, str)
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
PORT_10(fn, pfx##10, sfx), \
PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \
PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \
PORT_1(fn, pfx##118, sfx), \
PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \
PORT_10(fn, pfx##15, sfx), \
PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \
PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \
PORT_1(fn, pfx##164, sfx), \
PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
PORT_1(fn, pfx##260, sfx), PORT_1(fn, pfx##261, sfx), \
PORT_1(fn, pfx##262, sfx), PORT_1(fn, pfx##263, sfx), \
PORT_1(fn, pfx##264, sfx)
enum {
PINMUX_RESERVED = 0,
PINMUX_DATA_BEGIN,
PORT_265(DATA), /* PORT0_DATA -> PORT264_DATA */
PORT_ALL(DATA), /* PORT0_DATA -> PORT264_DATA */
PINMUX_DATA_END,
PINMUX_INPUT_BEGIN,
PORT_265(IN), /* PORT0_IN -> PORT264_IN */
PORT_ALL(IN), /* PORT0_IN -> PORT264_IN */
PINMUX_INPUT_END,
PINMUX_INPUT_PULLUP_BEGIN,
PORT_265(IN_PU), /* PORT0_IN_PU -> PORT264_IN_PU */
PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT264_IN_PU */
PINMUX_INPUT_PULLUP_END,
PINMUX_INPUT_PULLDOWN_BEGIN,
PORT_265(IN_PD), /* PORT0_IN_PD -> PORT264_IN_PD */
PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT264_IN_PD */
PINMUX_INPUT_PULLDOWN_END,
PINMUX_OUTPUT_BEGIN,
PORT_265(OUT), /* PORT0_OUT -> PORT264_OUT */
PORT_ALL(OUT), /* PORT0_OUT -> PORT264_OUT */
PINMUX_OUTPUT_END,
PINMUX_FUNCTION_BEGIN,
PORT_265(FN_IN), /* PORT0_FN_IN -> PORT264_FN_IN */
PORT_265(FN_OUT), /* PORT0_FN_OUT -> PORT264_FN_OUT */
PORT_265(FN0), /* PORT0_FN0 -> PORT264_FN0 */
PORT_265(FN1), /* PORT0_FN1 -> PORT264_FN1 */
PORT_265(FN2), /* PORT0_FN2 -> PORT264_FN2 */
PORT_265(FN3), /* PORT0_FN3 -> PORT264_FN3 */
PORT_265(FN4), /* PORT0_FN4 -> PORT264_FN4 */
PORT_265(FN5), /* PORT0_FN5 -> PORT264_FN5 */
PORT_265(FN6), /* PORT0_FN6 -> PORT264_FN6 */
PORT_265(FN7), /* PORT0_FN7 -> PORT264_FN7 */
PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT264_FN_IN */
PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT264_FN_OUT */
PORT_ALL(FN0), /* PORT0_FN0 -> PORT264_FN0 */
PORT_ALL(FN1), /* PORT0_FN1 -> PORT264_FN1 */
PORT_ALL(FN2), /* PORT0_FN2 -> PORT264_FN2 */
PORT_ALL(FN3), /* PORT0_FN3 -> PORT264_FN3 */
PORT_ALL(FN4), /* PORT0_FN4 -> PORT264_FN4 */
PORT_ALL(FN5), /* PORT0_FN5 -> PORT264_FN5 */
PORT_ALL(FN6), /* PORT0_FN6 -> PORT264_FN6 */
PORT_ALL(FN7), /* PORT0_FN7 -> PORT264_FN7 */
MSELBCR_MSEL17_1, MSELBCR_MSEL17_0,
MSELBCR_MSEL16_1, MSELBCR_MSEL16_0,
......@@ -360,45 +341,6 @@ enum {
PINMUX_MARK_END,
};
#define PORT_DATA_I(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
#define PORT_DATA_I_PD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_IN, PORT##nr##_IN_PD)
#define PORT_DATA_I_PU(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_IN, PORT##nr##_IN_PU)
#define PORT_DATA_I_PU_PD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_IN, PORT##nr##_IN_PD, \
PORT##nr##_IN_PU)
#define PORT_DATA_O(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_OUT)
#define PORT_DATA_IO(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_OUT, PORT##nr##_IN)
#define PORT_DATA_IO_PD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_OUT, PORT##nr##_IN, \
PORT##nr##_IN_PD)
#define PORT_DATA_IO_PU(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_OUT, PORT##nr##_IN, \
PORT##nr##_IN_PU)
#define PORT_DATA_IO_PU_PD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_OUT, PORT##nr##_IN, \
PORT##nr##_IN_PD, PORT##nr##_IN_PU)
static pinmux_enum_t pinmux_data[] = {
/* specify valid pin states for each pin in GPIO mode */
/* 55-1 (GPIO) */
......@@ -1078,13 +1020,9 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(RESETOUTS_MARK, PORT264_FN1),
};
#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
#define GPIO_PORT_265() _265(_GPIO_PORT, , unused)
#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
static struct pinmux_gpio pinmux_gpios[] = {
/* 55-1 -> 55-5 (GPIO) */
GPIO_PORT_265(),
GPIO_PORT_ALL(),
/* Special Pull-up / Pull-down Functions */
GPIO_FN(PORT66_KEYIN0_PU), GPIO_FN(PORT67_KEYIN1_PU),
......@@ -1362,23 +1300,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(RESETOUTS),
};
/* helper for top 4 bits in PORTnCR */
#define PCRH(in, in_pd, in_pu, out) \
0, (out), (in), 0, \
0, 0, 0, 0, \
0, 0, (in_pd), 0, \
0, 0, (in_pu), 0
#define PORTCR(nr, reg) \
{ PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \
PORT##nr##_IN_PU, PORT##nr##_OUT), \
PORT##nr##_FN0, PORT##nr##_FN1, \
PORT##nr##_FN2, PORT##nr##_FN3, \
PORT##nr##_FN4, PORT##nr##_FN5, \
PORT##nr##_FN6, PORT##nr##_FN7 } \
}
static struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(0, 0xe6050000), /* PORT0CR */
PORTCR(1, 0xe6050001), /* PORT1CR */
......
arch/arm/mach-shmobile/pfc-sh73a0.c
View file @ 7f80850d
......@@ -24,83 +24,71 @@
#include <mach/sh73a0.h>
#include <mach/irqs.h>
#define _1(fn, pfx, sfx) fn(pfx, sfx)
#define _10(fn, pfx, sfx) \
_1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \
_1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \
_1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \
_1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \
_1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx)
#define _310(fn, pfx, sfx) \
_10(fn, pfx, sfx), _10(fn, pfx##1, sfx), \
_10(fn, pfx##2, sfx), _10(fn, pfx##3, sfx), \
_10(fn, pfx##4, sfx), _10(fn, pfx##5, sfx), \
_10(fn, pfx##6, sfx), _10(fn, pfx##7, sfx), \
_10(fn, pfx##8, sfx), _10(fn, pfx##9, sfx), \
_10(fn, pfx##10, sfx), \
_1(fn, pfx##110, sfx), _1(fn, pfx##111, sfx), \
_1(fn, pfx##112, sfx), _1(fn, pfx##113, sfx), \
_1(fn, pfx##114, sfx), _1(fn, pfx##115, sfx), \
_1(fn, pfx##116, sfx), _1(fn, pfx##117, sfx), \
_1(fn, pfx##118, sfx), \
_1(fn, pfx##128, sfx), _1(fn, pfx##129, sfx), \
_10(fn, pfx##13, sfx), _10(fn, pfx##14, sfx), \
_10(fn, pfx##15, sfx), \
_1(fn, pfx##160, sfx), _1(fn, pfx##161, sfx), \
_1(fn, pfx##162, sfx), _1(fn, pfx##163, sfx), \
_1(fn, pfx##164, sfx), \
_1(fn, pfx##192, sfx), _1(fn, pfx##193, sfx), \
_1(fn, pfx##194, sfx), _1(fn, pfx##195, sfx), \
_1(fn, pfx##196, sfx), _1(fn, pfx##197, sfx), \
_1(fn, pfx##198, sfx), _1(fn, pfx##199, sfx), \
_10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx), \
_10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx), \
_10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx), \
_10(fn, pfx##26, sfx), _10(fn, pfx##27, sfx), \
_1(fn, pfx##280, sfx), _1(fn, pfx##281, sfx), \
_1(fn, pfx##282, sfx), \
_1(fn, pfx##288, sfx), _1(fn, pfx##289, sfx), \
_10(fn, pfx##29, sfx), _10(fn, pfx##30, sfx)
#define _PORT(pfx, sfx) pfx##_##sfx
#define PORT_310(str) _310(_PORT, PORT, str)
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_10(fn, pfx##2, sfx), PORT_10(fn, pfx##3, sfx), \
PORT_10(fn, pfx##4, sfx), PORT_10(fn, pfx##5, sfx), \
PORT_10(fn, pfx##6, sfx), PORT_10(fn, pfx##7, sfx), \
PORT_10(fn, pfx##8, sfx), PORT_10(fn, pfx##9, sfx), \
PORT_10(fn, pfx##10, sfx), \
PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \
PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \
PORT_1(fn, pfx##118, sfx), \
PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \
PORT_10(fn, pfx##15, sfx), \
PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \
PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \
PORT_1(fn, pfx##164, sfx), \
PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx), \
PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
PORT_1(fn, pfx##282, sfx), \
PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx)
enum {
PINMUX_RESERVED = 0,
PINMUX_DATA_BEGIN,
PORT_310(DATA), /* PORT0_DATA -> PORT309_DATA */
PORT_ALL(DATA), /* PORT0_DATA -> PORT309_DATA */
PINMUX_DATA_END,
PINMUX_INPUT_BEGIN,
PORT_310(IN), /* PORT0_IN -> PORT309_IN */
PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */
PINMUX_INPUT_END,
PINMUX_INPUT_PULLUP_BEGIN,
PORT_310(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */
PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */
PINMUX_INPUT_PULLUP_END,
PINMUX_INPUT_PULLDOWN_BEGIN,
PORT_310(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */
PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */
PINMUX_INPUT_PULLDOWN_END,
PINMUX_OUTPUT_BEGIN,
PORT_310(OUT), /* PORT0_OUT -> PORT309_OUT */
PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */
PINMUX_OUTPUT_END,
PINMUX_FUNCTION_BEGIN,
PORT_310(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */
PORT_310(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */
PORT_310(FN0), /* PORT0_FN0 -> PORT309_FN0 */
PORT_310(FN1), /* PORT0_FN1 -> PORT309_FN1 */
PORT_310(FN2), /* PORT0_FN2 -> PORT309_FN2 */
PORT_310(FN3), /* PORT0_FN3 -> PORT309_FN3 */
PORT_310(FN4), /* PORT0_FN4 -> PORT309_FN4 */
PORT_310(FN5), /* PORT0_FN5 -> PORT309_FN5 */
PORT_310(FN6), /* PORT0_FN6 -> PORT309_FN6 */
PORT_310(FN7), /* PORT0_FN7 -> PORT309_FN7 */
PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */
PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */
PORT_ALL(FN0), /* PORT0_FN0 -> PORT309_FN0 */
PORT_ALL(FN1), /* PORT0_FN1 -> PORT309_FN1 */
PORT_ALL(FN2), /* PORT0_FN2 -> PORT309_FN2 */
PORT_ALL(FN3), /* PORT0_FN3 -> PORT309_FN3 */
PORT_ALL(FN4), /* PORT0_FN4 -> PORT309_FN4 */
PORT_ALL(FN5), /* PORT0_FN5 -> PORT309_FN5 */
PORT_ALL(FN6), /* PORT0_FN6 -> PORT309_FN6 */
PORT_ALL(FN7), /* PORT0_FN7 -> PORT309_FN7 */
MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
......@@ -508,6 +496,14 @@ enum {
SDHICMD2_PU_MARK,
MMCCMD0_PU_MARK,
MMCCMD1_PU_MARK,
MMCD0_0_PU_MARK,
MMCD0_1_PU_MARK,
MMCD0_2_PU_MARK,
MMCD0_3_PU_MARK,
MMCD0_4_PU_MARK,
MMCD0_5_PU_MARK,
MMCD0_6_PU_MARK,
MMCD0_7_PU_MARK,
FSIBISLD_PU_MARK,
FSIACK_PU_MARK,
FSIAILR_PU_MARK,
......@@ -517,45 +513,6 @@ enum {
PINMUX_MARK_END,
};
#define PORT_DATA_I(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
#define PORT_DATA_I_PD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_IN, PORT##nr##_IN_PD)
#define PORT_DATA_I_PU(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_IN, PORT##nr##_IN_PU)
#define PORT_DATA_I_PU_PD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_IN, PORT##nr##_IN_PD, \
PORT##nr##_IN_PU)
#define PORT_DATA_O(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_OUT)
#define PORT_DATA_IO(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_OUT, PORT##nr##_IN)
#define PORT_DATA_IO_PD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_OUT, PORT##nr##_IN, \
PORT##nr##_IN_PD)
#define PORT_DATA_IO_PU(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_OUT, PORT##nr##_IN, \
PORT##nr##_IN_PU)
#define PORT_DATA_IO_PU_PD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_OUT, PORT##nr##_IN, \
PORT##nr##_IN_PD, PORT##nr##_IN_PU)
static pinmux_enum_t pinmux_data[] = {
/* specify valid pin states for each pin in GPIO mode */
......@@ -1561,6 +1518,24 @@ static pinmux_enum_t pinmux_data[] = {
MSEL4CR_MSEL15_0),
PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU,
MSEL4CR_MSEL15_1),
PINMUX_DATA(MMCD0_0_PU_MARK,
PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0),
PINMUX_DATA(MMCD0_1_PU_MARK,
PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0),
PINMUX_DATA(MMCD0_2_PU_MARK,
PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0),
PINMUX_DATA(MMCD0_3_PU_MARK,
PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0),
PINMUX_DATA(MMCD0_4_PU_MARK,
PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0),
PINMUX_DATA(MMCD0_5_PU_MARK,
PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0),
PINMUX_DATA(MMCD0_6_PU_MARK,
PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0),
PINMUX_DATA(MMCD0_7_PU_MARK,
PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0),
PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU),
PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU),
PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU),
......@@ -1568,12 +1543,8 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
};
#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
#define GPIO_PORT_310() _310(_GPIO_PORT, , unused)
#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
static struct pinmux_gpio pinmux_gpios[] = {
GPIO_PORT_310(),
GPIO_PORT_ALL(),
/* Table 25-1 (Functions 0-7) */
GPIO_FN(VBUS_0),
......@@ -2236,24 +2207,20 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(SDHICMD2_PU),
GPIO_FN(MMCCMD0_PU),
GPIO_FN(MMCCMD1_PU),
GPIO_FN(MMCD0_0_PU),
GPIO_FN(MMCD0_1_PU),
GPIO_FN(MMCD0_2_PU),
GPIO_FN(MMCD0_3_PU),
GPIO_FN(MMCD0_4_PU),
GPIO_FN(MMCD0_5_PU),
GPIO_FN(MMCD0_6_PU),
GPIO_FN(MMCD0_7_PU),
GPIO_FN(FSIACK_PU),
GPIO_FN(FSIAILR_PU),
GPIO_FN(FSIAIBT_PU),
GPIO_FN(FSIAISLD_PU),
};
#define PORTCR(nr, reg) \
{ PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
0, \
/*0001*/ PORT##nr##_OUT , \
/*0010*/ PORT##nr##_IN , 0, 0, 0, 0, 0, 0, 0, \
/*1010*/ PORT##nr##_IN_PD, 0, 0, 0, \
/*1110*/ PORT##nr##_IN_PU, 0, \
PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \
PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \
PORT##nr##_FN6, PORT##nr##_FN7, 0, 0, 0, 0, 0, 0, 0, 0 } \
}
static struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(0, 0xe6050000), /* PORT0CR */
PORTCR(1, 0xe6050001), /* PORT1CR */
......
arch/arm/mach-shmobile/pm-sh7372.c
View file @ 7f80850d
......@@ -402,22 +402,18 @@ static void sh7372_setup_a3sm(unsigned long msk, unsigned long msk2)
#ifdef CONFIG_CPU_IDLE
static void sh7372_cpuidle_setup(struct cpuidle_device *dev)
static void sh7372_cpuidle_setup(struct cpuidle_driver *drv)
{
struct cpuidle_state *state;
int i = dev->state_count;
struct cpuidle_state *state = &drv->states[drv->state_count];
state = &dev->states[i];
snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
state->exit_latency = 10;
state->target_residency = 20 + 10;
state->power_usage = 1; /* perhaps not */
state->flags = 0;
state->flags |= CPUIDLE_FLAG_TIME_VALID;
shmobile_cpuidle_modes[i] = sh7372_enter_core_standby;
state->flags = CPUIDLE_FLAG_TIME_VALID;
shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_core_standby;
dev->state_count = i + 1;
drv->state_count++;
}
static void sh7372_cpuidle_init(void)
......
include/linux/sh_pfc.h
View file @ 7f80850d
......@@ -104,4 +104,80 @@ struct pinmux_info {
int register_pinmux(struct pinmux_info *pip);
int unregister_pinmux(struct pinmux_info *pip);
/* helper macro for port */
#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)
#define PORT_10(fn, pfx, sfx) \
PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \
PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)
#define PORT_90(fn, pfx, sfx) \
PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \
PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \
PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx), \
PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx), \
PORT_10(fn, pfx##9, sfx)
#define _PORT_ALL(pfx, sfx) pfx##_##sfx
#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
#define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused)
#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
/* helper macro for pinmux_enum_t */
#define PORT_DATA_I(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
#define PORT_DATA_I_PD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_IN, PORT##nr##_IN_PD)
#define PORT_DATA_I_PU(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_IN, PORT##nr##_IN_PU)
#define PORT_DATA_I_PU_PD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
#define PORT_DATA_O(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
#define PORT_DATA_IO(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
PORT##nr##_IN)
#define PORT_DATA_IO_PD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
PORT##nr##_IN, PORT##nr##_IN_PD)
#define PORT_DATA_IO_PU(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
PORT##nr##_IN, PORT##nr##_IN_PU)
#define PORT_DATA_IO_PU_PD(nr) \
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
/* helper macro for top 4 bits in PORTnCR */
#define _PCRH(in, in_pd, in_pu, out) \
0, (out), (in), 0, \
0, 0, 0, 0, \
0, 0, (in_pd), 0, \
0, 0, (in_pu), 0
#define PORTCR(nr, reg) \
{ \
PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
_PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \
PORT##nr##_IN_PU, PORT##nr##_OUT), \
PORT##nr##_FN0, PORT##nr##_FN1, \
PORT##nr##_FN2, PORT##nr##_FN3, \
PORT##nr##_FN4, PORT##nr##_FN5, \
PORT##nr##_FN6, PORT##nr##_FN7 } \
}
#endif /* __SH_PFC_H */
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