x86/cpu/AMD: Remove now unused definition of MFENCE_RDTSC feature

CVE-2017-5753
CVE-2017-5715

With the switch to using LFENCE_RDTSC on AMD platforms there is no longer
a need for the MFENCE_RDTSC feature.  Remove it usage and definition.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Andy Whitcroft <apw@canonical.com>
(backported from commit 1faf0ed25006beed56fd6465d53c61250ed22d39)
Signed-off-by: Andy Whitcroft <apw@canonical.com>

arch/x86/include/asm/barrier.h

@@ -24,8 +24,7 @@
 #define wmb()	asm volatile("sfence" ::: "memory")
 #endif
 
-#define gmb() alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC, \
-				       "lfence", X86_FEATURE_LFENCE_RDTSC);
+#define gmb() alternative("", "lfence", X86_FEATURE_LFENCE_RDTSC);
 
 #ifdef CONFIG_X86_PPRO_FENCE
 #define dma_rmb()	rmb()

arch/x86/include/asm/cpufeatures.h

@@ -92,7 +92,6 @@
 #define X86_FEATURE_SYSCALL32	( 3*32+14) /* "" syscall in ia32 userspace */
 #define X86_FEATURE_SYSENTER32	( 3*32+15) /* "" sysenter in ia32 userspace */
 #define X86_FEATURE_REP_GOOD	( 3*32+16) /* rep microcode works well */
-#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */
 #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */
 /* free, was #define X86_FEATURE_11AP	( 3*32+19) * "" Bad local APIC aka 11AP */
 #define X86_FEATURE_NOPL	( 3*32+20) /* The NOPL (0F 1F) instructions */

arch/x86/include/asm/msr.h

@@ -147,8 +147,7 @@ static __always_inline unsigned long long rdtsc_ordered(void)
 	 * that some other imaginary CPU is updating continuously with a
 	 * time stamp.
 	 */
-	alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC,
-			  "lfence", X86_FEATURE_LFENCE_RDTSC);
+	alternative("", "lfence", X86_FEATURE_LFENCE_RDTSC);
 	return rdtsc();
 }
 

arch/x86/net/bpf_jit_comp.c

@@ -115,9 +115,6 @@ static void emit_memory_barrier(u8 **pprog)
 		if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
 			/* x86 LFENCE opcode 0F AE E8 */
 			EMIT3(0x0f, 0xae, 0xe8);
-		else if (boot_cpu_has(X86_FEATURE_MFENCE_RDTSC))
-			/* AMD MFENCE opcode 0F AE F0 */
-			EMIT3(0x0f, 0xae, 0xf0);
 		else
 			/* we should never end up here,
 			 * but if we do, better not to emit anything*/