PPC32: Updates for PPC405 processors. A lot of stuff that was under

CONFIG_4xx but which won't apply on the new 440GP has been changed
to depend on CONFIG_40x instead.  Also a few other fixes and updates
for 405GP-based systems from the linuxppc_2_4_devel tree.

arch/ppc/boot/common/crt0.S

@@ -69,7 +69,7 @@ __start:
 	bdnz	1b			# If we are not done yet, keep clearing
 2:
 
-#ifdef CONFIG_4xx
+#ifdef CONFIG_40x
 	## Set up the stack
 
 	lis	r9,_start@h		# r9 = &_start (text section entry)

arch/ppc/boot/simple/embed_config.c

@@ -4,9 +4,17 @@
 
 /* Board specific functions for those embedded 8xx boards that do
  * not have boot monitor support for board information.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
+
 #include <linux/types.h>
 #include <linux/config.h>
+#include <linux/string.h>
+#include <asm/io.h>
 #ifdef CONFIG_8xx
 #include <asm/mpc8xx.h>
 #endif
@@ -14,12 +22,6 @@
 #include <asm/mpc8260.h>
 #include <asm/immap_8260.h>
 #endif
-#ifdef CONFIG_4xx
-#include <asm/io.h>
-#endif
-#if defined(CONFIG_405GP) || defined(CONFIG_NP405H) || defined(CONFIG_NP405L)
-#include <linux/netdevice.h>
-#endif
 
 /* For those boards that don't provide one.
 */
@@ -222,6 +224,23 @@ rpx_memsize(bd_t *bd, u_char *cp)
 	bd->bi_memsize = size * 1024 * 1024;
 }
 #endif /* LITE || CLASSIC || EP405 */
+#if defined(CONFIG_EP405)
+static void
+rpx_nvramsize(bd_t *bd, u_char *cp)
+{
+	uint	size;
+
+	size = 0;
+
+	while (*cp != '\n') {
+		size *= 10;
+		size += (*cp) - '0';
+		cp++;
+	}
+
+	bd->bi_nvramsize = size * 1024;
+}
+#endif /* CONFIG_EP405 */
 
 #endif	/* Embedded Planet boards */
 
@@ -641,7 +660,11 @@ embed_config(bd_t **bdp)
 #ifdef CONFIG_TREEBOOT
 /* This could possibly work for all treeboot roms.
 */
+#if defined(CONFIG_ASH)
+#define BOARD_INFO_VECTOR       0xFFF80B50 /* openbios 1.19 moved this vector down  - armin */
+#else
 #define	BOARD_INFO_VECTOR	0xFFFE0B50
+#endif
 
 void
 embed_config(bd_t **bdp)
@@ -658,8 +681,8 @@ embed_config(bd_t **bdp)
 	/* shut down the Ethernet controller that the boot rom
 	 * sometimes leaves running.
 	 */
-	mtdcr(DCRN_MALCR, MALCR_MMSR);                /* 1st reset MAL */
-	while (mfdcr(DCRN_MALCR) & MALCR_MMSR) {};    /* wait for the reset */
+	mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR);     /* 1st reset MAL */
+	while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {}; /* wait for the reset */	
 	emacp->em0mr0 = 0x20000000;        /* then reset EMAC */
 	eieio();
 #endif
@@ -684,24 +707,20 @@ embed_config(bd_t **bdp)
 			bd->bi_pci_enetaddr[i] = *cp++;
 #endif
 		}
+		bd->bi_tbfreq = 200 * 1000 * 1000;
 		bd->bi_intfreq = 200000000;
 		bd->bi_busfreq = 100000000;
 #ifdef CONFIG_PCI
 		bd->bi_pci_busfreq = 66666666;
 #endif
+	}
 	/* Yeah, this look weird, but on Redwood 4 they are
 	 * different object in the structure.  When RW5 uses
 	 * OpenBIOS, it requires a special value.
 	 */
 #ifdef CONFIG_REDWOOD_5
-	bd->bi_intfreq = 200 * 1000 * 1000;
-	bd->bi_busfreq = 0;
-
 	bd->bi_tbfreq = 27 * 1000 * 1000;
-#elif CONFIG_REDWOOD_4
-		bd->bi_tbfreq = bd->bi_intfreq;
 #endif
-	}
 }
 #endif
 
@@ -751,6 +770,13 @@ embed_config(bd_t **bdp)
 	        	                }
                 	}
 
+			if (*cp == 'N') {
+				cp++;
+				if (*cp == 'V') {
+					cp += 2;
+					rpx_nvramsize(bd, cp);
+				}
+			}
 			while ((*cp != '\n') && (*cp != 0xff))
 			      cp++;
 
@@ -771,3 +797,28 @@ embed_config(bd_t **bdp)
 }
 #endif
 
+#ifdef CONFIG_RAINIER
+/* Rainier uses vxworks bootrom */
+void
+embed_config(bd_t **bdp)
+{
+	u_char	*cp;
+	int	i;
+	bd_t	*bd;
+	
+	bd = &bdinfo;
+	*bdp = bd;
+
+	bd->bi_memsize   = (32 * 1024 * 1024) ;
+	bd->bi_intfreq = 133000000; //the internal clock is 133 MHz
+	bd->bi_busfreq   = 100000000;
+	bd->bi_pci_busfreq= 33000000;
+
+	cp = (u_char *)def_enet_addr;
+	for (i=0; i<6; i++) {
+		bd->bi_enetaddr[i] = *cp++;
+	}
+
+}
+#endif
+

arch/ppc/config.in

@@ -18,11 +18,15 @@ define_bool CONFIG_PPC y
 define_bool CONFIG_PPC32 y
 choice 'Processor Type'	\
 	"6xx/7xx/74xx/8260	CONFIG_6xx	\
-	 4xx			CONFIG_4xx	\
+	 40x			CONFIG_40x	\
 	 POWER3               	CONFIG_POWER3	\
 	 8xx			CONFIG_8xx	\
 	 iSeries		CONFIG_PPC_ISERIES"	6xx
 
+if [ "$CONFIG_40x" = "y" ]; then
+  define_bool CONFIG_4xx y
+fi
+
 if [ "$CONFIG_6xx" = "y" ]; then
    bool 'MPC8260 CPM Support' CONFIG_8260
 fi
@@ -52,17 +56,21 @@ if [ "$CONFIG_8260" = "y" ]; then
 	 Willow		CONFIG_WILLOW"	Willow
 fi
 
-if [ "$CONFIG_4xx" = "y" ]; then
+if [ "$CONFIG_40x" = "y" ]; then
     choice 'Machine Type'			\
 	"Ash		CONFIG_ASH		\
 	 Ceder		CONFIG_CEDER		\
 	 CPCI405	CONFIG_CPCI405 		\
-	 EP405		CONFIG_EP405 		\
+	 EP405/EP405PC	CONFIG_EP405 		\
 	 Oak		CONFIG_OAK 		\
 	 Redwood-4	CONFIG_REDWOOD_4 	\
 	 Redwood-5	CONFIG_REDWOOD_5 	\
 	 Tivo		CONFIG_TIVO 		\
 	 Walnut		CONFIG_WALNUT"	Walnut
+
+   if [ "$CONFIG_EP405" = "y" ]; then
+      bool 'EP405PC Support' CONFIG_EP405PC
+   fi  
 fi
 
 if [ "$CONFIG_8xx" = "y" ]; then
@@ -182,7 +190,7 @@ if [ "$CONFIG_4xx" = "y" -o "$CONFIG_8xx" = "y" ]; then
    bool 'Math emulation' CONFIG_MATH_EMULATION
 fi
 
-if [ "$CONFIG_4xx" = "y" ]; then
+if [ "$CONFIG_40x" = "y" ]; then
 # It's often necessary to know the specific 4xx processor type.
 # Fortunately, it is impled (so far) from the board type, so we
 # don't need to ask more redundant questions.
@@ -238,11 +246,9 @@ if [ "$CONFIG_4xx" = "y" ]; then
    bool 'Blue Logic DMA' CONFIG_405_DMA
    dep_bool 'Power Management support (experimental)' CONFIG_PM $CONFIG_EXPERIMENTAL
 
-   if [ "$CONFIG_4xx" = "y" ]; then
    choice 'TTYS0 device and default console'	\
 	"UART0  CONFIG_UART0_TTYS0		\
 	 UART1	CONFIG_UART0_TTYS1"		UART0
-   fi
 
    define_bool CONFIG_IBM405_ERR51 y
    define_bool CONFIG_NOT_COHERENT_CACHE y
@@ -282,7 +288,7 @@ if [ "$CONFIG_ADVANCED_OPTIONS" = "y" ]; then
    if [ "$CONFIG_8xx" = "y" ]; then
       bool "Pinned Kernel TLBs (860 ONLY)" CONFIG_PIN_TLB
    fi
-   if [ "$CONFIG_4xx" = "y" ]; then
+   if [ "$CONFIG_40x" = "y" ]; then
       bool "Pinned Kernel TLBs" CONFIG_PIN_TLB
    fi
    if [ "$CONFIG_ALL_PPC" != "y" ]; then
@@ -575,9 +581,9 @@ if [ "$CONFIG_8260" = "y" ]; then
    source arch/ppc/8260_io/Config.in
 fi
 
-if [ "$CONFIG_4xx" = "y" ]; then
+if [ "$CONFIG_40x" = "y" ]; then
    mainmenu_option next_comment
-   comment 'IBM 4xx options'
+   comment 'IBM 40x options'
    if [ "$CONFIG_STB03xxx" = "y" ]; then
       bool 'STB IR Keyboard' CONFIG_STB_KB
       bool 'SICC Serial port' CONFIG_SERIAL_SICC

arch/ppc/kernel/Makefile

@@ -21,7 +21,7 @@ CFLAGS_btext.o		+= -mrelocatable-lib
 
 # Start off with 'head.o', change as needed.
 HEAD-y				:= head.o
-HEAD-$(CONFIG_4xx)		:= head_4xx.o
+HEAD-$(CONFIG_40x)		:= head_4xx.o
 HEAD-$(CONFIG_8xx)		:= head_8xx.o
 HEAD-$(CONFIG_PPC_ISERIES)	:= iSeries_head.o
 

arch/ppc/kernel/cputable.c

@@ -283,7 +283,7 @@ struct cpu_spec	cpu_specs[] = {
 	__setup_cpu_8xx	/* Empty */
     },
 #endif /* CONFIG_8xx */
-#ifdef CONFIG_4xx
+#ifdef CONFIG_40x
     {	/* 403GC */
     	0xffffff00, 0x00200200, "403GC",
     	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
@@ -333,7 +333,38 @@ struct cpu_spec	cpu_specs[] = {
 	16, 8,
 	0, /*__setup_cpu_405 */
     },
-#endif /* CONFIG_4xx */
+    {	/* NP4GS3 */
+    	0xffff0000, 0x40B10000, "NP4GS3",
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+    	PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+	16, 8,
+	0, /*__setup_cpu_405 */
+    },
+    {   /* NP405H */
+        0xffff0000, 0x41410000, "NP405H",
+        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+        PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+        16, 8,
+        0, /*__setup_cpu_405 */
+     },
+
+#endif /* CONFIG_40x */
+#ifdef CONFIG_440
+    { /* 440GP Rev. B */
+        0xf0000fff, 0x40000440, "440GP Rev. B",
+        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+        PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
+        32, 32,
+        0, /*__setup_cpu_440 */
+    },
+    { /* 440GP Rev. C */
+        0xf0000fff, 0x40000481, "440GP Rev. C",
+        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+        PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
+        32, 32,
+        0, /*__setup_cpu_440 */
+    },
+#endif /* CONFIG_440 */
 #if !CLASSIC_PPC
     {	/* default match */
     	0x00000000, 0x00000000, "(generic PPC)",

arch/ppc/kernel/misc.S

@@ -354,7 +354,7 @@ _GLOBAL(_nmask_and_or_msr)
  * Flush MMU TLB
  */
 _GLOBAL(_tlbia)
-#if defined(CONFIG_4xx) && defined(CONFIG_PIN_TLB)
+#if defined(CONFIG_40x) && defined(CONFIG_PIN_TLB)
 	/* This needs to be coordinated with other pinning functions since
 	 * we don't keep a memory location of number of entries to reduce
 	 * cache pollution during these operations.
@@ -401,14 +401,14 @@ _GLOBAL(_tlbia)
 	tlbia
 	sync
 #endif /* CONFIG_SMP */
-#endif /* CONFIG_4xx */
+#endif /* defined(CONFIG_40x) && defined(CONFIG_PIN_TLB) */
 	blr	
 
 /*
  * Flush MMU TLB for a particular address
  */
 _GLOBAL(_tlbie)
-#ifdef CONFIG_4xx
+#ifdef CONFIG_40x
 	tlbsx.	r3, 0, r3
 	bne	10f
 	sync
@@ -418,7 +418,7 @@ _GLOBAL(_tlbie)
 	tlbwe	r3, r3, TLB_TAG
 	isync
 10:
-#else
+#else /* ! CONFIG_40x */
 #if defined(CONFIG_SMP)
 	rlwinm	r8,r1,0,0,18
 	lwz	r8,TI_CPU(r8)
@@ -451,7 +451,7 @@ _GLOBAL(_tlbie)
 	tlbie	r3
 	sync
 #endif /* CONFIG_SMP */
-#endif /* CONFIG_4xx */
+#endif /* ! CONFIG_40x */
 	blr
 
 /*
@@ -463,7 +463,7 @@ _GLOBAL(flush_instruction_cache)
 	isync
 	lis	r5, IDC_INVALL@h
 	mtspr	IC_CST, r5
-#elif defined(CONFIG_4xx)
+#elif defined(CONFIG_40x)
 #ifdef CONFIG_403GCX
 	li      r3, 512
 	mtctr   r3

arch/ppc/kernel/ppc-stub.c

@@ -514,7 +514,7 @@ static struct hard_trap_info
 	unsigned int tt;		/* Trap type code for powerpc */
 	unsigned char signo;		/* Signal that we map this trap into */
 } hard_trap_info[] = {
-#if defined(CONFIG_4xx)
+#if defined(CONFIG_40x)
 	{ 0x100, SIGINT  },		/* critical input interrupt */
 	{ 0x200, SIGSEGV },		/* machine check */
 	{ 0x300, SIGSEGV },		/* data storage */
@@ -613,7 +613,7 @@ handle_exception (struct pt_regs *regs)
 	sigval = computeSignal(regs->trap);
 	ptr = remcomOutBuffer;
 
-#if defined(CONFIG_4xx)
+#if defined(CONFIG_40x)
 	*ptr++ = 'S';
 	*ptr++ = hexchars[sigval >> 4];
 	*ptr++ = hexchars[sigval & 0xf];
@@ -785,7 +785,7 @@ handle_exception (struct pt_regs *regs)
  * some location may have changed something that is in the instruction cache.
  */
 			kgdb_flush_cache_all();
-#if defined(CONFIG_4xx)
+#if defined(CONFIG_40x)
 			strcpy(remcomOutBuffer, "OK");
 			putpacket(remcomOutBuffer);
 #endif
@@ -802,7 +802,7 @@ handle_exception (struct pt_regs *regs)
 
 		case 's':
 			kgdb_flush_cache_all();
-#if defined(CONFIG_4xx)
+#if defined(CONFIG_40x)
 			regs->msr |= MSR_DE;
 			regs->dbcr0 |= (DBCR0_IDM | DBCR0_IC);
 			set_msr(msr);

arch/ppc/mm/Makefile

@@ -21,7 +21,7 @@ obj-y				:= fault.o init.o mem_pieces.o extable.o \
 
 obj-$(CONFIG_PPC_STD_MMU)	+= hashtable.o ppc_mmu.o tlb.o
 obj-$(CONFIG_PPC_ISERIES)	+= iSeries_hashtable.o iSeries_mmu.o tlb.o
-obj-$(CONFIG_4xx)		+= 4xx_mmu.o
+obj-$(CONFIG_40x)		+= 4xx_mmu.o
 obj-$(CONFIG_NOT_COHERENT_CACHE)	+= cachemap.o
 
 include $(TOPDIR)/Rules.make

arch/ppc/platforms/Makefile

@@ -12,7 +12,7 @@
 ifdef CONFIG_PPC64BRIDGE
 EXTRA_AFLAGS		:= -Wa,-mppc64bridge
 endif
-ifdef CONFIG_4xx
+ifdef CONFIG_40x
 EXTRA_AFLAGS		:= -Wa,-m405
 endif
 

arch/ppc/platforms/ep405.c

@@ -32,42 +32,51 @@
 #define DBG(x...)
 #endif
 
-void *ep405_bcsr;
-void *ep405_nvram;
+u8 *ep405_bcsr;
+u8 *ep405_nvram;
+
+static struct {
+	u8 cpld_xirq_select;
+	int pci_idsel;
+	int irq;
+} ep405_devtable[] = {
+#ifdef CONFIG_EP405PC
+	{0x07, 0x0E, 25},		/* EP405PC: USB */
+#endif
+};
+#define EP405_DEVTABLE_SIZE (sizeof(ep405_devtable)/sizeof(ep405_devtable[0]))
 
 int __init
 ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 {
-	static char pci_irq_table[][4] =
-	    /*
-	     *      PCI IDSEL/INTPIN->INTLINE
-	     *      A       B       C       D
-	     */
-	{
-		{28, 28, 28, 28},	/* IDSEL 1 - PCI slot 1 */
-		{29, 29, 29, 29},	/* IDSEL 2 - PCI slot 2 */
-		{30, 30, 30, 30},	/* IDSEL 3 - PCI slot 3 */
-		{31, 31, 31, 31},	/* IDSEL 4 - PCI slot 4 */
-	};
-	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
+	int i;
+
+	/* AFAICT this is only called a few times during PCI setup, so
+	   performance is not critical */
+	for (i = 0; i < EP405_DEVTABLE_SIZE; i++) {
+		if (idsel == ep405_devtable[i].pci_idsel)
+			return ep405_devtable[i].irq;
+	}
+	return -1;
 };
 
 void __init
 board_setup_arch(void)
 {
+	bd_t *bip = (bd_t *) __res;
+
 #ifdef CONFIG_PPC_RTC
-	/* FIXME: what if NVRAM size is not 512k */
+	if (bip->bi_nvramsize == 512*1024) {
+		/* FIXME: we should properly handle NVRTCs of different sizes */
 		TODC_INIT(TODC_TYPE_DS1557, ep405_nvram, ep405_nvram, ep405_nvram, 8);
-#endif				/* CONFIG_PPC_RTC */
+	}
+#endif
 }
 
 void __init
-bios_fixup(struct pci_controller *hose, void *pcil0_base)
+bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
 {
-
 	unsigned int bar_response, bar;
-	struct pcil0_regs *pcip;
 	/*
 	 * Expected PCI mapping:
 	 *
@@ -82,29 +91,7 @@ bios_fixup(struct pci_controller *hose, void *pcil0_base)
 	 *
 	 */
 
-#ifdef DEBUG
-	int i;
-	pcip = (struct pcil0_regs *) pcil0_base;
-
-	printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
-	printk("PCI bridge regs before fixup \n");
-	for (i = 0; i <= 3; i++) {
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
-	}
-	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
-	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
-	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
-	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-#else
-	pcip = (struct pcil0_regs *) pcil0_base;
-#endif
-	/* added for IBM boot rom version 1.15 bios bar changes  -AK */
-
-	/* Disable region first */
+	/* Disable region zero first */
 	out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
 	/* PLB starting addr, PCI: 0x80000000 */
 	out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
@@ -133,6 +120,11 @@ bios_fixup(struct pci_controller *hose, void *pcil0_base)
 	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 	out_le32((void *) &(pcip->ptm2ms), 0x00000000);
 
+	/* Configure PTM (PCI->PLB) region 1 */
+	out_le32((void *) &(pcip->ptm1la), 0x00000000); /* PLB base address */
+	/* Disable PTM region 2 */
+	out_le32((void *) &(pcip->ptm2ms), 0x00000000);
+
 	/* Zero config bars */
 	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
 		early_write_config_dword(hose, hose->first_busno,
@@ -146,42 +138,60 @@ bios_fixup(struct pci_controller *hose, void *pcil0_base)
 		    PCI_FUNC(hose->first_busno), bar, bar_response);
 	}
 	/* end work arround */
-
-#ifdef DEBUG
-	printk("PCI bridge regs after fixup \n");
-	for (i = 0; i <= 3; i++) {
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
-	}
-	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
-	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
-	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
-	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-#endif
 }
 
 void __init
 board_io_mapping(void)
 {
+	bd_t *bip = (bd_t *) __res;
+
 	ep405_bcsr = ioremap(EP405_BCSR_PADDR, EP405_BCSR_SIZE);
-	ep405_nvram = ioremap(EP405_NVRAM_PADDR, EP405_NVRAM_SIZE);
+
+	if (bip->bi_nvramsize > 0) {
+		ep405_nvram = ioremap(EP405_NVRAM_PADDR, bip->bi_nvramsize);
+	}
 }
 
 void __init
 board_setup_irq(void)
 {
+	int i;
+
+	/* Workaround for a bug in the firmware it incorrectly sets
+	   the IRQ polarities for XIRQ0 and XIRQ1 */
+	mtdcr(DCRN_UIC_PR(DCRN_UIC0_BASE), 0xffffff80); /* set the polarity */
+	mtdcr(DCRN_UIC_SR(DCRN_UIC0_BASE), 0x00000060); /* clear bogus interrupts */
+
+	/* Activate the XIRQs from the CPLD */
+	writeb(0xf0, ep405_bcsr+10);
+
+	/* Set up IRQ routing */
+	for (i = 0; i < EP405_DEVTABLE_SIZE; i++) {
+		if ( (ep405_devtable[i].irq >= 25)
+		     && (ep405_devtable[i].irq) <= 31) {
+			writeb(ep405_devtable[i].cpld_xirq_select, ep405_bcsr+5);
+			writeb(ep405_devtable[i].irq - 25, ep405_bcsr+6);
+		}
+	}
 }
 
 void __init
 board_init(void)
 {
+	bd_t *bip = (bd_t *) __res;
+
 #ifdef CONFIG_PPC_RTC
+	/* FIXME: we should be able to access the NVRAM even if PPC_RTC is not configured */
+	ppc_md.nvram_read_val = todc_direct_read_val;
+	ppc_md.nvram_write_val = todc_direct_write_val;
+
+	if (bip->bi_nvramsize == 512*1024) {
 		ppc_md.time_init = todc_time_init;
 		ppc_md.set_rtc_time = todc_set_rtc_time;
 		ppc_md.get_rtc_time = todc_get_rtc_time;
-	ppc_md.nvram_read_val = todc_direct_read_val;
-	ppc_md.nvram_write_val = todc_direct_write_val;
+	} else {
+		printk("EP405: NVRTC size is not 512k (not a DS1557).  Not sure what to do with it\n");
+	}
+
 #endif
 }

arch/ppc/platforms/ep405.h

@@ -22,37 +22,20 @@ typedef struct board_info {
 	unsigned int	 bi_intfreq;		/* Processor speed, in Hz */
 	unsigned int	 bi_busfreq;		/* PLB Bus speed, in Hz */
 	unsigned int	 bi_pci_busfreq;	/* PCI Bus speed, in Hz */
+	unsigned int	 bi_nvramsize;		/* Size of the NVRAM/RTC */
 } bd_t;
 
 /* Some 4xx parts use a different timebase frequency from the internal clock.
 */
 #define bi_tbfreq bi_intfreq
 
-extern void *ep405_bcsr;
-extern void *ep405_nvram;
+extern u8 *ep405_bcsr;
+extern u8 *ep405_nvram;
 
 /* Map for the BCSR and NVRAM space */
 #define EP405_BCSR_PADDR	((uint)0xf4000000)
 #define EP405_BCSR_SIZE		((uint)16)
 #define EP405_NVRAM_PADDR	((uint)0xf4200000)
-/* FIXME: what if the board has something other than 512k NVRAM */
-#define EP405_NVRAM_SIZE	((uint)512*1024)
-
-/* Early initialization address mapping for block_io.
- * Standard 405GP map.
- */
-#define PPC4xx_PCI_IO_PADDR	((uint)PPC405_PCI_PHY_IO_BASE)
-#define PPC4xx_PCI_IO_VADDR	PPC4xx_PCI_IO_PADDR
-#define PPC4xx_PCI_IO_SIZE	((uint)64*1024)
-#define PPC4xx_PCI_CFG_PADDR	((uint)PPC405_PCI_CONFIG_ADDR)
-#define PPC4xx_PCI_CFG_VADDR	PPC4xx_PCI_CFG_PADDR
-#define PPC4xx_PCI_CFG_SIZE	((uint)4*1024)
-#define PPC4xx_PCI_LCFG_PADDR	((uint)0xef400000)
-#define PPC4xx_PCI_LCFG_VADDR	PPC4xx_PCI_LCFG_PADDR
-#define PPC4xx_PCI_LCFG_SIZE	((uint)4*1024)
-#define PPC4xx_ONB_IO_PADDR	((uint)0xef600000)
-#define PPC4xx_ONB_IO_VADDR	PPC4xx_ONB_IO_PADDR
-#define PPC4xx_ONB_IO_SIZE	((uint)4*1024)
 
 /* serial defines */
 #define BASE_BAUD		399193

arch/ppc/platforms/ibm405.h

@@ -32,6 +32,9 @@
  *
  *	Version 1.0 (02/01/17) - A. Kuster
  *	Initial version	 - moved 405  specific out of the other core.h's
+ *
+ *	Version 1.0 (02/08/02) - A. Kuster
+ *	removed DCRN_UIC1_BASE to NP405L & H
  */
 
 #ifdef __KERNEL__
@@ -57,7 +60,6 @@
 #define DCRN_CHCR0	(DCRN_CHCR_BASE + 0x0)	/* Chip Control Register 1 */
 #define DCRN_CHCR1	(DCRN_CHCR_BASE + 0x1)	/* Chip Control Register 2 */
 #endif
-#define CHR1_CETE	0x00800000	/* CPU external timer enable */
 #define CHR1_PCIPW	0x00008000	/* PCI Int enable/Peripheral Write enable */
 
 #ifdef DCRN_CHPSR_BASE
@@ -211,24 +213,37 @@
 #define IOCR_SCS	0x00000002
 #define IOCR_SPC	0x00000001
 
-#ifdef DCRN_MAL_BASE
-#define DCRN_MALCR		(DCRN_MAL_BASE + 0x0)	/* MAL Configuration */
-#define DCRN_MALDBR		(DCRN_MAL_BASE + 0x3)	/* Debug Register */
-#define DCRN_MALESR		(DCRN_MAL_BASE + 0x1)	/* Error Status */
-#define DCRN_MALIER		(DCRN_MAL_BASE + 0x2)	/* Interrupt Enable */
-#define DCRN_MALTXCARR		(DCRN_MAL_BASE + 0x5)	/* TX Channed Active Reset Register */
-#define DCRN_MALTXCASR		(DCRN_MAL_BASE + 0x4)	/* TX Channel Active Set Register */
-#define DCRN_MALTXDEIR		(DCRN_MAL_BASE + 0x7)	/* Tx Descriptor Error Interrupt */
-#define DCRN_MALTXEOBISR	(DCRN_MAL_BASE + 0x6)	/* Tx End of Buffer Interrupt Status */
-#define DCRN_MALRXCARR		(DCRN_MAL_BASE + 0x11)	/* RX Channed Active Reset Register */
-#define DCRN_MALRXCASR		(DCRN_MAL_BASE + 0x10)	/* RX Channel Active Set Register */
-#define DCRN_MALRXDEIR		(DCRN_MAL_BASE + 0x13)	/* Rx Descriptor Error Interrupt */
-#define DCRN_MALRXEOBISR	(DCRN_MAL_BASE + 0x12)	/* Rx End of Buffer Interrupt Status */
-#define DCRN_MALRXCTP0R		(DCRN_MAL_BASE + 0x40)	/* Channel Rx 0 Channel Table Pointer */
-#define DCRN_MALTXCTP0R		(DCRN_MAL_BASE + 0x20)	/* Channel Tx 0 Channel Table Pointer */
-#define DCRN_MALTXCTP1R		(DCRN_MAL_BASE + 0x21)	/* Channel Tx 1 Channel Table Pointer */
-#define DCRN_MALRCBS0		(DCRN_MAL_BASE + 0x60)	/* Channel Rx 0 Channel Buffer Size */
-#endif
+#define DCRN_MALCR(base)	(base + 0x0)	/* MAL Configuration */
+#define DCRN_MALDBR(base)	((base) + 0x3)	/* Debug Register */
+#define DCRN_MALESR(base)	((base) + 0x1)	/* Error Status */
+#define DCRN_MALIER(base)	((base) + 0x2)	/* Interrupt Enable */
+#define DCRN_MALTXCARR(base)	((base) + 0x5)	/* TX Channed Active Reset Register */
+#define DCRN_MALTXCASR(base)	((base) + 0x4)	/* TX Channel Active Set Register */
+#define DCRN_MALTXDEIR(base)	((base) + 0x7)	/* Tx Descriptor Error Interrupt */
+#define DCRN_MALTXEOBISR(base)	((base) + 0x6)	/* Tx End of Buffer Interrupt Status */
+#define DCRN_MALRXCARR(base)	((base) + 0x11)	/* RX Channed Active Reset Register */
+#define DCRN_MALRXCASR(base)	((base) + 0x10)	/* RX Channel Active Set Register */
+#define DCRN_MALRXDEIR(base)	((base) + 0x13)	/* Rx Descriptor Error Interrupt */
+#define DCRN_MALRXEOBISR(base)	((base) + 0x12)	/* Rx End of Buffer Interrupt Status */
+#define DCRN_MALRXCTP0R(base)	((base) + 0x40)	/* Channel Rx 0 Channel Table Pointer */
+#define DCRN_MALRXCTP1R(base)	((base) + 0x41)	/* Channel Rx 1 Channel Table Pointer */
+#define DCRN_MALTXCTP0R(base)	((base) + 0x20)	/* Channel Tx 0 Channel Table Pointer */
+#define DCRN_MALTXCTP1R(base)	((base) + 0x21)	/* Channel Tx 1 Channel Table Pointer */
+#define DCRN_MALTXCTP2R(base)	((base) + 0x22)	/* Channel Tx 2 Channel Table Pointer */
+#define DCRN_MALTXCTP3R(base)	((base) + 0x23)	/* Channel Tx 3 Channel Table Pointer */
+#define DCRN_MALRCBS0(base)	((base) + 0x60)	/* Channel Rx 0 Channel Buffer Size */
+#define DCRN_MALRCBS1(base)	((base) + 0x61)	/* Channel Rx 1 Channel Buffer Size */
+
+/* EMAC DCRN's */
+#define DCRN_MALRXCTP2R(base)	((base) + 0x42)	/* Channel Rx 2 Channel Table Pointer */
+#define DCRN_MALRXCTP3R(base)	((base) + 0x43)	/* Channel Rx 3 Channel Table Pointer */
+#define DCRN_MALTXCTP4R(base)	((base) + 0x24)	/* Channel Tx 4 Channel Table Pointer */
+#define DCRN_MALTXCTP5R(base)	((base) + 0x25)	/* Channel Tx 5 Channel Table Pointer */
+#define DCRN_MALTXCTP6R(base)	((base) + 0x26)	/* Channel Tx 6 Channel Table Pointer */
+#define DCRN_MALTXCTP7R(base)	((base) + 0x27)	/* Channel Tx 7 Channel Table Pointer */
+#define DCRN_MALRCBS2(base)	((base) + 0x62)	/* Channel Rx 2 Channel Buffer Size */
+#define DCRN_MALRCBS3(base)	((base) + 0x63)	/* Channel Rx 3 Channel Buffer Size */
+
  /* DCRN_MALCR */
 #define MALCR_MMSR		0x80000000	/* MAL Software reset */
 #define MALCR_PLBP_1		0x00400000	/* MAL reqest priority: */
@@ -294,28 +309,14 @@
 #define DCRN_POB0_BESR1	(DCRN_POB0_BASE + 0x4)
 #endif
 
-#ifdef DCRN_UIC0_BASE
-#define DCRN_UIC0_SR	(DCRN_UIC0_BASE + 0x0)
-#define DCRN_UIC0_ER	(DCRN_UIC0_BASE + 0x2)
-#define DCRN_UIC0_CR	(DCRN_UIC0_BASE + 0x3)
-#define DCRN_UIC0_PR	(DCRN_UIC0_BASE + 0x4)
-#define DCRN_UIC0_TR	(DCRN_UIC0_BASE + 0x5)
-#define DCRN_UIC0_MSR	(DCRN_UIC0_BASE + 0x6)
-#define DCRN_UIC0_VR	(DCRN_UIC0_BASE + 0x7)
-#define DCRN_UIC0_VCR	(DCRN_UIC0_BASE + 0x8)
-#endif
-
-#ifdef DCRN_UIC1_BASE
-#define DCRN_UIC1_SR	(DCRN_UIC1_BASE + 0x0)
-#define DCRN_UIC1_SRS	(DCRN_UIC1_BASE + 0x1)
-#define DCRN_UIC1_ER	(DCRN_UIC1_BASE + 0x2)
-#define DCRN_UIC1_CR	(DCRN_UIC1_BASE + 0x3)
-#define DCRN_UIC1_PR	(DCRN_UIC1_BASE + 0x4)
-#define DCRN_UIC1_TR	(DCRN_UIC1_BASE + 0x5)
-#define DCRN_UIC1_MSR	(DCRN_UIC1_BASE + 0x6)
-#define DCRN_UIC1_VR	(DCRN_UIC1_BASE + 0x7)
-#define DCRN_UIC1_VCR	(DCRN_UIC1_BASE + 0x8)
-#endif
+#define DCRN_UIC_SR(base)	(base + 0x0)
+#define DCRN_UIC_ER(base)	(base + 0x2)
+#define DCRN_UIC_CR(base)	(base + 0x3)
+#define DCRN_UIC_PR(base)	(base + 0x4)
+#define DCRN_UIC_TR(base)	(base + 0x5)
+#define DCRN_UIC_MSR(base)	(base + 0x6)
+#define DCRN_UIC_VR(base)	(base + 0x7)
+#define DCRN_UIC_VCR(base)	(base + 0x8)
 
 #ifdef DCRN_SDRAM0_BASE
 #define DCRN_SDRAM0_CFGADDR	(DCRN_SDRAM0_BASE + 0x0)	/* Memory Controller Address */

arch/ppc/platforms/ibm405gp.h

@@ -36,6 +36,13 @@
  *
  *	Version 1.1 02/01/17 - A. Kuster
  *	Moved offsets to ibm405.h
+ *
+ *	Version 1.2 05/01/02 - Armin
+ *	 added IIC_PORT_DFNS
+ *
+ *	Version 1.3 - armin
+ *	  removed iic & uart num defines
+ *	  and IIC_PORT_DFNS
  */
 
 #ifdef __KERNEL__
@@ -88,30 +95,36 @@
 #define UART1_INT	1
 
 #define PCIL0_BASE	0xEF400000
-#define UART0_IO_BASE	(u8 *) 0xEF600300
-#define UART1_IO_BASE	(u8 *) 0xEF600400
+#define UART0_IO_BASE	0xEF600300
+#define UART1_IO_BASE	0xEF600400
 #define IIC0_BASE	0xEF600500
 #define OPB0_BASE	0xEF600600
 #define GPIO0_BASE	0xEF600700
 #define EMAC0_BASE	0xEF600800
 
 #define EMAC_NUMS	1
-#define UART_NUMS	2
+#define IIC0_IRQ	2
+#define IIC1_IRQ	0
+
+#define IIC_OWN		0x55
+#define IIC_CLOCK	50
 #define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
 
 #define STD_UART_OP(num)					\
 	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
 		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: UART##num##_IO_BASE,		\
+		iomem_base: (u8 *)UART##num##_IO_BASE,		\
 		io_type: SERIAL_IO_MEM},
 
 #if defined(CONFIG_UART0_TTYS0)
+#define SERIAL_DEBUG_IO_BASE	UART0_IO_BASE
 #define SERIAL_PORT_DFNS	\
 	STD_UART_OP(0)		\
 	STD_UART_OP(1)
 #endif
 
 #if defined(CONFIG_UART0_TTYS1)
+#define SERIAL_DEBUG_IO_BASE	UART1_IO_BASE
 #define SERIAL_PORT_DFNS	\
 	STD_UART_OP(1)		\
 	STD_UART_OP(0)
@@ -123,6 +136,11 @@
 #define DCRN_CPMSR_BASE		0x0B8
 #define DCRN_CPMFR_BASE		0x0BA
 
+#define CHR0_U0EC	0x00000080	/* Select external clock for UART0 */
+#define CHR0_U1EC	0x00000040	/* Select external clock for UART1 */
+#define CHR0_UDIV	0x0000003E	/* UART internal clock divisor */
+#define CHR1_CETE	0x00800000	/* CPU external timer enable */
+
 #define DCRN_CHPSR_BASE         0x0B4
 #define  PSR_PLL_FWD_MASK        0xC0000000
 #define  PSR_PLL_FDBACK_MASK     0x30000000
@@ -169,6 +187,7 @@
 #define DCRN_POB0_BASE		0x0A0
 #define DCRN_SDRAM0_BASE	0x010
 #define DCRN_UIC0_BASE		0x0C0
+#define UIC0 DCRN_UIC0_BASE
 
 #include <platforms/ibm405.h>
 

arch/ppc/platforms/ibm_ocp.h

 /*
- * ibm_ips.h
+ * ibm_ocp.h
  *
  *	This was dirived from the ppc4xx.h and all 405GP specific definition and board
  *	inclusions where moved here.
@@ -36,8 +36,8 @@
  */
 
 #ifdef __KERNEL__
-#ifndef __ASM_IBM_IPS_H__
-#define __ASM_IBM_IPS_H__
+#ifndef __ASM_IBM_OCP_H__
+#define __ASM_IBM_OCP_H__
 
 #ifndef __ASSEMBLY__
 #include <linux/types.h>
@@ -188,5 +188,5 @@ typedef struct ide_regs {
 } ide_t;
 
 #endif				/* __ASSEMBLY__ */
-#endif				/* __ASM_IBM_IPS_H__ */
+#endif				/* __ASM_IBM_OCP_H__ */
 #endif				/* __KERNEL__ */

include/asm-ppc/ibm4xx.h

@@ -16,7 +16,7 @@
 
 #include <linux/config.h>
 
-#ifdef CONFIG_4xx
+#ifdef CONFIG_40x
 
 #if defined(CONFIG_ASH)
 #include <platforms/ash.h>
@@ -54,9 +54,7 @@
 #define PPC4xx_MACHINE_NAME	"Unidentified 4xx class"
 #endif
 
-#ifndef NR_BOARD_IRQS
-#define NR_BOARD_IRQS 0
-#endif
+
 
 /* IO_BASE is for PCI I/O.
  * ISA not supported, just here to resolve copilation.
@@ -95,6 +93,6 @@ extern unsigned char __res[];
 		asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v));}
 
 #endif /* __ASSEMBLY__ */
-#endif /* CONFIG_4xx */
+#endif /* CONFIG_40x */
 #endif /* __ASM_IBM4XX_H__ */
 #endif /* __KERNEL__ */

include/asm-ppc/io.h

@@ -26,7 +26,7 @@
 #define PREP_ISA_MEM_BASE 	0xc0000000
 #define PREP_PCI_DRAM_OFFSET 	0x80000000
 
-#if defined(CONFIG_4xx)
+#if defined(CONFIG_40x)
 #include <asm/ibm4xx.h>
 #elif defined(CONFIG_8xx)
 #include <asm/mpc8xx.h>
@@ -412,11 +412,43 @@ static inline int isa_check_signature(unsigned long io_addr,
 	return 0;
 }
 
-/* Nothing to do */
+#ifdef CONFIG_NOT_COHERENT_CACHE
+
+/*
+ * DMA-consistent mapping functions for PowerPCs that don't support
+ * cache snooping.  These allocate/free a region of uncached mapped
+ * memory space for use with DMA devices.  Alternatively, you could
+ * allocate the space "normally" and use the cache management functions
+ * to ensure it is consistent.
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+extern void consistent_sync_page(struct page *page, unsigned long offset,
+				 size_t size, int rw);
+
+#define dma_cache_inv(_start,_size) \
+	invalidate_dcache_range(_start, (_start + _size))
+#define dma_cache_wback(_start,_size) \
+	clean_dcache_range(_start, (_start + _size))
+#define dma_cache_wback_inv(_start,_size) \
+	flush_dcache_range(_start, (_start + _size))
+
+#else /* ! CONFIG_NOT_COHERENT_CACHE */
+
+/*
+ * Cache coherent cores.
+ */
 
 #define dma_cache_inv(_start,_size)		do { } while (0)
 #define dma_cache_wback(_start,_size)		do { } while (0)
 #define dma_cache_wback_inv(_start,_size)	do { } while (0)
 
-#endif
+#define consistent_alloc(gfp, size, handle)	NULL
+#define consistent_free(addr, size)		do { } while (0)
+#define consistent_sync(addr, size, rw)		do { } while (0)
+#define consistent_sync_page(pg, off, sz, rw)	do { } while (0)
+
+#endif /* ! CONFIG_NOT_COHERENT_CACHE */
+#endif /* _PPC_IO_H */
 #endif /* __KERNEL__ */

include/asm-ppc/irq.h

@@ -13,8 +13,22 @@ extern void disable_irq(unsigned int);
 extern void disable_irq_nosync(unsigned int);
 extern void enable_irq(unsigned int);
 
-#if defined(CONFIG_4xx)
+#if defined(CONFIG_40x)
 #include <asm/ibm4xx.h>
+
+#ifndef NR_BOARD_IRQS
+#define NR_BOARD_IRQS 0
+#endif
+
+#ifndef UIC_WIDTH /* Number of interrupts per device */
+#define UIC_WIDTH 32
+#endif
+
+#ifndef NR_UICS /* number  of UIC devices */
+#define NR_UICS 1
+#endif
+
+#if defined (CONFIG_403)
 /*
  * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
  * 32 possible interrupts, a majority of which are not implemented on
@@ -22,6 +36,14 @@ extern void enable_irq(unsigned int);
  * there are eight internal interrupts for the on-chip serial port
  * (SPU), DMA controller, and JTAG controller.
  *
+ */
+
+#define	NR_AIC_IRQS 32 
+#define	NR_IRQS	 (NR_AIC_IRQS + NR_BOARD_IRQS)
+
+#elif !defined (CONFIG_403)
+
+/*
  *  The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
  * possible interrupts as well. There are seven, configurable external
  * interrupt pins and there are 17 internal interrupts for the on-chip
@@ -29,19 +51,21 @@ extern void enable_irq(unsigned int);
  *
  */
 
-#define	NR_AIC_IRQS	32
-#define	NR_IRQS		(NR_AIC_IRQS + NR_BOARD_IRQS)
 
+#define NR_UIC_IRQS UIC_WIDTH
+#define NR_IRQS		((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
+#endif
 static __inline__ int
 irq_cannonicalize(int irq)
 {
 	return (irq);
 }
 
-#elif defined (CONFIG_NP405)
+#elif defined(CONFIG_440)
+#include <asm/ibm440.h>
 
-#define NR_AIC_IRQS	32
-#define NR_IRQS		(NR_AIC_IRQS + NR_BOARD_IRQS)
+#define	NR_UIC_IRQS	64
+#define	NR_IRQS		(NR_UIC_IRQS + NR_BOARD_IRQS)
 
 static __inline__ int
 irq_cannonicalize(int irq)
@@ -119,7 +143,7 @@ static __inline__ int irq_cannonicalize(int irq)
 	return irq;
 }
 
-#else /* CONFIG_4xx + CONFIG_8xx */
+#else /* CONFIG_40x + CONFIG_8xx */
 /*
  * this is the # irq's for all ppc arch's (pmac/chrp/prep)
  * so it is the max of them all

include/asm-ppc/pgtable.h

@@ -125,9 +125,9 @@ extern unsigned long ioremap_bot, ioremap_base;
  * (hardware-defined) PowerPC PTE as closely as possible.
  */
 
-#if defined(CONFIG_4xx)
+#if defined(CONFIG_40x)
 
-/* There are several potential gotchas here.  The 4xx hardware TLBLO
+/* There are several potential gotchas here.  The 40x hardware TLBLO
    field looks like this:
 
    0  1  2  3  4  ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
@@ -135,7 +135,7 @@ extern unsigned long ioremap_bot, ioremap_base;
 
    Where possible we make the Linux PTE bits match up with this
 
-   - bits 20 and 21 must be cleared, because we use 4k pages (4xx can
+   - bits 20 and 21 must be cleared, because we use 4k pages (40x can
      support down to 1k pages), this is done in the TLBMiss exception
      handler.
    - We use only zones 0 (for kernel pages) and 1 (for user pages)
@@ -143,7 +143,7 @@ extern unsigned long ioremap_bot, ioremap_base;
      miss handler.  Bit 27 is PAGE_USER, thus selecting the correct
      zone.
    - PRESENT *must* be in the bottom two bits because swap cache
-     entries use the top 30 bits.  Because 4xx doesn't support SMP
+     entries use the top 30 bits.  Because 40x doesn't support SMP
      anyway, M is irrelevant so we borrow it for PAGE_PRESENT.  Bit 30
      is cleared in the TLB miss handler before the TLB entry is loaded.
    - All other bits of the PTE are loaded into TLBLO without
@@ -153,7 +153,7 @@ extern unsigned long ioremap_bot, ioremap_base;
      PRESENT.
 */
 
-/* Definitions for 4xx embedded chips. */
+/* Definitions for 40x embedded chips. */
 #define	_PAGE_GUARDED	0x001	/* G: page is guarded from prefetch */
 #define _PAGE_PRESENT	0x002	/* software: PTE contains a translation */
 #define	_PAGE_NO_CACHE	0x004	/* I: caching is inhibited */
@@ -451,7 +451,7 @@ static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
 
 /* Find an entry in the third-level page table.. */
 #define __pte_offset(address)		\
-	((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 #define pte_offset_kernel(dir, addr)	\
 	((pte_t *) pmd_page_kernel(*(dir)) + __pte_offset(addr))
 #define pte_offset_map(dir, addr)		\

include/asm-ppc/serial.h

@@ -33,7 +33,7 @@
 #include <platforms/spruce_serial.h>
 #elif defined(CONFIG_ZX4500)
 #include <platforms/zx4500_serial.h>
-#elif defined(CONFIG_4xx)
+#elif defined(CONFIG_40x)
 #include <asm/ibm4xx.h>
 #else
 

include/asm-ppc/time.h

@@ -43,7 +43,7 @@ int via_calibrate_decr(void);
  */
 static __inline__ unsigned int get_dec(void)
 {
-#if defined(CONFIG_4xx)
+#if defined(CONFIG_40x)
 	return (mfspr(SPRN_PIT));
 #else
 	return (mfspr(SPRN_DEC));
@@ -52,7 +52,7 @@ static __inline__ unsigned int get_dec(void)
 
 static __inline__ void set_dec(unsigned int val)
 {
-#if defined(CONFIG_4xx)
+#if defined(CONFIG_40x)
 	return;		/* Have to let it auto-reload */
 #elif defined(CONFIG_8xx_CPU6)
 	set_dec_cpu6(val);