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Commit 869ce69e authored by Len Brown's avatar Len Brown
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tools/power turbostat: use intel-family.h model strings 

All except for model 1F, a Nehalem, which is currently incorrectly
indentified as a Westmere in that new header.
Signed-off-by: default avatarLen Brown <len.brown@intel.com>
parent 0f644909
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Showing with 126 additions and 124 deletions
tools/power/x86/turbostat/Makefile
View file @ 869ce69e
...@@ -10,6 +10,7 @@ endif ...@@ -10,6 +10,7 @@ endif
turbostat : turbostat.c turbostat : turbostat.c
CFLAGS += -Wall CFLAGS += -Wall
CFLAGS += -DMSRHEADER='"../../../../arch/x86/include/asm/msr-index.h"' CFLAGS += -DMSRHEADER='"../../../../arch/x86/include/asm/msr-index.h"'
CFLAGS += -DINTEL_FAMILY_HEADER='"../../../../arch/x86/include/asm/intel-family.h"'
%: %.c %: %.c
@mkdir -p $(BUILD_OUTPUT) @mkdir -p $(BUILD_OUTPUT)
......
tools/power/x86/turbostat/turbostat.c
View file @ 869ce69e
...@@ -21,6 +21,7 @@ ...@@ -21,6 +21,7 @@
#define _GNU_SOURCE #define _GNU_SOURCE
#include MSRHEADER #include MSRHEADER
#include INTEL_FAMILY_HEADER
#include <stdarg.h> #include <stdarg.h>
#include <stdio.h> #include <stdio.h>
#include <err.h> #include <err.h>
...@@ -2163,48 +2164,48 @@ int probe_nhm_msrs(unsigned int family, unsigned int model) ...@@ -2163,48 +2164,48 @@ int probe_nhm_msrs(unsigned int family, unsigned int model)
bclk = discover_bclk(family, model); bclk = discover_bclk(family, model);
switch (model) { switch (model) {
case 0x1A: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
case 0x1E: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
case 0x1F: /* Core i7 and i5 Processor - Nehalem */ case 0x1F: /* Core i7 and i5 Processor - Nehalem */
case 0x25: /* Westmere Client - Clarkdale, Arrandale */ case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */
case 0x2C: /* Westmere EP - Gulftown */ case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */
case 0x2E: /* Nehalem-EX Xeon - Beckton */ case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
case 0x2F: /* Westmere-EX Xeon - Eagleton */ case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
pkg_cstate_limits = nhm_pkg_cstate_limits; pkg_cstate_limits = nhm_pkg_cstate_limits;
break; break;
case 0x2A: /* SNB */ case INTEL_FAM6_SANDYBRIDGE: /* SNB */
case 0x2D: /* SNB Xeon */ case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */
case 0x3A: /* IVB */ case INTEL_FAM6_IVYBRIDGE: /* IVB */
case 0x3E: /* IVB Xeon */ case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
pkg_cstate_limits = snb_pkg_cstate_limits; pkg_cstate_limits = snb_pkg_cstate_limits;
break; break;
case 0x3C: /* HSW */ case INTEL_FAM6_HASWELL_CORE: /* HSW */
case 0x3F: /* HSX */ case INTEL_FAM6_HASWELL_X: /* HSX */
case 0x45: /* HSW */ case INTEL_FAM6_HASWELL_ULT: /* HSW */
case 0x46: /* HSW */ case INTEL_FAM6_HASWELL_GT3E: /* HSW */
case 0x3D: /* BDW */ case INTEL_FAM6_BROADWELL_CORE: /* BDW */
case 0x47: /* BDW */ case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
case 0x4F: /* BDX */ case INTEL_FAM6_BROADWELL_X: /* BDX */
case 0x56: /* BDX-DE */ case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
case 0x4E: /* SKL */ case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
case 0x5E: /* SKL */ case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
case 0x8E: /* KBL */ case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
case 0x9E: /* KBL */ case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
case 0x55: /* SKX */ case INTEL_FAM6_SKYLAKE_X: /* SKX */
pkg_cstate_limits = hsw_pkg_cstate_limits; pkg_cstate_limits = hsw_pkg_cstate_limits;
break; break;
case 0x37: /* BYT */ case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */
case 0x4D: /* AVN */ case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */
pkg_cstate_limits = slv_pkg_cstate_limits; pkg_cstate_limits = slv_pkg_cstate_limits;
break; break;
case 0x4C: /* AMT */ case INTEL_FAM6_ATOM_AIRMONT: /* AMT */
pkg_cstate_limits = amt_pkg_cstate_limits; pkg_cstate_limits = amt_pkg_cstate_limits;
break; break;
case 0x57: /* PHI */ case INTEL_FAM6_XEON_PHI_KNL: /* PHI */
pkg_cstate_limits = phi_pkg_cstate_limits; pkg_cstate_limits = phi_pkg_cstate_limits;
break; break;
case 0x5C: /* BXT */ case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
case 0x5F: /* DNV */ case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
pkg_cstate_limits = bxt_pkg_cstate_limits; pkg_cstate_limits = bxt_pkg_cstate_limits;
break; break;
default: default:
...@@ -2224,9 +2225,9 @@ int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model) ...@@ -2224,9 +2225,9 @@ int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model)
{ {
switch (model) { switch (model) {
/* Nehalem compatible, but do not include turbo-ratio limit support */ /* Nehalem compatible, but do not include turbo-ratio limit support */
case 0x2E: /* Nehalem-EX Xeon - Beckton */ case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
case 0x2F: /* Westmere-EX Xeon - Eagleton */ case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
case 0x57: /* PHI - Knights Landing (different MSR definition) */ case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */
return 0; return 0;
default: default:
return 1; return 1;
...@@ -2241,8 +2242,8 @@ int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) ...@@ -2241,8 +2242,8 @@ int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model)
return 0; return 0;
switch (model) { switch (model) {
case 0x3E: /* IVB Xeon */ case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
case 0x3F: /* HSW Xeon */ case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
return 1; return 1;
default: default:
return 0; return 0;
...@@ -2257,7 +2258,7 @@ int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) ...@@ -2257,7 +2258,7 @@ int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model)
return 0; return 0;
switch (model) { switch (model) {
case 0x3F: /* HSW Xeon */ case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
return 1; return 1;
default: default:
return 0; return 0;
...@@ -2273,7 +2274,7 @@ int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) ...@@ -2273,7 +2274,7 @@ int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model)
return 0; return 0;
switch (model) { switch (model) {
case 0x57: /* Knights Landing */ case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
return 1; return 1;
default: default:
return 0; return 0;
...@@ -2288,22 +2289,22 @@ int has_config_tdp(unsigned int family, unsigned int model) ...@@ -2288,22 +2289,22 @@ int has_config_tdp(unsigned int family, unsigned int model)
return 0; return 0;
switch (model) { switch (model) {
case 0x3A: /* IVB */ case INTEL_FAM6_IVYBRIDGE: /* IVB */
case 0x3C: /* HSW */ case INTEL_FAM6_HASWELL_CORE: /* HSW */
case 0x3F: /* HSX */ case INTEL_FAM6_HASWELL_X: /* HSX */
case 0x45: /* HSW */ case INTEL_FAM6_HASWELL_ULT: /* HSW */
case 0x46: /* HSW */ case INTEL_FAM6_HASWELL_GT3E: /* HSW */
case 0x3D: /* BDW */ case INTEL_FAM6_BROADWELL_CORE: /* BDW */
case 0x47: /* BDW */ case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
case 0x4F: /* BDX */ case INTEL_FAM6_BROADWELL_X: /* BDX */
case 0x56: /* BDX-DE */ case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
case 0x4E: /* SKL */ case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
case 0x5E: /* SKL */ case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
case 0x8E: /* KBL */ case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
case 0x9E: /* KBL */ case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
case 0x55: /* SKX */ case INTEL_FAM6_SKYLAKE_X: /* SKX */
case 0x57: /* Knights Landing */ case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
return 1; return 1;
default: default:
return 0; return 0;
...@@ -2583,8 +2584,8 @@ double get_tdp(unsigned int model) ...@@ -2583,8 +2584,8 @@ double get_tdp(unsigned int model)
return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units;
switch (model) { switch (model) {
case 0x37: case INTEL_FAM6_ATOM_SILVERMONT1:
case 0x4D: case INTEL_FAM6_ATOM_SILVERMONT2:
return 30.0; return 30.0;
default: default:
return 135.0; return 135.0;
...@@ -2601,10 +2602,10 @@ rapl_dram_energy_units_probe(int model, double rapl_energy_units) ...@@ -2601,10 +2602,10 @@ rapl_dram_energy_units_probe(int model, double rapl_energy_units)
/* only called for genuine_intel, family 6 */ /* only called for genuine_intel, family 6 */
switch (model) { switch (model) {
case 0x3F: /* HSX */ case INTEL_FAM6_HASWELL_X: /* HSX */
case 0x4F: /* BDX */ case INTEL_FAM6_BROADWELL_X: /* BDX */
case 0x56: /* BDX-DE */ case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
case 0x57: /* KNL */ case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
return (rapl_dram_energy_units = 15.3 / 1000000); return (rapl_dram_energy_units = 15.3 / 1000000);
default: default:
return (rapl_energy_units); return (rapl_energy_units);
...@@ -2630,40 +2631,40 @@ void rapl_probe(unsigned int family, unsigned int model) ...@@ -2630,40 +2631,40 @@ void rapl_probe(unsigned int family, unsigned int model)
return; return;
switch (model) { switch (model) {
case 0x2A: case INTEL_FAM6_SANDYBRIDGE:
case 0x3A: case INTEL_FAM6_IVYBRIDGE:
case 0x3C: /* HSW */ case INTEL_FAM6_HASWELL_CORE: /* HSW */
case 0x45: /* HSW */ case INTEL_FAM6_HASWELL_ULT: /* HSW */
case 0x46: /* HSW */ case INTEL_FAM6_HASWELL_GT3E: /* HSW */
case 0x3D: /* BDW */ case INTEL_FAM6_BROADWELL_CORE: /* BDW */
case 0x47: /* BDW */ case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
break; break;
case 0x5C: /* BXT */ case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO;
break; break;
case 0x4E: /* SKL */ case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
case 0x5E: /* SKL */ case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
case 0x8E: /* KBL */ case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
case 0x9E: /* KBL */ case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
break; break;
case 0x3F: /* HSX */ case INTEL_FAM6_HASWELL_X: /* HSX */
case 0x4F: /* BDX */ case INTEL_FAM6_BROADWELL_X: /* BDX */
case 0x56: /* BDX-DE */ case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
case 0x55: /* SKX */ case INTEL_FAM6_SKYLAKE_X: /* SKX */
case 0x57: /* KNL */ case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
break; break;
case 0x2D: case INTEL_FAM6_SANDYBRIDGE_X:
case 0x3E: case INTEL_FAM6_IVYBRIDGE_X:
do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
break; break;
case 0x37: /* BYT */ case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */
case 0x4D: /* AVN */ case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */
do_rapl = RAPL_PKG | RAPL_CORES; do_rapl = RAPL_PKG | RAPL_CORES;
break; break;
case 0x5f: /* DNV */ case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS; do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS;
break; break;
default: default:
...@@ -2675,7 +2676,7 @@ void rapl_probe(unsigned int family, unsigned int model) ...@@ -2675,7 +2676,7 @@ void rapl_probe(unsigned int family, unsigned int model)
return; return;
rapl_power_units = 1.0 / (1 << (msr & 0xF)); rapl_power_units = 1.0 / (1 << (msr & 0xF));
if (model == 0x37) if (model == INTEL_FAM6_ATOM_SILVERMONT1)
rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
else else
rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));
...@@ -2706,11 +2707,11 @@ void perf_limit_reasons_probe(unsigned int family, unsigned int model) ...@@ -2706,11 +2707,11 @@ void perf_limit_reasons_probe(unsigned int family, unsigned int model)
return; return;
switch (model) { switch (model) {
case 0x3C: /* HSW */ case INTEL_FAM6_HASWELL_CORE: /* HSW */
case 0x45: /* HSW */ case INTEL_FAM6_HASWELL_ULT: /* HSW */
case 0x46: /* HSW */ case INTEL_FAM6_HASWELL_GT3E: /* HSW */
do_gfx_perf_limit_reasons = 1; do_gfx_perf_limit_reasons = 1;
case 0x3F: /* HSX */ case INTEL_FAM6_HASWELL_X: /* HSX */
do_core_perf_limit_reasons = 1; do_core_perf_limit_reasons = 1;
do_ring_perf_limit_reasons = 1; do_ring_perf_limit_reasons = 1;
default: default:
...@@ -2919,24 +2920,24 @@ int has_snb_msrs(unsigned int family, unsigned int model) ...@@ -2919,24 +2920,24 @@ int has_snb_msrs(unsigned int family, unsigned int model)
return 0; return 0;
switch (model) { switch (model) {
case 0x2A: case INTEL_FAM6_SANDYBRIDGE:
case 0x2D: case INTEL_FAM6_SANDYBRIDGE_X:
case 0x3A: /* IVB */ case INTEL_FAM6_IVYBRIDGE: /* IVB */
case 0x3E: /* IVB Xeon */ case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
case 0x3C: /* HSW */ case INTEL_FAM6_HASWELL_CORE: /* HSW */
case 0x3F: /* HSW */ case INTEL_FAM6_HASWELL_X: /* HSW */
case 0x45: /* HSW */ case INTEL_FAM6_HASWELL_ULT: /* HSW */
case 0x46: /* HSW */ case INTEL_FAM6_HASWELL_GT3E: /* HSW */
case 0x3D: /* BDW */ case INTEL_FAM6_BROADWELL_CORE: /* BDW */
case 0x47: /* BDW */ case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
case 0x4F: /* BDX */ case INTEL_FAM6_BROADWELL_X: /* BDX */
case 0x56: /* BDX-DE */ case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
case 0x4E: /* SKL */ case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
case 0x5E: /* SKL */ case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
case 0x8E: /* KBL */ case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
case 0x9E: /* KBL */ case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
case 0x55: /* SKX */ case INTEL_FAM6_SKYLAKE_X: /* SKX */
case 0x5C: /* BXT */ case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
return 1; return 1;
} }
return 0; return 0;
...@@ -2960,13 +2961,13 @@ int has_hsw_msrs(unsigned int family, unsigned int model) ...@@ -2960,13 +2961,13 @@ int has_hsw_msrs(unsigned int family, unsigned int model)
return 0; return 0;
switch (model) { switch (model) {
case 0x45: /* HSW */ case INTEL_FAM6_HASWELL_ULT: /* HSW */
case 0x3D: /* BDW */ case INTEL_FAM6_BROADWELL_CORE: /* BDW */
case 0x4E: /* SKL */ case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
case 0x5E: /* SKL */ case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
case 0x8E: /* KBL */ case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
case 0x9E: /* KBL */ case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
case 0x5C: /* BXT */ case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
return 1; return 1;
} }
return 0; return 0;
...@@ -2986,10 +2987,10 @@ int has_skl_msrs(unsigned int family, unsigned int model) ...@@ -2986,10 +2987,10 @@ int has_skl_msrs(unsigned int family, unsigned int model)
return 0; return 0;
switch (model) { switch (model) {
case 0x4E: /* SKL */ case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
case 0x5E: /* SKL */ case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
case 0x8E: /* KBL */ case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
case 0x9E: /* KBL */ case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
return 1; return 1;
} }
return 0; return 0;
...@@ -3002,8 +3003,8 @@ int is_slm(unsigned int family, unsigned int model) ...@@ -3002,8 +3003,8 @@ int is_slm(unsigned int family, unsigned int model)
if (!genuine_intel) if (!genuine_intel)
return 0; return 0;
switch (model) { switch (model) {
case 0x37: /* BYT */ case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */
case 0x4D: /* AVN */ case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */
return 1; return 1;
} }
return 0; return 0;
...@@ -3014,7 +3015,7 @@ int is_knl(unsigned int family, unsigned int model) ...@@ -3014,7 +3015,7 @@ int is_knl(unsigned int family, unsigned int model)
if (!genuine_intel) if (!genuine_intel)
return 0; return 0;
switch (model) { switch (model) {
case 0x57: /* KNL */ case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
return 1; return 1;
} }
return 0; return 0;
...@@ -3295,17 +3296,17 @@ void process_cpuid() ...@@ -3295,17 +3296,17 @@ void process_cpuid()
if (crystal_hz == 0) if (crystal_hz == 0)
switch(model) { switch(model) {
case 0x4E: /* SKL */ case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
case 0x5E: /* SKL */ case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
case 0x8E: /* KBL */ case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
case 0x9E: /* KBL */ case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
crystal_hz = 24000000; /* 24.0 MHz */ crystal_hz = 24000000; /* 24.0 MHz */
break; break;
case 0x55: /* SKX */ case INTEL_FAM6_SKYLAKE_X: /* SKX */
crystal_hz = 25000000; /* 25.0 MHz */ crystal_hz = 25000000; /* 25.0 MHz */
break; break;
case 0x5C: /* BXT */ case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
case 0x5F: /* DNV */ case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
crystal_hz = 19200000; /* 19.2 MHz */ crystal_hz = 19200000; /* 19.2 MHz */
break; break;
default: default:
......
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