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Commit 86c87bea authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'devicetree-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 

Pull devicetree updates from Rob Herring:
 "Bindings:

   - Convert smsc,lan91c111, qcom,spi-qup, qcom,msm-uartdm,
     qcom,i2c-qup, qcom,gsbi, i2c-mt65xx, TI wkup_m3_ipc (and new
     props), qcom,smp2p, TI timer, Mediatek gnss, Mediatek topckgen,
     Mediatek apmixedsys, Mediatek infracfg, fsl,ls-extirq,
     fsl,layerscape-dcfg, QCom PMIC SPMI, rda,8810pl-timer, Xilinx
     zynqmp_ipi, uniphier-pcie, and Ilitek touchscreen controllers

   - Convert various Arm Ltd peripheral IP bindings to schemas

   - New bindings for Menlo board CPLD, DH electronics board CPLD,
     Qualcomm Geni based QUP I2C, Renesas RZ/G2UL OSTM, Broafcom BCM4751
     GNSS, MT6360 PMIC, ASIX USB Ethernet controllers, and
     Microchip/SMSC LAN95xx USB Ethernet controllers

   - Add vendor prefix for Enclustra

   - Add various compatible string additions

   - Various example fixes and cleanups

   - Remove unused hisilicon,hi6220-reset binding

   - Treewide fix properties missing type definition

   - Drop some empty and unreferenced .txt bindings

   - Documentation improvements for writing schemas

  DT driver core:

   - Drop static IRQ resources for DT platform devices as IRQ setup is
     dynamic and drivers have all been converted to use
     platform_get_irq() and friends

   - Rework memory allocations and frees for overlays

   - Continue overlay notifier callbacks on successful calls and add
     unittests

   - Handle 'interrupts-extended' in early DT IRQ setup

   - Fix of_property_read_string() errors to match documentation

   - Ignore disabled nodes in FDT API calls"

* tag 'devicetree-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (86 commits)
  of/irq: fix typo in comment
  dt-bindings: Fix properties without any type
  Revert "dt-bindings: mailbox: qcom-ipcc: add missing properties into example"
  dt-bindings: input: touchscreen: ilitek_ts_i2c: Absorb ili2xxx bindings
  dt-bindings: timer: samsung,exynos4210-mct: define strict clock order
  dt-bindings: timer: samsung,exynos4210-mct: drop unneeded minItems
  dt-bindings: timer: cdns,ttc: drop unneeded minItems
  dt-bindings: mailbox: zynqmp_ipi: convert to yaml
  dt-bindings: usb: ci-hdrc-usb2: fix node node for ethernet controller
  dt-bindings: net: add schema for Microchip/SMSC LAN95xx USB Ethernet controllers
  dt-bindings: net: add schema for ASIX USB Ethernet controllers
  of/fdt: Ignore disabled memory nodes
  dt-bindings: arm: fix typos in compatible
  dt-bindings: mfd: Add bindings child nodes for the Mediatek MT6360
  dt-bindings: display: convert Arm Komeda to DT schema
  dt-bindings: display: convert Arm Mali-DP to DT schema
  dt-bindings: display: convert Arm HDLCD to DT schema
  dt-bindings: display: convert PL110/PL111 to DT schema
  dt-bindings: arm: convert vexpress-config to DT schema
  dt-bindings: arm: convert vexpress-sysregs to DT schema
  ...
parents d223575e d036d915
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Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt
View file @ 86c87bea
......@@ -30,7 +30,7 @@ Example:
cpus {
cpu@0 {
compatible = "arm,cotex-a9";
compatible = "arm,cortex-a9";
reg = <0>;
...
enable-method = "brcm,bcm63138";
......
Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt deleted 100644 → 0
View file @ d223575e
Freescale DCFG
DCFG is the device configuration unit, that provides general purpose
configuration and status for the device. Such as setting the secondary
core start address and release the secondary core from holdoff and startup.
Required properties:
- compatible: Should contain a chip-specific compatible string,
Chip-specific strings are of the form "fsl,<chip>-dcfg",
The following <chip>s are known to be supported:
ls1012a, ls1021a, ls1043a, ls1046a, ls2080a, lx2160a
- reg : should contain base address and length of DCFG memory-mapped registers
Example:
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1021a-dcfg";
reg = <0x0 0x1ee0000 0x0 0x10000>;
};
Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-scfg.txt deleted 100644 → 0
View file @ d223575e
Freescale SCFG
SCFG is the supplemental configuration unit, that provides SoC specific
configuration and status registers for the chip. Such as getting PEX port
status.
Required properties:
- compatible: Should contain a chip-specific compatible string,
Chip-specific strings are of the form "fsl,<chip>-scfg",
The following <chip>s are known to be supported:
ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
- reg: should contain base address and length of SCFG memory-mapped registers
Example:
scfg: scfg@1570000 {
compatible = "fsl,ls1021a-scfg";
reg = <0x0 0x1570000 0x0 0x10000>;
};
Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml
View file @ 86c87bea
......@@ -17,14 +17,15 @@ properties:
- const: hisilicon,hip04-bootwrapper
boot-method:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
Address and size of boot method.
[0]: bootwrapper physical address
[1]: bootwrapper size
[2]: relocation physical address
[3]: relocation size
minItems: 1
maxItems: 2
minItems: 2
maxItems: 4
required:
- compatible
......
Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt deleted 100644 → 0
View file @ d223575e
Mediatek apmixedsys controller
==============================
The Mediatek apmixedsys controller provides the PLLs to the system.
Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-apmixedsys"
- "mediatek,mt2712-apmixedsys", "syscon"
- "mediatek,mt6765-apmixedsys", "syscon"
- "mediatek,mt6779-apmixedsys", "syscon"
- "mediatek,mt6797-apmixedsys"
- "mediatek,mt7622-apmixedsys"
- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
- "mediatek,mt7629-apmixedsys"
- "mediatek,mt7986-apmixedsys"
- "mediatek,mt8135-apmixedsys"
- "mediatek,mt8167-apmixedsys", "syscon"
- "mediatek,mt8173-apmixedsys"
- "mediatek,mt8183-apmixedsys", "syscon"
- "mediatek,mt8516-apmixedsys"
- #clock-cells: Must be 1
The apmixedsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Example:
apmixedsys: clock-controller@10209000 {
compatible = "mediatek,mt8173-apmixedsys";
reg = <0 0x10209000 0 0x1000>;
#clock-cells = <1>;
};
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt deleted 100644 → 0
View file @ d223575e
Mediatek infracfg controller
============================
The Mediatek infracfg controller provides various clocks and reset
outputs to the system.
Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-infracfg", "syscon"
- "mediatek,mt2712-infracfg", "syscon"
- "mediatek,mt6765-infracfg", "syscon"
- "mediatek,mt6779-infracfg_ao", "syscon"
- "mediatek,mt6797-infracfg", "syscon"
- "mediatek,mt7622-infracfg", "syscon"
- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
- "mediatek,mt7629-infracfg", "syscon"
- "mediatek,mt7986-infracfg", "syscon"
- "mediatek,mt8135-infracfg", "syscon"
- "mediatek,mt8167-infracfg", "syscon"
- "mediatek,mt8173-infracfg", "syscon"
- "mediatek,mt8183-infracfg", "syscon"
- "mediatek,mt8516-infracfg", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1
The infracfg controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Also it uses the common reset controller binding from
Documentation/devicetree/bindings/reset/reset.txt.
The available reset outputs are defined in
dt-bindings/reset/mt*-resets.h
Example:
infracfg: power-controller@10001000 {
compatible = "mediatek,mt8173-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: MediaTek Infrastructure System Configuration Controller
maintainers:
- Matthias Brugger <matthias.bgg@gmail.com>
description:
The Mediatek infracfg controller provides various clocks and reset outputs
to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,
and reset values in <dt-bindings/reset/mt*-reset.h> and
<dt-bindings/reset/mt*-resets.h>.
properties:
compatible:
oneOf:
- items:
- enum:
- mediatek,mt2701-infracfg
- mediatek,mt2712-infracfg
- mediatek,mt6765-infracfg
- mediatek,mt6779-infracfg_ao
- mediatek,mt6797-infracfg
- mediatek,mt7622-infracfg
- mediatek,mt7629-infracfg
- mediatek,mt7986-infracfg
- mediatek,mt8135-infracfg
- mediatek,mt8167-infracfg
- mediatek,mt8173-infracfg
- mediatek,mt8183-infracfg
- mediatek,mt8516-infracfg
- const: syscon
- items:
- const: mediatek,mt7623-infracfg
- const: mediatek,mt2701-infracfg
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
if:
properties:
compatible:
contains:
enum:
- mediatek,mt2701-infracfg
- mediatek,mt2712-infracfg
- mediatek,mt7622-infracfg
- mediatek,mt7986-infracfg
- mediatek,mt8135-infracfg
- mediatek,mt8173-infracfg
- mediatek,mt8183-infracfg
then:
required:
- '#reset-cells'
additionalProperties: false
examples:
- |
infracfg: clock-controller@10001000 {
compatible = "mediatek,mt8173-infracfg", "syscon";
reg = <0x10001000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt deleted 100644 → 0
View file @ d223575e
Mediatek topckgen controller
============================
The Mediatek topckgen controller provides various clocks to the system.
Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-topckgen"
- "mediatek,mt2712-topckgen", "syscon"
- "mediatek,mt6765-topckgen", "syscon"
- "mediatek,mt6779-topckgen", "syscon"
- "mediatek,mt6797-topckgen"
- "mediatek,mt7622-topckgen"
- "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
- "mediatek,mt7629-topckgen"
- "mediatek,mt7986-topckgen", "syscon"
- "mediatek,mt8135-topckgen"
- "mediatek,mt8167-topckgen", "syscon"
- "mediatek,mt8173-topckgen"
- "mediatek,mt8183-topckgen", "syscon"
- "mediatek,mt8516-topckgen"
- #clock-cells: Must be 1
The topckgen controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Example:
topckgen: power-controller@10000000 {
compatible = "mediatek,mt8173-topckgen";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
Documentation/devicetree/bindings/arm/sp810.txt deleted 100644 → 0
View file @ d223575e
SP810 System Controller
-----------------------
Required properties:
- compatible: standard compatible string for a Primecell peripheral,
see Documentation/devicetree/bindings/arm/primecell.yaml
for more details
should be: "arm,sp810", "arm,primecell"
- reg: standard registers property, physical address and size
of the control registers
- clock-names: from the common clock bindings, for more details see
Documentation/devicetree/bindings/clock/clock-bindings.txt;
should be: "refclk", "timclk", "apb_pclk"
- clocks: from the common clock bindings, phandle and clock
specifier pairs for the entries of clock-names property
- #clock-cells: from the common clock bindings;
should be: <1>
- clock-output-names: from the common clock bindings;
should be: "timerclken0", "timerclken1", "timerclken2", "timerclken3"
- assigned-clocks: from the common clock binding;
should be: clock specifier for each output clock of this
provider node
- assigned-clock-parents: from the common clock binding;
should be: phandle of input clock listed in clocks
property with the highest frequency
Example:
v2m_sysctl: sysctl@20000 {
compatible = "arm,sp810", "arm,primecell";
reg = <0x020000 0x1000>;
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
clock-names = "refclk", "timclk", "apb_pclk";
#clock-cells = <1>;
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
};
Documentation/devicetree/bindings/arm/sp810.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sp810.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Versatile Express SP810 System Controller bindings
maintainers:
- Andre Przywara <andre.przywara@arm.com>
description:
The Arm SP810 system controller provides clocks, timers and a watchdog.
# We need a select here so we don't match all nodes with 'arm,primecell'
select:
properties:
compatible:
contains:
const: arm,sp810
required:
- compatible
properties:
compatible:
items:
- const: arm,sp810
- const: arm,primecell
reg:
maxItems: 1
clock-names:
items:
- const: refclk
- const: timclk
- const: apb_pclk
clocks:
items:
- description: reference clock
- description: timer clock
- description: APB register access clock
"#clock-cells":
const: 1
clock-output-names:
maxItems: 4
assigned-clocks:
maxItems: 4
assigned-clock-parents:
maxItems: 4
additionalProperties: false
required:
- compatible
- reg
- clocks
- clock-names
- "#clock-cells"
examples:
- |
sysctl@20000 {
compatible = "arm,sp810", "arm,primecell";
reg = <0x020000 0x1000>;
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
clock-names = "refclk", "timclk", "apb_pclk";
#clock-cells = <1>;
clock-output-names = "timerclken0", "timerclken1",
"timerclken2", "timerclken3";
assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>,
<&v2m_sysctl 3>, <&v2m_sysctl 3>;
assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>,
<&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
};
Documentation/devicetree/bindings/arm/spe-pmu.txt deleted 100644 → 0
View file @ d223575e
* ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)
ARMv8.2 introduces the optional Statistical Profiling Extension for collecting
performance sample data using an in-memory trace buffer.
** SPE Required properties:
- compatible : should be one of:
"arm,statistical-profiling-extension-v1"
- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where
SPE is only supported on a subset of the CPUs, please consult
the arm,gic-v3 binding for details on describing a PPI partition.
** Example:
spe-pmu {
compatible = "arm,statistical-profiling-extension-v1";
interrupts = <GIC_PPI 05 IRQ_TYPE_LEVEL_HIGH &part1>;
};
Documentation/devicetree/bindings/arm/vexpress-config.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/vexpress-config.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Versatile Express configuration bus bindings
maintainers:
- Andre Przywara <andre.przywara@arm.com>
description:
This is a system control register block, acting as a bridge to the
platform's configuration bus via "system control" interface, addressing
devices with site number, position in the board stack, config controller,
function and device numbers - see motherboard's TRM for more details.
properties:
compatible:
const: arm,vexpress,config-bus
arm,vexpress,config-bridge:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the sysreg node.
muxfpga:
type: object
properties:
compatible:
const: arm,vexpress-muxfpga
arm,vexpress-sysreg,func:
description: FPGA specifier
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- const: 7
- description: device number
additionalProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
shutdown:
type: object
properties:
compatible:
const: arm,vexpress-shutdown
arm,vexpress-sysreg,func:
description: shutdown identifier
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- const: 8
- description: device number
additionalProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
reboot:
type: object
properties:
compatible:
const: arm,vexpress-reboot
arm,vexpress-sysreg,func:
description: reboot identifier
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- const: 9
- description: device number
additionalProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
dvimode:
type: object
properties:
compatible:
const: arm,vexpress-dvimode
arm,vexpress-sysreg,func:
description: DVI mode identifier
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- const: 11
- description: device number
additionalProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
additionalProperties: false
required:
- compatible
- arm,vexpress,config-bridge
patternProperties:
'clk[0-9]*$':
type: object
description:
clocks
properties:
compatible:
const: arm,vexpress-osc
arm,vexpress-sysreg,func:
description: clock specifier
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- const: 1
- description: clock number
freq-range:
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: minimal clock frequency
- description: maximum clock frequency
"#clock-cells":
const: 0
clock-output-names:
maxItems: 1
additionalProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
- "#clock-cells"
"^volt-.+$":
$ref: /schemas/regulator/regulator.yaml#
properties:
compatible:
const: arm,vexpress-volt
arm,vexpress-sysreg,func:
description: regulator specifier
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- const: 2
- description: device number
label:
maxItems: 1
unevaluatedProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
"^amp-.+$":
type: object
properties:
compatible:
const: arm,vexpress-amp
arm,vexpress-sysreg,func:
description: current sensor identifier
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- const: 3
- description: device number
label:
maxItems: 1
additionalProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
"^temp-.+$":
type: object
properties:
compatible:
const: arm,vexpress-temp
arm,vexpress-sysreg,func:
description: temperature sensor identifier
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- const: 4
- description: device number
label:
maxItems: 1
additionalProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
"^reset[0-9]*$":
type: object
properties:
compatible:
const: arm,vexpress-reset
arm,vexpress-sysreg,func:
description: reset specifier
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- const: 5
- description: reset device number
additionalProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
"^power-.+$":
type: object
properties:
compatible:
const: arm,vexpress-power
arm,vexpress-sysreg,func:
description: power sensor identifier
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- const: 12
- description: device number
label:
maxItems: 1
additionalProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
"^energy(-.+)?$":
type: object
properties:
compatible:
const: arm,vexpress-energy
arm,vexpress-sysreg,func:
description: energy sensor identifier
$ref: /schemas/types.yaml#/definitions/uint32-array
oneOf:
- items:
- const: 13
- description: device number
- items:
- const: 13
- description: device number
- const: 13
- description: second device number
label:
maxItems: 1
additionalProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
examples:
- |
mcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
clk0 {
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
#clock-cells = <0>;
};
energy {
compatible = "arm,vexpress-energy";
arm,vexpress-sysreg,func = <13 0>, <13 1>;
};
};
Documentation/devicetree/bindings/arm/vexpress-sysreg.txt deleted 100644 → 0
View file @ d223575e
ARM Versatile Express system registers
--------------------------------------
This is a system control registers block, providing multiple low level
platform functions like board detection and identification, software
interrupt generation, MMC and NOR Flash control etc.
Required node properties:
- compatible value : = "arm,vexpress,sysreg";
- reg : physical base address and the size of the registers window
Deprecated properties, replaced by GPIO subnodes (see below):
- gpio-controller : specifies that the node is a GPIO controller
- #gpio-cells : size of the GPIO specifier, should be 2:
- first cell is the pseudo-GPIO line number:
0 - MMC CARDIN
1 - MMC WPROT
2 - NOR FLASH WPn
- second cell can take standard GPIO flags (currently ignored).
Control registers providing pseudo-GPIO lines must be represented
by subnodes, each of them requiring the following properties:
- compatible value : one of
"arm,vexpress-sysreg,sys_led"
"arm,vexpress-sysreg,sys_mci"
"arm,vexpress-sysreg,sys_flash"
- gpio-controller : makes the node a GPIO controller
- #gpio-cells : size of the GPIO specifier, must be 2:
- first cell is the function number:
- for sys_led : 0..7 = LED 0..7
- for sys_mci : 0 = MMC CARDIN, 1 = MMC WPROT
- for sys_flash : 0 = NOR FLASH WPn
- second cell can take standard GPIO flags (currently ignored).
Example:
v2m_sysreg: sysreg@10000000 {
compatible = "arm,vexpress-sysreg";
reg = <0x10000000 0x1000>;
v2m_led_gpios: sys_led@8 {
compatible = "arm,vexpress-sysreg,sys_led";
gpio-controller;
#gpio-cells = <2>;
};
v2m_mmc_gpios: sys_mci@48 {
compatible = "arm,vexpress-sysreg,sys_mci";
gpio-controller;
#gpio-cells = <2>;
};
v2m_flash_gpios: sys_flash@4c {
compatible = "arm,vexpress-sysreg,sys_flash";
gpio-controller;
#gpio-cells = <2>;
};
};
This block also can also act a bridge to the platform's configuration
bus via "system control" interface, addressing devices with site number,
position in the board stack, config controller, function and device
numbers - see motherboard's TRM for more details. All configuration
controller accessible via this interface must reference the sysreg
node via "arm,vexpress,config-bridge" phandle and define appropriate
topology properties - see main vexpress node documentation for more
details. Each child of such node describes one function and must
define the following properties:
- compatible value : must be one of (corresponding to the TRM):
"arm,vexpress-amp"
"arm,vexpress-dvimode"
"arm,vexpress-energy"
"arm,vexpress-muxfpga"
"arm,vexpress-osc"
"arm,vexpress-power"
"arm,vexpress-reboot"
"arm,vexpress-reset"
"arm,vexpress-scc"
"arm,vexpress-shutdown"
"arm,vexpress-temp"
"arm,vexpress-volt"
- arm,vexpress-sysreg,func : must contain a set of two cells long groups:
- first cell of each group defines the function number
(eg. 1 for clock generator, 2 for voltage regulators etc.)
- second cell of each group defines device number (eg. osc 0,
osc 1 etc.)
- some functions (eg. energy meter, with its 64 bit long counter)
are using more than one function/device number pair
Example:
mcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
osc@0 {
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
};
energy@0 {
compatible = "arm,vexpress-energy";
arm,vexpress-sysreg,func = <13 0>, <13 1>;
};
};
Documentation/devicetree/bindings/arm/vexpress-sysreg.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/vexpress-sysreg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Versatile Express system registers bindings
maintainers:
- Andre Przywara <andre.przywara@arm.com>
description:
This is a system control registers block, providing multiple low level
platform functions like board detection and identification, software
interrupt generation, MMC and NOR Flash control, etc.
properties:
compatible:
const: arm,vexpress-sysreg
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
additionalProperties: false
patternProperties:
'^gpio@[0-9a-f]+$':
type: object
additionalProperties: false
description:
GPIO children
properties:
compatible:
enum:
- arm,vexpress-sysreg,sys_led
- arm,vexpress-sysreg,sys_mci
- arm,vexpress-sysreg,sys_flash
gpio-controller: true
"#gpio-cells":
const: 2
description: |
The first cell is the function number:
for sys_led : 0..7 = LED 0..7
for sys_mci : 0 = MMC CARDIN, 1 = MMC WPROT
for sys_flash : 0 = NOR FLASH WPn
The second cell can take standard GPIO flags.
reg:
maxItems: 1
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
required:
- compatible
- "#address-cells"
- "#size-cells"
examples:
- |
sysreg@0 {
compatible = "arm,vexpress-sysreg";
reg = <0x00000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x1000>;
v2m_led_gpios: gpio@8 {
compatible = "arm,vexpress-sysreg,sys_led";
reg = <0x008 4>;
gpio-controller;
#gpio-cells = <2>;
};
};
...
Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: MediaTek AP Mixedsys Controller
maintainers:
- Michael Turquette <mturquette@baylibre.com>
- Stephen Boyd <sboyd@kernel.org>
description:
The Mediatek apmixedsys controller provides PLLs to the system.
The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
properties:
compatible:
oneOf:
- enum:
- mediatek,mt6797-apmixedsys
- mediatek,mt7622-apmixedsys
- mediatek,mt7986-apmixedsys
- mediatek,mt8135-apmixedsys
- mediatek,mt8173-apmixedsys
- mediatek,mt8516-apmixedsys
- items:
- const: mediatek,mt7623-apmixedsys
- const: mediatek,mt2701-apmixedsys
- const: syscon
- items:
- enum:
- mediatek,mt2701-apmixedsys
- mediatek,mt2712-apmixedsys
- mediatek,mt6765-apmixedsys
- mediatek,mt6779-apmixedsys
- mediatek,mt7629-apmixedsys
- mediatek,mt8167-apmixedsys
- mediatek,mt8183-apmixedsys
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
apmixedsys: clock-controller@10209000 {
compatible = "mediatek,mt8173-apmixedsys";
reg = <0x10209000 0x1000>;
#clock-cells = <1>;
};
Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: MediaTek Top Clock Generator Controller
maintainers:
- Michael Turquette <mturquette@baylibre.com>
- Stephen Boyd <sboyd@kernel.org>
description:
The Mediatek topckgen controller provides various clocks to the system.
The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
properties:
compatible:
oneOf:
- enum:
- mediatek,mt6797-topckgen
- mediatek,mt7622-topckgen
- mediatek,mt8135-topckgen
- mediatek,mt8173-topckgen
- mediatek,mt8516-topckgen
- items:
- const: mediatek,mt7623-topckgen
- const: mediatek,mt2701-topckgen
- const: syscon
- items:
- enum:
- mediatek,mt2701-topckgen
- mediatek,mt2712-topckgen
- mediatek,mt6765-topckgen
- mediatek,mt6779-topckgen
- mediatek,mt7629-topckgen
- mediatek,mt7986-topckgen
- mediatek,mt8167-topckgen
- mediatek,mt8183-topckgen
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
topckgen: clock-controller@10000000 {
compatible = "mediatek,mt8173-topckgen";
reg = <0x10000000 0x1000>;
#clock-cells = <1>;
};
Documentation/devicetree/bindings/clock/samsung,exynos4412-isp-clock.yaml
View file @ 86c87bea
......@@ -61,4 +61,3 @@ examples:
clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
clock-names = "aclk200", "aclk400_mcuisp";
};
Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml
View file @ 86c87bea
......@@ -82,4 +82,3 @@ examples:
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_CE>;
};
Documentation/devicetree/bindings/display/arm,hdlcd.txt deleted 100644 → 0
View file @ d223575e
ARM HDLCD
This is a display controller found on several development platforms produced
by ARM Ltd and in more modern of its' Fast Models. The HDLCD is an RGB
streamer that reads the data from a framebuffer and sends it to a single
digital encoder (DVI or HDMI).
Required properties:
- compatible: "arm,hdlcd"
- reg: Physical base address and length of the controller's registers.
- interrupts: One interrupt used by the display controller to notify the
interrupt controller when any of the interrupt sources programmed in
the interrupt mask register have activated.
- clocks: A list of phandle + clock-specifier pairs, one for each
entry in 'clock-names'.
- clock-names: A list of clock names. For HDLCD it should contain:
- "pxlclk" for the clock feeding the output PLL of the controller.
Required sub-nodes:
- port: The HDLCD connection to an encoder chip. The connection is modeled
using the OF graph bindings specified in
Documentation/devicetree/bindings/graph.txt.
Optional properties:
- memory-region: phandle to a node describing memory (see
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) to be
used for the framebuffer; if not present, the framebuffer may be located
anywhere in memory.
Example:
/ {
...
hdlcd@2b000000 {
compatible = "arm,hdlcd";
reg = <0 0x2b000000 0 0x1000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&oscclk5>;
clock-names = "pxlclk";
port {
hdlcd_output: endpoint@0 {
remote-endpoint = <&hdmi_enc_input>;
};
};
};
/* HDMI encoder on I2C bus */
i2c@7ffa0000 {
....
hdmi-transmitter@70 {
compatible = ".....";
reg = <0x70>;
port@0 {
hdmi_enc_input: endpoint {
remote-endpoint = <&hdlcd_output>;
};
hdmi_enc_output: endpoint {
remote-endpoint = <&hdmi_1_port>;
};
};
};
};
hdmi1: connector@1 {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_1_port: endpoint {
remote-endpoint = <&hdmi_enc_output>;
};
};
};
...
};
Documentation/devicetree/bindings/display/arm,hdlcd.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/arm,hdlcd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm HDLCD display controller binding
maintainers:
- Liviu Dudau <Liviu.Dudau@arm.com>
- Andre Przywara <andre.przywara@arm.com>
description:
The Arm HDLCD is a display controller found on several development platforms
produced by ARM Ltd and in more modern of its Fast Models. The HDLCD is an
RGB streamer that reads the data from a framebuffer and sends it to a single
digital encoder (DVI or HDMI).
properties:
compatible:
const: arm,hdlcd
reg:
maxItems: 1
interrupts:
maxItems: 1
clock-names:
const: pxlclk
clocks:
maxItems: 1
description: The input reference for the pixel clock.
memory-region:
maxItems: 1
description:
Phandle to a node describing memory to be used for the framebuffer.
If not present, the framebuffer may be located anywhere in memory.
iommus:
maxItems: 1
port:
$ref: /schemas/graph.yaml#/properties/port
unevaluatedProperties: false
description:
Output endpoint of the controller, connecting the LCD panel signals.
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- port
examples:
- |
hdlcd@2b000000 {
compatible = "arm,hdlcd";
reg = <0x2b000000 0x1000>;
interrupts = <0 85 4>;
clocks = <&oscclk5>;
clock-names = "pxlclk";
port {
hdlcd_output: endpoint {
remote-endpoint = <&hdmi_enc_input>;
};
};
};
/* HDMI encoder on I2C bus */
i2c {
#address-cells = <1>;
#size-cells = <0>;
hdmi-transmitter@70 {
compatible = "nxp,tda998x";
reg = <0x70>;
port {
hdmi_enc_input: endpoint {
remote-endpoint = <&hdlcd_output>;
};
};
};
};
...
Documentation/devicetree/bindings/display/arm,komeda.txt deleted 100644 → 0
View file @ d223575e
Device Tree bindings for Arm Komeda display driver
Required properties:
- compatible: Should be "arm,mali-d71"
- reg: Physical base address and length of the registers in the system
- interrupts: the interrupt line number of the device in the system
- clocks: A list of phandle + clock-specifier pairs, one for each entry
in 'clock-names'
- clock-names: A list of clock names. It should contain:
- "aclk": for the main processor clock
- #address-cells: Must be 1
- #size-cells: Must be 0
- iommus: configure the stream id to IOMMU, Must be configured if want to
enable iommu in display. for how to configure this node please reference
devicetree/bindings/iommu/arm,smmu-v3.txt,
devicetree/bindings/iommu/iommu.txt
Required properties for sub-node: pipeline@nq
Each device contains one or two pipeline sub-nodes (at least one), each
pipeline node should provide properties:
- reg: Zero-indexed identifier for the pipeline
- clocks: A list of phandle + clock-specifier pairs, one for each entry
in 'clock-names'
- clock-names: should contain:
- "pxclk": pixel clock
- port: each pipeline connect to an encoder input port. The connection is
modeled using the OF graph bindings specified in
Documentation/devicetree/bindings/graph.txt
Optional properties:
- memory-region: phandle to a node describing memory (see
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
to be used for the framebuffer; if not present, the framebuffer may
be located anywhere in memory.
Example:
/ {
...
dp0: display@c00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "arm,mali-d71";
reg = <0xc00000 0x20000>;
interrupts = <0 168 4>;
clocks = <&dpu_aclk>;
clock-names = "aclk";
iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
<&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
<&smmu 8>, <&smmu 9>;
dp0_pipe0: pipeline@0 {
clocks = <&fpgaosc2>;
clock-names = "pxclk";
reg = <0>;
port {
dp0_pipe0_out: endpoint {
remote-endpoint = <&db_dvi0_in>;
};
};
};
dp0_pipe1: pipeline@1 {
clocks = <&fpgaosc2>;
clock-names = "pxclk";
reg = <1>;
port {
dp0_pipe1_out: endpoint {
remote-endpoint = <&db_dvi1_in>;
};
};
};
};
...
};
Documentation/devicetree/bindings/display/arm,komeda.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/arm,komeda.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm Komeda display processor
maintainers:
- Liviu Dudau <Liviu.Dudau@arm.com>
- Andre Przywara <andre.przywara@arm.com>
description:
The Arm Mali D71 display processor supports up to two displays with up
to a 4K resolution each. Each pipeline can be composed of up to four
layers. It is typically connected to a digital display connector like HDMI.
properties:
compatible:
oneOf:
- items:
- const: arm,mali-d32
- const: arm,mali-d71
- const: arm,mali-d71
reg:
maxItems: 1
interrupts:
maxItems: 1
clock-names:
const: aclk
clocks:
maxItems: 1
description: The main DPU processor clock
"#address-cells":
const: 1
"#size-cells":
const: 0
memory-region:
maxItems: 1
description:
Phandle to a node describing memory to be used for the framebuffer.
If not present, the framebuffer may be located anywhere in memory.
iommus:
description:
The stream IDs for each of the used pipelines, each four IDs for the
four layers, plus one for the write-back stream.
minItems: 5
maxItems: 10
patternProperties:
'^pipeline@[01]$':
type: object
description:
clocks
properties:
reg:
enum: [ 0, 1 ]
clock-names:
const: pxclk
clocks:
maxItems: 1
description: The input reference for the pixel clock.
port:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
additionalProperties: false
required:
- "#address-cells"
- "#size-cells"
- compatible
- reg
- interrupts
- clock-names
- clocks
- pipeline@0
examples:
- |
display@c00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "arm,mali-d71";
reg = <0xc00000 0x20000>;
interrupts = <168>;
clocks = <&dpu_aclk>;
clock-names = "aclk";
iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
<&smmu 8>,
<&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
<&smmu 9>;
dp0_pipe0: pipeline@0 {
clocks = <&fpgaosc2>;
clock-names = "pxclk";
reg = <0>;
port {
dp0_pipe0_out: endpoint {
remote-endpoint = <&db_dvi0_in>;
};
};
};
dp0_pipe1: pipeline@1 {
clocks = <&fpgaosc2>;
clock-names = "pxclk";
reg = <1>;
port {
dp0_pipe1_out: endpoint {
remote-endpoint = <&db_dvi1_in>;
};
};
};
};
...
Documentation/devicetree/bindings/display/arm,malidp.txt deleted 100644 → 0
View file @ d223575e
ARM Mali-DP
The following bindings apply to a family of Display Processors sold as
licensable IP by ARM Ltd. The bindings describe the Mali DP500, DP550 and
DP650 processors that offer multiple composition layers, support for
rotation and scaling output.
Required properties:
- compatible: should be one of
"arm,mali-dp500"
"arm,mali-dp550"
"arm,mali-dp650"
depending on the particular implementation present in the hardware
- reg: Physical base address and size of the block of registers used by
the processor.
- interrupts: Interrupt list, as defined in ../interrupt-controller/interrupts.txt,
interrupt client nodes.
- interrupt-names: name of the engine inside the processor that will
use the corresponding interrupt. Should be one of "DE" or "SE".
- clocks: A list of phandle + clock-specifier pairs, one for each entry
in 'clock-names'
- clock-names: A list of clock names. It should contain:
- "pclk": for the APB interface clock
- "aclk": for the AXI interface clock
- "mclk": for the main processor clock
- "pxlclk": for the pixel clock feeding the output PLL of the processor.
- arm,malidp-output-port-lines: Array of u8 values describing the number
of output lines per channel (R, G and B).
Required sub-nodes:
- port: The Mali DP connection to an encoder input port. The connection
is modelled using the OF graph bindings specified in
Documentation/devicetree/bindings/graph.txt
Optional properties:
- memory-region: phandle to a node describing memory (see
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
to be used for the framebuffer; if not present, the framebuffer may
be located anywhere in memory.
- arm,malidp-arqos-high-level: integer of u32 value describing the ARQoS
levels of DP500's QoS signaling.
Example:
/ {
...
dp0: malidp@6f200000 {
compatible = "arm,mali-dp650";
reg = <0 0x6f200000 0 0x20000>;
memory-region = <&display_reserved>;
interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>,
<0 168 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "DE", "SE";
clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>;
clock-names = "pxlclk", "mclk", "aclk", "pclk";
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
arm,malidp-arqos-high-level = <0xd000d000>;
port {
dp0_output: endpoint {
remote-endpoint = <&tda998x_2_input>;
};
};
};
...
};
Documentation/devicetree/bindings/display/arm,malidp.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/arm,malidp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm Mali Display Processor (Mali-DP) binding
maintainers:
- Liviu Dudau <Liviu.Dudau@arm.com>
- Andre Przywara <andre.przywara@arm.com>
description:
The following bindings apply to a family of Display Processors sold as
licensable IP by ARM Ltd. The bindings describe the Mali DP500, DP550 and
DP650 processors that offer multiple composition layers, support for
rotation and scaling output.
properties:
compatible:
enum:
- arm,mali-dp500
- arm,mali-dp550
- arm,mali-dp650
reg:
maxItems: 1
interrupts:
items:
- description:
The interrupt used by the Display Engine (DE). Can be shared with
the interrupt for the Scaling Engine (SE), but it will have to be
listed individually.
- description:
The interrupt used by the Scaling Engine (SE). Can be shared with
the interrupt for the Display Engine (DE), but it will have to be
listed individually.
interrupt-names:
items:
- const: DE
- const: SE
clock-names:
items:
- const: pxlclk
- const: mclk
- const: aclk
- const: pclk
clocks:
items:
- description: the pixel clock feeding the output PLL of the processor
- description: the main processor clock
- description: the AXI interface clock
- description: the APB interface clock
memory-region:
maxItems: 1
description:
Phandle to a node describing memory to be used for the framebuffer.
If not present, the framebuffer may be located anywhere in memory.
arm,malidp-output-port-lines:
$ref: /schemas/types.yaml#/definitions/uint8-array
description:
Number of output lines/bits for each colour channel.
items:
- description: number of output lines for the red channel (R)
- description: number of output lines for the green channel (G)
- description: number of output lines for the blue channel (B)
arm,malidp-arqos-high-level:
$ref: /schemas/types.yaml#/definitions/uint32
description:
integer describing the ARQoS levels of DP500's QoS signaling
arm,malidp-arqos-value:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Quality-of-Service value for the display engine FIFOs, to write
into the RQOS register of the DP500.
See the ARM Mali-DP500 TRM for details on the encoding.
If omitted, the RQOS register will not be changed.
port:
$ref: /schemas/graph.yaml#/properties/port
unevaluatedProperties: false
description:
Output endpoint of the controller, connecting the LCD panel signals.
additionalProperties: false
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
- clock-names
- port
- arm,malidp-output-port-lines
examples:
- |
dp0: malidp@6f200000 {
compatible = "arm,mali-dp650";
reg = <0x6f200000 0x20000>;
memory-region = <&display_reserved>;
interrupts = <168>, <168>;
interrupt-names = "DE", "SE";
clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>;
clock-names = "pxlclk", "mclk", "aclk", "pclk";
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
arm,malidp-arqos-high-level = <0xd000d000>;
port {
dp0_output: endpoint {
remote-endpoint = <&tda998x_2_input>;
};
};
};
...
Documentation/devicetree/bindings/display/arm,pl11x.txt deleted 100644 → 0
View file @ d223575e
* ARM PrimeCell Color LCD Controller PL110/PL111
See also Documentation/devicetree/bindings/arm/primecell.yaml
Required properties:
- compatible: must be one of:
"arm,pl110", "arm,primecell"
"arm,pl111", "arm,primecell"
- reg: base address and size of the control registers block
- interrupt-names: either the single entry "combined" representing a
combined interrupt output (CLCDINTR), or the four entries
"mbe", "vcomp", "lnbu", "fuf" representing the individual
CLCDMBEINTR, CLCDVCOMPINTR, CLCDLNBUINTR, CLCDFUFINTR interrupts
- interrupts: contains an interrupt specifier for each entry in
interrupt-names
- clock-names: should contain "clcdclk" and "apb_pclk"
- clocks: contains phandle and clock specifier pairs for the entries
in the clock-names property. See
Documentation/devicetree/bindings/clock/clock-bindings.txt
Optional properties:
- memory-region: phandle to a node describing memory (see
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
to be used for the framebuffer; if not present, the framebuffer
may be located anywhere in the memory
- max-memory-bandwidth: maximum bandwidth in bytes per second that the
cell's memory interface can handle; if not present, the memory
interface is fast enough to handle all possible video modes
Required sub-nodes:
- port: describes LCD panel signals, following the common binding
for video transmitter interfaces; see
Documentation/devicetree/bindings/media/video-interfaces.txt
Deprecated properties:
The port's endbpoint subnode had this, now deprecated property
in the past. Drivers should be able to survive without it:
- arm,pl11x,tft-r0g0b0-pads: an array of three 32-bit values,
defining the way CLD pads are wired up; first value
contains index of the "CLD" external pin (pad) used
as R0 (first bit of the red component), second value
index of the pad used as G0, third value index of the
pad used as B0, see also "LCD panel signal multiplexing
details" paragraphs in the PL110/PL111 Technical
Reference Manuals; this implicitly defines available
color modes, for example:
- PL111 TFT 4:4:4 panel:
arm,pl11x,tft-r0g0b0-pads = <4 15 20>;
- PL110 TFT (1:)5:5:5 panel:
arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
- PL111 TFT (1:)5:5:5 panel:
arm,pl11x,tft-r0g0b0-pads = <3 11 19>;
- PL111 TFT 5:6:5 panel:
arm,pl11x,tft-r0g0b0-pads = <3 10 19>;
- PL110 and PL111 TFT 8:8:8 panel:
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
- PL110 and PL111 TFT 8:8:8 panel, R & B components swapped:
arm,pl11x,tft-r0g0b0-pads = <16 8 0>;
Example:
clcd@10020000 {
compatible = "arm,pl111", "arm,primecell";
reg = <0x10020000 0x1000>;
interrupt-names = "combined";
interrupts = <0 44 4>;
clocks = <&oscclk1>, <&oscclk2>;
clock-names = "clcdclk", "apb_pclk";
max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */
port {
clcd_pads: endpoint {
remote-endpoint = <&clcd_panel>;
};
};
};
panel {
compatible = "panel-dpi";
port {
clcd_panel: endpoint {
remote-endpoint = <&clcd_pads>;
};
};
panel-timing {
clock-frequency = <25175000>;
hactive = <640>;
hback-porch = <40>;
hfront-porch = <24>;
hsync-len = <96>;
vactive = <480>;
vback-porch = <32>;
vfront-porch = <11>;
vsync-len = <2>;
};
};
Documentation/devicetree/bindings/display/arm,pl11x.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/arm,pl11x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm PrimeCell Color LCD Controller PL110/PL111
maintainers:
- Liviu Dudau <Liviu.Dudau@arm.com>
- Andre Przywara <andre.przywara@arm.com>
description:
The Arm Primcell PL010/PL111 is an LCD controller IP, than scans out
a framebuffer region in system memory, and creates timed signals for
a variety of LCD panels.
# We need a select here so we don't match all nodes with 'arm,primecell'
select:
properties:
compatible:
contains:
enum:
- arm,pl110
- arm,pl111
required:
- compatible
properties:
compatible:
items:
- enum:
- arm,pl110
- arm,pl111
- const: arm,primecell
reg:
maxItems: 1
interrupt-names:
oneOf:
- const: combined
description:
The IP provides four individual interrupt lines, but also one
combined line. If the integration only connects this line to the
interrupt controller, this single interrupt is noted here.
- items:
- const: mbe # CLCDMBEINTR
- const: vcomp # CLCDVCOMPINTR
- const: lnbu # CLCDLNBUINTR
- const: fuf # CLCDFUFINTR
interrupts:
minItems: 1
maxItems: 4
clock-names:
items:
- const: clcdclk
- const: apb_pclk
clocks:
items:
- description: The CLCDCLK reference clock for the controller.
- description: The HCLK AHB slave clock for the register access.
memory-region:
maxItems: 1
description:
Phandle to a node describing memory to be used for the framebuffer.
If not present, the framebuffer may be located anywhere in memory.
max-memory-bandwidth:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Maximum bandwidth in bytes per second that the cell's memory interface
can handle.
If not present, the memory interface is fast enough to handle all
possible video modes.
port:
$ref: /schemas/graph.yaml#/$defs/port-base
additionalProperties: false
description:
Output endpoint of the controller, connecting the LCD panel signals.
properties:
endpoint:
$ref: /schemas/graph.yaml#/$defs/endpoint-base
unevaluatedProperties: false
properties:
arm,pl11x,tft-r0g0b0-pads:
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: index of CLD pad used for first red bit (R0)
- description: index of CLD pad used for first green bit (G0)
- description: index of CLD pad used for first blue bit (G0)
deprecated: true
description: |
DEPRECATED. An array of three 32-bit values, defining the way
CLD[23:0] pads are wired up.
The first value contains the index of the "CLD" external pin (pad)
used as R0 (first bit of the red component), the second value for
green, the third value for blue.
See also "LCD panel signal multiplexing details" paragraphs in the
PL110/PL111 Technical Reference Manuals.
This implicitly defines available color modes, for example:
- PL111 TFT 4:4:4 panel:
arm,pl11x,tft-r0g0b0-pads = <4 15 20>;
- PL110 TFT (1:)5:5:5 panel:
arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
- PL111 TFT (1:)5:5:5 panel:
arm,pl11x,tft-r0g0b0-pads = <3 11 19>;
- PL111 TFT 5:6:5 panel:
arm,pl11x,tft-r0g0b0-pads = <3 10 19>;
- PL110 and PL111 TFT 8:8:8 panel:
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
- PL110 and PL111 TFT 8:8:8 panel, R & B components swapped:
arm,pl11x,tft-r0g0b0-pads = <16 8 0>;
additionalProperties: false
required:
- compatible
- reg
- clock-names
- clocks
- port
allOf:
- if:
properties:
interrupts:
minItems: 2
required:
- interrupts
then:
required:
- interrupt-names
examples:
- |
clcd@10020000 {
compatible = "arm,pl111", "arm,primecell";
reg = <0x10020000 0x1000>;
interrupt-names = "combined";
interrupts = <44>;
clocks = <&oscclk1>, <&oscclk2>;
clock-names = "clcdclk", "apb_pclk";
max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */
port {
clcd_pads: endpoint {
remote-endpoint = <&clcd_panel>;
};
};
};
panel {
compatible = "arm,rtsm-display", "panel-dpi";
power-supply = <&vcc_supply>;
port {
clcd_panel: endpoint {
remote-endpoint = <&clcd_pads>;
};
};
panel-timing {
clock-frequency = <25175000>;
hactive = <640>;
hback-porch = <40>;
hfront-porch = <24>;
hsync-len = <96>;
vactive = <480>;
vback-porch = <32>;
vfront-porch = <11>;
vsync-len = <2>;
};
};
...
Documentation/devicetree/bindings/display/bridge/toshiba,tc358768.yaml
View file @ 86c87bea
......@@ -58,6 +58,7 @@ properties:
properties:
data-lines:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 16, 18, 24 ]
port@1:
......
Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
View file @ 86c87bea
......@@ -102,4 +102,3 @@ examples:
clock-names = "merge";
};
};
Documentation/devicetree/bindings/display/panel/panel-timing.yaml
View file @ 86c87bea
......@@ -146,6 +146,7 @@ properties:
Horizontal sync pulse.
0 selects active low, 1 selects active high.
If omitted then it is not used by the hardware
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
vsync-active:
......@@ -153,6 +154,7 @@ properties:
Vertical sync pulse.
0 selects active low, 1 selects active high.
If omitted then it is not used by the hardware
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
de-active:
......@@ -160,6 +162,7 @@ properties:
Data enable.
0 selects active low, 1 selects active high.
If omitted then it is not used by the hardware
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
pixelclk-active:
......@@ -169,6 +172,7 @@ properties:
sample data on rising edge.
Use 1 to drive pixel data on rising edge and
sample data on falling edge
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
syncclk-active:
......@@ -179,6 +183,7 @@ properties:
sample sync on rising edge of pixel clock.
Use 1 to drive sync on rising edge and
sample sync on falling edge of pixel clock
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
interlaced:
......
Documentation/devicetree/bindings/display/panel/raydium,rm67191.yaml
View file @ 86c87bea
......@@ -24,6 +24,7 @@ properties:
dsi-lanes:
description: Number of DSI lanes to be used must be <3> or <4>
$ref: /schemas/types.yaml#/definitions/uint32
enum: [3, 4]
v3p3-supply:
......
Documentation/devicetree/bindings/display/panel/samsung,s6e8aa0.yaml
View file @ 86c87bea
......@@ -36,6 +36,7 @@ properties:
init-delay:
description: delay after initialization sequence [ms]
$ref: /schemas/types.yaml#/definitions/uint32
panel-width-mm:
description: physical panel width [mm]
......
Documentation/devicetree/bindings/display/sprd/sprd,display-subsystem.yaml
View file @ 86c87bea
......@@ -63,4 +63,3 @@ examples:
compatible = "sprd,display-subsystem";
ports = <&dpu_out>;
};
Documentation/devicetree/bindings/eeprom/at24.yaml
View file @ 86c87bea
......@@ -120,7 +120,9 @@ properties:
- const: giantec,gt24c32a
- const: atmel,24c32
- items:
- const: renesas,r1ex24128
- enum:
- renesas,r1ex24128
- samsung,s524ad0xd1
- const: atmel,24c128
label:
......
Documentation/devicetree/bindings/example-schema.yaml
View file @ 86c87bea
......@@ -249,7 +249,7 @@ examples:
# be overridden or an appropriate parent bus node should be shown (such as on
# i2c buses).
#
# Any includes used have to be explicitly included.
# Any includes used have to be explicitly included. Use 4-space indentation.
- |
node@1000 {
compatible = "vendor,soc4-ip", "vendor,soc1-ip";
......
Documentation/devicetree/bindings/gnss/brcm,bcm4751.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gnss/brcm,bcm4751.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM4751 family GNSS Receiver Device Tree Bindings
maintainers:
- Johan Hovold <johan@kernel.org>
- Linus Walleij <linus.walleij@linaro.org>
description:
Broadcom GPS chips can be used over the UART or I2C bus. The UART
bus requires CTS/RTS support. The number of the capsule is more
elaborate than the compatibles BCM4751 may be printed
BCM4751IFBG for example.
allOf:
- $ref: gnss-common.yaml#
properties:
compatible:
enum:
- brcm,bcm4751
- brcm,bcm4752
- brcm,bcm4753
reg:
description:
The I2C Address, not required on UART buses.
vdd-auxin-supply:
description:
Main voltage supply, pin name VDD_AUXIN, typically connected
directly to a battery such as LiIon 3.8V battery or a 2.6V supply.
vddio-supply:
description:
IO voltage supply, pin name VDDIO, typically 1.8V
reset-gpios:
maxItems: 1
description: An optional active low reset line, should be flagged with
GPIO_ACTIVE_LOW.
enable-gpios:
description: Enable GPIO line, connected to pins named REGPU or NSTANDBY.
If the line is active low such as NSTANDBY, it should be tagged
GPIO_ACTIVE_LOW.
required:
- compatible
- enable-gpios
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
serial {
gnss {
compatible = "brcm,bcm4751";
vdd-auxin-supply = <&vbat>;
reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
enable-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
current-speed = <38400>;
};
};
Documentation/devicetree/bindings/gnss/mediatek.txt deleted 100644 → 0
View file @ d223575e
Mediatek-based GNSS Receiver DT binding
Mediatek chipsets are used in GNSS-receiver modules produced by several
vendors and can use a UART interface.
Please see Documentation/devicetree/bindings/gnss/gnss.txt for generic
properties.
Required properties:
- compatible : Must be
"globaltop,pa6h"
- vcc-supply : Main voltage regulator (pin name: VCC)
Optional properties:
- current-speed : Default UART baud rate
- gnss-fix-gpios : GPIO used to determine device position fix state
(pin name: FIX, 3D_FIX)
- reset-gpios : GPIO used to reset the device (pin name: RESET, NRESET)
- timepulse-gpios : Time pulse GPIO (pin name: PPS1, 1PPS)
- vbackup-supply : Backup voltage regulator (pin name: VBAT, VBACKUP)
Example:
serial@1234 {
compatible = "ns16550a";
gnss {
compatible = "globaltop,pa6h";
vcc-supply = <&vcc_3v3>;
};
};
Documentation/devicetree/bindings/gnss/mediatek.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gnss/mediatek.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek GNSS Receiver Device Tree Bindings
maintainers:
- Johan Hovold <johan@kernel.org>
description:
Mediatek chipsets are used in GNSS-receiver modules produced by several
vendors and can use a UART interface.
allOf:
- $ref: gnss-common.yaml#
properties:
compatible:
const: globaltop,pa6h
vcc-supply:
description:
Main voltage regulator, pin name VCC.
reset-gpios:
maxItems: 1
description: An optional reset line, with names such as RESET or NRESET.
If the line is active low it should be flagged with GPIO_ACTIVE_LOW.
timepulse-gpios:
description: Comes with pin names such as PPS1 or 1PPS.
gnss-fix-gpios:
maxItems: 1
description: GPIO used to determine device position fix state, pin names
FIX or 3D_FIX.
vbackup-supply:
description:
Regulator providing backup voltage, pin names such as VBAT or VBACKUP.
required:
- compatible
- vcc-supply
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
serial {
gnss {
compatible = "globaltop,pa6h";
vcc-supply = <&vcc_3v3>;
reset-gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
};
};
Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml
View file @ 86c87bea
......@@ -26,6 +26,7 @@ properties:
const: 2
registers-number:
$ref: /schemas/types.yaml#/definitions/uint32
description: Number of daisy-chained shift registers
enable-gpios:
......
Documentation/devicetree/bindings/gpu/samsung-rotator.yaml
View file @ 86c87bea
......@@ -53,4 +53,3 @@ examples:
clocks = <&clock 278>;
clock-names = "rotator";
};
Documentation/devicetree/bindings/hwmon/adt7475.yaml
View file @ 86c87bea
......@@ -103,4 +103,3 @@ examples:
adi,pin14-function = "tach4";
};
};
Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt deleted 100644 → 0
View file @ d223575e
* MediaTek's I2C controller
The MediaTek's I2C controller is used to interface with I2C devices.
Required properties:
- compatible: value should be either of the following.
"mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for MediaTek MT2701
"mediatek,mt2712-i2c": for MediaTek MT2712
"mediatek,mt6577-i2c": for MediaTek MT6577
"mediatek,mt6589-i2c": for MediaTek MT6589
"mediatek,mt6797-i2c", "mediatek,mt6577-i2c": for MediaTek MT6797
"mediatek,mt7622-i2c": for MediaTek MT7622
"mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
"mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
"mediatek,mt8168-i2c": for MediaTek MT8168
"mediatek,mt8173-i2c": for MediaTek MT8173
"mediatek,mt8183-i2c": for MediaTek MT8183
"mediatek,mt8186-i2c": for MediaTek MT8186
"mediatek,mt8192-i2c": for MediaTek MT8192
"mediatek,mt8195-i2c", "mediatek,mt8192-i2c": for MediaTek MT8195
"mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516
- reg: physical base address of the controller and dma base, length of memory
mapped region.
- interrupts: interrupt number to the cpu.
- clock-div: the fixed value for frequency divider of clock source in i2c
module. Each IC may be different.
- clocks: clock name from clock manager
- clock-names: Must include "main" and "dma", "arb" is for multi-master that
one bus has more than two i2c controllers, if enable have-pmic need include
"pmic" extra.
Optional properties:
- clock-frequency: Frequency in Hz of the bus when transfer, the default value
is 100000.
- mediatek,have-pmic: platform can control i2c form special pmic side.
Only mt6589 and mt8135 support this feature.
- mediatek,use-push-pull: IO config use push-pull mode.
- vbus-supply: phandle to the regulator that provides power to SCL/SDA.
Example:
i2c0: i2c@1100d000 {
compatible = "mediatek,mt6577-i2c";
reg = <0x1100d000 0x70>,
<0x11000300 0x80>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <400000>;
mediatek,have-pmic;
clock-div = <16>;
clocks = <&i2c0_ck>, <&ap_dma_ck>;
clock-names = "main", "dma";
};
Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-mt65xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek I2C controller
description:
This driver interfaces with the native I2C controller present in
various MediaTek SoCs.
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
maintainers:
- Qii Wang <qii.wang@mediatek.com>
properties:
compatible:
oneOf:
- const: mediatek,mt2712-i2c
- const: mediatek,mt6577-i2c
- const: mediatek,mt6589-i2c
- const: mediatek,mt7622-i2c
- const: mediatek,mt8168-i2c
- const: mediatek,mt8173-i2c
- const: mediatek,mt8183-i2c
- const: mediatek,mt8186-i2c
- const: mediatek,mt8192-i2c
- items:
- enum:
- mediatek,mt7629-i2c
- mediatek,mt8516-i2c
- const: mediatek,mt2712-i2c
- items:
- enum:
- mediatek,mt2701-i2c
- mediatek,mt6797-i2c
- mediatek,mt7623-i2c
- const: mediatek,mt6577-i2c
- items:
- enum:
- mediatek,mt8195-i2c
- const: mediatek,mt8192-i2c
reg:
items:
- description: Physical base address
- description: DMA base address
interrupts:
maxItems: 1
clocks:
minItems: 2
items:
- description: Main clock for I2C bus
- description: Clock for I2C via DMA
- description: Bus arbitrator clock
- description: Clock for I2C from PMIC
clock-names:
minItems: 2
items:
- const: main
- const: dma
- const: arb
- const: pmic
clock-div:
$ref: /schemas/types.yaml#/definitions/uint32
description: Frequency divider of clock source in I2C module
clock-frequency:
default: 100000
description:
SCL frequency to use (in Hz). If omitted, 100kHz is used.
mediatek,have-pmic:
description: Platform controls I2C from PMIC side
type: boolean
mediatek,use-push-pull:
description: Use push-pull mode I/O config
type: boolean
vbus-supply:
description: Phandle to the regulator providing power to SCL/SDA
required:
- compatible
- reg
- clocks
- clock-names
- clock-div
- interrupts
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c0: i2c@1100d000 {
compatible = "mediatek,mt6577-i2c";
reg = <0x1100d000 0x70>, <0x11000300 0x80>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
clocks = <&i2c0_ck>, <&ap_dma_ck>;
clock-names = "main", "dma";
clock-div = <16>;
clock-frequency = <400000>;
mediatek,have-pmic;
#address-cells = <1>;
#size-cells = <0>;
};
Documentation/devicetree/bindings/i2c/i2c-mux-gpmux.yaml
View file @ 86c87bea
......@@ -28,7 +28,6 @@ description: |+
'------------' '-----' '-----' '-----'
allOf:
- $ref: /schemas/i2c/i2c-mux.yaml#
......
Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/i2c/qcom,i2c-geni-qcom.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Geni based QUP I2C Controller
maintainers:
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
properties:
compatible:
const: qcom,geni-i2c
clocks:
maxItems: 1
clock-names:
const: se
clock-frequency:
default: 100000
dmas:
maxItems: 2
dma-names:
items:
- const: tx
- const: rx
interconnects:
maxItems: 3
interconnect-names:
items:
- const: qup-core
- const: qup-config
- const: qup-memory
interrupts:
maxItems: 1
pinctrl-0: true
pinctrl-1: true
pinctrl-names:
minItems: 1
items:
- const: default
- const: sleep
power-domains:
maxItems: 1
reg:
maxItems: 1
required-opps:
maxItems: 1
required:
- compatible
- interrupts
- clocks
- clock-names
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
#include <dt-bindings/interconnect/qcom,sc7180.h>
#include <dt-bindings/power/qcom-rpmpd.h>
i2c@88000 {
compatible = "qcom,geni-i2c";
reg = <0x00880000 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
power-domains = <&rpmhpd SC7180_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...
Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt deleted 100644 → 0
View file @ d223575e
Qualcomm Universal Peripheral (QUP) I2C controller
Required properties:
- compatible: Should be:
* "qcom,i2c-qup-v1.1.1" for 8660, 8960 and 8064.
* "qcom,i2c-qup-v2.1.1" for 8974 v1.
* "qcom,i2c-qup-v2.2.1" for 8974 v2 and later.
- reg: Should contain QUP register address and length.
- interrupts: Should contain I2C interrupt.
- clocks: A list of phandles + clock-specifiers, one for each entry in
clock-names.
- clock-names: Should contain:
* "core" for the core clock
* "iface" for the AHB clock
- #address-cells: Should be <1> Address cells for i2c device address
- #size-cells: Should be <0> as i2c addresses have no size component
Optional properties:
- clock-frequency: Should specify the desired i2c bus clock frequency in Hz,
defaults to 100kHz if omitted.
Child nodes should conform to i2c bus binding.
Example:
i2c@f9924000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9924000 0x1000>;
interrupts = <0 96 0>;
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <355000>;
#address-cells = <1>;
#size-cells = <0>;
};
Documentation/devicetree/bindings/i2c/qcom,i2c-qup.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/qcom,i2c-qup.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Universal Peripheral (QUP) I2C controller
maintainers:
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
properties:
compatible:
enum:
- qcom,i2c-qup-v1.1.1 # for 8660, 8960 and 8064
- qcom,i2c-qup-v2.1.1 # for 8974 v1
- qcom,i2c-qup-v2.2.1 # for 8974 v2 and later
clocks:
maxItems: 2
clock-names:
items:
- const: core
- const: iface
clock-frequency:
default: 100000
dmas:
maxItems: 2
dma-names:
items:
- const: tx
- const: rx
interrupts:
maxItems: 1
pinctrl-0: true
pinctrl-1: true
pinctrl-names:
minItems: 1
items:
- const: default
- const: sleep
reg:
maxItems: 1
required:
- compatible
- clock-names
- clocks
- interrupts
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8998.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
i2c@c175000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c175000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c1_default>;
pinctrl-1 = <&blsp1_i2c1_sleep>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
Documentation/devicetree/bindings/i2c/renesas,riic.yaml
View file @ 86c87bea
......@@ -19,6 +19,7 @@ properties:
- enum:
- renesas,riic-r7s72100 # RZ/A1H
- renesas,riic-r7s9210 # RZ/A2M
- renesas,riic-r9a07g043 # RZ/G2UL
- renesas,riic-r9a07g044 # RZ/G2{L,LC}
- renesas,riic-r9a07g054 # RZ/V2L
- const: renesas,riic-rz # RZ/A or RZ/G2L
......@@ -75,6 +76,7 @@ if:
compatible:
contains:
enum:
- renesas,riic-r9a07g043
- renesas,riic-r9a07g044
- renesas,riic-r9a07g054
then:
......
Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml
View file @ 86c87bea
......@@ -123,7 +123,7 @@ examples:
samsung,i2c-slave-addr = <0x66>;
eeprom@50 {
compatible = "samsung,s524ad0xd1";
compatible = "samsung,s524ad0xd1", "atmel,24c128";
reg = <0x50>;
};
};
......
Documentation/devicetree/bindings/input/google,cros-ec-keyb.yaml
View file @ 86c87bea
......@@ -31,6 +31,7 @@ properties:
type: boolean
function-row-physmap:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 15
description: |
......
Documentation/devicetree/bindings/input/ilitek,ili2xxx.txt deleted 100644 → 0
View file @ d223575e
Ilitek ILI210x/ILI2117/ILI2120/ILI251x touchscreen controller
Required properties:
- compatible:
ilitek,ili210x for ILI210x
ilitek,ili2117 for ILI2117
ilitek,ili2120 for ILI2120
ilitek,ili251x for ILI251x
- reg: The I2C address of the device
- interrupts: The sink for the touchscreen's IRQ output
See ../interrupt-controller/interrupts.txt
Optional properties for main touchpad device:
- reset-gpios: GPIO specifier for the touchscreen's reset pin (active low)
Example:
touchscreen@41 {
compatible = "ilitek,ili251x";
reg = <0x41>;
interrupt-parent = <&gpio4>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
};
Documentation/devicetree/bindings/input/touchscreen/ilitek_ts_i2c.yaml
View file @ 86c87bea
......@@ -15,6 +15,9 @@ allOf:
properties:
compatible:
enum:
- ilitek,ili210x
- ilitek,ili2117
- ilitek,ili2120
- ilitek,ili2130
- ilitek,ili2131
- ilitek,ili2132
......@@ -22,11 +25,12 @@ properties:
- ilitek,ili2322
- ilitek,ili2323
- ilitek,ili2326
- ilitek,ili251x
- ilitek,ili2520
- ilitek,ili2521
reg:
const: 0x41
maxItems: 1
interrupts:
maxItems: 1
......@@ -50,7 +54,6 @@ required:
- compatible
- reg
- interrupts
- reset-gpios
examples:
- |
......
Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt deleted 100644 → 0
View file @ d223575e
* Freescale Layerscape external IRQs
Some Layerscape SOCs (LS1021A, LS1043A, LS1046A
LS1088A, LS208xA, LX216xA) support inverting
the polarity of certain external interrupt lines.
The device node must be a child of the node representing the
Supplemental Configuration Unit (SCFG).
Required properties:
- compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq".
"fsl,ls1043a-extirq": for LS1043A, LS1046A.
"fsl,ls1088a-extirq": for LS1088A, LS208xA, LX216xA.
- #interrupt-cells: Must be 2. The first element is the index of the
external interrupt line. The second element is the trigger type.
- #address-cells: Must be 0.
- interrupt-controller: Identifies the node as an interrupt controller
- reg: Specifies the Interrupt Polarity Control Register (INTPCR) in
the SCFG or the External Interrupt Control Register (IRQCR) in
the ISC.
- interrupt-map: Specifies the mapping from external interrupts to GIC
interrupts.
- interrupt-map-mask: Must be <0xffffffff 0>.
Example:
scfg: scfg@1570000 {
compatible = "fsl,ls1021a-scfg", "syscon";
reg = <0x0 0x1570000 0x0 0x10000>;
big-endian;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x1570000 0x10000>;
extirq: interrupt-controller@1ac {
compatible = "fsl,ls1021a-extirq";
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
reg = <0x1ac 4>;
interrupt-map =
<0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0xffffffff 0x0>;
};
};
interrupts-extended = <&gic GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<&extirq 1 IRQ_TYPE_LEVEL_LOW>;
Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-extirq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Layerscape External Interrupt Controller
maintainers:
- Shawn Guo <shawnguo@kernel.org>
- Li Yang <leoyang.li@nxp.com>
description: |
Some Layerscape SOCs (LS1021A, LS1043A, LS1046A LS1088A, LS208xA,
LX216xA) support inverting the polarity of certain external interrupt
lines.
properties:
compatible:
oneOf:
- enum:
- fsl,ls1021a-extirq
- fsl,ls1043a-extirq
- fsl,ls1088a-extirq
- items:
- enum:
- fsl,ls1046a-extirq
- const: fsl,ls1043a-extirq
- items:
- enum:
- fsl,ls2080a-extirq
- fsl,lx2160a-extirq
- const: fsl,ls1088a-extirq
'#interrupt-cells':
const: 2
'#address-cells':
const: 0
interrupt-controller: true
reg:
maxItems: 1
description:
Specifies the Interrupt Polarity Control Register (INTPCR) in the
SCFG or the External Interrupt Control Register (IRQCR) in the ISC.
interrupt-map:
description: Specifies the mapping from external interrupts to GIC interrupts.
interrupt-map-mask: true
required:
- compatible
- '#interrupt-cells'
- '#address-cells'
- interrupt-controller
- reg
- interrupt-map
- interrupt-map-mask
allOf:
- if:
properties:
compatible:
contains:
enum:
- fsl,ls1021a-extirq
then:
properties:
interrupt-map:
minItems: 6
maxItems: 6
interrupt-map-mask:
items:
- const: 0x7
- const: 0
- if:
properties:
compatible:
contains:
enum:
- fsl,ls1043a-extirq
- fsl,ls1046a-extirq
- fsl,ls1088a-extirq
- fsl,ls2080a-extirq
- fsl,lx2160a-extirq
then:
properties:
interrupt-map:
minItems: 12
maxItems: 12
interrupt-map-mask:
items:
- const: 0xf
- const: 0
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
interrupt-controller@1ac {
compatible = "fsl,ls1021a-extirq";
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
reg = <0x1ac 4>;
interrupt-map =
<0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0x7 0x0>;
};
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
View file @ 86c87bea
......@@ -21,8 +21,9 @@ Properties:
- "qcom,sc7180-pdc": For SC7180
- "qcom,sc7280-pdc": For SC7280
- "qcom,sdm845-pdc": For SDM845
- "qcom,sdm8250-pdc": For SM8250
- "qcom,sdm8350-pdc": For SM8350
- "qcom,sm6350-pdc": For SM6350
- "qcom,sm8250-pdc": For SM8250
- "qcom,sm8350-pdc": For SM8350
- reg:
Usage: required
......
Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
View file @ 86c87bea
......@@ -37,12 +37,18 @@ properties:
hardware supports just a single, combined interrupt line.
If provided, then the combined interrupt will be used in preference to
any others.
- minItems: 2
- minItems: 1
items:
- const: eventq # Event Queue not empty
- const: gerror # Global Error activated
- const: priq # PRI Queue not empty
- const: cmdq-sync # CMD_SYNC complete
- enum:
- eventq # Event Queue not empty
- gerror # Global Error activated
- const: gerror
- enum:
- cmdq-sync # CMD_SYNC complete
- priq # PRI Queue not empty
- enum:
- cmdq-sync
- priq
'#iommu-cells':
const: 1
......
Documentation/devicetree/bindings/iommu/samsung,sysmmu.yaml
View file @ 86c87bea
......@@ -107,4 +107,3 @@ examples:
power-domains = <&pd_gsc>;
#iommu-cells = <0>;
};
Documentation/devicetree/bindings/leds/leds-mt6360.yaml
View file @ 86c87bea
......@@ -11,7 +11,7 @@ maintainers:
description: |
This module is part of the MT6360 MFD device.
see Documentation/devicetree/bindings/mfd/mt6360.yaml
see Documentation/devicetree/bindings/mfd/mediatek,mt6360.yaml
Add MT6360 LED driver include 2-channel Flash LED with torch/strobe mode,
and 4-channel RGB LED support Register/Flash/Breath Mode
......
Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml
View file @ 86c87bea
......@@ -51,4 +51,3 @@ examples:
interrupts = <208>, <209>, <210>;
#mbox-cells = <1>;
};
Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
View file @ 86c87bea
......@@ -27,6 +27,7 @@ properties:
- qcom,sm6350-ipcc
- qcom,sm8250-ipcc
- qcom,sm8350-ipcc
- qcom,sm8450-ipcc
- qcom,sc7280-ipcc
- const: qcom,ipcc
......
Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt deleted 100644 → 0
View file @ d223575e
Xilinx IPI Mailbox Controller
========================================
The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
agent owns registers used for notification and buffers for message.
+-------------------------------------+
| Xilinx ZynqMP IPI Controller |
+-------------------------------------+
+--------------------------------------------------+
ATF | |
| |
| |
+--------------------------+ |
| |
| |
+--------------------------------------------------+
+------------------------------------------+
| +----------------+ +----------------+ |
Hardware | | IPI Agent | | IPI Buffers | |
| | Registers | | | |
| | | | | |
| +----------------+ +----------------+ |
| |
| Xilinx IPI Agent Block |
+------------------------------------------+
Controller Device Node:
===========================
Required properties:
--------------------
IPI agent node:
- compatible: Shall be: "xlnx,zynqmp-ipi-mailbox"
- interrupt-parent: Phandle for the interrupt controller
- interrupts: Interrupt information corresponding to the
interrupt-names property.
- xlnx,ipi-id: local Xilinx IPI agent ID
- #address-cells: number of address cells of internal IPI mailbox nodes
- #size-cells: number of size cells of internal IPI mailbox nodes
Internal IPI mailbox node:
- reg: IPI buffers address ranges
- reg-names: Names of the reg resources. It should have:
* local_request_region
- IPI request msg buffer written by local and read
by remote
* local_response_region
- IPI response msg buffer written by local and read
by remote
* remote_request_region
- IPI request msg buffer written by remote and read
by local
* remote_response_region
- IPI response msg buffer written by remote and read
by local
- #mbox-cells: Shall be 1. It contains:
* tx(0) or rx(1) channel
- xlnx,ipi-id: remote Xilinx IPI agent ID of which the mailbox is
connected to.
Optional properties:
--------------------
- method: The method of accessing the IPI agent registers.
Permitted values are: "smc" and "hvc". Default is
"smc".
Client Device Node:
===========================
Required properties:
--------------------
- mboxes: Standard property to specify a mailbox
(See ./mailbox.txt)
- mbox-names: List of identifier strings for each mailbox
channel.
Example:
===========================
zynqmp_ipi {
compatible = "xlnx,zynqmp-ipi-mailbox";
interrupt-parent = <&gic>;
interrupts = <0 29 4>;
xlnx,ipi-id = <0>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* APU<->RPU0 IPI mailbox controller */
ipi_mailbox_rpu0: mailbox@ff990400 {
reg = <0xff990400 0x20>,
<0xff990420 0x20>,
<0xff990080 0x20>,
<0xff9900a0 0x20>;
reg-names = "local_request_region",
"local_response_region",
"remote_request_region",
"remote_response_region";
#mbox-cells = <1>;
xlnx,ipi-id = <1>;
};
/* APU<->RPU1 IPI mailbox controller */
ipi_mailbox_rpu1: mailbox@ff990440 {
reg = <0xff990440 0x20>,
<0xff990460 0x20>,
<0xff990280 0x20>,
<0xff9902a0 0x20>;
reg-names = "local_request_region",
"local_response_region",
"remote_request_region",
"remote_response_region";
#mbox-cells = <1>;
xlnx,ipi-id = <2>;
};
};
rpu0 {
...
mboxes = <&ipi_mailbox_rpu0 0>,
<&ipi_mailbox_rpu0 1>;
mbox-names = "tx", "rx";
};
rpu1 {
...
mboxes = <&ipi_mailbox_rpu1 0>,
<&ipi_mailbox_rpu1 1>;
mbox-names = "tx", "rx";
};
Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Xilinx IPI(Inter Processor Interrupt) mailbox controller
description: |
The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
agent owns registers used for notification and buffers for message.
+-------------------------------------+
| Xilinx ZynqMP IPI Controller |
+-------------------------------------+
+--------------------------------------------------+
TF-A | |
| |
| |
+--------------------------+ |
| |
| |
+--------------------------------------------------+
+------------------------------------------+
| +----------------+ +----------------+ |
Hardware | | IPI Agent | | IPI Buffers | |
| | Registers | | | |
| | | | | |
| +----------------+ +----------------+ |
| |
| Xilinx IPI Agent Block |
+------------------------------------------+
maintainers:
- Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
properties:
compatible:
const: xlnx,zynqmp-ipi-mailbox
method:
description: |
The method of calling the PM-API firmware layer.
Permitted values are.
- "smc" : SMC #0, following the SMCCC
- "hvc" : HVC #0, following the SMCCC
$ref: /schemas/types.yaml#/definitions/string
enum:
- smc
- hvc
default: smc
'#address-cells':
const: 2
'#size-cells':
const: 2
xlnx,ipi-id:
description: |
Remote Xilinx IPI agent ID of which the mailbox is connected to.
$ref: /schemas/types.yaml#/definitions/uint32
interrupts:
maxItems: 1
ranges: true
patternProperties:
'^mailbox@[0-9a-f]+$':
description: Internal ipi mailbox node
type: object # DT nodes are json objects
properties:
xlnx,ipi-id:
description:
Remote Xilinx IPI agent ID of which the mailbox is connected to.
$ref: /schemas/types.yaml#/definitions/uint32
'#mbox-cells':
const: 1
description:
It contains tx(0) or rx(1) channel IPI id number.
reg:
maxItems: 4
reg-names:
items:
- const: local_request_region
- const: local_response_region
- const: remote_request_region
- const: remote_response_region
required:
- reg
- reg-names
- "#mbox-cells"
additionalProperties: false
required:
- compatible
- interrupts
- '#address-cells'
- '#size-cells'
- xlnx,ipi-id
examples:
- |
#include<dt-bindings/interrupt-controller/arm-gic.h>
amba {
#address-cells = <0x2>;
#size-cells = <0x2>;
zynqmp-mailbox {
compatible = "xlnx,zynqmp-ipi-mailbox";
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
xlnx,ipi-id = <0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
mailbox: mailbox@ff9905c0 {
reg = <0x0 0xff9905c0 0x0 0x20>,
<0x0 0xff9905e0 0x0 0x20>,
<0x0 0xff990e80 0x0 0x20>,
<0x0 0xff990ea0 0x0 0x20>;
reg-names = "local_request_region",
"local_response_region",
"remote_request_region",
"remote_response_region";
#mbox-cells = <1>;
xlnx,ipi-id = <4>;
};
};
};
...
Documentation/devicetree/bindings/media/i2c/adv7604.yaml
View file @ 86c87bea
......@@ -60,7 +60,8 @@ properties:
enables hot-plug detection.
default-input:
maxItems: 1
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 0, 1 ]
description:
Select which input is selected after reset.
......
Documentation/devicetree/bindings/mfd/mediatek,mt6360.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/mediatek,mt6360.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MT6360 PMIC from MediaTek Integrated
maintainers:
- Gene Chen <gene_chen@richtek.com>
description: |
MT6360 is a PMIC device with the following sub modules.
It is interfaced to host controller using I2C interface.
This document describes the binding for PMIC device and its sub module.
properties:
compatible:
const: mediatek,mt6360
reg:
maxItems: 1
wakeup-source: true
interrupts:
maxItems: 1
interrupt-names:
const: IRQB
interrupt-controller: true
"#interrupt-cells":
const: 1
description:
The first cell is the IRQ number.
regulators:
$ref: /schemas/regulator/mt6360-regulator.yaml#
charger:
$ref: /schemas/power/supply/mt6360_charger.yaml#
tcpc:
$ref: /schemas/usb/mediatek,mt6360-tcpc.yaml#
led-controller:
$ref: /schemas/leds/leds-mt6360.yaml#
required:
- compatible
- reg
- interrupts
- interrupt-controller
- "#interrupt-cells"
additionalProperties:
type: object
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/usb/pd.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
pmic@34 {
compatible = "mediatek,mt6360";
reg = <0x34>;
wakeup-source;
interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "IRQB";
interrupt-controller;
#interrupt-cells = <1>;
mt6360_charger: charger {
compatible = "mediatek,mt6360-chg";
richtek,vinovp-microvolt = <14500000>;
otg_vbus_regulator: usb-otg-vbus-regulator {
regulator-compatible = "usb-otg-vbus";
regulator-name = "usb-otg-vbus";
regulator-min-microvolt = <4425000>;
regulator-max-microvolt = <5825000>;
};
};
led-controller {
compatible = "mediatek,mt6360-led";
#address-cells = <1>;
#size-cells = <0>;
multi-led@0 {
reg = <0>;
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_RGB>;
led-max-microamp = <24000>;
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_RED>;
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
};
};
led@3 {
reg = <3>;
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_WHITE>;
led-max-microamp = <150000>;
};
led@4 {
reg = <4>;
function = LED_FUNCTION_FLASH;
color = <LED_COLOR_ID_WHITE>;
function-enumerator = <1>;
led-max-microamp = <200000>;
flash-max-microamp = <500000>;
flash-max-timeout-us = <1024000>;
};
led@5 {
reg = <5>;
function = LED_FUNCTION_FLASH;
color = <LED_COLOR_ID_WHITE>;
function-enumerator = <2>;
led-max-microamp = <200000>;
flash-max-microamp = <500000>;
flash-max-timeout-us = <1024000>;
};
};
regulators {
compatible = "mediatek,mt6360-regulator";
LDO_VIN3-supply = <&BUCK2>;
buck1 {
regulator-compatible = "BUCK1";
regulator-name = "mt6360,buck1";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1300000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP
MT6360_OPMODE_ULP>;
};
BUCK2: buck2 {
regulator-compatible = "BUCK2";
regulator-name = "mt6360,buck2";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1300000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP
MT6360_OPMODE_ULP>;
};
ldo6 {
regulator-compatible = "LDO6";
regulator-name = "mt6360,ldo6";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2100000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP>;
};
ldo7 {
regulator-compatible = "LDO7";
regulator-name = "mt6360,ldo7";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2100000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP>;
};
ldo1 {
regulator-compatible = "LDO1";
regulator-name = "mt6360,ldo1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP>;
};
ldo2 {
regulator-compatible = "LDO2";
regulator-name = "mt6360,ldo2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP>;
};
ldo3 {
regulator-compatible = "LDO3";
regulator-name = "mt6360,ldo3";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP>;
};
ldo5 {
regulator-compatible = "LDO5";
regulator-name = "mt6360,ldo5";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3600000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP>;
};
};
tcpc {
compatible = "mediatek,mt6360-tcpc";
interrupts-extended = <&gpio26 3 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "PD_IRQB";
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
power-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 1000, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>;
sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>;
op-sink-microwatt = <10000000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&usb_hs>;
};
};
port@1 {
reg = <1>;
endpoint {
remote-endpoint = <&usb_ss>;
};
};
port@2 {
reg = <2>;
endpoint {
remote-endpoint = <&dp_aux>;
};
};
};
};
};
};
};
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt
View file @ 86c87bea
......@@ -59,7 +59,7 @@ Required properties for peripheral child nodes:
Optional properties for peripheral child nodes:
- interrupts: Interrupts are specified as a 4-tuple. For more information
see:
Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml
- interrupt-names: Corresponding interrupt name to the interrupts property
Each child node of SPMI slave id represents a function of the PMIC. In the
......
Documentation/devicetree/bindings/mtd/hisilicon,fmc-spi-nor.txt
View file @ 86c87bea
......@@ -17,7 +17,7 @@ spi-nor-controller@10000000 {
reg = <0x10000000 0x1000>, <0x14000000 0x1000000>;
reg-names = "control", "memory";
clocks = <&clock HI3519_FMC_CLK>;
spi-nor@0 {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
};
......
Documentation/devicetree/bindings/mux/reg-mux.yaml
View file @ 86c87bea
......@@ -25,8 +25,12 @@ properties:
const: 1
mux-reg-masks:
description: an array of register offset and pre-shifted bitfield mask
pairs, each describing a single mux control.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description: register offset
- description: pre-shifted bitfield mask
description: Each entry pair describes a single mux control.
idle-states: true
......
Documentation/devicetree/bindings/net/asix,ax88178.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/asix,ax88178.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: The device tree bindings for the USB Ethernet controllers
maintainers:
- Oleksij Rempel <o.rempel@pengutronix.de>
description: |
Device tree properties for hard wired USB Ethernet devices.
allOf:
- $ref: ethernet-controller.yaml#
properties:
compatible:
items:
- enum:
- usbb95,1720 # ASIX AX88172
- usbb95,172a # ASIX AX88172A
- usbb95,1780 # ASIX AX88178
- usbb95,7720 # ASIX AX88772
- usbb95,772a # ASIX AX88772A
- usbb95,772b # ASIX AX88772B
- usbb95,7e2b # ASIX AX88772B
reg: true
local-mac-address: true
mac-address: true
required:
- compatible
- reg
additionalProperties: false
examples:
- |
usb {
#address-cells = <1>;
#size-cells = <0>;
ethernet@1 {
compatible = "usbb95,7e2b";
reg = <1>;
local-mac-address = [00 00 00 00 00 00];
};
};
- |
usb {
#address-cells = <1>;
#size-cells = <0>;
usb1@1 {
compatible = "usb1234,5678";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
ethernet@1 {
compatible = "usbb95,772b";
reg = <1>;
};
};
};
Documentation/devicetree/bindings/net/cdns,macb.yaml
View file @ 86c87bea
......@@ -122,6 +122,7 @@ patternProperties:
reset-gpios: true
magic-packet:
type: boolean
description:
Indicates that the hardware supports waking up via magic packet.
......
Documentation/devicetree/bindings/net/ingenic,mac.yaml
View file @ 86c87bea
......@@ -37,6 +37,7 @@ properties:
const: stmmaceth
mode-reg:
$ref: /schemas/types.yaml#/definitions/phandle
description: An extra syscon register that control ethernet interface and timing delay
rx-clk-delay-ps:
......
Documentation/devicetree/bindings/net/microchip,lan95xx.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/microchip,lan95xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: The device tree bindings for the USB Ethernet controllers
maintainers:
- Oleksij Rempel <o.rempel@pengutronix.de>
description: |
Device tree properties for hard wired SMSC95xx compatible USB Ethernet
controller.
allOf:
- $ref: ethernet-controller.yaml#
properties:
compatible:
items:
- enum:
- usb424,9500 # SMSC9500 USB Ethernet Device
- usb424,9505 # SMSC9505 USB Ethernet Device
- usb424,9530 # SMSC LAN9530 USB Ethernet Device
- usb424,9730 # SMSC LAN9730 USB Ethernet Device
- usb424,9900 # SMSC9500 USB Ethernet Device (SAL10)
- usb424,9901 # SMSC9505 USB Ethernet Device (SAL10)
- usb424,9902 # SMSC9500A USB Ethernet Device (SAL10)
- usb424,9903 # SMSC9505A USB Ethernet Device (SAL10)
- usb424,9904 # SMSC9512/9514 USB Hub & Ethernet Device (SAL10)
- usb424,9905 # SMSC9500A USB Ethernet Device (HAL)
- usb424,9906 # SMSC9505A USB Ethernet Device (HAL)
- usb424,9907 # SMSC9500 USB Ethernet Device (Alternate ID)
- usb424,9908 # SMSC9500A USB Ethernet Device (Alternate ID)
- usb424,9909 # SMSC9512/9514 USB Hub & Ethernet Devic. ID)
- usb424,9e00 # SMSC9500A USB Ethernet Device
- usb424,9e01 # SMSC9505A USB Ethernet Device
- usb424,9e08 # SMSC LAN89530 USB Ethernet Device
- usb424,ec00 # SMSC9512/9514 USB Hub & Ethernet Device
reg: true
local-mac-address: true
mac-address: true
required:
- compatible
- reg
additionalProperties: false
examples:
- |
usb {
#address-cells = <1>;
#size-cells = <0>;
ethernet@1 {
compatible = "usb424,9e00";
reg = <1>;
local-mac-address = [00 00 00 00 00 00];
};
};
Documentation/devicetree/bindings/net/qcom,ipa.yaml
View file @ 86c87bea
......@@ -182,6 +182,12 @@ examples:
smp2p-mpss {
compatible = "qcom,smp2p";
interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 6>;
qcom,smem = <94>, <432>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
ipa_smp2p_out: ipa-ap-to-modem {
qcom,entry-name = "ipa";
#qcom,smem-state-cells = <1>;
......@@ -193,6 +199,7 @@ examples:
#interrupt-cells = <2>;
};
};
ipa@1e40000 {
compatible = "qcom,sdm845-ipa";
......
Documentation/devicetree/bindings/net/smsc,lan91c111.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/smsc,lan91c111.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Smart Mixed-Signal Connectivity (SMSC) LAN91C9x/91C1xx Controller
maintainers:
- Nicolas Pitre <nico@fluxnic.net>
allOf:
- $ref: ethernet-controller.yaml#
properties:
compatible:
const: smsc,lan91c111
reg:
maxItems: 1
interrupts:
maxItems: 1
reg-shift: true
reg-io-width:
enum: [ 1, 2, 4 ]
default: 4
reset-gpios:
description: GPIO connected to control RESET pin
maxItems: 1
power-gpios:
description: GPIO connect to control PWRDWN pin
maxItems: 1
pxa-u16-align4:
description: put in place the workaround the force all u16 writes to be
32 bits aligned
type: boolean
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
ethernet@4010000 {
compatible = "smsc,lan91c111";
reg = <0x40100000 0x10000>;
phy-mode = "mii";
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <2>;
};
Documentation/devicetree/bindings/net/smsc-lan91c111.txt deleted 100644 → 0
View file @ d223575e
SMSC LAN91c111 Ethernet mac
Required properties:
- compatible = "smsc,lan91c111";
- reg : physical address and size of registers
- interrupts : interrupt connection
Optional properties:
- phy-device : see ethernet.txt file in the same directory
- reg-io-width : Mask of sizes (in bytes) of the IO accesses that
are supported on the device. Valid value for SMSC LAN91c111 are
1, 2 or 4. If it's omitted or invalid, the size would be 2 meaning
16-bit access only.
- power-gpios: GPIO to control the PWRDWN pin
- reset-gpios: GPIO to control the RESET pin
- pxa-u16-align4 : Boolean, put in place the workaround the force all
u16 writes to be 32 bits aligned
Documentation/devicetree/bindings/net/ti,davinci-mdio.yaml
View file @ 86c87bea
......@@ -34,6 +34,7 @@ properties:
maxItems: 1
bus_freq:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 2500000
description: MDIO Bus frequency
......
Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml
View file @ 86c87bea
......@@ -142,4 +142,3 @@ examples:
assigned-clock-parents = <&k3_clks 118 11>;
};
};
Documentation/devicetree/bindings/net/wireless/ti,wlcore.yaml
View file @ 86c87bea
......@@ -54,9 +54,11 @@ properties:
ref-clock-frequency:
$ref: /schemas/types.yaml#/definitions/uint32
description: Reference clock frequency.
tcxo-clock-frequency:
$ref: /schemas/types.yaml#/definitions/uint32
description: TCXO clock frequency.
clock-xtal:
......
Documentation/devicetree/bindings/nvmem/snvs-lpgpr.yaml
View file @ 86c87bea
......@@ -15,6 +15,10 @@ properties:
- fsl,imx6q-snvs-lpgpr
- fsl,imx6ul-snvs-lpgpr
- fsl,imx7d-snvs-lpgpr
- fsl,imx8mm-snvs-lpgpr
- fsl,imx8mn-snvs-lpgpr
- fsl,imx8mp-snvs-lpgpr
- fsl,imx8mq-snvs-lpgpr
required:
- compatible
......
Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
View file @ 86c87bea
......@@ -55,13 +55,15 @@ properties:
Translation Unit) registers.
num-ib-windows:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 256
description: number of inbound address translation windows
maxItems: 1
deprecated: true
num-ob-windows:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 256
description: number of outbound address translation windows
maxItems: 1
deprecated: true
required:
......
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
View file @ 86c87bea
......@@ -68,6 +68,8 @@ properties:
Translation Unit) registers.
num-viewport:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 256
description: |
number of view ports configured in hardware. If a platform
does not specify it, the driver autodetects it.
......
Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Socionext UniPhier PCIe host controller
description: |
UniPhier PCIe host controller is based on the Synopsys DesignWare
PCI core. It shares common features with the PCIe DesignWare core and
inherits common properties defined in
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
maintainers:
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
allOf:
- $ref: /schemas/pci/snps,dw-pcie.yaml#
properties:
compatible:
enum:
- socionext,uniphier-pcie
reg:
minItems: 3
maxItems: 4
reg-names:
minItems: 3
items:
- const: dbi
- const: link
- const: config
- const: atu
clocks:
maxItems: 1
resets:
maxItems: 1
num-viewport: true
num-lanes: true
phys:
maxItems: 1
phy-names:
const: pcie-phy
required:
- compatible
- reg
- reg-names
- clocks
- resets
unevaluatedProperties: false
examples:
- |
pcie: pcie@66000000 {
compatible = "socionext,uniphier-pcie";
reg-names = "dbi", "link", "config";
reg = <0x66000000 0x1000>, <0x66010000 0x10000>, <0x2fff0000 0x10000>;
#address-cells = <3>;
#size-cells = <2>;
clocks = <&sys_clk 24>;
resets = <&sys_rst 24>;
num-lanes = <1>;
num-viewport = <1>;
bus-range = <0x0 0xff>;
device_type = "pci";
ranges = <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
<0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>;
phy-names = "pcie-phy";
phys = <&pcie_phy>;
#interrupt-cells = <1>;
interrupt-names = "dma", "msi";
interrupts = <0 224 4>, <0 225 4>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc 0>,
<0 0 0 2 &pcie_intc 1>,
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <0 226 4>;
};
};
Documentation/devicetree/bindings/pci/uniphier-pcie.txt deleted 100644 → 0
View file @ d223575e
Socionext UniPhier PCIe host controller bindings
This describes the devicetree bindings for PCIe host controller implemented
on Socionext UniPhier SoCs.
UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
It shares common functions with the PCIe DesignWare core driver and inherits
common properties defined in
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
Required properties:
- compatible: Should be "socionext,uniphier-pcie".
- reg: Specifies offset and length of the register set for the device.
According to the reg-names, appropriate register sets are required.
- reg-names: Must include the following entries:
"dbi" - controller configuration registers
"link" - SoC-specific glue layer registers
"config" - PCIe configuration space
"atu" - iATU registers for DWC version 4.80 or later
- clocks: A phandle to the clock gate for PCIe glue layer including
the host controller.
- resets: A phandle to the reset line for PCIe glue layer including
the host controller.
- interrupts: A list of interrupt specifiers. According to the
interrupt-names, appropriate interrupts are required.
- interrupt-names: Must include the following entries:
"dma" - DMA interrupt
"msi" - MSI interrupt
Optional properties:
- phys: A phandle to generic PCIe PHY. According to the phy-names, appropriate
phys are required.
- phy-names: Must be "pcie-phy".
Required sub-node:
- legacy-interrupt-controller: Specifies interrupt controller for legacy PCI
interrupts.
Required properties for legacy-interrupt-controller:
- interrupt-controller: identifies the node as an interrupt controller.
- #interrupt-cells: specifies the number of cells needed to encode an
interrupt source. The value must be 1.
- interrupt-parent: Phandle to the parent interrupt controller.
- interrupts: An interrupt specifier for legacy interrupt.
Example:
pcie: pcie@66000000 {
compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
status = "disabled";
reg-names = "dbi", "link", "config";
reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
<0x2fff0000 0x10000>;
#address-cells = <3>;
#size-cells = <2>;
clocks = <&sys_clk 24>;
resets = <&sys_rst 24>;
num-lanes = <1>;
num-viewport = <1>;
bus-range = <0x0 0xff>;
device_type = "pci";
ranges =
/* downstream I/O */
<0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000
/* non-prefetchable memory */
0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>;
#interrupt-cells = <1>;
interrupt-names = "dma", "msi";
interrupts = <0 224 4>, <0 225 4>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
<0 0 0 2 &pcie_intc 1>, /* INTB */
<0 0 0 3 &pcie_intc 2>, /* INTC */
<0 0 0 4 &pcie_intc 3>; /* INTD */
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <0 226 4>;
};
};
Documentation/devicetree/bindings/perf/spe-pmu.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/spe-pmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)
maintainers:
- Will Deacon <will@kernel.org>
description:
ARMv8.2 introduces the optional Statistical Profiling Extension for collecting
performance sample data using an in-memory trace buffer.
properties:
compatible:
const: arm,statistical-profiling-extension-v1
interrupts:
maxItems: 1
description: |
The PPI to signal SPE events. For heterogeneous systems where SPE is only
supported on a subset of the CPUs, please consult the arm,gic-v3 binding
for details on describing a PPI partition.
additionalProperties: false
required:
- compatible
- interrupts
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
spe-pmu {
compatible = "arm,statistical-profiling-extension-v1";
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
};
Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml
View file @ 86c87bea
......@@ -120,6 +120,7 @@ patternProperties:
input-schmitt-disable: true
input-polarity-invert:
type: boolean
description:
Enable or disable pin input polarity inversion.
......@@ -132,6 +133,7 @@ patternProperties:
output-low: true
output-polarity-invert:
type: boolean
description:
Enable or disable pin output polarity inversion.
......
Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
View file @ 86c87bea
......@@ -40,4 +40,3 @@ examples:
#power-domain-cells = <1>;
};
};
Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml
View file @ 86c87bea
......@@ -51,6 +51,7 @@ properties:
supported by the CPR power domain.
acc-syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description: A phandle to the syscon used for writing ACC settings.
nvmem-cells:
......
Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml
View file @ 86c87bea
......@@ -10,9 +10,11 @@ maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
- Magnus Damm <magnus.damm@gmail.com>
description:
description: |
The R-Car (RZ/G) System Controller provides power management for the CPU
cores and various coprocessors.
The power domain IDs for consumers are defined in header files::
include/dt-bindings/power/r8*-sysc.h
properties:
compatible:
......@@ -64,14 +66,3 @@ examples:
reg = <0xe6180000 0x0200>;
#power-domain-cells = <1>;
};
- |
// Power Domain consumers
#include <dt-bindings/power/r8a7791-sysc.h>
cache-controller-0 {
compatible = "cache";
power-domains = <&sysc R8A7791_PD_CA15_SCU>;
cache-unified;
cache-level = <2>;
};
Documentation/devicetree/bindings/power/supply/battery.yaml
View file @ 86c87bea
......@@ -85,8 +85,13 @@ properties:
description: battery factory internal resistance
resistance-temp-table:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description: the temperature in degree Celsius
- description: battery internal resistance percent
description: |
An array providing the temperature in degree Celsius
A table providing the temperature in degree Celsius
and corresponding battery internal resistance percent, which is used to
look up the resistance percent according to current temperature to get an
accurate batterty internal resistance in different temperatures.
......
Documentation/devicetree/bindings/power/supply/charger-manager.yaml
View file @ 86c87bea
......@@ -36,6 +36,7 @@ properties:
cm-poll-mode:
description: polling mode
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
enum:
- 0 # disabled
......
Documentation/devicetree/bindings/power/supply/cw2015_battery.yaml
View file @ 86c87bea
......@@ -78,4 +78,3 @@ examples:
power-supplies = <&mains_charger>, <&usb_charger>;
};
};
Documentation/devicetree/bindings/power/supply/power-supply.yaml
View file @ 86c87bea
......@@ -19,4 +19,3 @@ properties:
supply it power, referenced by their phandles.
additionalProperties: true
Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt
View file @ 86c87bea
......@@ -2,7 +2,7 @@
Required properties:
- compatible: Shall contain "ti,omap-dmtimer-pwm".
- ti,timers: phandle to PWM capable OMAP timer. See timer/ti,timer.txt for info
- ti,timers: phandle to PWM capable OMAP timer. See timer/ti,timer-dm.yaml for info
about these timers.
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
the cells format.
......
Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt deleted 100644 → 0
View file @ d223575e
Hisilicon System Reset Controller
======================================
Please also refer to reset.txt in this directory for common reset
controller binding usage.
The reset controller registers are part of the system-ctl block on
hi6220 SoC.
Required properties:
- compatible: should be one of the following:
- "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller.
- "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller.
- "hisilicon,hi6220-aoctrl", "syscon" : For ao reset controller.
- reg: should be register base and length as documented in the
datasheet
- #reset-cells: 1, see below
Example:
sys_ctrl: sys_ctrl@f7030000 {
compatible = "hisilicon,hi6220-sysctrl", "syscon";
reg = <0x0 0xf7030000 0x0 0x2000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Specifying reset lines connected to IP modules
==============================================
example:
uart1: serial@..... {
...
resets = <&sys_ctrl PERIPH_RSTEN3_UART1>;
...
};
The index could be found in <dt-bindings/reset/hisi,hi6220-resets.h>.
Documentation/devicetree/bindings/reset/microchip,rst.yaml
View file @ 86c87bea
......@@ -57,4 +57,3 @@ examples:
#reset-cells = <1>;
cpu-syscon = <&cpu_ctrl>;
};
Documentation/devicetree/bindings/rng/intel,ixp46x-rng.yaml
View file @ 86c87bea
......@@ -33,4 +33,3 @@ examples:
compatible = "intel,ixp46x-rng";
reg = <0x70002100 4>;
};
Documentation/devicetree/bindings/rng/st,stm32-rng.yaml
View file @ 86c87bea
......@@ -27,6 +27,7 @@ properties:
maxItems: 1
clock-error-detect:
type: boolean
description: If set enable the clock detection management
required:
......
Documentation/devicetree/bindings/rtc/rtc.txt deleted 100644 → 0
View file @ d223575e
This file has been moved to rtc.yaml.
Documentation/devicetree/bindings/serial/8250.yaml
View file @ 86c87bea
......@@ -138,6 +138,7 @@ properties:
description: The current active speed of the UART.
reg-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Offset to apply to the mapbase from the start of the registers.
......
Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt deleted 100644 → 0
View file @ d223575e
* MSM Serial UARTDM
The MSM serial UARTDM hardware is designed for high-speed use cases where the
transmit and/or receive channels can be offloaded to a dma-engine. From a
software perspective it's mostly compatible with the MSM serial UART except
that it supports reading and writing multiple characters at a time.
Required properties:
- compatible: Should contain at least "qcom,msm-uartdm".
A more specific property should be specified as follows depending
on the version:
"qcom,msm-uartdm-v1.1"
"qcom,msm-uartdm-v1.2"
"qcom,msm-uartdm-v1.3"
"qcom,msm-uartdm-v1.4"
- reg: Should contain UART register locations and lengths. The first
register shall specify the main control registers. An optional second
register location shall specify the GSBI control region.
"qcom,msm-uartdm-v1.3" is the only compatible value that might
need the GSBI control region.
- interrupts: Should contain UART interrupt.
- clocks: Should contain the core clock and the AHB clock.
- clock-names: Should be "core" for the core clock and "iface" for the
AHB clock.
Optional properties:
- dmas: Should contain dma specifiers for transmit and receive channels
- dma-names: Should contain "tx" for transmit and "rx" for receive channels
- qcom,tx-crci: Identificator <u32> for Client Rate Control Interface to be
used with TX DMA channel. Required when using DMA for transmission
with UARTDM v1.3 and below.
- qcom,rx-crci: Identificator <u32> for Client Rate Control Interface to be
used with RX DMA channel. Required when using DMA for reception
with UARTDM v1.3 and below.
Note: Aliases may be defined to ensure the correct ordering of the UARTs.
The alias serialN will result in the UART being assigned port N. If any
serialN alias exists, then an alias must exist for each enabled UART. The
serialN aliases should be in a .dts file instead of in a .dtsi file.
Examples:
- A uartdm v1.4 device with dma capabilities.
serial@f991e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991e000 0x1000>;
interrupts = <0 108 0x0>;
clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>;
clock-names = "core", "iface";
dmas = <&dma0 0>, <&dma0 1>;
dma-names = "tx", "rx";
};
- A uartdm v1.3 device without dma capabilities and part of a GSBI complex.
serial@19c40000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x19c40000 0x1000>,
<0x19c00000 0x1000>;
interrupts = <0 195 0x0>;
clocks = <&gsbi5_uart_cxc>, <&gsbi5_ahb_cxc>;
clock-names = "core", "iface";
};
- serialN alias.
aliases {
serial0 = &uarta;
serial1 = &uartc;
serial2 = &uartb;
};
uarta: serial@12490000 {
};
uartb: serial@16340000 {
};
uartc: serial@1a240000 {
};
Documentation/devicetree/bindings/serial/qcom,msm-uartdm.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/qcom,msm-uartdm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm MSM Serial UARTDM
maintainers:
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
description: |
The MSM serial UARTDM hardware is designed for high-speed use cases where the
transmit and/or receive channels can be offloaded to a dma-engine. From a
software perspective it's mostly compatible with the MSM serial UART except
that it supports reading and writing multiple characters at a time.
Note:: Aliases may be defined to ensure the correct ordering of the UARTs.
The alias serialN will result in the UART being assigned port N. If any
serialN alias exists, then an alias must exist for each enabled UART. The
serialN aliases should be in a .dts file instead of in a .dtsi file.
properties:
compatible:
items:
- enum:
- qcom,msm-uartdm-v1.1
- qcom,msm-uartdm-v1.2
- qcom,msm-uartdm-v1.3
- qcom,msm-uartdm-v1.4
- const: qcom,msm-uartdm
clocks:
maxItems: 2
clock-names:
items:
- const: core
- const: iface
dmas:
maxItems: 2
dma-names:
items:
- const: tx
- const: rx
interrupts:
maxItems: 1
qcom,rx-crci:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Identificator for Client Rate Control Interface to be used with RX DMA
channel. Required when using DMA for reception with UARTDM v1.3 and
below.
qcom,tx-crci:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Identificator for Client Rate Control Interface to be used with TX DMA
channel. Required when using DMA for transmission with UARTDM v1.3 and
below.
reg:
minItems: 1
items:
- description: Main control registers
- description: An optional second register location shall specify the GSBI control region.
required:
- compatible
- clock-names
- clocks
- interrupts
- reg
unevaluatedProperties: false
allOf:
- $ref: /schemas/serial/serial.yaml#
- if:
properties:
compatible:
contains:
const: qcom,msm-uartdm-v1.3
then:
properties:
reg:
minItems: 2
else:
properties:
reg:
maxItems: 1
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
serial@f991e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991e000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>;
clock-names = "core", "iface";
dmas = <&dma0 0>, <&dma0 1>;
dma-names = "tx", "rx";
};
Documentation/devicetree/bindings/serio/arm,pl050.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serio/arm,pl050.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm Ltd. PrimeCell PL050 PS/2 Keyboard/Mouse Interface
maintainers:
- Andre Przywara <andre.przywara@arm.com>
description:
The Arm PrimeCell PS2 Keyboard/Mouse Interface (KMI) is an AMBA compliant
peripheral that can be used to implement a keyboard or mouse interface that
is IBM PS2 or AT compatible.
# We need a select here so we don't match all nodes with 'arm,primecell'
select:
properties:
compatible:
contains:
const: arm,pl050
required:
- compatible
properties:
compatible:
items:
- const: arm,pl050
- const: arm,primecell
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: KMI reference clock, used to generate the bus timing
- description: APB register access clock
clock-names:
items:
- const: KMIREFCLK
- const: apb_pclk
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
serio@70000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x070000 0x1000>;
interrupts = <8>;
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
...
Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml
View file @ 86c87bea
......@@ -48,4 +48,3 @@ examples:
compatible = "amlogic,canvas";
reg = <0x48 0x14>;
};
Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/fsl/fsl,layerscape-dcfg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Layerscape Device Configuration Unit
maintainers:
- Shawn Guo <shawnguo@kernel.org>
- Li Yang <leoyang.li@nxp.com>
description: |
DCFG is the device configuration unit, that provides general purpose
configuration and status for the device. Such as setting the secondary
core start address and release the secondary core from holdoff and
startup.
properties:
compatible:
oneOf:
- items:
- enum:
- fsl,ls1012a-dcfg
- fsl,ls1021a-dcfg
- fsl,ls1043a-dcfg
- fsl,ls1046a-dcfg
- fsl,ls1088a-dcfg
- fsl,ls2080a-dcfg
- fsl,lx2160a-dcfg
- const: syscon
- items:
- enum:
- fsl,ls1028a-dcfg
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
little-endian: true
big-endian: true
'#address-cells':
const: 1
'#size-cells':
const: 1
ranges: true
patternProperties:
"^clock-controller@[0-9a-z]+$":
$ref: /schemas/clock/fsl,flexspi-clock.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
syscon@1ee0000 {
compatible = "fsl,ls1021a-dcfg", "syscon";
reg = <0x1ee0000 0x10000>;
};
Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-scfg.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/fsl/fsl,layerscape-scfg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Layerscape Supplemental Configuration Unit
maintainers:
- Shawn Guo <shawnguo@kernel.org>
- Li Yang <leoyang.li@nxp.com>
description: |
SCFG is the supplemental configuration unit, that provides SoC specific
configuration and status registers for the chip. Such as getting PEX port
status.
properties:
compatible:
items:
- enum:
- fsl,ls1012a-scfg
- fsl,ls1021a-scfg
- fsl,ls1028a-scfg
- fsl,ls1043a-scfg
- fsl,ls1046a-scfg
- const: syscon
reg:
maxItems: 1
little-endian: true
big-endian: true
'#address-cells':
const: 1
'#size-cells':
const: 1
ranges: true
patternProperties:
"^interrupt-controller@[a-z0-9]+$":
$ref: /schemas/interrupt-controller/fsl,ls-extirq.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
syscon@1570000 {
compatible = "fsl,ls1021a-scfg", "syscon";
reg = <0x1570000 0x10000>;
};
Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
View file @ 86c87bea
......@@ -7,8 +7,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: GENI Serial Engine QUP Wrapper Controller
maintainers:
- Mukesh Savaliya <msavaliy@codeaurora.org>
- Akash Asthana <akashast@codeaurora.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
......
Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt deleted 100644 → 0
View file @ d223575e
QCOM GSBI (General Serial Bus Interface) Driver
The GSBI controller is modeled as a node with zero or more child nodes, each
representing a serial sub-node device that is mux'd as part of the GSBI
configuration settings. The mode setting will govern the input/output mode of
the 4 GSBI IOs.
Required properties:
- compatible: Should contain "qcom,gsbi-v1.0.0"
- cell-index: Should contain the GSBI index
- reg: Address range for GSBI registers
- clocks: required clock
- clock-names: must contain "iface" entry
- qcom,mode : indicates MUX value for configuration of the serial interface.
Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values.
Optional properties:
- qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
- syscon-tcsr: indicates phandle of TCSR syscon node. Required if child uses
dma.
Required properties if child node exists:
- #address-cells: Must be 1
- #size-cells: Must be 1
- ranges: Must be present
Properties for children:
A GSBI controller node can contain 0 or more child nodes representing serial
devices. These serial devices can be a QCOM UART, I2C controller, spi
controller, or some combination of aforementioned devices.
See the following for child node definitions:
Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt
Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
Example for APQ8064:
#include <dt-bindings/soc/qcom,gsbi.h>
gsbi4@16300000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <4>;
reg = <0x16300000 0x100>;
clocks = <&gcc GSBI4_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
ranges;
qcom,mode = <GSBI_PROT_I2C_UART>;
qcom,crci = <GSBI_CRCI_QUP>;
syscon-tcsr = <&tcsr>;
/* child nodes go under here */
i2c_qup4: i2c@16380000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x16380000 0x1000>;
interrupts = <0 153 0>;
clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
clock-names = "core", "iface";
clock-frequency = <200000>;
#address-cells = <1>;
#size-cells = <0>;
};
uart4: serial@16340000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16340000 0x1000>,
<0x16300000 0x1000>;
interrupts = <0 152 0x0>;
clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
clock-names = "core", "iface";
};
};
tcsr: syscon@1a400000 {
compatible = "qcom,apq8064-tcsr", "syscon";
reg = <0x1a400000 0x100>;
};
Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,gsbi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm General Serial Bus Interface (GSBI)
maintainers:
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
description:
The GSBI controller is modeled as a node with zero or more child nodes, each
representing a serial sub-node device that is mux'd as part of the GSBI
configuration settings. The mode setting will govern the input/output mode
of the 4 GSBI IOs.
A GSBI controller node can contain 0 or more child nodes representing serial
devices. These serial devices can be a QCOM UART, I2C controller, spi
controller, or some combination of aforementioned devices.
properties:
compatible:
const: qcom,gsbi-v1.0.0
'#address-cells':
const: 1
cell-index:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The GSBI index.
clocks:
maxItems: 1
clock-names:
const: iface
qcom,crci:
$ref: /schemas/types.yaml#/definitions/uint32
description:
CRCI MUX value for QUP CRCI ports. Please reference
include/dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
qcom,mode:
$ref: /schemas/types.yaml#/definitions/uint32
description:
MUX value for configuration of the serial interface. Please reference
include/dt-bindings/soc/qcom,gsbi.h for valid mux values.
'#size-cells':
const: 1
syscon-tcsr:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle of TCSR syscon node.Required if child uses dma.
ranges: true
reg:
maxItems: 1
patternProperties:
"spi@[0-9a-f]+$":
type: object
$ref: /schemas/spi/qcom,spi-qup.yaml#
"i2c@[0-9a-f]+$":
type: object
$ref: /schemas/i2c/qcom,i2c-qup.yaml#
"serial@[0-9a-f]+$":
type: object
$ref: /schemas/serial/qcom,msm-uartdm.yaml#
required:
- compatible
- cell-index
- clocks
- clock-names
- qcom,mode
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,gsbi.h>
gsbi@12440000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x12440000 0x100>;
cell-index = <1>;
clocks = <&gcc GSBI1_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
ranges;
syscon-tcsr = <&tcsr>;
qcom,mode = <GSBI_PROT_I2C_UART>;
serial@12450000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x12450000 0x100>,
<0x12400000 0x03>;
interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
clock-names = "core", "iface";
};
i2c@12460000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x12460000 0x1000>;
pinctrl-0 = <&i2c1_pins>;
pinctrl-1 = <&i2c1_pins_sleep>;
pinctrl-names = "default", "sleep";
interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled"; /* UART chosen */
};
};
Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
View file @ 86c87bea
......@@ -34,6 +34,7 @@ properties:
- qcom,rpm-ipq6018
- qcom,rpm-msm8226
- qcom,rpm-msm8916
- qcom,rpm-msm8936
- qcom,rpm-msm8953
- qcom,rpm-msm8974
- qcom,rpm-msm8976
......
Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt deleted 100644 → 0
View file @ d223575e
Qualcomm Shared Memory Point 2 Point binding
The Shared Memory Point to Point (SMP2P) protocol facilitates communication of
a single 32-bit value between two processors. Each value has a single writer
(the local side) and a single reader (the remote side). Values are uniquely
identified in the system by the directed edge (local processor ID to remote
processor ID) and a string identifier.
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,smp2p"
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: one entry specifying the smp2p notification interrupt
- mboxes:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to the associated doorbell in APCS, as described
in mailbox/mailbox.txt
- qcom,ipc:
Usage: required, unless mboxes is specified
Value type: <prop-encoded-array>
Definition: three entries specifying the outgoing ipc bit used for
signaling the remote end of the smp2p edge:
- phandle to a syscon node representing the apcs registers
- u32 representing offset to the register within the syscon
- u32 representing the ipc bit within the register
- qcom,smem:
Usage: required
Value type: <u32 array>
Definition: two identifiers of the inbound and outbound smem items used
for this edge
- qcom,local-pid:
Usage: required
Value type: <u32>
Definition: specifies the identifier of the local endpoint of this edge
- qcom,remote-pid:
Usage: required
Value type: <u32>
Definition: specifies the identifier of the remote endpoint of this edge
= SUBNODES
Each SMP2P pair contain a set of inbound and outbound entries, these are
described in subnodes of the smp2p device node. The node names are not
important.
- qcom,entry-name:
Usage: required
Value type: <string>
Definition: specifies the name of this entry, for inbound entries this
will be used to match against the remotely allocated entry
and for outbound entries this name is used for allocating
entries
- interrupt-controller:
Usage: required for incoming entries
Value type: <empty>
Definition: marks the entry as inbound; the node should be specified
as a two cell interrupt-controller as defined in
"../interrupt-controller/interrupts.txt"
If not specified this node will denote the outgoing entry
- #interrupt-cells:
Usage: required for incoming entries
Value type: <u32>
Definition: must be 2 - denoting the bit in the entry and IRQ flags
- #qcom,smem-state-cells:
Usage: required for outgoing entries
Value type: <u32>
Definition: must be 1 - denoting the bit in the entry
= EXAMPLE
The following example shows the SMP2P setup with the wireless processor,
defined from the 8974 apps processor's point-of-view. It encompasses one
inbound and one outbound entry:
wcnss-smp2p {
compatible = "qcom,smp2p";
qcom,smem = <431>, <451>;
interrupts = <0 143 1>;
qcom,ipc = <&apcs 8 18>;
qcom,local-pid = <0>;
qcom,remote-pid = <4>;
wcnss_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
wcnss_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,smp2p.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Shared Memory Point 2 Point
maintainers:
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
description:
The Shared Memory Point to Point (SMP2P) protocol facilitates communication
of a single 32-bit value between two processors. Each value has a single
writer (the local side) and a single reader (the remote side). Values are
uniquely identified in the system by the directed edge (local processor ID to
remote processor ID) and a string identifier.
properties:
compatible:
const: qcom,smp2p
interrupts:
maxItems: 1
mboxes:
maxItems: 1
description:
Reference to the mailbox representing the outgoing doorbell in APCS for
this client.
qcom,ipc:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to a syscon node representing the APCS registers
- description: u32 representing offset to the register within the syscon
- description: u32 representing the ipc bit within the register
description:
Three entries specifying the outgoing ipc bit used for signaling the
remote end of the smp2p edge.
qcom,local-pid:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The identifier of the local endpoint of this edge.
qcom,remote-pid:
$ref: /schemas/types.yaml#/definitions/uint32
description:
The identifier of the remote endpoint of this edge.
qcom,smem:
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
maxItems: 2
description:
Two identifiers of the inbound and outbound smem items used for this edge.
patternProperties:
"^master-kernel|slave-kernel|ipa-ap-to-modem|ipa-modem-to-ap$":
type: object
description:
Each SMP2P pair contain a set of inbound and outbound entries, these are
described in subnodes of the smp2p device node. The node names are not
important.
properties:
interrupt-controller:
description:
Marks the entry as inbound; the node should be specified as a two
cell interrupt-controller. If not specified this node will denote
the outgoing entry.
'#interrupt-cells':
const: 2
qcom,entry-name:
$ref: /schemas/types.yaml#/definitions/string
description:
The name of this entry, for inbound entries this will be used to
match against the remotely allocated entry and for outbound entries
this name is used for allocating entries.
'#qcom,smem-state-cells':
$ref: /schemas/types.yaml#/definitions/uint32
const: 1
description:
Required for outgoing entries.
required:
- qcom,entry-name
oneOf:
- required:
- interrupt-controller
- '#interrupt-cells'
- required:
- '#qcom,smem-state-cells'
additionalProperties: false
required:
- compatible
- interrupts
- qcom,local-pid
- qcom,remote-pid
- qcom,smem
oneOf:
- required:
- mboxes
- required:
- qcom,ipc
additionalProperties: false
examples:
# The following example shows the SMP2P setup with the wireless processor,
# defined from the 8974 apps processor's point-of-view. It encompasses one
# inbound and one outbound entry.
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
shared-memory {
compatible = "qcom,smp2p";
qcom,smem = <431>, <451>;
interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 18>;
qcom,local-pid = <0>;
qcom,remote-pid = <4>;
wcnss_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
wcnss_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
Documentation/devicetree/bindings/soc/ti/wkup-m3-ipc.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/ti/wkup-m3-ipc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Wakeup M3 IPC device
maintainers:
- Dave Gerlach <d-gerlach@ti.com>
- Drew Fustini <dfustini@baylibre.com>
description: |+
The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
(commonly referred to as Wakeup M3 or CM3) to help with various low power tasks
that cannot be controlled from the MPU, like suspend/resume and certain deep
C-states for CPU Idle. Once the wkup_m3_ipc driver uses the wkup_m3_rproc driver
to boot the wkup_m3, it handles communication with the CM3 using IPC registers
present in the SoC's control module and a mailbox. The wkup_m3_ipc exposes an
API to allow the SoC PM code to execute specific PM tasks.
Wkup M3 Device Node
====================
A wkup_m3_ipc device node is used to represent the IPC registers within an
SoC.
Support for VTT Toggle with GPIO pin
====================================
On some boards like the AM335x EVM-SK and the AM437x GP EVM, a GPIO pin is
connected to the enable pin on the DDR VTT regulator. This allows the
regulator to be disabled upon suspend and enabled upon resume. Please note
that the GPIO pin must be part of the GPIO0 module as only this GPIO module
is in the wakeup power domain.
Support for IO Isolation
========================
On AM437x SoCs, certain pins can be forced into an alternate state when IO
isolation is activated. Those pins have pad control registers prefixed by
'CTRL_CONF_' that contain DS0 (e.g. deep sleep) configuration bits that can
override the pin's existing bias (pull-up/pull-down) and value (high/low) when
IO isolation is active.
Support for I2C PMIC Voltage Scaling
====================================
It is possible to pass the name of a binary file to load into the CM3 memory.
The binary data is the I2C sequences for the CM3 to send out to the PMIC
during low power mode entry.
properties:
compatible:
enum:
- ti,am3352-wkup-m3-ipc # for AM33xx SoCs
- ti,am4372-wkup-m3-ipc # for AM43xx SoCs
reg:
description:
The IPC register address space to communicate with the Wakeup M3 processor
maxItems: 1
interrupts:
description: wkup_m3 interrupt that signals the MPU
maxItems: 1
ti,rproc:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to the wkup_m3 rproc node so the IPC driver can boot it
mboxes:
description:
phandles used by IPC framework to get correct mbox
channel for communication. Must point to appropriate
mbox_wkupm3 child node.
maxItems: 1
firmware-name:
description:
Name of binary file with I2C sequences for PMIC voltage scaling
ti,vtt-gpio-pin:
$ref: /schemas/types.yaml#/definitions/uint32
description: GPIO pin connected to enable pin on VTT regulator
ti,set-io-isolation:
type: boolean
description:
If this property is present, then the wkup_m3_ipc driver will instruct
the CM3 firmware to activate IO isolation when suspending to deep sleep.
This can be leveraged by a board design to put other devices on the board
into a low power state.
allOf:
- if:
properties:
compatible:
not:
contains:
const: ti,am4372-wkup-m3-ipc
then:
properties:
ti,set-io-isolation: false
required:
- compatible
- reg
- interrupts
- ti,rproc
- mboxes
additionalProperties: false
examples:
- |
/* Example for AM335x SoC */
soc {
#address-cells = <1>;
#size-cells = <1>;
am335x_mailbox: mailbox {
#mbox-cells = <1>;
};
wkup_m3_ipc@1324 {
compatible = "ti,am3352-wkup-m3-ipc";
reg = <0x1324 0x24>;
interrupts = <78>;
ti,rproc = <&wkup_m3>;
mboxes = <&am335x_mailbox &mbox_wkupm3>;
ti,vtt-gpio-pin = <7>;
firmware-name = "am335x-evm-scale-data.bin";
};
};
- |
/*
* Example for AM473x SoC:
* On the AM437x-GP-EVM board, gpio5_7 is wired to enable pin of the DDR VTT
* regulator. The 'ddr_vtt_toggle_default' pinmux node configures gpio5_7
* for pull-up during normal system operation. However, the DS0 (deep sleep)
* state of the pin is configured for pull-down and thus the VTT regulator
* will be disabled to save power when IO isolation is active. Note that
* this method is an alternative to using the 'ti,vtt-gpio-pin' property.
*/
#include <dt-bindings/pinctrl/am43xx.h>
soc {
#address-cells = <1>;
#size-cells = <1>;
am437x_mailbox: mailbox {
#mbox-cells = <1>;
};
am43xx_pinmux {
pinctrl-names = "default";
pinctrl-0 = <&ddr3_vtt_toggle_default>;
ddr3_vtt_toggle_default: ddr_vtt_toggle_default {
pinctrl-single,pins = <
0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7)
>;
};
};
wkup_m3_ipc@1324 {
compatible = "ti,am4372-wkup-m3-ipc";
reg = <0x1324 0x24>;
interrupts = <78>;
ti,rproc = <&wkup_m3>;
mboxes = <&am437x_mailbox &mbox_wkupm3>;
ti,set-io-isolation;
firmware-name = "am43x-evm-scale-data.bin";
};
};
...
Documentation/devicetree/bindings/soc/ti/wkup_m3_ipc.txt deleted 100644 → 0
View file @ d223575e
Wakeup M3 IPC Driver
=====================
The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
(commonly referred to as Wakeup M3 or CM3) to help with various low power tasks
that cannot be controlled from the MPU, like suspend/resume and certain deep
C-states for CPU Idle. Once the wkup_m3_ipc driver uses the wkup_m3_rproc driver
to boot the wkup_m3, it handles communication with the CM3 using IPC registers
present in the SoC's control module and a mailbox. The wkup_m3_ipc exposes an
API to allow the SoC PM code to execute specific PM tasks.
Wkup M3 Device Node:
====================
A wkup_m3_ipc device node is used to represent the IPC registers within an
SoC.
Required properties:
--------------------
- compatible: Should be,
"ti,am3352-wkup-m3-ipc" for AM33xx SoCs
"ti,am4372-wkup-m3-ipc" for AM43xx SoCs
- reg: Contains the IPC register address space to communicate
with the Wakeup M3 processor
- interrupts: Contains the interrupt information for the wkup_m3
interrupt that signals the MPU.
- ti,rproc: phandle to the wkup_m3 rproc node so the IPC driver
can boot it.
- mboxes: phandles used by IPC framework to get correct mbox
channel for communication. Must point to appropriate
mbox_wkupm3 child node.
Example:
--------
/* AM33xx */
l4_wkup: l4_wkup@44c00000 {
...
scm: scm@210000 {
compatible = "ti,am3-scm", "simple-bus";
reg = <0x210000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x210000 0x2000>;
...
wkup_m3_ipc: wkup_m3_ipc@1324 {
compatible = "ti,am3352-wkup-m3-ipc";
reg = <0x1324 0x24>;
interrupts = <78>;
ti,rproc = <&wkup_m3>;
mboxes = <&mailbox &mbox_wkupm3>;
};
...
};
};
Documentation/devicetree/bindings/sound/adi,adau1372.yaml
View file @ 86c87bea
......@@ -64,4 +64,3 @@ examples:
clock-frequency = <12288000>;
};
...
Documentation/devicetree/bindings/sound/arm,pl041.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/arm,pl041.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm Ltd. PrimeCell PL041 AACI sound interface
maintainers:
- Andre Przywara <andre.przywara@arm.com>
description:
The Arm PrimeCell Advanced Audio CODEC Interface (AACI) is an AMBA compliant
peripheral that provides communication with an audio CODEC using the AC-link
protocol.
# We need a select here so we don't match all nodes with 'arm,primecell'
select:
properties:
compatible:
contains:
const: arm,pl041
required:
- compatible
properties:
compatible:
items:
- const: arm,pl041
- const: arm,primecell
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
description: APB register access clock
clock-names:
const: apb_pclk
required:
- compatible
- reg
- interrupts
- clocks
additionalProperties: false
examples:
- |
audio-controller@40000 {
compatible = "arm,pl041", "arm,primecell";
reg = <0x040000 0x1000>;
interrupts = <11>;
clocks = <&v2m_clk24mhz>;
clock-names = "apb_pclk";
};
...
Documentation/devicetree/bindings/sound/audio-graph-card2.yaml
View file @ 86c87bea
......@@ -24,10 +24,13 @@ properties:
connection's sink, the second being the connection's source.
$ref: /schemas/types.yaml#/definitions/non-unique-string-array
multi:
type: object
description: Multi-CPU/Codec node
dpcm:
type: object
description: DPCM node
codec2codec:
type: object
description: Codec to Codec node
required:
......
Documentation/devicetree/bindings/sound/imx-audio-hdmi.yaml
View file @ 86c87bea
......@@ -20,9 +20,11 @@ properties:
description: User specified audio sound card name
audio-cpu:
$ref: /schemas/types.yaml#/definitions/phandle
description: The phandle of an CPU DAI controller
hdmi-out:
type: boolean
description: |
This is a boolean property. If present, the transmitting function
of HDMI will be enabled, indicating there's a physical HDMI out
......@@ -30,6 +32,7 @@ properties:
block, such as an HDMI encoder or display-controller.
hdmi-in:
type: boolean
description: |
This is a boolean property. If present, the receiving function of
HDMI will be enabled, indicating there is a physical HDMI in
......
Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.yaml
View file @ 86c87bea
......@@ -82,4 +82,3 @@ examples:
clocks = <&clk 216>, <&clk 217>, <&clk 120>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
Documentation/devicetree/bindings/sound/samsung,aries-wm8994.yaml
View file @ 86c87bea
......@@ -149,4 +149,3 @@ examples:
sound-dai = <&wm8994>;
};
};
Documentation/devicetree/bindings/sound/samsung,odroid.yaml
View file @ 86c87bea
......@@ -92,4 +92,3 @@ examples:
sound-dai = <&hdmi>, <&max98090>;
};
};
Documentation/devicetree/bindings/sound/tas2562.yaml
View file @ 86c87bea
......@@ -76,4 +76,3 @@ examples:
ti,imon-slot-no = <0>;
};
};
Documentation/devicetree/bindings/sound/tas2770.yaml
View file @ 86c87bea
......@@ -80,4 +80,3 @@ examples:
ti,vmon-slot-no = <2>;
};
};
Documentation/devicetree/bindings/spi/amlogic,meson6-spifc.yaml
View file @ 86c87bea
......@@ -52,4 +52,3 @@ examples:
spi-max-frequency = <40000000>;
};
};
Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml
View file @ 86c87bea
......@@ -8,8 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Quad Serial Peripheral Interface (QSPI)
maintainers:
- Mukesh Savaliya <msavaliy@codeaurora.org>
- Akash Asthana <akashast@codeaurora.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: The QSPI controller allows SPI protocol communication in single,
dual, or quad wire transmission modes for read/write access to slaves such
......
Documentation/devicetree/bindings/spi/qcom,spi-qup.txt deleted 100644 → 0
View file @ d223575e
Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
The QUP core is an AHB slave that provides a common data path (an output FIFO
and an input FIFO) for serial peripheral interface (SPI) mini-core.
SPI in master mode supports up to 50MHz, up to four chip selects, programmable
data path from 4 bits to 32 bits and numerous protocol variants.
Required properties:
- compatible: Should contain:
"qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
"qcom,spi-qup-v2.1.1" for 8974 and later
"qcom,spi-qup-v2.2.1" for 8974 v2 and later.
- reg: Should contain base register location and length
- interrupts: Interrupt number used by this controller
- clocks: Should contain the core clock and the AHB clock.
- clock-names: Should be "core" for the core clock and "iface" for the
AHB clock.
- #address-cells: Number of cells required to define a chip select
address on the SPI bus. Should be set to 1.
- #size-cells: Should be zero.
Optional properties:
- spi-max-frequency: Specifies maximum SPI clock frequency,
Units - Hz. Definition as per
Documentation/devicetree/bindings/spi/spi-bus.txt
- num-cs: total number of chipselects
- cs-gpios: should specify GPIOs used for chipselects.
The gpios will be referred to as reg = <index> in the SPI child
nodes. If unspecified, a single SPI device without a chip
select can be used.
- dmas: Two DMA channel specifiers following the convention outlined
in bindings/dma/dma.txt
- dma-names: Names for the dma channels, if present. There must be at
least one channel named "tx" for transmit and named "rx" for
receive.
SPI slave nodes must be children of the SPI master node and can contain
properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
Example:
spi_8: spi@f9964000 { /* BLSP2 QUP2 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf9964000 0x1000>;
interrupts = <0 102 0>;
spi-max-frequency = <19200000>;
clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_bam 13>, <&blsp1_bam 12>;
dma-names = "rx", "tx";
pinctrl-names = "default";
pinctrl-0 = <&spi8_default>;
device@0 {
compatible = "arm,pl022-dummy";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>; /* Chip select 0 */
spi-max-frequency = <19200000>;
spi-cpol;
};
device@1 {
compatible = "arm,pl022-dummy";
#address-cells = <1>;
#size-cells = <1>;
reg = <1>; /* Chip select 1 */
spi-max-frequency = <9600000>;
spi-cpha;
};
device@2 {
compatible = "arm,pl022-dummy";
#address-cells = <1>;
#size-cells = <1>;
reg = <2>; /* Chip select 2 */
spi-max-frequency = <19200000>;
spi-cpol;
spi-cpha;
};
device@3 {
compatible = "arm,pl022-dummy";
#address-cells = <1>;
#size-cells = <1>;
reg = <3>; /* Chip select 3 */
spi-max-frequency = <19200000>;
spi-cpol;
spi-cpha;
spi-cs-high;
};
};
Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/qcom,spi-qup.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
maintainers:
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
description:
The QUP core is an AHB slave that provides a common data path (an output FIFO
and an input FIFO) for serial peripheral interface (SPI) mini-core.
SPI in master mode supports up to 50MHz, up to four chip selects,
programmable data path from 4 bits to 32 bits and numerous protocol variants.
allOf:
- $ref: /schemas/spi/spi-controller.yaml#
properties:
compatible:
enum:
- qcom,spi-qup-v1.1.1 # for 8660, 8960 and 8064
- qcom,spi-qup-v2.1.1 # for 8974 and later
- qcom,spi-qup-v2.2.1 # for 8974 v2 and later
clocks:
maxItems: 2
clock-names:
items:
- const: core
- const: iface
dmas:
maxItems: 2
dma-names:
items:
- const: tx
- const: rx
interrupts:
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- clock-names
- interrupts
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
spi@7575000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07575000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_spi1_default>;
pinctrl-1 = <&blsp1_spi1_sleep>;
dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
};
Documentation/devicetree/bindings/spi/renesas,hspi.yaml
View file @ 86c87bea
......@@ -56,4 +56,3 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
};
Documentation/devicetree/bindings/spi/spi-davinci.txt
View file @ 86c87bea
......@@ -78,7 +78,7 @@ spi0:spi@20bf0000 {
interrupts = <338>;
clocks = <&clkspi>;
flash: n25q032@0 {
flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32";
......
Documentation/devicetree/bindings/spi/spi-pl022.yaml
View file @ 86c87bea
......@@ -143,7 +143,7 @@ examples:
<&dma_controller 24 0>;
dma-names = "rx", "tx";
m25p80@1 {
flash@1 {
compatible = "st,m25p80";
reg = <1>;
spi-max-frequency = <12000000>;
......
Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt deleted 100644 → 0
View file @ d223575e
Qualcomm SPMI Controller (PMIC Arbiter)
The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI
controller with wrapping arbitration logic to allow for multiple on-chip
devices to control a single SPMI master.
The PMIC Arbiter can also act as an interrupt controller, providing interrupts
to slave devices.
See Documentation/devicetree/bindings/spmi/spmi.yaml for the generic SPMI
controller binding requirements for child nodes.
See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
generic interrupt controller binding documentation.
Required properties:
- compatible : should be "qcom,spmi-pmic-arb".
- reg-names : must contain:
"core" - core registers
"intr" - interrupt controller registers
"cnfg" - configuration registers
Registers used only for V2 PMIC Arbiter:
"chnls" - tx-channel per virtual slave registers.
"obsrvr" - rx-channel (called observer) per virtual slave registers.
- reg : address + size pairs describing the PMIC arb register sets; order must
correspond with the order of entries in reg-names
- #address-cells : must be set to 2
- #size-cells : must be set to 0
- qcom,ee : indicates the active Execution Environment identifier (0-5)
- qcom,channel : which of the PMIC Arb provided channels to use for accesses (0-5)
- interrupts : interrupt list for the PMIC Arb controller, must contain a
single interrupt entry for the peripheral interrupt
- interrupt-names : corresponding interrupt names for the interrupts
listed in the 'interrupts' property, must contain:
"periph_irq" - summary interrupt for PMIC peripherals
- interrupt-controller : boolean indicator that the PMIC arbiter is an interrupt controller
- #interrupt-cells : must be set to 4. Interrupts are specified as a 4-tuple:
cell 1: slave ID for the requested interrupt (0-15)
cell 2: peripheral ID for requested interrupt (0-255)
cell 3: the requested peripheral interrupt (0-7)
cell 4: interrupt flags indicating level-sense information, as defined in
dt-bindings/interrupt-controller/irq.h
Example:
spmi {
compatible = "qcom,spmi-pmic-arb";
reg-names = "core", "intr", "cnfg";
reg = <0xfc4cf000 0x1000>,
<0xfc4cb000 0x1000>,
<0xfc4ca000 0x1000>;
interrupt-names = "periph_irq";
interrupts = <0 190 0>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
};
Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/spmi/qcom,spmi-pmic-arb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SPMI Controller (PMIC Arbiter)
maintainers:
- Stephen Boyd <sboyd@kernel.org>
description: |
The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI
controller with wrapping arbitration logic to allow for multiple on-chip
devices to control a single SPMI master.
The PMIC Arbiter can also act as an interrupt controller, providing interrupts
to slave devices.
allOf:
- $ref: spmi.yaml
properties:
compatible:
const: qcom,spmi-pmic-arb
reg:
oneOf:
- items: # V1
- description: core registers
- description: interrupt controller registers
- description: configuration registers
- items: # V2
- description: core registers
- description: tx-channel per virtual slave regosters
- description: rx-channel (called observer) per virtual slave registers
- description: interrupt controller registers
- description: configuration registers
reg-names:
oneOf:
- items:
- const: core
- const: intr
- const: cnfg
- items:
- const: core
- const: chnls
- const: obsrvr
- const: intr
- const: cnfg
interrupts:
maxItems: 1
interrupt-names:
const: periph_irq
interrupt-controller: true
'#address-cells': true
'#interrupt-cells':
const: 4
description: |
cell 1: slave ID for the requested interrupt (0-15)
cell 2: peripheral ID for requested interrupt (0-255)
cell 3: the requested peripheral interrupt (0-7)
cell 4: interrupt flags indicating level-sense information,
as defined in dt-bindings/interrupt-controller/irq.h
'#size-cells': true
qcom,ee:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 5
description: >
indicates the active Execution Environment identifier
qcom,channel:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 5
description: >
which of the PMIC Arb provided channels to use for accesses
required:
- compatible
- reg-names
- qcom,ee
- qcom,channel
unevaluatedProperties: false
examples:
- |
spmi@fc4cf000 {
compatible = "qcom,spmi-pmic-arb";
reg-names = "core", "intr", "cnfg";
reg = <0xfc4cf000 0x1000>,
<0xfc4cb000 0x1000>,
<0xfc4ca000 0x1000>;
interrupt-names = "periph_irq";
interrupts = <0 190 0>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
};
Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
View file @ 86c87bea
......@@ -53,6 +53,7 @@ properties:
- qcom,sc8280xp-tsens
- qcom,sdm630-tsens
- qcom,sdm845-tsens
- qcom,sm6350-tsens
- qcom,sm8150-tsens
- qcom,sm8250-tsens
- qcom,sm8350-tsens
......
Documentation/devicetree/bindings/timer/cdns,ttc.yaml
View file @ 86c87bea
......@@ -17,7 +17,6 @@ properties:
maxItems: 1
interrupts:
minItems: 3
maxItems: 3
description: |
A list of 3 interrupts; one per timer channel.
......
Documentation/devicetree/bindings/timer/rda,8810pl-timer.txt deleted 100644 → 0
View file @ d223575e
RDA Micro RDA8810PL Timer
Required properties:
- compatible : "rda,8810pl-timer"
- reg : Offset and length of the register set for the device.
- interrupts : Should contain two interrupts.
- interrupt-names : Should be "hwtimer", "ostimer".
Example:
apb@20900000 {
compatible = "simple-bus";
...
timer@10000 {
compatible = "rda,8810pl-timer";
reg = <0x10000 0x1000>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>,
<17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hwtimer", "ostimer";
};
Documentation/devicetree/bindings/timer/rda,8810pl-timer.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/rda,8810pl-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: RDA Micro RDA8810PL Timer
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
properties:
compatible:
const: rda,8810pl-timer
reg:
maxItems: 1
interrupts:
minItems: 2
maxItems: 2
interrupt-names:
items:
- const: hwtimer
- const: ostimer
required:
- compatible
- reg
- interrupts
- interrupt-names
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
timer@20910000 {
compatible = "rda,8810pl-timer";
reg = <0x20910000 0x1000>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>,
<17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hwtimer", "ostimer";
};
...
Documentation/devicetree/bindings/timer/renesas,ostm.yaml
View file @ 86c87bea
......@@ -23,6 +23,7 @@ properties:
- enum:
- renesas,r7s72100-ostm # RZ/A1H
- renesas,r7s9210-ostm # RZ/A2M
- renesas,r9a07g043-ostm # RZ/G2UL
- renesas,r9a07g044-ostm # RZ/G2{L,LC}
- renesas,r9a07g054-ostm # RZ/V2L
- const: renesas,ostm # Generic
......@@ -54,6 +55,7 @@ if:
compatible:
contains:
enum:
- renesas,r9a07g043-ostm
- renesas,r9a07g044-ostm
- renesas,r9a07g054-ostm
then:
......
Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
View file @ 86c87bea
......@@ -24,13 +24,12 @@ properties:
- samsung,exynos4412-mct
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- pattern: "^(fin_pll|mct)$"
- pattern: "^(fin_pll|mct)$"
- const: fin_pll
- const: mct
reg:
maxItems: 1
......
Documentation/devicetree/bindings/timer/ti,timer-dm.yaml 0 → 100644
View file @ 86c87bea
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI dual-mode timer
maintainers:
- Tony Lindgren <tony@atomide.com>
description: |
The TI dual-mode timer is a general purpose timer with PWM capabilities.
properties:
compatible:
oneOf:
- items:
- enum:
- ti,am335x-timer
- ti,am335x-timer-1ms
- ti,am654-timer
- ti,dm814-timer
- ti,dm816-timer
- ti,omap2420-timer
- ti,omap3430-timer
- ti,omap4430-timer
- ti,omap5430-timer
- items:
- const: ti,am4372-timer
- const: ti,am335x-timer
- items:
- const: ti,am4372-timer-1ms
- const: ti,am335x-timer-1ms
reg:
items:
- description: IO address
- description: L3 to L4 mapping for omap4/5 L4 ABE
minItems: 1
clocks:
items:
- description: Functional clock
- description: System clock for omap4/5 and dra7
minItems: 1
clock-names:
items:
- const: fck
- const: timer_sys_ck
minItems: 1
interrupts:
description:
Interrupt if available. The timer PWM features may be usable
in a limited way even without interrupts.
maxItems: 1
ti,timer-alwon:
description:
Timer is always enabled when the SoC is powered. Note that some SoCs like
am335x can suspend to PM coprocessor RTC only mode and in that case the
SoC power is cut including timers.
type: boolean
ti,timer-dsp:
description:
Timer is routable to the DSP in addition to the operating system.
type: boolean
ti,timer-pwm:
description:
Timer has been wired for PWM capability.
type: boolean
ti,timer-secure:
description:
Timer access has been limited to secure mode only.
type: boolean
ti,hwmods:
description:
Name of the HWMOD associated with timer. This is for legacy
omap2/3 platforms only.
$ref: /schemas/types.yaml#/definitions/string
deprecated: true
required:
- compatible
- reg
additionalProperties: false
allOf:
- if:
not:
properties:
compatible:
contains:
const: ti,am654-timer
then:
required:
- interrupts
- if:
not:
properties:
compatible:
contains:
enum:
- ti,omap3430-timer
- ti,omap4430-timer
- ti,omap5430-timer
then:
properties:
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
maxItems: 1
- if:
properties:
compatible:
contains:
enum:
- ti,dm814-timer
- ti,dm816-timer
- ti,omap2420-timer
- ti,omap3430-timer
then:
properties:
ti,hwmods:
items:
- pattern: "^timer([1-9]|1[0-2])$"
else:
properties:
ti,hwmods: false
examples:
- |
timer1: timer@0 {
compatible = "ti,am335x-timer-1ms";
reg = <0x0 0x400>;
interrupts = <67>;
ti,timer-alwon;
clocks = <&timer1_fck>;
clock-names = "fck";
};
...
Documentation/devicetree/bindings/timer/ti,timer.txt deleted 100644 → 0
View file @ d223575e
OMAP Timer bindings
Required properties:
- compatible: Should be set to one of the below. Please note that
OMAP44xx devices have timer instances that are 100%
register compatible with OMAP3xxx devices as well as
newer timers that are not 100% register compatible.
So for OMAP44xx devices timer instances may use
different compatible strings.
ti,omap2420-timer (applicable to OMAP24xx devices)
ti,omap3430-timer (applicable to OMAP3xxx/44xx devices)
ti,omap4430-timer (applicable to OMAP44xx devices)
ti,omap5430-timer (applicable to OMAP543x devices)
ti,am335x-timer (applicable to AM335x devices)
ti,am335x-timer-1ms (applicable to AM335x devices)
- reg: Contains timer register address range (base address and
length).
- interrupts: Contains the interrupt information for the timer. The
format is being dependent on which interrupt controller
the OMAP device uses.
- ti,hwmods: Name of the hwmod associated to the timer, "timer<X>",
where <X> is the instance number of the timer from the
HW spec.
Optional properties:
- ti,timer-alwon: Indicates the timer is in an alway-on power domain.
- ti,timer-dsp: Indicates the timer can interrupt the on-chip DSP in
addition to the ARM CPU.
- ti,timer-pwm: Indicates the timer can generate a PWM output.
- ti,timer-secure: Indicates the timer is reserved on a secure OMAP device
and therefore cannot be used by the kernel.
Example:
timer12: timer@48304000 {
compatible = "ti,omap3430-timer";
reg = <0x48304000 0x400>;
interrupts = <95>;
ti,hwmods = "timer12"
ti,timer-alwon;
ti,timer-secure;
};
Documentation/devicetree/bindings/trivial-devices.yaml
View file @ 86c87bea
......@@ -87,6 +87,8 @@ properties:
- devantech,srf08
# Devantech SRF10 ultrasonic ranger
- devantech,srf10
# DH electronics GmbH on-board CPLD trivial SPI device
- dh,dhcom-board
# DA9053: flexible system level PMIC with multicore support
- dlg,da9053
# DA9063: system PMIC for quad-core application processors
......@@ -219,6 +221,8 @@ properties:
- memsic,mxc6255
# MEMSIC 3-axis accelerometer
- memsic,mxc6655
# Menlo on-board CPLD trivial SPI device
- menlo,m53cpld
# Microchip differential I2C ADC, 1 Channel, 18 bit
- microchip,mcp3421
# Microchip differential I2C ADC, 2 Channel, 18 bit
......
Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
View file @ 86c87bea
......@@ -151,7 +151,7 @@ Example for HSIC:
#address-cells = <1>;
#size-cells = <0>;
usbnet: smsc@1 {
usbnet: ethernet@1 {
compatible = "usb424,9730";
reg = <1>;
};
......
Documentation/devicetree/bindings/usb/mediatek,mt6360-tcpc.yaml
View file @ 86c87bea
......@@ -50,6 +50,11 @@ examples:
mt6360@34 {
compatible = "mediatek,mt6360";
reg = <0x34>;
interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "IRQB";
interrupt-controller;
#interrupt-cells = <1>;
tcpc {
compatible = "mediatek,mt6360-tcpc";
interrupts-extended = <&gpio26 3 IRQ_TYPE_LEVEL_LOW>;
......
Documentation/devicetree/bindings/usb/smsc,usb3503.yaml
View file @ 86c87bea
......@@ -45,6 +45,7 @@ properties:
property if all ports have to be enabled.
initial-mode:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2]
description: >
Specifies initial mode. 1 for Hub mode, 2 for standby mode.
......
Documentation/devicetree/bindings/vendor-prefixes.yaml
View file @ 86c87bea
......@@ -385,6 +385,8 @@ patternProperties:
description: Empire Electronix
"^emtrion,.*":
description: emtrion GmbH
"^enclustra,.*":
description: Enclustra GmbH
"^endless,.*":
description: Endless Mobile, Inc.
"^ene,.*":
......
Documentation/devicetree/bindings/writing-bindings.rst
View file @ 86c87bea
......@@ -58,6 +58,31 @@ Properties
- DO define properties in terms of constraints. How many entries? What are
possible values? What is the order?
Typical cases and caveats
=========================
- Phandle entries, like clocks/dmas/interrupts/resets, should always be
explicitly ordered. Include the {clock,dma,interrupt,reset}-names if there is
more than one phandle. When used, both of these fields need the same
constraints (e.g. list of items).
- For names used in {clock,dma,interrupt,reset}-names, do not add any suffix,
e.g.: "tx" instead of "txirq" (for interrupt).
- Properties without schema types (e.g. without standard suffix or not defined
by schema) need the type, even if this is an enum.
- If schema includes other schema (e.g. /schemas/i2c/i2c-controller.yaml) use
"unevaluatedProperties:false". In other cases, usually use
"additionalProperties:false".
- For sub-blocks/components of bigger device (e.g. SoC blocks) use rather
device-based compatible (e.g. SoC-based compatible), instead of custom
versioning of that component.
For example use "vendor,soc1234-i2c" instead of "vendor,i2c-v2".
- "syscon" is not a generic property. Use vendor and type, e.g.
"vendor,power-manager-syscon".
Board/SoC .dts Files
====================
......
Documentation/devicetree/bindings/writing-schema.rst
View file @ 86c87bea
......@@ -108,6 +108,12 @@ The YAML Devicetree format also makes all string values an array and scalar
values a matrix (in order to define groupings) even when only a single value
is present. Single entries in schemas are fixed up to match this encoding.
Coding style
------------
Use YAML coding style (two-space indentation). For DTS examples in the schema,
preferred is four-space indentation.
Testing
-------
......@@ -128,6 +134,8 @@ installed first. On Debian/Ubuntu systems::
Several executables (dt-doc-validate, dt-mk-schema, dt-validate) will be
installed. Ensure they are in your PATH (~/.local/bin by default).
Recommended is also to install yamllint (used by dtschema when present).
Running checks
~~~~~~~~~~~~~~
......
Documentation/devicetree/overlay-notes.rst
View file @ 86c87bea
......@@ -119,10 +119,32 @@ Finally, if you need to remove all overlays in one-go, just call
of_overlay_remove_all() which will remove every single one in the correct
order.
In addition, there is the option to register notifiers that get called on
There is the option to register notifiers that get called on
overlay operations. See of_overlay_notifier_register/unregister and
enum of_overlay_notify_action for details.
Note that a notifier callback is not supposed to store pointers to a device
tree node or its content beyond OF_OVERLAY_POST_REMOVE corresponding to the
respective node it received.
A notifier callback for OF_OVERLAY_PRE_APPLY, OF_OVERLAY_POST_APPLY, or
OF_OVERLAY_PRE_REMOVE may store pointers to a device tree node in the overlay
or its content but these pointers must not persist past the notifier callback
for OF_OVERLAY_POST_REMOVE. The memory containing the overlay will be
kfree()ed after OF_OVERLAY_POST_REMOVE notifiers are called. Note that the
memory will be kfree()ed even if the notifier for OF_OVERLAY_POST_REMOVE
returns an error.
The changeset notifiers in drivers/of/dynamic.c are a second type of notifier
that could be triggered by applying or removing an overlay. These notifiers
are not allowed to store pointers to a device tree node in the overlay
or its content. The overlay code does not protect against such pointers
remaining active when the memory containing the overlay is freed as a result
of removing the overlay.
Any other code that retains a pointer to the overlay nodes or data is
considered to be a bug because after removing the overlay the pointer
will refer to freed memory.
Users of overlays must be especially aware of the overall operations that
occur on the system to ensure that other kernel code does not retain any
pointers to the overlay nodes or data. Any example of an inadvertent use
of such pointers is if a driver or subsystem module is loaded after an
overlay has been applied, and the driver or subsystem scans the entire
devicetree or a large portion of it, including the overlay nodes.
MAINTAINERS
View file @ 86c87bea
......@@ -2572,7 +2572,7 @@ F: Documentation/devicetree/bindings/arm/rda.yaml
F: Documentation/devicetree/bindings/gpio/gpio-rda.yaml
F: Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.txt
F: Documentation/devicetree/bindings/serial/rda,8810pl-uart.yaml
F: Documentation/devicetree/bindings/timer/rda,8810pl-timer.txt
F: Documentation/devicetree/bindings/timer/rda,8810pl-timer.yaml
F: arch/arm/boot/dts/rda8810pl-*
F: drivers/clocksource/timer-rda.c
F: drivers/gpio/gpio-rda.c
......@@ -12413,7 +12413,7 @@ MEDIATEK I2C CONTROLLER DRIVER
M: Qii Wang <qii.wang@mediatek.com>
L: linux-i2c@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt
F: Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml
F: drivers/i2c/busses/i2c-mt65xx.c
MEDIATEK IOMMU DRIVER
......@@ -15456,7 +15456,7 @@ PCIE DRIVER FOR SOCIONEXT UNIPHIER
M: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
L: linux-pci@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pci/uniphier-pcie*
F: Documentation/devicetree/bindings/pci/socionext,uniphier-pcie*
F: drivers/pci/controller/dwc/pcie-uniphier*
PCIE DRIVER FOR ST SPEAR13XX
......
drivers/of/fdt.c
View file @ 86c87bea
......@@ -1118,6 +1118,9 @@ int __init early_init_dt_scan_memory(void)
if (type == NULL || strcmp(type, "memory") != 0)
continue;
if (!of_fdt_device_is_available(fdt, node))
continue;
reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
if (reg == NULL)
reg = of_get_flat_dt_prop(node, "reg", &l);
......
drivers/of/irq.c
View file @ 86c87bea
......@@ -284,7 +284,7 @@ int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *out_irq)
}
/*
* Successfully parsed an interrrupt-map translation; copy new
* Successfully parsed an interrupt-map translation; copy new
* interrupt specifier into the out_irq structure
*/
match_array = imap - newaddrsize - newintsize;
......@@ -550,9 +550,18 @@ void __init of_irq_init(const struct of_device_id *matches)
desc->irq_init_cb = match->data;
desc->dev = of_node_get(np);
/*
* interrupts-extended can reference multiple parent domains.
* Arbitrarily pick the first one; assume any other parents
* are the same distance away from the root irq controller.
*/
desc->interrupt_parent = of_parse_phandle(np, "interrupts-extended", 0);
if (!desc->interrupt_parent)
desc->interrupt_parent = of_irq_find_parent(np);
if (desc->interrupt_parent == np)
if (desc->interrupt_parent == np) {
of_node_put(desc->interrupt_parent);
desc->interrupt_parent = NULL;
}
list_add_tail(&desc->list, &intc_desc_list);
}
......
drivers/of/overlay.c
View file @ 86c87bea
......@@ -57,8 +57,10 @@ struct fragment {
* struct overlay_changeset
* @id: changeset identifier
* @ovcs_list: list on which we are located
* @fdt: base of memory allocated to hold aligned FDT that was unflattened to create @overlay_tree
* @overlay_tree: expanded device tree that contains the fragment nodes
* @new_fdt: Memory allocated to hold unflattened aligned FDT
* @overlay_mem: the memory chunk that contains @overlay_root
* @overlay_root: expanded device tree that contains the fragment nodes
* @notify_state: most recent notify action used on overlay
* @count: count of fragment structures
* @fragments: fragment nodes in the overlay expanded device tree
* @symbols_fragment: last element of @fragments[] is the __symbols__ node
......@@ -67,8 +69,10 @@ struct fragment {
struct overlay_changeset {
int id;
struct list_head ovcs_list;
const void *fdt;
struct device_node *overlay_tree;
const void *new_fdt;
const void *overlay_mem;
struct device_node *overlay_root;
enum of_overlay_notify_action notify_state;
int count;
struct fragment *fragments;
bool symbols_fragment;
......@@ -115,7 +119,6 @@ void of_overlay_mutex_unlock(void)
mutex_unlock(&of_overlay_phandle_mutex);
}
static LIST_HEAD(ovcs_list);
static DEFINE_IDR(ovcs_idr);
......@@ -149,19 +152,14 @@ int of_overlay_notifier_unregister(struct notifier_block *nb)
}
EXPORT_SYMBOL_GPL(of_overlay_notifier_unregister);
static char *of_overlay_action_name[] = {
"pre-apply",
"post-apply",
"pre-remove",
"post-remove",
};
static int overlay_notify(struct overlay_changeset *ovcs,
enum of_overlay_notify_action action)
{
struct of_overlay_notify_data nd;
int i, ret;
ovcs->notify_state = action;
for (i = 0; i < ovcs->count; i++) {
struct fragment *fragment = &ovcs->fragments[i];
......@@ -170,12 +168,10 @@ static int overlay_notify(struct overlay_changeset *ovcs,
ret = blocking_notifier_call_chain(&overlay_notify_chain,
action, &nd);
if (ret == NOTIFY_OK || ret == NOTIFY_STOP)
return 0;
if (ret) {
if (notifier_to_errno(ret)) {
ret = notifier_to_errno(ret);
pr_err("overlay changeset %s notifier error %d, target: %pOF\n",
of_overlay_action_name[action], ret, nd.target);
of_overlay_action_name(action), ret, nd.target);
return ret;
}
}
......@@ -185,7 +181,7 @@ static int overlay_notify(struct overlay_changeset *ovcs,
/*
* The values of properties in the "/__symbols__" node are paths in
* the ovcs->overlay_tree. When duplicating the properties, the paths
* the ovcs->overlay_root. When duplicating the properties, the paths
* need to be adjusted to be the correct path for the live device tree.
*
* The paths refer to a node in the subtree of a fragment node's "__overlay__"
......@@ -221,7 +217,7 @@ static struct property *dup_and_fixup_symbol_prop(
if (path_len < 1)
return NULL;
fragment_node = __of_find_node_by_path(ovcs->overlay_tree, path + 1);
fragment_node = __of_find_node_by_path(ovcs->overlay_root, path + 1);
overlay_node = __of_find_node_by_path(fragment_node, "__overlay__/");
of_node_put(fragment_node);
of_node_put(overlay_node);
......@@ -719,52 +715,49 @@ static struct device_node *find_target(struct device_node *info_node)
/**
* init_overlay_changeset() - initialize overlay changeset from overlay tree
* @ovcs: Overlay changeset to build
* @fdt: base of memory allocated to hold aligned FDT that was unflattened to create @tree
* @tree: Contains the overlay fragments and overlay fixup nodes
*
* Initialize @ovcs. Populate @ovcs->fragments with node information from
* the top level of @tree. The relevant top level nodes are the fragment
* nodes and the __symbols__ node. Any other top level node will be ignored.
* the top level of @overlay_root. The relevant top level nodes are the
* fragment nodes and the __symbols__ node. Any other top level node will
* be ignored. Populate other @ovcs fields.
*
* Return: 0 on success, -ENOMEM if memory allocation failure, -EINVAL if error
* detected in @tree, or -ENOSPC if idr_alloc() error.
* detected in @overlay_root. On error return, the caller of
* init_overlay_changeset() must call free_overlay_changeset().
*/
static int init_overlay_changeset(struct overlay_changeset *ovcs,
const void *fdt, struct device_node *tree)
static int init_overlay_changeset(struct overlay_changeset *ovcs)
{
struct device_node *node, *overlay_node;
struct fragment *fragment;
struct fragment *fragments;
int cnt, id, ret;
int cnt, ret;
/*
* None of the resources allocated by this function will be freed in
* the error paths. Instead the caller of this function is required
* to call free_overlay_changeset() (which will free the resources)
* if error return.
*/
/*
* Warn for some issues. Can not return -EINVAL for these until
* of_unittest_apply_overlay() is fixed to pass these checks.
*/
if (!of_node_check_flag(tree, OF_DYNAMIC))
pr_debug("%s() tree is not dynamic\n", __func__);
if (!of_node_check_flag(tree, OF_DETACHED))
pr_debug("%s() tree is not detached\n", __func__);
if (!of_node_check_flag(ovcs->overlay_root, OF_DYNAMIC))
pr_debug("%s() ovcs->overlay_root is not dynamic\n", __func__);
if (!of_node_is_root(tree))
pr_debug("%s() tree is not root\n", __func__);
if (!of_node_check_flag(ovcs->overlay_root, OF_DETACHED))
pr_debug("%s() ovcs->overlay_root is not detached\n", __func__);
ovcs->overlay_tree = tree;
ovcs->fdt = fdt;
INIT_LIST_HEAD(&ovcs->ovcs_list);
if (!of_node_is_root(ovcs->overlay_root))
pr_debug("%s() ovcs->overlay_root is not root\n", __func__);
of_changeset_init(&ovcs->cset);
id = idr_alloc(&ovcs_idr, ovcs, 1, 0, GFP_KERNEL);
if (id <= 0)
return id;
cnt = 0;
/* fragment nodes */
for_each_child_of_node(tree, node) {
for_each_child_of_node(ovcs->overlay_root, node) {
overlay_node = of_get_child_by_name(node, "__overlay__");
if (overlay_node) {
cnt++;
......@@ -772,7 +765,7 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
}
}
node = of_get_child_by_name(tree, "__symbols__");
node = of_get_child_by_name(ovcs->overlay_root, "__symbols__");
if (node) {
cnt++;
of_node_put(node);
......@@ -781,11 +774,12 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
fragments = kcalloc(cnt, sizeof(*fragments), GFP_KERNEL);
if (!fragments) {
ret = -ENOMEM;
goto err_free_idr;
goto err_out;
}
ovcs->fragments = fragments;
cnt = 0;
for_each_child_of_node(tree, node) {
for_each_child_of_node(ovcs->overlay_root, node) {
overlay_node = of_get_child_by_name(node, "__overlay__");
if (!overlay_node)
continue;
......@@ -797,7 +791,7 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
of_node_put(fragment->overlay);
ret = -EINVAL;
of_node_put(node);
goto err_free_fragments;
goto err_out;
}
cnt++;
......@@ -807,7 +801,7 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
* if there is a symbols fragment in ovcs->fragments[i] it is
* the final element in the array
*/
node = of_get_child_by_name(tree, "__symbols__");
node = of_get_child_by_name(ovcs->overlay_root, "__symbols__");
if (node) {
ovcs->symbols_fragment = 1;
fragment = &fragments[cnt];
......@@ -817,7 +811,7 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
if (!fragment->target) {
pr_err("symbols in overlay, but not in live tree\n");
ret = -EINVAL;
goto err_free_fragments;
goto err_out;
}
cnt++;
......@@ -826,20 +820,14 @@ static int init_overlay_changeset(struct overlay_changeset *ovcs,
if (!cnt) {
pr_err("no fragments or symbols in overlay\n");
ret = -EINVAL;
goto err_free_fragments;
goto err_out;
}
ovcs->id = id;
ovcs->count = cnt;
ovcs->fragments = fragments;
return 0;
err_free_fragments:
kfree(fragments);
err_free_idr:
idr_remove(&ovcs_idr, id);
err_out:
pr_err("%s() failed, ret = %d\n", __func__, ret);
return ret;
......@@ -852,21 +840,34 @@ static void free_overlay_changeset(struct overlay_changeset *ovcs)
if (ovcs->cset.entries.next)
of_changeset_destroy(&ovcs->cset);
if (ovcs->id)
if (ovcs->id) {
idr_remove(&ovcs_idr, ovcs->id);
list_del(&ovcs->ovcs_list);
ovcs->id = 0;
}
for (i = 0; i < ovcs->count; i++) {
of_node_put(ovcs->fragments[i].target);
of_node_put(ovcs->fragments[i].overlay);
}
kfree(ovcs->fragments);
/*
* There should be no live pointers into ovcs->overlay_tree and
* ovcs->fdt due to the policy that overlay notifiers are not allowed
* to retain pointers into the overlay devicetree.
* There should be no live pointers into ovcs->overlay_mem and
* ovcs->new_fdt due to the policy that overlay notifiers are not
* allowed to retain pointers into the overlay devicetree other
* than during the window from OF_OVERLAY_PRE_APPLY overlay
* notifiers until the OF_OVERLAY_POST_REMOVE overlay notifiers.
*
* A memory leak will occur here if within the window.
*/
kfree(ovcs->overlay_tree);
kfree(ovcs->fdt);
if (ovcs->notify_state == OF_OVERLAY_INIT ||
ovcs->notify_state == OF_OVERLAY_POST_REMOVE) {
kfree(ovcs->overlay_mem);
kfree(ovcs->new_fdt);
}
kfree(ovcs);
}
......@@ -874,28 +875,13 @@ static void free_overlay_changeset(struct overlay_changeset *ovcs)
* internal documentation
*
* of_overlay_apply() - Create and apply an overlay changeset
* @fdt: base of memory allocated to hold the aligned FDT
* @tree: Expanded overlay device tree
* @ovcs_id: Pointer to overlay changeset id
* @ovcs: overlay changeset
*
* Creates and applies an overlay changeset.
*
* If an error occurs in a pre-apply notifier, then no changes are made
* to the device tree.
*
* A non-zero return value will not have created the changeset if error is from:
* - parameter checks
* - building the changeset
* - overlay changeset pre-apply notifier
*
* If an error is returned by an overlay changeset pre-apply notifier
* then no further overlay changeset pre-apply notifier will be called.
*
* A non-zero return value will have created the changeset if error is from:
* - overlay changeset entry notifier
* - overlay changeset post-apply notifier
*
* If an error is returned by an overlay changeset post-apply notifier
* then no further overlay changeset post-apply notifier will be called.
*
......@@ -909,64 +895,35 @@ static void free_overlay_changeset(struct overlay_changeset *ovcs)
* following attempt to apply or remove an overlay changeset will be
* refused.
*
* Returns 0 on success, or a negative error number. Overlay changeset
* id is returned to *ovcs_id.
* Returns 0 on success, or a negative error number. On error return,
* the caller of of_overlay_apply() must call free_overlay_changeset().
*/
static int of_overlay_apply(const void *fdt, struct device_node *tree,
int *ovcs_id)
static int of_overlay_apply(struct overlay_changeset *ovcs)
{
struct overlay_changeset *ovcs;
int ret = 0, ret_revert, ret_tmp;
/*
* As of this point, fdt and tree belong to the overlay changeset.
* overlay changeset code is responsible for freeing them.
*/
if (devicetree_corrupt()) {
pr_err("devicetree state suspect, refuse to apply overlay\n");
kfree(fdt);
kfree(tree);
ret = -EBUSY;
goto out;
}
ovcs = kzalloc(sizeof(*ovcs), GFP_KERNEL);
if (!ovcs) {
kfree(fdt);
kfree(tree);
ret = -ENOMEM;
goto out;
}
of_overlay_mutex_lock();
mutex_lock(&of_mutex);
ret = of_resolve_phandles(tree);
ret = of_resolve_phandles(ovcs->overlay_root);
if (ret)
goto err_free_tree;
goto out;
ret = init_overlay_changeset(ovcs, fdt, tree);
ret = init_overlay_changeset(ovcs);
if (ret)
goto err_free_tree;
goto out;
/*
* after overlay_notify(), ovcs->overlay_tree related pointers may have
* leaked to drivers, so can not kfree() tree, aka ovcs->overlay_tree;
* and can not free memory containing aligned fdt. The aligned fdt
* is contained within the memory at ovcs->fdt, possibly at an offset
* from ovcs->fdt.
*/
ret = overlay_notify(ovcs, OF_OVERLAY_PRE_APPLY);
if (ret) {
pr_err("overlay changeset pre-apply notify error %d\n", ret);
goto err_free_overlay_changeset;
}
if (ret)
goto out;
ret = build_changeset(ovcs);
if (ret)
goto err_free_overlay_changeset;
goto out;
ret_revert = 0;
ret = __of_changeset_apply_entries(&ovcs->cset, &ret_revert);
......@@ -976,7 +933,7 @@ static int of_overlay_apply(const void *fdt, struct device_node *tree,
ret_revert);
devicetree_state_flags |= DTSF_APPLY_FAIL;
}
goto err_free_overlay_changeset;
goto out;
}
ret = __of_changeset_apply_notify(&ovcs->cset);
......@@ -984,29 +941,10 @@ static int of_overlay_apply(const void *fdt, struct device_node *tree,
pr_err("overlay apply changeset entry notify error %d\n", ret);
/* notify failure is not fatal, continue */
list_add_tail(&ovcs->ovcs_list, &ovcs_list);
*ovcs_id = ovcs->id;
ret_tmp = overlay_notify(ovcs, OF_OVERLAY_POST_APPLY);
if (ret_tmp) {
pr_err("overlay changeset post-apply notify error %d\n",
ret_tmp);
if (ret_tmp)
if (!ret)
ret = ret_tmp;
}
goto out_unlock;
err_free_tree:
kfree(fdt);
kfree(tree);
err_free_overlay_changeset:
free_overlay_changeset(ovcs);
out_unlock:
mutex_unlock(&of_mutex);
of_overlay_mutex_unlock();
out:
pr_debug("%s() err=%d\n", __func__, ret);
......@@ -1014,16 +952,36 @@ static int of_overlay_apply(const void *fdt, struct device_node *tree,
return ret;
}
/*
* of_overlay_fdt_apply() - Create and apply an overlay changeset
* @overlay_fdt: pointer to overlay FDT
* @overlay_fdt_size: number of bytes in @overlay_fdt
* @ret_ovcs_id: pointer for returning created changeset id
*
* Creates and applies an overlay changeset.
*
* See of_overlay_apply() for important behavior information.
*
* Return: 0 on success, or a negative error number. *@ret_ovcs_id is set to
* the value of overlay changeset id, which can be passed to of_overlay_remove()
* to remove the overlay.
*
* On error return, the changeset may be partially applied. This is especially
* likely if an OF_OVERLAY_POST_APPLY notifier returns an error. In this case
* the caller should call of_overlay_remove() with the value in *@ret_ovcs_id.
*/
int of_overlay_fdt_apply(const void *overlay_fdt, u32 overlay_fdt_size,
int *ovcs_id)
int *ret_ovcs_id)
{
void *new_fdt;
void *new_fdt_align;
void *overlay_mem;
int ret;
u32 size;
struct device_node *overlay_root = NULL;
struct overlay_changeset *ovcs;
*ovcs_id = 0;
*ret_ovcs_id = 0;
if (overlay_fdt_size < sizeof(struct fdt_header) ||
fdt_check_header(overlay_fdt)) {
......@@ -1035,41 +993,71 @@ int of_overlay_fdt_apply(const void *overlay_fdt, u32 overlay_fdt_size,
if (overlay_fdt_size < size)
return -EINVAL;
ovcs = kzalloc(sizeof(*ovcs), GFP_KERNEL);
if (!ovcs)
return -ENOMEM;
of_overlay_mutex_lock();
mutex_lock(&of_mutex);
/*
* ovcs->notify_state must be set to OF_OVERLAY_INIT before allocating
* ovcs resources, implicitly set by kzalloc() of ovcs
*/
ovcs->id = idr_alloc(&ovcs_idr, ovcs, 1, 0, GFP_KERNEL);
if (ovcs->id <= 0) {
ret = ovcs->id;
goto err_free_ovcs;
}
INIT_LIST_HEAD(&ovcs->ovcs_list);
list_add_tail(&ovcs->ovcs_list, &ovcs_list);
/*
* Must create permanent copy of FDT because of_fdt_unflatten_tree()
* will create pointers to the passed in FDT in the unflattened tree.
*/
new_fdt = kmalloc(size + FDT_ALIGN_SIZE, GFP_KERNEL);
if (!new_fdt)
return -ENOMEM;
if (!new_fdt) {
ret = -ENOMEM;
goto err_free_ovcs;
}
ovcs->new_fdt = new_fdt;
new_fdt_align = PTR_ALIGN(new_fdt, FDT_ALIGN_SIZE);
memcpy(new_fdt_align, overlay_fdt, size);
of_fdt_unflatten_tree(new_fdt_align, NULL, &overlay_root);
if (!overlay_root) {
overlay_mem = of_fdt_unflatten_tree(new_fdt_align, NULL,
&ovcs->overlay_root);
if (!overlay_mem) {
pr_err("unable to unflatten overlay_fdt\n");
ret = -EINVAL;
goto out_free_new_fdt;
goto err_free_ovcs;
}
ovcs->overlay_mem = overlay_mem;
ret = of_overlay_apply(new_fdt, overlay_root, ovcs_id);
if (ret < 0) {
ret = of_overlay_apply(ovcs);
/*
* new_fdt and overlay_root now belong to the overlay
* changeset.
* overlay changeset code is responsible for freeing them.
* If of_overlay_apply() error, calling free_overlay_changeset() may
* result in a memory leak if the apply partly succeeded, so do NOT
* goto err_free_ovcs. Instead, the caller of of_overlay_fdt_apply()
* can call of_overlay_remove();
*/
goto out;
}
return 0;
mutex_unlock(&of_mutex);
of_overlay_mutex_unlock();
*ret_ovcs_id = ovcs->id;
out_free_new_fdt:
kfree(new_fdt);
return ret;
err_free_ovcs:
free_overlay_changeset(ovcs);
mutex_unlock(&of_mutex);
of_overlay_mutex_unlock();
out:
return ret;
}
EXPORT_SYMBOL_GPL(of_overlay_fdt_apply);
......@@ -1206,28 +1194,24 @@ int of_overlay_remove(int *ovcs_id)
if (!ovcs) {
ret = -ENODEV;
pr_err("remove: Could not find overlay #%d\n", *ovcs_id);
goto out_unlock;
goto err_unlock;
}
if (!overlay_removal_is_ok(ovcs)) {
ret = -EBUSY;
goto out_unlock;
goto err_unlock;
}
ret = overlay_notify(ovcs, OF_OVERLAY_PRE_REMOVE);
if (ret) {
pr_err("overlay changeset pre-remove notify error %d\n", ret);
goto out_unlock;
}
list_del(&ovcs->ovcs_list);
if (ret)
goto err_unlock;
ret_apply = 0;
ret = __of_changeset_revert_entries(&ovcs->cset, &ret_apply);
if (ret) {
if (ret_apply)
devicetree_state_flags |= DTSF_REVERT_FAIL;
goto out_unlock;
goto err_unlock;
}
ret = __of_changeset_revert_notify(&ovcs->cset);
......@@ -1237,17 +1221,24 @@ int of_overlay_remove(int *ovcs_id)
*ovcs_id = 0;
/*
* Note that the overlay memory will be kfree()ed by
* free_overlay_changeset() even if the notifier for
* OF_OVERLAY_POST_REMOVE returns an error.
*/
ret_tmp = overlay_notify(ovcs, OF_OVERLAY_POST_REMOVE);
if (ret_tmp) {
pr_err("overlay changeset post-remove notify error %d\n",
ret_tmp);
if (ret_tmp)
if (!ret)
ret = ret_tmp;
}
free_overlay_changeset(ovcs);
out_unlock:
err_unlock:
/*
* If jumped over free_overlay_changeset(), then did not kfree()
* overlay related memory. This is a memory leak unless a subsequent
* of_overlay_remove() of this overlay is successful.
*/
mutex_unlock(&of_mutex);
out:
......
drivers/of/platform.c
View file @ 86c87bea
......@@ -114,35 +114,31 @@ struct platform_device *of_device_alloc(struct device_node *np,
struct device *parent)
{
struct platform_device *dev;
int rc, i, num_reg = 0, num_irq;
int rc, i, num_reg = 0;
struct resource *res, temp_res;
dev = platform_device_alloc("", PLATFORM_DEVID_NONE);
if (!dev)
return NULL;
/* count the io and irq resources */
/* count the io resources */
while (of_address_to_resource(np, num_reg, &temp_res) == 0)
num_reg++;
num_irq = of_irq_count(np);
/* Populate the resource table */
if (num_irq || num_reg) {
res = kcalloc(num_irq + num_reg, sizeof(*res), GFP_KERNEL);
if (num_reg) {
res = kcalloc(num_reg, sizeof(*res), GFP_KERNEL);
if (!res) {
platform_device_put(dev);
return NULL;
}
dev->num_resources = num_reg + num_irq;
dev->num_resources = num_reg;
dev->resource = res;
for (i = 0; i < num_reg; i++, res++) {
rc = of_address_to_resource(np, i, res);
WARN_ON(rc);
}
if (of_irq_to_resource_table(np, res, num_irq) != num_irq)
pr_debug("not all legacy IRQ resources mapped for %pOFn\n",
np);
}
dev->dev.of_node = of_node_get(np);
......
drivers/of/property.c
View file @ 86c87bea
......@@ -432,6 +432,9 @@ EXPORT_SYMBOL_GPL(of_property_read_variable_u64_array);
* property does not have a value, and -EILSEQ if the string is not
* null-terminated within the length of the property data.
*
* Note that the empty string "" has length of 1, thus -ENODATA cannot
* be interpreted as an empty string.
*
* The out_string pointer is modified only if a valid string can be decoded.
*/
int of_property_read_string(const struct device_node *np, const char *propname,
......@@ -440,7 +443,7 @@ int of_property_read_string(const struct device_node *np, const char *propname,
const struct property *prop = of_find_property(np, propname, NULL);
if (!prop)
return -EINVAL;
if (!prop->value)
if (!prop->length)
return -ENODATA;
if (strnlen(prop->value, prop->length) >= prop->length)
return -EILSEQ;
......
drivers/of/unittest-data/Makefile
View file @ 86c87bea
......@@ -17,6 +17,11 @@ obj-$(CONFIG_OF_OVERLAY) += overlay.dtb.o \
overlay_12.dtb.o \
overlay_13.dtb.o \
overlay_15.dtb.o \
overlay_16.dtb.o \
overlay_17.dtb.o \
overlay_18.dtb.o \
overlay_19.dtb.o \
overlay_20.dtb.o \
overlay_bad_add_dup_node.dtb.o \
overlay_bad_add_dup_prop.dtb.o \
overlay_bad_phandle.dtb.o \
......@@ -75,6 +80,11 @@ apply_static_overlay_1 := overlay_0.dtbo \
overlay_12.dtbo \
overlay_13.dtbo \
overlay_15.dtbo \
overlay_16.dtbo \
overlay_17.dtbo \
overlay_18.dtbo \
overlay_19.dtbo \
overlay_20.dtbo \
overlay_gpio_01.dtbo \
overlay_gpio_02a.dtbo \
overlay_gpio_02b.dtbo \
......
drivers/of/unittest-data/overlay_16.dts 0 → 100644
View file @ 86c87bea
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/plugin/;
/* overlay_16 - notify test */
&unittest_test_bus {
#address-cells = <1>;
#size-cells = <0>;
test-unittest16 {
compatible = "unittest";
reg = <16>;
};
};
drivers/of/unittest-data/overlay_17.dts 0 → 100644
View file @ 86c87bea
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/plugin/;
/* overlay_17 - notify test */
&unittest_test_bus {
#address-cells = <1>;
#size-cells = <0>;
test-unittest17 {
compatible = "unittest";
reg = <17>;
};
};
drivers/of/unittest-data/overlay_18.dts 0 → 100644
View file @ 86c87bea
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/plugin/;
/* overlay_18 - notify test */
&unittest_test_bus {
#address-cells = <1>;
#size-cells = <0>;
test-unittest18 {
compatible = "unittest";
reg = <18>;
};
};
drivers/of/unittest-data/overlay_19.dts 0 → 100644
View file @ 86c87bea
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/plugin/;
/* overlay_19 - notify test */
&unittest_test_bus {
#address-cells = <1>;
#size-cells = <0>;
test-unittest19 {
compatible = "unittest";
reg = <19>;
};
};
drivers/of/unittest-data/overlay_20.dts 0 → 100644
View file @ 86c87bea
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/plugin/;
/* overlay_20 - notify test */
&unittest_test_bus {
#address-cells = <1>;
#size-cells = <0>;
test-unittest20 {
compatible = "unittest";
reg = <20>;
};
};
drivers/of/unittest.c
View file @ 86c87bea
......@@ -2741,6 +2741,195 @@ static inline void of_unittest_overlay_i2c_15(void) { }
#endif
static int of_notify(struct notifier_block *nb, unsigned long action,
void *arg)
{
struct of_overlay_notify_data *nd = arg;
struct device_node *found;
int ret;
/*
* For overlay_16 .. overlay_19, check that returning an error
* works for each of the actions by setting an arbitrary return
* error number that matches the test number. e.g. for unittest16,
* ret = -EBUSY which is -16.
*
* OVERLAY_INFO() for the overlays is declared to expect the same
* error number, so overlay_data_apply() will return no error.
*
* overlay_20 will return NOTIFY_DONE
*/
ret = 0;
of_node_get(nd->overlay);
switch (action) {
case OF_OVERLAY_PRE_APPLY:
found = of_find_node_by_name(nd->overlay, "test-unittest16");
if (found) {
of_node_put(found);
ret = -EBUSY;
}
break;
case OF_OVERLAY_POST_APPLY:
found = of_find_node_by_name(nd->overlay, "test-unittest17");
if (found) {
of_node_put(found);
ret = -EEXIST;
}
break;
case OF_OVERLAY_PRE_REMOVE:
found = of_find_node_by_name(nd->overlay, "test-unittest18");
if (found) {
of_node_put(found);
ret = -EXDEV;
}
break;
case OF_OVERLAY_POST_REMOVE:
found = of_find_node_by_name(nd->overlay, "test-unittest19");
if (found) {
of_node_put(found);
ret = -ENODEV;
}
break;
default: /* should not happen */
of_node_put(nd->overlay);
ret = -EINVAL;
break;
}
if (ret)
return notifier_from_errno(ret);
return NOTIFY_DONE;
}
static struct notifier_block of_nb = {
.notifier_call = of_notify,
};
static void __init of_unittest_overlay_notify(void)
{
int ovcs_id;
int ret;
ret = of_overlay_notifier_register(&of_nb);
unittest(!ret,
"of_overlay_notifier_register() failed, ret = %d\n", ret);
if (ret)
return;
/*
* The overlays are applied by overlay_data_apply()
* instead of of_unittest_apply_overlay() so that they
* will not be tracked. Thus they will not be removed
* by of_unittest_remove_tracked_overlays().
*
* Applying overlays 16 - 19 will each trigger an error for a
* different action in of_notify().
*
* Applying overlay 20 will not trigger any error in of_notify().
*/
/* --- overlay 16 --- */
EXPECT_BEGIN(KERN_INFO, "OF: overlay: overlay changeset pre-apply notifier error -16, target: /testcase-data/overlay-node/test-bus");
unittest(overlay_data_apply("overlay_16", &ovcs_id),
"test OF_OVERLAY_PRE_APPLY notify injected error\n");
EXPECT_END(KERN_INFO, "OF: overlay: overlay changeset pre-apply notifier error -16, target: /testcase-data/overlay-node/test-bus");
unittest(ovcs_id, "ovcs_id not created for overlay_16\n");
/* --- overlay 17 --- */
EXPECT_BEGIN(KERN_INFO, "OF: overlay: overlay changeset post-apply notifier error -17, target: /testcase-data/overlay-node/test-bus");
unittest(overlay_data_apply("overlay_17", &ovcs_id),
"test OF_OVERLAY_POST_APPLY notify injected error\n");
EXPECT_END(KERN_INFO, "OF: overlay: overlay changeset post-apply notifier error -17, target: /testcase-data/overlay-node/test-bus");
unittest(ovcs_id, "ovcs_id not created for overlay_17\n");
if (ovcs_id) {
ret = of_overlay_remove(&ovcs_id);
unittest(!ret,
"overlay_17 of_overlay_remove(), ret = %d\n", ret);
}
/* --- overlay 18 --- */
unittest(overlay_data_apply("overlay_18", &ovcs_id),
"OF_OVERLAY_PRE_REMOVE notify injected error\n");
unittest(ovcs_id, "ovcs_id not created for overlay_18\n");
if (ovcs_id) {
EXPECT_BEGIN(KERN_INFO, "OF: overlay: overlay changeset pre-remove notifier error -18, target: /testcase-data/overlay-node/test-bus");
ret = of_overlay_remove(&ovcs_id);
EXPECT_END(KERN_INFO, "OF: overlay: overlay changeset pre-remove notifier error -18, target: /testcase-data/overlay-node/test-bus");
if (ret == -EXDEV) {
/*
* change set ovcs_id should still exist
*/
unittest(1, "overlay_18 of_overlay_remove() injected error for OF_OVERLAY_PRE_REMOVE\n");
} else {
unittest(0, "overlay_18 of_overlay_remove() injected error for OF_OVERLAY_PRE_REMOVE not returned\n");
}
} else {
unittest(1, "ovcs_id not created for overlay_18\n");
}
unittest(ovcs_id, "ovcs_id removed for overlay_18\n");
/* --- overlay 19 --- */
unittest(overlay_data_apply("overlay_19", &ovcs_id),
"OF_OVERLAY_POST_REMOVE notify injected error\n");
unittest(ovcs_id, "ovcs_id not created for overlay_19\n");
if (ovcs_id) {
EXPECT_BEGIN(KERN_INFO, "OF: overlay: overlay changeset post-remove notifier error -19, target: /testcase-data/overlay-node/test-bus");
ret = of_overlay_remove(&ovcs_id);
EXPECT_END(KERN_INFO, "OF: overlay: overlay changeset post-remove notifier error -19, target: /testcase-data/overlay-node/test-bus");
if (ret == -ENODEV)
unittest(1, "overlay_19 of_overlay_remove() injected error for OF_OVERLAY_POST_REMOVE\n");
else
unittest(0, "overlay_19 of_overlay_remove() injected error for OF_OVERLAY_POST_REMOVE not returned\n");
} else {
unittest(1, "ovcs_id removed for overlay_19\n");
}
unittest(!ovcs_id, "changeset ovcs_id = %d not removed for overlay_19\n",
ovcs_id);
/* --- overlay 20 --- */
unittest(overlay_data_apply("overlay_20", &ovcs_id),
"overlay notify no injected error\n");
if (ovcs_id) {
ret = of_overlay_remove(&ovcs_id);
if (ret)
unittest(1, "overlay_20 failed to be destroyed, ret = %d\n",
ret);
} else {
unittest(1, "ovcs_id not created for overlay_20\n");
}
unittest(!of_overlay_notifier_unregister(&of_nb),
"of_overlay_notifier_unregister() failed, ret = %d\n", ret);
}
static void __init of_unittest_overlay(void)
{
struct device_node *bus_np = NULL;
......@@ -2804,6 +2993,8 @@ static void __init of_unittest_overlay(void)
of_unittest_remove_tracked_overlays();
of_unittest_overlay_notify();
out:
of_node_put(bus_np);
}
......@@ -2855,6 +3046,11 @@ OVERLAY_INFO_EXTERN(overlay_11);
OVERLAY_INFO_EXTERN(overlay_12);
OVERLAY_INFO_EXTERN(overlay_13);
OVERLAY_INFO_EXTERN(overlay_15);
OVERLAY_INFO_EXTERN(overlay_16);
OVERLAY_INFO_EXTERN(overlay_17);
OVERLAY_INFO_EXTERN(overlay_18);
OVERLAY_INFO_EXTERN(overlay_19);
OVERLAY_INFO_EXTERN(overlay_20);
OVERLAY_INFO_EXTERN(overlay_gpio_01);
OVERLAY_INFO_EXTERN(overlay_gpio_02a);
OVERLAY_INFO_EXTERN(overlay_gpio_02b);
......@@ -2885,6 +3081,11 @@ static struct overlay_info overlays[] = {
OVERLAY_INFO(overlay_12, 0),
OVERLAY_INFO(overlay_13, 0),
OVERLAY_INFO(overlay_15, 0),
OVERLAY_INFO(overlay_16, -EBUSY),
OVERLAY_INFO(overlay_17, -EEXIST),
OVERLAY_INFO(overlay_18, 0),
OVERLAY_INFO(overlay_19, 0),
OVERLAY_INFO(overlay_20, 0),
OVERLAY_INFO(overlay_gpio_01, 0),
OVERLAY_INFO(overlay_gpio_02a, 0),
OVERLAY_INFO(overlay_gpio_02b, 0),
......
include/linux/of.h
View file @ 86c87bea
......@@ -1543,12 +1543,26 @@ static inline bool of_device_is_system_power_controller(const struct device_node
*/
enum of_overlay_notify_action {
OF_OVERLAY_PRE_APPLY = 0,
OF_OVERLAY_INIT = 0, /* kzalloc() of ovcs sets this value */
OF_OVERLAY_PRE_APPLY,
OF_OVERLAY_POST_APPLY,
OF_OVERLAY_PRE_REMOVE,
OF_OVERLAY_POST_REMOVE,
};
static inline char *of_overlay_action_name(enum of_overlay_notify_action action)
{
static char *of_overlay_action_name[] = {
"init",
"pre-apply",
"post-apply",
"pre-remove",
"post-remove",
};
return of_overlay_action_name[action];
}
struct of_overlay_notify_data {
struct device_node *overlay;
struct device_node *target;
......
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