Skip to content

L
linux
Commit 886fd9a4 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Stephen Boyd
Browse files
Options

clk: qcom: gcc-sm8350: use ARRAY_SIZE instead of specifying num_parents 

Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-34-dmitry.baryshkov@linaro.orgSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent c864cd5f
Show whitespace changes
Inline Side-by-side
Showing with 54 additions and 54 deletions
drivers/clk/qcom/gcc-sm8350.c
View file @ 886fd9a4
...@@ -297,7 +297,7 @@ static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { ...@@ -297,7 +297,7 @@ static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk_src", .name = "gcc_pcie_0_pipe_clk_src",
.parent_data = gcc_parent_data_4, .parent_data = gcc_parent_data_4,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_regmap_mux_closest_ops, .ops = &clk_regmap_mux_closest_ops,
}, },
}, },
...@@ -312,7 +312,7 @@ static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { ...@@ -312,7 +312,7 @@ static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk_src", .name = "gcc_pcie_1_pipe_clk_src",
.parent_data = gcc_parent_data_5, .parent_data = gcc_parent_data_5,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_regmap_mux_closest_ops, .ops = &clk_regmap_mux_closest_ops,
}, },
}, },
...@@ -327,7 +327,7 @@ static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src = { ...@@ -327,7 +327,7 @@ static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_rx_symbol_0_clk_src", .name = "gcc_ufs_card_rx_symbol_0_clk_src",
.parent_data = gcc_parent_data_7, .parent_data = gcc_parent_data_7,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_parent_data_7),
.ops = &clk_regmap_mux_closest_ops, .ops = &clk_regmap_mux_closest_ops,
}, },
}, },
...@@ -342,7 +342,7 @@ static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src = { ...@@ -342,7 +342,7 @@ static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_rx_symbol_1_clk_src", .name = "gcc_ufs_card_rx_symbol_1_clk_src",
.parent_data = gcc_parent_data_8, .parent_data = gcc_parent_data_8,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_regmap_mux_closest_ops, .ops = &clk_regmap_mux_closest_ops,
}, },
}, },
...@@ -357,7 +357,7 @@ static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src = { ...@@ -357,7 +357,7 @@ static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_tx_symbol_0_clk_src", .name = "gcc_ufs_card_tx_symbol_0_clk_src",
.parent_data = gcc_parent_data_9, .parent_data = gcc_parent_data_9,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_parent_data_9),
.ops = &clk_regmap_mux_closest_ops, .ops = &clk_regmap_mux_closest_ops,
}, },
}, },
...@@ -372,7 +372,7 @@ static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { ...@@ -372,7 +372,7 @@ static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk_src", .name = "gcc_ufs_phy_rx_symbol_0_clk_src",
.parent_data = gcc_parent_data_10, .parent_data = gcc_parent_data_10,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_parent_data_10),
.ops = &clk_regmap_mux_closest_ops, .ops = &clk_regmap_mux_closest_ops,
}, },
}, },
...@@ -387,7 +387,7 @@ static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = { ...@@ -387,7 +387,7 @@ static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_1_clk_src", .name = "gcc_ufs_phy_rx_symbol_1_clk_src",
.parent_data = gcc_parent_data_11, .parent_data = gcc_parent_data_11,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_parent_data_11),
.ops = &clk_regmap_mux_closest_ops, .ops = &clk_regmap_mux_closest_ops,
}, },
}, },
...@@ -402,7 +402,7 @@ static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = { ...@@ -402,7 +402,7 @@ static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk_src", .name = "gcc_ufs_phy_tx_symbol_0_clk_src",
.parent_data = gcc_parent_data_12, .parent_data = gcc_parent_data_12,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_parent_data_12),
.ops = &clk_regmap_mux_closest_ops, .ops = &clk_regmap_mux_closest_ops,
}, },
}, },
...@@ -417,7 +417,7 @@ static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { ...@@ -417,7 +417,7 @@ static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk_src", .name = "gcc_usb3_prim_phy_pipe_clk_src",
.parent_data = gcc_parent_data_13, .parent_data = gcc_parent_data_13,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_parent_data_13),
.ops = &clk_regmap_mux_closest_ops, .ops = &clk_regmap_mux_closest_ops,
}, },
}, },
...@@ -432,7 +432,7 @@ static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = { ...@@ -432,7 +432,7 @@ static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_pipe_clk_src", .name = "gcc_usb3_sec_phy_pipe_clk_src",
.parent_data = gcc_parent_data_14, .parent_data = gcc_parent_data_14,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_parent_data_14),
.ops = &clk_regmap_mux_closest_ops, .ops = &clk_regmap_mux_closest_ops,
}, },
}, },
...@@ -454,7 +454,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = { ...@@ -454,7 +454,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src", .name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_1, .parent_data = gcc_parent_data_1,
.num_parents = 5, .num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -469,7 +469,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = { ...@@ -469,7 +469,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src", .name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_1, .parent_data = gcc_parent_data_1,
.num_parents = 5, .num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -484,7 +484,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = { ...@@ -484,7 +484,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src", .name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_1, .parent_data = gcc_parent_data_1,
.num_parents = 5, .num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -505,7 +505,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { ...@@ -505,7 +505,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk_src", .name = "gcc_pcie_0_aux_clk_src",
.parent_data = gcc_parent_data_2, .parent_data = gcc_parent_data_2,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -526,7 +526,7 @@ static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { ...@@ -526,7 +526,7 @@ static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_phy_rchng_clk_src", .name = "gcc_pcie_0_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -541,7 +541,7 @@ static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { ...@@ -541,7 +541,7 @@ static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk_src", .name = "gcc_pcie_1_aux_clk_src",
.parent_data = gcc_parent_data_2, .parent_data = gcc_parent_data_2,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -556,7 +556,7 @@ static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { ...@@ -556,7 +556,7 @@ static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_phy_rchng_clk_src", .name = "gcc_pcie_1_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -576,7 +576,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { ...@@ -576,7 +576,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src", .name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -600,7 +600,7 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { ...@@ -600,7 +600,7 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
.name = "gcc_qupv3_wrap0_s0_clk_src", .name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}; };
...@@ -617,7 +617,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { ...@@ -617,7 +617,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
.name = "gcc_qupv3_wrap0_s1_clk_src", .name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}; };
...@@ -634,7 +634,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { ...@@ -634,7 +634,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
.name = "gcc_qupv3_wrap0_s2_clk_src", .name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}; };
...@@ -651,7 +651,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { ...@@ -651,7 +651,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
.name = "gcc_qupv3_wrap0_s3_clk_src", .name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}; };
...@@ -668,7 +668,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { ...@@ -668,7 +668,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
.name = "gcc_qupv3_wrap0_s4_clk_src", .name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}; };
...@@ -685,7 +685,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { ...@@ -685,7 +685,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
.name = "gcc_qupv3_wrap0_s5_clk_src", .name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}; };
...@@ -702,7 +702,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { ...@@ -702,7 +702,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
.name = "gcc_qupv3_wrap0_s6_clk_src", .name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}; };
...@@ -719,7 +719,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { ...@@ -719,7 +719,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
.name = "gcc_qupv3_wrap0_s7_clk_src", .name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}; };
...@@ -755,7 +755,7 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = { ...@@ -755,7 +755,7 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src", .name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}; };
...@@ -772,7 +772,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { ...@@ -772,7 +772,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src", .name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}; };
...@@ -789,7 +789,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { ...@@ -789,7 +789,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
.name = "gcc_qupv3_wrap1_s2_clk_src", .name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}; };
...@@ -806,7 +806,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { ...@@ -806,7 +806,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src", .name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}; };
...@@ -823,7 +823,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { ...@@ -823,7 +823,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src", .name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}; };
...@@ -840,7 +840,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { ...@@ -840,7 +840,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src", .name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}; };
...@@ -857,7 +857,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { ...@@ -857,7 +857,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
.name = "gcc_qupv3_wrap2_s0_clk_src", .name = "gcc_qupv3_wrap2_s0_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}; };
...@@ -874,7 +874,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { ...@@ -874,7 +874,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
.name = "gcc_qupv3_wrap2_s1_clk_src", .name = "gcc_qupv3_wrap2_s1_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}; };
...@@ -891,7 +891,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { ...@@ -891,7 +891,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
.name = "gcc_qupv3_wrap2_s2_clk_src", .name = "gcc_qupv3_wrap2_s2_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}; };
...@@ -908,7 +908,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { ...@@ -908,7 +908,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
.name = "gcc_qupv3_wrap2_s3_clk_src", .name = "gcc_qupv3_wrap2_s3_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}; };
...@@ -925,7 +925,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { ...@@ -925,7 +925,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
.name = "gcc_qupv3_wrap2_s4_clk_src", .name = "gcc_qupv3_wrap2_s4_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}; };
...@@ -942,7 +942,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { ...@@ -942,7 +942,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
.name = "gcc_qupv3_wrap2_s5_clk_src", .name = "gcc_qupv3_wrap2_s5_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}; };
...@@ -974,7 +974,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { ...@@ -974,7 +974,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk_src", .name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_6, .parent_data = gcc_parent_data_6,
.num_parents = 6, .num_parents = ARRAY_SIZE(gcc_parent_data_6),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_floor_ops, .ops = &clk_rcg2_floor_ops,
}, },
...@@ -996,7 +996,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { ...@@ -996,7 +996,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk_src", .name = "gcc_sdcc4_apps_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_floor_ops, .ops = &clk_rcg2_floor_ops,
}, },
...@@ -1019,7 +1019,7 @@ static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { ...@@ -1019,7 +1019,7 @@ static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_axi_clk_src", .name = "gcc_ufs_card_axi_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -1041,7 +1041,7 @@ static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { ...@@ -1041,7 +1041,7 @@ static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ice_core_clk_src", .name = "gcc_ufs_card_ice_core_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -1061,7 +1061,7 @@ static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { ...@@ -1061,7 +1061,7 @@ static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_phy_aux_clk_src", .name = "gcc_ufs_card_phy_aux_clk_src",
.parent_data = gcc_parent_data_3, .parent_data = gcc_parent_data_3,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_parent_data_3),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -1076,7 +1076,7 @@ static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { ...@@ -1076,7 +1076,7 @@ static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_unipro_core_clk_src", .name = "gcc_ufs_card_unipro_core_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -1091,7 +1091,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { ...@@ -1091,7 +1091,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk_src", .name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -1106,7 +1106,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { ...@@ -1106,7 +1106,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk_src", .name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -1121,7 +1121,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { ...@@ -1121,7 +1121,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk_src", .name = "gcc_ufs_phy_phy_aux_clk_src",
.parent_data = gcc_parent_data_3, .parent_data = gcc_parent_data_3,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_parent_data_3),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -1136,7 +1136,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { ...@@ -1136,7 +1136,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk_src", .name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -1159,7 +1159,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { ...@@ -1159,7 +1159,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk_src", .name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -1174,7 +1174,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { ...@@ -1174,7 +1174,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk_src", .name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -1189,7 +1189,7 @@ static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { ...@@ -1189,7 +1189,7 @@ static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk_src", .name = "gcc_usb30_sec_master_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -1204,7 +1204,7 @@ static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { ...@@ -1204,7 +1204,7 @@ static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_mock_utmi_clk_src", .name = "gcc_usb30_sec_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -1219,7 +1219,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { ...@@ -1219,7 +1219,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk_src", .name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parent_data_2, .parent_data = gcc_parent_data_2,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -1234,7 +1234,7 @@ static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { ...@@ -1234,7 +1234,7 @@ static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_aux_clk_src", .name = "gcc_usb3_sec_phy_aux_clk_src",
.parent_data = gcc_parent_data_2, .parent_data = gcc_parent_data_2,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7