Revert "x86/cpu/AMD: Make the LFENCE instruction serialized"

CVE-2017-5753 (Spectre v1 Intel -> upstream)
BugLink: http://bugs.launchpad.net/bugs/1754375

This reverts commit b9d71080
to be replaced by upstream changes.
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>
Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>

arch/x86/include/asm/msr-index.h

@@ -343,8 +343,6 @@
 #define FAM10H_MMIO_CONF_BASE_MASK	0xfffffffULL
 #define FAM10H_MMIO_CONF_BASE_SHIFT	20
 #define MSR_FAM10H_NODE_ID		0xc001100c
-#define MSR_F10H_DECFG			0xc0011029
-#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT	1
 
 /* K8 MSRs */
 #define MSR_K8_TOP_MEM1			0xc001001a

arch/x86/kernel/cpu/amd.c

@@ -746,17 +746,8 @@ static void init_amd(struct cpuinfo_x86 *c)
 		set_cpu_cap(c, X86_FEATURE_K8);
 
 	if (cpu_has_xmm2) {
-		/*
-		 * Use LFENCE for execution serialization. On some families
-		 * LFENCE is already serialized and the MSR is not available,
-		 * but msr_set_bit() uses rdmsrl_safe() and wrmsrl_safe().
-		 */
-		if (c->x86 > 0xf)
-			msr_set_bit(MSR_F10H_DECFG,
-				    MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
-
-		/* LFENCE with MSR_F10H_DECFG[1]=1 stops RDTSC speculation */
-		set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
+		/* MFENCE stops RDTSC speculation */
+		set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
 	}
 
 	/*