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Commit 8aae803f authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
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perf vendor events intel: Broadwellde v9 events 

Updates descriptions and encodings. Adds BR_MISP_EXEC.INDIRECT events.
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Samantha Alt <samantha.alt@intel.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20230324072218.181880-2-irogers@google.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 78036545
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Showing with 495 additions and 183 deletions
tools/perf/pmu-events/arch/x86/broadwellde/frontend.json
View file @ 8aae803f
......@@ -125,16 +125,16 @@
"UMask": "0x4"
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
"SampleAfterValue": "2000003",
"UMask": "0x30"
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
......@@ -143,7 +143,7 @@
"UMask": "0x10"
},
{
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
......@@ -153,7 +153,7 @@
"UMask": "0x10"
},
{
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
......@@ -161,10 +161,10 @@
"UMask": "0x10"
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
"SampleAfterValue": "2000003",
"UMask": "0x20"
},
......@@ -178,10 +178,10 @@
"UMask": "0x30"
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
"SampleAfterValue": "2000003",
"UMask": "0x30"
},
......
tools/perf/pmu-events/arch/x86/broadwellde/memory.json
View file @ 8aae803f
[
{
"BriefDescription": "Number of times HLE abort was triggered (PEBS)",
"BriefDescription": "Number of times HLE abort was triggered",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED",
"PEBS": "1",
"PublicDescription": "Number of times HLE abort was triggered (PEBS).",
"PublicDescription": "Number of times HLE abort was triggered.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
......@@ -73,98 +73,106 @@
"UMask": "0x2"
},
{
"BriefDescription": "Loads with latency value being above 128",
"BriefDescription": "Randomly selected loads with latency value being above 128",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 128.",
"PublicDescription": "Counts randomly selected loads with latency value being above 128.",
"SampleAfterValue": "1009",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 16",
"BriefDescription": "Randomly selected loads with latency value being above 16",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
"MSRValue": "0x10",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 16.",
"PublicDescription": "Counts randomly selected loads with latency value being above 16.",
"SampleAfterValue": "20011",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 256",
"BriefDescription": "Randomly selected loads with latency value being above 256",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
"MSRValue": "0x100",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 256.",
"PublicDescription": "Counts randomly selected loads with latency value being above 256.",
"SampleAfterValue": "503",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 32",
"BriefDescription": "Randomly selected loads with latency value being above 32",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
"MSRValue": "0x20",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 32.",
"PublicDescription": "Counts randomly selected loads with latency value being above 32.",
"SampleAfterValue": "100007",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 4",
"BriefDescription": "Randomly selected loads with latency value being above 4",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
"MSRValue": "0x4",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above four.",
"PublicDescription": "Counts randomly selected loads with latency value being above four.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 512",
"BriefDescription": "Randomly selected loads with latency value being above 512",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
"MSRValue": "0x200",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 512.",
"PublicDescription": "Counts randomly selected loads with latency value being above 512.",
"SampleAfterValue": "101",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 64",
"BriefDescription": "Randomly selected loads with latency value being above 64",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 64.",
"PublicDescription": "Counts randomly selected loads with latency value being above 64.",
"SampleAfterValue": "2003",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 8",
"BriefDescription": "Randomly selected loads with latency value being above 8",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above eight.",
"PublicDescription": "Counts randomly selected loads with latency value being above eight.",
"SampleAfterValue": "50021",
"UMask": "0x1"
},
......@@ -185,11 +193,11 @@
"UMask": "0x2"
},
{
"BriefDescription": "Number of times RTM abort was triggered (PEBS)",
"BriefDescription": "Number of times RTM abort was triggered",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBS": "1",
"PublicDescription": "Number of times RTM abort was triggered (PEBS).",
"PublicDescription": "Number of times RTM abort was triggered .",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
......
tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json
View file @ 8aae803f
......@@ -101,6 +101,7 @@
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
"PerPkg": "1",
"PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
"UMask": "0x10",
"Unit": "IRP"
},
......@@ -109,6 +110,7 @@
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_RD_INSERT",
"PerPkg": "1",
"PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
"UMask": "0x4",
"Unit": "IRP"
},
......@@ -117,6 +119,7 @@
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_WR_INSERT",
"PerPkg": "1",
"PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
"UMask": "0x8",
"Unit": "IRP"
},
......@@ -125,6 +128,7 @@
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.FAST_REJ",
"PerPkg": "1",
"PublicDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
"UMask": "0x2",
"Unit": "IRP"
},
......@@ -133,6 +137,7 @@
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.FAST_REQ",
"PerPkg": "1",
"PublicDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
"UMask": "0x1",
"Unit": "IRP"
},
......@@ -141,6 +146,7 @@
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.FAST_XFER",
"PerPkg": "1",
"PublicDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
"UMask": "0x20",
"Unit": "IRP"
},
......@@ -149,6 +155,7 @@
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.PF_ACK_HINT",
"PerPkg": "1",
"PublicDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
"UMask": "0x40",
"Unit": "IRP"
},
......@@ -175,6 +182,7 @@
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.LOST_FWD",
"PerPkg": "1",
"PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed",
"UMask": "0x10",
"Unit": "IRP"
},
......@@ -241,6 +249,7 @@
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
"EventCode": "0x4",
"EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
"PerPkg": "1",
......@@ -256,6 +265,7 @@
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY",
"EventCode": "0x7",
"EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
"PerPkg": "1",
......@@ -263,6 +273,7 @@
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
"EventCode": "0x5",
"EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
"PerPkg": "1",
......@@ -278,6 +289,7 @@
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY",
"EventCode": "0x8",
"EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
"PerPkg": "1",
......@@ -285,6 +297,7 @@
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
"EventCode": "0x6",
"EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
"PerPkg": "1",
......@@ -300,6 +313,7 @@
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY",
"EventCode": "0x9",
"EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
"PerPkg": "1",
......@@ -311,6 +325,7 @@
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.HIT_ES",
"PerPkg": "1",
"PublicDescription": "Snoop Responses : Hit E or S",
"UMask": "0x4",
"Unit": "IRP"
},
......@@ -319,6 +334,7 @@
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.HIT_I",
"PerPkg": "1",
"PublicDescription": "Snoop Responses : Hit I",
"UMask": "0x2",
"Unit": "IRP"
},
......@@ -327,6 +343,7 @@
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.HIT_M",
"PerPkg": "1",
"PublicDescription": "Snoop Responses : Hit M",
"UMask": "0x8",
"Unit": "IRP"
},
......@@ -335,6 +352,7 @@
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.MISS",
"PerPkg": "1",
"PublicDescription": "Snoop Responses : Miss",
"UMask": "0x1",
"Unit": "IRP"
},
......@@ -343,6 +361,7 @@
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPCODE",
"PerPkg": "1",
"PublicDescription": "Snoop Responses : SnpCode",
"UMask": "0x10",
"Unit": "IRP"
},
......@@ -351,6 +370,7 @@
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPDATA",
"PerPkg": "1",
"PublicDescription": "Snoop Responses : SnpData",
"UMask": "0x20",
"Unit": "IRP"
},
......@@ -359,6 +379,7 @@
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPINV",
"PerPkg": "1",
"PublicDescription": "Snoop Responses : SnpInv",
"UMask": "0x40",
"Unit": "IRP"
},
......@@ -453,7 +474,7 @@
"EventCode": "0xD",
"EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
"PerPkg": "1",
"PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
"PublicDescription": "Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.",
"Unit": "IRP"
},
{
......@@ -465,6 +486,7 @@
"Unit": "R2PCIe"
},
{
"BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
"EventCode": "0x2D",
"EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
"PerPkg": "1",
......@@ -472,6 +494,7 @@
"Unit": "R2PCIe"
},
{
"BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
"EventCode": "0x2D",
"EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
"PerPkg": "1",
......@@ -479,6 +502,7 @@
"Unit": "R2PCIe"
},
{
"BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
"EventCode": "0x2D",
"EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
"PerPkg": "1",
......@@ -486,6 +510,7 @@
"Unit": "R2PCIe"
},
{
"BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
"EventCode": "0x2D",
"EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
"PerPkg": "1",
......
tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json
View file @ 8aae803f
......@@ -395,7 +395,7 @@
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"PerPkg": "1",
"PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
......@@ -403,7 +403,7 @@
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"PerPkg": "1",
"PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
......@@ -411,7 +411,7 @@
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"PerPkg": "1",
"PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
......@@ -427,7 +427,7 @@
"EventCode": "0x9",
"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that we are in Interal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
"PublicDescription": "Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
......@@ -439,6 +439,7 @@
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV",
"EventCode": "0x79",
"EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
"PerPkg": "1",
......@@ -450,6 +451,7 @@
"EventCode": "0x42",
"EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",
"PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot. Does not cover DRAM VRs",
"Unit": "PCU"
}
]
tools/perf/pmu-events/arch/x86/mapfile.csv
View file @ 8aae803f
......@@ -3,7 +3,7 @@ GenuineIntel-6-(97|9A|B7|BA|BF),v1.19,alderlake,core
GenuineIntel-6-BE,v1.19,alderlaken,core
GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core
GenuineIntel-6-(3D|47),v27,broadwell,core
GenuineIntel-6-56,v7,broadwellde,core
GenuineIntel-6-56,v9,broadwellde,core
GenuineIntel-6-4F,v19,broadwellx,core
GenuineIntel-6-55-[56789ABCDEF],v1.17,cascadelakex,core
GenuineIntel-6-9[6C],v1.03,elkhartlake,core
......
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