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Commit 8ce75f8a authored by Sinclair Yeh's avatar Sinclair Yeh Committed by Thomas Hellstrom
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drm/vmwgfx: Update device includes for DX device functionality 

Add DX includes and move all device includes to a separate directory.

Co-authored with Thomas Hellstrom, Charmaine Lee and above all,
the VMware device team.
Signed-off-by: default avatarSinclair Yeh <syeh@vmware.com>
Signed-off-by: default avatarThomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: default avatarCharmaine Lee <charmainel@vmware.com>
parent 5101020c
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Showing with 7597 additions and 231 deletions
drivers/gpu/drm/vmwgfx/device_include/svga3d_caps.h 0 → 100644
View file @ 8ce75f8a
/**********************************************************
* Copyright 2007-2015 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
/*
* svga3d_caps.h --
*
* Definitions for SVGA3D hardware capabilities. Capabilities
* are used to query for optional rendering features during
* driver initialization. The capability data is stored as very
* basic key/value dictionary within the "FIFO register" memory
* area at the beginning of BAR2.
*
* Note that these definitions are only for 3D capabilities.
* The SVGA device also has "device capabilities" and "FIFO
* capabilities", which are non-3D-specific and are stored as
* bitfields rather than key/value pairs.
*/
#ifndef _SVGA3D_CAPS_H_
#define _SVGA3D_CAPS_H_
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#include "includeCheck.h"
#include "svga_reg.h"
#define SVGA_FIFO_3D_CAPS_SIZE (SVGA_FIFO_3D_CAPS_LAST - \
SVGA_FIFO_3D_CAPS + 1)
/*
* SVGA3dCapsRecordType
*
* Record types that can be found in the caps block.
* Related record types are grouped together numerically so that
* SVGA3dCaps_FindRecord() can be applied on a range of record
* types.
*/
typedef enum {
SVGA3DCAPS_RECORD_UNKNOWN = 0,
SVGA3DCAPS_RECORD_DEVCAPS_MIN = 0x100,
SVGA3DCAPS_RECORD_DEVCAPS = 0x100,
SVGA3DCAPS_RECORD_DEVCAPS_MAX = 0x1ff,
} SVGA3dCapsRecordType;
/*
* SVGA3dCapsRecordHeader
*
* Header field leading each caps block record. Contains the offset (in
* register words, NOT bytes) to the next caps block record (or the end
* of caps block records which will be a zero word) and the record type
* as defined above.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCapsRecordHeader {
uint32 length;
SVGA3dCapsRecordType type;
}
#include "vmware_pack_end.h"
SVGA3dCapsRecordHeader;
/*
* SVGA3dCapsRecord
*
* Caps block record; "data" is a placeholder for the actual data structure
* contained within the record;
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCapsRecord {
SVGA3dCapsRecordHeader header;
uint32 data[1];
}
#include "vmware_pack_end.h"
SVGA3dCapsRecord;
typedef uint32 SVGA3dCapPair[2];
#endif
drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h 0 → 100644
View file @ 8ce75f8a
/**********************************************************
* Copyright 1998-2015 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
/*
* svga3d_cmd.h --
*
* SVGA 3d hardware cmd definitions
*/
#ifndef _SVGA3D_CMD_H_
#define _SVGA3D_CMD_H_
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#define INCLUDE_ALLOW_VMCORE
#include "includeCheck.h"
#include "svga3d_types.h"
/*
* Identifiers for commands in the command FIFO.
*
* IDs between 1000 and 1039 (inclusive) were used by obsolete versions of
* the SVGA3D protocol and remain reserved; they should not be used in the
* future.
*
* IDs between 1040 and 1999 (inclusive) are available for use by the
* current SVGA3D protocol.
*
* FIFO clients other than SVGA3D should stay below 1000, or at 2000
* and up.
*/
typedef enum {
SVGA_3D_CMD_LEGACY_BASE = 1000,
SVGA_3D_CMD_BASE = 1040,
SVGA_3D_CMD_SURFACE_DEFINE = 1040,
SVGA_3D_CMD_SURFACE_DESTROY = 1041,
SVGA_3D_CMD_SURFACE_COPY = 1042,
SVGA_3D_CMD_SURFACE_STRETCHBLT = 1043,
SVGA_3D_CMD_SURFACE_DMA = 1044,
SVGA_3D_CMD_CONTEXT_DEFINE = 1045,
SVGA_3D_CMD_CONTEXT_DESTROY = 1046,
SVGA_3D_CMD_SETTRANSFORM = 1047,
SVGA_3D_CMD_SETZRANGE = 1048,
SVGA_3D_CMD_SETRENDERSTATE = 1049,
SVGA_3D_CMD_SETRENDERTARGET = 1050,
SVGA_3D_CMD_SETTEXTURESTATE = 1051,
SVGA_3D_CMD_SETMATERIAL = 1052,
SVGA_3D_CMD_SETLIGHTDATA = 1053,
SVGA_3D_CMD_SETLIGHTENABLED = 1054,
SVGA_3D_CMD_SETVIEWPORT = 1055,
SVGA_3D_CMD_SETCLIPPLANE = 1056,
SVGA_3D_CMD_CLEAR = 1057,
SVGA_3D_CMD_PRESENT = 1058,
SVGA_3D_CMD_SHADER_DEFINE = 1059,
SVGA_3D_CMD_SHADER_DESTROY = 1060,
SVGA_3D_CMD_SET_SHADER = 1061,
SVGA_3D_CMD_SET_SHADER_CONST = 1062,
SVGA_3D_CMD_DRAW_PRIMITIVES = 1063,
SVGA_3D_CMD_SETSCISSORRECT = 1064,
SVGA_3D_CMD_BEGIN_QUERY = 1065,
SVGA_3D_CMD_END_QUERY = 1066,
SVGA_3D_CMD_WAIT_FOR_QUERY = 1067,
SVGA_3D_CMD_PRESENT_READBACK = 1068,
SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN = 1069,
SVGA_3D_CMD_SURFACE_DEFINE_V2 = 1070,
SVGA_3D_CMD_GENERATE_MIPMAPS = 1071,
SVGA_3D_CMD_VIDEO_CREATE_DECODER = 1072,
SVGA_3D_CMD_VIDEO_DESTROY_DECODER = 1073,
SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR = 1074,
SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR = 1075,
SVGA_3D_CMD_VIDEO_DECODE_START_FRAME = 1076,
SVGA_3D_CMD_VIDEO_DECODE_RENDER = 1077,
SVGA_3D_CMD_VIDEO_DECODE_END_FRAME = 1078,
SVGA_3D_CMD_VIDEO_PROCESS_FRAME = 1079,
SVGA_3D_CMD_ACTIVATE_SURFACE = 1080,
SVGA_3D_CMD_DEACTIVATE_SURFACE = 1081,
SVGA_3D_CMD_SCREEN_DMA = 1082,
SVGA_3D_CMD_SET_UNITY_SURFACE_COOKIE = 1083,
SVGA_3D_CMD_OPEN_CONTEXT_SURFACE = 1084,
SVGA_3D_CMD_LOGICOPS_BITBLT = 1085,
SVGA_3D_CMD_LOGICOPS_TRANSBLT = 1086,
SVGA_3D_CMD_LOGICOPS_STRETCHBLT = 1087,
SVGA_3D_CMD_LOGICOPS_COLORFILL = 1088,
SVGA_3D_CMD_LOGICOPS_ALPHABLEND = 1089,
SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND = 1090,
SVGA_3D_CMD_SET_OTABLE_BASE = 1091,
SVGA_3D_CMD_READBACK_OTABLE = 1092,
SVGA_3D_CMD_DEFINE_GB_MOB = 1093,
SVGA_3D_CMD_DESTROY_GB_MOB = 1094,
SVGA_3D_CMD_DEAD3 = 1095,
SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING = 1096,
SVGA_3D_CMD_DEFINE_GB_SURFACE = 1097,
SVGA_3D_CMD_DESTROY_GB_SURFACE = 1098,
SVGA_3D_CMD_BIND_GB_SURFACE = 1099,
SVGA_3D_CMD_COND_BIND_GB_SURFACE = 1100,
SVGA_3D_CMD_UPDATE_GB_IMAGE = 1101,
SVGA_3D_CMD_UPDATE_GB_SURFACE = 1102,
SVGA_3D_CMD_READBACK_GB_IMAGE = 1103,
SVGA_3D_CMD_READBACK_GB_SURFACE = 1104,
SVGA_3D_CMD_INVALIDATE_GB_IMAGE = 1105,
SVGA_3D_CMD_INVALIDATE_GB_SURFACE = 1106,
SVGA_3D_CMD_DEFINE_GB_CONTEXT = 1107,
SVGA_3D_CMD_DESTROY_GB_CONTEXT = 1108,
SVGA_3D_CMD_BIND_GB_CONTEXT = 1109,
SVGA_3D_CMD_READBACK_GB_CONTEXT = 1110,
SVGA_3D_CMD_INVALIDATE_GB_CONTEXT = 1111,
SVGA_3D_CMD_DEFINE_GB_SHADER = 1112,
SVGA_3D_CMD_DESTROY_GB_SHADER = 1113,
SVGA_3D_CMD_BIND_GB_SHADER = 1114,
SVGA_3D_CMD_SET_OTABLE_BASE64 = 1115,
SVGA_3D_CMD_BEGIN_GB_QUERY = 1116,
SVGA_3D_CMD_END_GB_QUERY = 1117,
SVGA_3D_CMD_WAIT_FOR_GB_QUERY = 1118,
SVGA_3D_CMD_NOP = 1119,
SVGA_3D_CMD_ENABLE_GART = 1120,
SVGA_3D_CMD_DISABLE_GART = 1121,
SVGA_3D_CMD_MAP_MOB_INTO_GART = 1122,
SVGA_3D_CMD_UNMAP_GART_RANGE = 1123,
SVGA_3D_CMD_DEFINE_GB_SCREENTARGET = 1124,
SVGA_3D_CMD_DESTROY_GB_SCREENTARGET = 1125,
SVGA_3D_CMD_BIND_GB_SCREENTARGET = 1126,
SVGA_3D_CMD_UPDATE_GB_SCREENTARGET = 1127,
SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL = 1128,
SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL = 1129,
SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE = 1130,
SVGA_3D_CMD_GB_SCREEN_DMA = 1131,
SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH = 1132,
SVGA_3D_CMD_GB_MOB_FENCE = 1133,
SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 = 1134,
SVGA_3D_CMD_DEFINE_GB_MOB64 = 1135,
SVGA_3D_CMD_REDEFINE_GB_MOB64 = 1136,
SVGA_3D_CMD_NOP_ERROR = 1137,
SVGA_3D_CMD_SET_VERTEX_STREAMS = 1138,
SVGA_3D_CMD_SET_VERTEX_DECLS = 1139,
SVGA_3D_CMD_SET_VERTEX_DIVISORS = 1140,
SVGA_3D_CMD_DRAW = 1141,
SVGA_3D_CMD_DRAW_INDEXED = 1142,
/*
* DX10 Commands
*/
SVGA_3D_CMD_DX_MIN = 1143,
SVGA_3D_CMD_DX_DEFINE_CONTEXT = 1143,
SVGA_3D_CMD_DX_DESTROY_CONTEXT = 1144,
SVGA_3D_CMD_DX_BIND_CONTEXT = 1145,
SVGA_3D_CMD_DX_READBACK_CONTEXT = 1146,
SVGA_3D_CMD_DX_INVALIDATE_CONTEXT = 1147,
SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER = 1148,
SVGA_3D_CMD_DX_SET_SHADER_RESOURCES = 1149,
SVGA_3D_CMD_DX_SET_SHADER = 1150,
SVGA_3D_CMD_DX_SET_SAMPLERS = 1151,
SVGA_3D_CMD_DX_DRAW = 1152,
SVGA_3D_CMD_DX_DRAW_INDEXED = 1153,
SVGA_3D_CMD_DX_DRAW_INSTANCED = 1154,
SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED = 1155,
SVGA_3D_CMD_DX_DRAW_AUTO = 1156,
SVGA_3D_CMD_DX_SET_INPUT_LAYOUT = 1157,
SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS = 1158,
SVGA_3D_CMD_DX_SET_INDEX_BUFFER = 1159,
SVGA_3D_CMD_DX_SET_TOPOLOGY = 1160,
SVGA_3D_CMD_DX_SET_RENDERTARGETS = 1161,
SVGA_3D_CMD_DX_SET_BLEND_STATE = 1162,
SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE = 1163,
SVGA_3D_CMD_DX_SET_RASTERIZER_STATE = 1164,
SVGA_3D_CMD_DX_DEFINE_QUERY = 1165,
SVGA_3D_CMD_DX_DESTROY_QUERY = 1166,
SVGA_3D_CMD_DX_BIND_QUERY = 1167,
SVGA_3D_CMD_DX_SET_QUERY_OFFSET = 1168,
SVGA_3D_CMD_DX_BEGIN_QUERY = 1169,
SVGA_3D_CMD_DX_END_QUERY = 1170,
SVGA_3D_CMD_DX_READBACK_QUERY = 1171,
SVGA_3D_CMD_DX_SET_PREDICATION = 1172,
SVGA_3D_CMD_DX_SET_SOTARGETS = 1173,
SVGA_3D_CMD_DX_SET_VIEWPORTS = 1174,
SVGA_3D_CMD_DX_SET_SCISSORRECTS = 1175,
SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW = 1176,
SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW = 1177,
SVGA_3D_CMD_DX_PRED_COPY_REGION = 1178,
SVGA_3D_CMD_DX_PRED_COPY = 1179,
SVGA_3D_CMD_DX_STRETCHBLT = 1180,
SVGA_3D_CMD_DX_GENMIPS = 1181,
SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE = 1182,
SVGA_3D_CMD_DX_READBACK_SUBRESOURCE = 1183,
SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE = 1184,
SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW = 1185,
SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW = 1186,
SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW = 1187,
SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW = 1188,
SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW = 1189,
SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW = 1190,
SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT = 1191,
SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT = 1192,
SVGA_3D_CMD_DX_DEFINE_BLEND_STATE = 1193,
SVGA_3D_CMD_DX_DESTROY_BLEND_STATE = 1194,
SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE = 1195,
SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE = 1196,
SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE = 1197,
SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE = 1198,
SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE = 1199,
SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE = 1200,
SVGA_3D_CMD_DX_DEFINE_SHADER = 1201,
SVGA_3D_CMD_DX_DESTROY_SHADER = 1202,
SVGA_3D_CMD_DX_BIND_SHADER = 1203,
SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT = 1204,
SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT = 1205,
SVGA_3D_CMD_DX_SET_STREAMOUTPUT = 1206,
SVGA_3D_CMD_DX_SET_COTABLE = 1207,
SVGA_3D_CMD_DX_READBACK_COTABLE = 1208,
SVGA_3D_CMD_DX_BUFFER_COPY = 1209,
SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER = 1210,
SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK = 1211,
SVGA_3D_CMD_DX_MOVE_QUERY = 1212,
SVGA_3D_CMD_DX_BIND_ALL_QUERY = 1213,
SVGA_3D_CMD_DX_READBACK_ALL_QUERY = 1214,
SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER = 1215,
SVGA_3D_CMD_DX_MOB_FENCE_64 = 1216,
SVGA_3D_CMD_DX_BIND_SHADER_ON_CONTEXT = 1217,
SVGA_3D_CMD_DX_HINT = 1218,
SVGA_3D_CMD_DX_BUFFER_UPDATE = 1219,
SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET = 1220,
SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET = 1221,
SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET = 1222,
/*
* Reserve some IDs to be used for the DX11 shader types.
*/
SVGA_3D_CMD_DX_RESERVED1 = 1223,
SVGA_3D_CMD_DX_RESERVED2 = 1224,
SVGA_3D_CMD_DX_RESERVED3 = 1225,
SVGA_3D_CMD_DX_MAX = 1226,
SVGA_3D_CMD_MAX = 1226,
SVGA_3D_CMD_FUTURE_MAX = 3000
} SVGAFifo3dCmdId;
/*
* FIFO command format definitions:
*/
/*
* The data size header following cmdNum for every 3d command
*/
typedef
#include "vmware_pack_begin.h"
struct {
uint32 id;
uint32 size;
}
#include "vmware_pack_end.h"
SVGA3dCmdHeader;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 numMipLevels;
}
#include "vmware_pack_end.h"
SVGA3dSurfaceFace;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 sid;
SVGA3dSurfaceFlags surfaceFlags;
SVGA3dSurfaceFormat format;
/*
* If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
* structures must have the same value of numMipLevels field.
* Otherwise, all but the first SVGA3dSurfaceFace structures must have the
* numMipLevels set to 0.
*/
SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
/*
* Followed by an SVGA3dSize structure for each mip level in each face.
*
* A note on surface sizes: Sizes are always specified in pixels,
* even if the true surface size is not a multiple of the minimum
* block size of the surface's format. For example, a 3x3x1 DXT1
* compressed texture would actually be stored as a 4x4x1 image in
* memory.
*/
}
#include "vmware_pack_end.h"
SVGA3dCmdDefineSurface; /* SVGA_3D_CMD_SURFACE_DEFINE */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 sid;
SVGA3dSurfaceFlags surfaceFlags;
SVGA3dSurfaceFormat format;
/*
* If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
* structures must have the same value of numMipLevels field.
* Otherwise, all but the first SVGA3dSurfaceFace structures must have the
* numMipLevels set to 0.
*/
SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
uint32 multisampleCount;
SVGA3dTextureFilter autogenFilter;
/*
* Followed by an SVGA3dSize structure for each mip level in each face.
*
* A note on surface sizes: Sizes are always specified in pixels,
* even if the true surface size is not a multiple of the minimum
* block size of the surface's format. For example, a 3x3x1 DXT1
* compressed texture would actually be stored as a 4x4x1 image in
* memory.
*/
}
#include "vmware_pack_end.h"
SVGA3dCmdDefineSurface_v2; /* SVGA_3D_CMD_SURFACE_DEFINE_V2 */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 sid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDestroySurface; /* SVGA_3D_CMD_SURFACE_DESTROY */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDefineContext; /* SVGA_3D_CMD_CONTEXT_DEFINE */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDestroyContext; /* SVGA_3D_CMD_CONTEXT_DESTROY */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dClearFlag clearFlag;
uint32 color;
float depth;
uint32 stencil;
/* Followed by variable number of SVGA3dRect structures */
}
#include "vmware_pack_end.h"
SVGA3dCmdClear; /* SVGA_3D_CMD_CLEAR */
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dLightType type;
SVGA3dBool inWorldSpace;
float diffuse[4];
float specular[4];
float ambient[4];
float position[4];
float direction[4];
float range;
float falloff;
float attenuation0;
float attenuation1;
float attenuation2;
float theta;
float phi;
}
#include "vmware_pack_end.h"
SVGA3dLightData;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 sid;
/* Followed by variable number of SVGA3dCopyRect structures */
}
#include "vmware_pack_end.h"
SVGA3dCmdPresent; /* SVGA_3D_CMD_PRESENT */
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dRenderStateName state;
union {
uint32 uintValue;
float floatValue;
};
}
#include "vmware_pack_end.h"
SVGA3dRenderState;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
/* Followed by variable number of SVGA3dRenderState structures */
}
#include "vmware_pack_end.h"
SVGA3dCmdSetRenderState; /* SVGA_3D_CMD_SETRENDERSTATE */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dRenderTargetType type;
SVGA3dSurfaceImageId target;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetRenderTarget; /* SVGA_3D_CMD_SETRENDERTARGET */
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dSurfaceImageId src;
SVGA3dSurfaceImageId dest;
/* Followed by variable number of SVGA3dCopyBox structures */
}
#include "vmware_pack_end.h"
SVGA3dCmdSurfaceCopy; /* SVGA_3D_CMD_SURFACE_COPY */
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dSurfaceImageId src;
SVGA3dSurfaceImageId dest;
SVGA3dBox boxSrc;
SVGA3dBox boxDest;
SVGA3dStretchBltMode mode;
}
#include "vmware_pack_end.h"
SVGA3dCmdSurfaceStretchBlt; /* SVGA_3D_CMD_SURFACE_STRETCHBLT */
typedef
#include "vmware_pack_begin.h"
struct {
/*
* If the discard flag is present in a surface DMA operation, the host may
* discard the contents of the current mipmap level and face of the target
* surface before applying the surface DMA contents.
*/
uint32 discard : 1;
/*
* If the unsynchronized flag is present, the host may perform this upload
* without syncing to pending reads on this surface.
*/
uint32 unsynchronized : 1;
/*
* Guests *MUST* set the reserved bits to 0 before submitting the command
* suffix as future flags may occupy these bits.
*/
uint32 reserved : 30;
}
#include "vmware_pack_end.h"
SVGA3dSurfaceDMAFlags;
typedef
#include "vmware_pack_begin.h"
struct {
SVGAGuestImage guest;
SVGA3dSurfaceImageId host;
SVGA3dTransferType transfer;
/*
* Followed by variable number of SVGA3dCopyBox structures. For consistency
* in all clipping logic and coordinate translation, we define the
* "source" in each copyBox as the guest image and the
* "destination" as the host image, regardless of transfer
* direction.
*
* For efficiency, the SVGA3D device is free to copy more data than
* specified. For example, it may round copy boxes outwards such
* that they lie on particular alignment boundaries.
*/
}
#include "vmware_pack_end.h"
SVGA3dCmdSurfaceDMA; /* SVGA_3D_CMD_SURFACE_DMA */
/*
* SVGA3dCmdSurfaceDMASuffix --
*
* This is a command suffix that will appear after a SurfaceDMA command in
* the FIFO. It contains some extra information that hosts may use to
* optimize performance or protect the guest. This suffix exists to preserve
* backwards compatibility while also allowing for new functionality to be
* implemented.
*/
typedef
#include "vmware_pack_begin.h"
struct {
uint32 suffixSize;
/*
* The maximum offset is used to determine the maximum offset from the
* guestPtr base address that will be accessed or written to during this
* surfaceDMA. If the suffix is supported, the host will respect this
* boundary while performing surface DMAs.
*
* Defaults to MAX_UINT32
*/
uint32 maximumOffset;
/*
* A set of flags that describes optimizations that the host may perform
* while performing this surface DMA operation. The guest should never rely
* on behaviour that is different when these flags are set for correctness.
*
* Defaults to 0
*/
SVGA3dSurfaceDMAFlags flags;
}
#include "vmware_pack_end.h"
SVGA3dCmdSurfaceDMASuffix;
/*
* SVGA_3D_CMD_DRAW_PRIMITIVES --
*
* This command is the SVGA3D device's generic drawing entry point.
* It can draw multiple ranges of primitives, optionally using an
* index buffer, using an arbitrary collection of vertex buffers.
*
* Each SVGA3dVertexDecl defines a distinct vertex array to bind
* during this draw call. The declarations specify which surface
* the vertex data lives in, what that vertex data is used for,
* and how to interpret it.
*
* Each SVGA3dPrimitiveRange defines a collection of primitives
* to render using the same vertex arrays. An index buffer is
* optional.
*/
typedef
#include "vmware_pack_begin.h"
struct {
/*
* A range hint is an optional specification for the range of indices
* in an SVGA3dArray that will be used. If 'last' is zero, it is assumed
* that the entire array will be used.
*
* These are only hints. The SVGA3D device may use them for
* performance optimization if possible, but it's also allowed to
* ignore these values.
*/
uint32 first;
uint32 last;
}
#include "vmware_pack_end.h"
SVGA3dArrayRangeHint;
typedef
#include "vmware_pack_begin.h"
struct {
/*
* Define the origin and shape of a vertex or index array. Both
* 'offset' and 'stride' are in bytes. The provided surface will be
* reinterpreted as a flat array of bytes in the same format used
* by surface DMA operations. To avoid unnecessary conversions, the
* surface should be created with the SVGA3D_BUFFER format.
*
* Index 0 in the array starts 'offset' bytes into the surface.
* Index 1 begins at byte 'offset + stride', etc. Array indices may
* not be negative.
*/
uint32 surfaceId;
uint32 offset;
uint32 stride;
}
#include "vmware_pack_end.h"
SVGA3dArray;
typedef
#include "vmware_pack_begin.h"
struct {
/*
* Describe a vertex array's data type, and define how it is to be
* used by the fixed function pipeline or the vertex shader. It
* isn't useful to have two VertexDecls with the same
* VertexArrayIdentity in one draw call.
*/
SVGA3dDeclType type;
SVGA3dDeclMethod method;
SVGA3dDeclUsage usage;
uint32 usageIndex;
}
#include "vmware_pack_end.h"
SVGA3dVertexArrayIdentity;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dVertexDecl {
SVGA3dVertexArrayIdentity identity;
SVGA3dArray array;
SVGA3dArrayRangeHint rangeHint;
}
#include "vmware_pack_end.h"
SVGA3dVertexDecl;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dPrimitiveRange {
/*
* Define a group of primitives to render, from sequential indices.
*
* The value of 'primitiveType' and 'primitiveCount' imply the
* total number of vertices that will be rendered.
*/
SVGA3dPrimitiveType primType;
uint32 primitiveCount;
/*
* Optional index buffer. If indexArray.surfaceId is
* SVGA3D_INVALID_ID, we render without an index buffer. Rendering
* without an index buffer is identical to rendering with an index
* buffer containing the sequence [0, 1, 2, 3, ...].
*
* If an index buffer is in use, indexWidth specifies the width in
* bytes of each index value. It must be less than or equal to
* indexArray.stride.
*
* (Currently, the SVGA3D device requires index buffers to be tightly
* packed. In other words, indexWidth == indexArray.stride)
*/
SVGA3dArray indexArray;
uint32 indexWidth;
/*
* Optional index bias. This number is added to all indices from
* indexArray before they are used as vertex array indices. This
* can be used in multiple ways:
*
* - When not using an indexArray, this bias can be used to
* specify where in the vertex arrays to begin rendering.
*
* - A positive number here is equivalent to increasing the
* offset in each vertex array.
*
* - A negative number can be used to render using a small
* vertex array and an index buffer that contains large
* values. This may be used by some applications that
* crop a vertex buffer without modifying their index
* buffer.
*
* Note that rendering with a negative bias value may be slower and
* use more memory than rendering with a positive or zero bias.
*/
int32 indexBias;
}
#include "vmware_pack_end.h"
SVGA3dPrimitiveRange;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint32 numVertexDecls;
uint32 numRanges;
/*
* There are two variable size arrays after the
* SVGA3dCmdDrawPrimitives structure. In order,
* they are:
*
* 1. SVGA3dVertexDecl, quantity 'numVertexDecls', but no more than
* SVGA3D_MAX_VERTEX_ARRAYS;
* 2. SVGA3dPrimitiveRange, quantity 'numRanges', but no more than
* SVGA3D_MAX_DRAW_PRIMITIVE_RANGES;
* 3. Optionally, SVGA3dVertexDivisor, quantity 'numVertexDecls' (contains
* the frequency divisor for the corresponding vertex decl).
*/
}
#include "vmware_pack_end.h"
SVGA3dCmdDrawPrimitives; /* SVGA_3D_CMD_DRAWPRIMITIVES */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint32 primitiveCount; /* How many primitives to render */
uint32 startVertexLocation; /* Which vertex do we start rendering at. */
uint8 primitiveType; /* SVGA3dPrimitiveType */
uint8 padding[3];
}
#include "vmware_pack_end.h"
SVGA3dCmdDraw;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint8 primitiveType; /* SVGA3dPrimitiveType */
uint32 indexBufferSid; /* Valid index buffer sid. */
uint32 indexBufferOffset; /* Byte offset into the vertex buffer, almost */
/* always 0 for DX9 guests, non-zero for OpenGL */
/* guests. We can't represent non-multiple of */
/* stride offsets in D3D9Renderer... */
uint8 indexBufferStride; /* Allowable values = 1, 2, or 4 */
int32 baseVertexLocation; /* Bias applied to the index when selecting a */
/* vertex from the streams, may be negative */
uint32 primitiveCount; /* How many primitives to render */
uint32 pad0;
uint16 pad1;
}
#include "vmware_pack_end.h"
SVGA3dCmdDrawIndexed;
typedef
#include "vmware_pack_begin.h"
struct {
/*
* Describe a vertex array's data type, and define how it is to be
* used by the fixed function pipeline or the vertex shader. It
* isn't useful to have two VertexDecls with the same
* VertexArrayIdentity in one draw call.
*/
uint16 streamOffset;
uint8 stream;
uint8 type; /* SVGA3dDeclType */
uint8 method; /* SVGA3dDeclMethod */
uint8 usage; /* SVGA3dDeclUsage */
uint8 usageIndex;
uint8 padding;
}
#include "vmware_pack_end.h"
SVGA3dVertexElement;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint32 numElements;
/*
* Followed by numElements SVGA3dVertexElement structures.
*
* If numElements < SVGA3D_MAX_VERTEX_ARRAYS, the remaining elements
* are cleared and will not be used by following draws.
*/
}
#include "vmware_pack_end.h"
SVGA3dCmdSetVertexDecls;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 sid;
uint32 stride;
uint32 offset;
}
#include "vmware_pack_end.h"
SVGA3dVertexStream;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint32 numStreams;
/*
* Followed by numStream SVGA3dVertexStream structures.
*
* If numStreams < SVGA3D_MAX_VERTEX_ARRAYS, the remaining streams
* are cleared and will not be used by following draws.
*/
}
#include "vmware_pack_end.h"
SVGA3dCmdSetVertexStreams;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint32 numDivisors;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetVertexDivisors;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 stage;
SVGA3dTextureStateName name;
union {
uint32 value;
float floatValue;
};
}
#include "vmware_pack_end.h"
SVGA3dTextureState;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
/* Followed by variable number of SVGA3dTextureState structures */
}
#include "vmware_pack_end.h"
SVGA3dCmdSetTextureState; /* SVGA_3D_CMD_SETTEXTURESTATE */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dTransformType type;
float matrix[16];
}
#include "vmware_pack_end.h"
SVGA3dCmdSetTransform; /* SVGA_3D_CMD_SETTRANSFORM */
typedef
#include "vmware_pack_begin.h"
struct {
float min;
float max;
}
#include "vmware_pack_end.h"
SVGA3dZRange;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dZRange zRange;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetZRange; /* SVGA_3D_CMD_SETZRANGE */
typedef
#include "vmware_pack_begin.h"
struct {
float diffuse[4];
float ambient[4];
float specular[4];
float emissive[4];
float shininess;
}
#include "vmware_pack_end.h"
SVGA3dMaterial;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dFace face;
SVGA3dMaterial material;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetMaterial; /* SVGA_3D_CMD_SETMATERIAL */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint32 index;
SVGA3dLightData data;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetLightData; /* SVGA_3D_CMD_SETLIGHTDATA */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint32 index;
uint32 enabled;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetLightEnabled; /* SVGA_3D_CMD_SETLIGHTENABLED */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dRect rect;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetViewport; /* SVGA_3D_CMD_SETVIEWPORT */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dRect rect;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetScissorRect; /* SVGA_3D_CMD_SETSCISSORRECT */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint32 index;
float plane[4];
}
#include "vmware_pack_end.h"
SVGA3dCmdSetClipPlane; /* SVGA_3D_CMD_SETCLIPPLANE */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint32 shid;
SVGA3dShaderType type;
/* Followed by variable number of DWORDs for shader bycode */
}
#include "vmware_pack_end.h"
SVGA3dCmdDefineShader; /* SVGA_3D_CMD_SHADER_DEFINE */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint32 shid;
SVGA3dShaderType type;
}
#include "vmware_pack_end.h"
SVGA3dCmdDestroyShader; /* SVGA_3D_CMD_SHADER_DESTROY */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint32 reg; /* register number */
SVGA3dShaderType type;
SVGA3dShaderConstType ctype;
uint32 values[4];
/*
* Followed by a variable number of additional values.
*/
}
#include "vmware_pack_end.h"
SVGA3dCmdSetShaderConst; /* SVGA_3D_CMD_SET_SHADER_CONST */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dShaderType type;
uint32 shid;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetShader; /* SVGA_3D_CMD_SET_SHADER */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dQueryType type;
}
#include "vmware_pack_end.h"
SVGA3dCmdBeginQuery; /* SVGA_3D_CMD_BEGIN_QUERY */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dQueryType type;
SVGAGuestPtr guestResult; /* Points to an SVGA3dQueryResult structure */
}
#include "vmware_pack_end.h"
SVGA3dCmdEndQuery; /* SVGA_3D_CMD_END_QUERY */
/*
* SVGA3D_CMD_WAIT_FOR_QUERY --
*
* Will read the SVGA3dQueryResult structure pointed to by guestResult,
* and if the state member is set to anything else than
* SVGA3D_QUERYSTATE_PENDING, this command will always be a no-op.
*
* Otherwise, in addition to the query explicitly waited for,
* All queries with the same type and issued with the same cid, for which
* an SVGA_3D_CMD_END_QUERY command has previously been sent, will
* be finished after execution of this command.
*
* A query will be identified by the gmrId and offset of the guestResult
* member. If the device can't find an SVGA_3D_CMD_END_QUERY that has
* been sent previously with an indentical gmrId and offset, it will
* effectively end all queries with an identical type issued with the
* same cid, and the SVGA3dQueryResult structure pointed to by
* guestResult will not be written to. This property can be used to
* implement a query barrier for a given cid and query type.
*/
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid; /* Same parameters passed to END_QUERY */
SVGA3dQueryType type;
SVGAGuestPtr guestResult;
}
#include "vmware_pack_end.h"
SVGA3dCmdWaitForQuery; /* SVGA_3D_CMD_WAIT_FOR_QUERY */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 totalSize; /* Set by guest before query is ended. */
SVGA3dQueryState state; /* Set by host or guest. See SVGA3dQueryState. */
union { /* Set by host on exit from PENDING state */
uint32 result32;
uint32 queryCookie; /* May be used to identify which QueryGetData this
result corresponds to. */
};
}
#include "vmware_pack_end.h"
SVGA3dQueryResult;
/*
* SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN --
*
* This is a blit from an SVGA3D surface to a Screen Object.
* This blit must be directed at a specific screen.
*
* The blit copies from a rectangular region of an SVGA3D surface
* image to a rectangular region of a screen.
*
* This command takes an optional variable-length list of clipping
* rectangles after the body of the command. If no rectangles are
* specified, there is no clipping region. The entire destRect is
* drawn to. If one or more rectangles are included, they describe
* a clipping region. The clip rectangle coordinates are measured
* relative to the top-left corner of destRect.
*
* The srcImage must be from mip=0 face=0.
*
* This supports scaling if the src and dest are of different sizes.
*
* Availability:
* SVGA_FIFO_CAP_SCREEN_OBJECT
*/
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dSurfaceImageId srcImage;
SVGASignedRect srcRect;
uint32 destScreenId; /* Screen Object ID */
SVGASignedRect destRect;
/* Clipping: zero or more SVGASignedRects follow */
}
#include "vmware_pack_end.h"
SVGA3dCmdBlitSurfaceToScreen; /* SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 sid;
SVGA3dTextureFilter filter;
}
#include "vmware_pack_end.h"
SVGA3dCmdGenerateMipmaps; /* SVGA_3D_CMD_GENERATE_MIPMAPS */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 sid;
}
#include "vmware_pack_end.h"
SVGA3dCmdActivateSurface; /* SVGA_3D_CMD_ACTIVATE_SURFACE */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 sid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDeactivateSurface; /* SVGA_3D_CMD_DEACTIVATE_SURFACE */
/*
* Screen DMA command
*
* Available with SVGA_FIFO_CAP_SCREEN_OBJECT_2. The SVGA_CAP_3D device
* cap bit is not required.
*
* - refBuffer and destBuffer are 32bit BGRX; refBuffer and destBuffer could
* be different, but it is required that guest makes sure refBuffer has
* exactly the same contents that were written to when last time screen DMA
* command is received by host.
*
* - changemap is generated by lib/blit, and it has the changes from last
* received screen DMA or more.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdScreenDMA {
uint32 screenId;
SVGAGuestImage refBuffer;
SVGAGuestImage destBuffer;
SVGAGuestImage changeMap;
}
#include "vmware_pack_end.h"
SVGA3dCmdScreenDMA; /* SVGA_3D_CMD_SCREEN_DMA */
/*
* Set Unity Surface Cookie
*
* Associates the supplied cookie with the surface id for use with
* Unity. This cookie is a hint from guest to host, there is no way
* for the guest to readback the cookie and the host is free to drop
* the cookie association at will. The default value for the cookie
* on all surfaces is 0.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdSetUnitySurfaceCookie {
uint32 sid;
uint64 cookie;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetUnitySurfaceCookie; /* SVGA_3D_CMD_SET_UNITY_SURFACE_COOKIE */
/*
* Open a context-specific surface in a non-context-specific manner.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdOpenContextSurface {
uint32 sid;
}
#include "vmware_pack_end.h"
SVGA3dCmdOpenContextSurface; /* SVGA_3D_CMD_OPEN_CONTEXT_SURFACE */
/*
* Logic ops
*/
#define SVGA3D_LOTRANSBLT_HONORALPHA (0x01)
#define SVGA3D_LOSTRETCHBLT_MIRRORX (0x01)
#define SVGA3D_LOSTRETCHBLT_MIRRORY (0x02)
#define SVGA3D_LOALPHABLEND_SRCHASALPHA (0x01)
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdLogicOpsBitBlt {
/*
* All LogicOps surfaces are one-level
* surfaces so mipmap & face should always
* be zero.
*/
SVGA3dSurfaceImageId src;
SVGA3dSurfaceImageId dst;
SVGA3dLogicOp logicOp;
/* Followed by variable number of SVGA3dCopyBox structures */
}
#include "vmware_pack_end.h"
SVGA3dCmdLogicOpsBitBlt; /* SVGA_3D_CMD_LOGICOPS_BITBLT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdLogicOpsTransBlt {
/*
* All LogicOps surfaces are one-level
* surfaces so mipmap & face should always
* be zero.
*/
SVGA3dSurfaceImageId src;
SVGA3dSurfaceImageId dst;
uint32 color;
uint32 flags;
SVGA3dBox srcBox;
SVGA3dBox dstBox;
}
#include "vmware_pack_end.h"
SVGA3dCmdLogicOpsTransBlt; /* SVGA_3D_CMD_LOGICOPS_TRANSBLT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdLogicOpsStretchBlt {
/*
* All LogicOps surfaces are one-level
* surfaces so mipmap & face should always
* be zero.
*/
SVGA3dSurfaceImageId src;
SVGA3dSurfaceImageId dst;
uint16 mode;
uint16 flags;
SVGA3dBox srcBox;
SVGA3dBox dstBox;
}
#include "vmware_pack_end.h"
SVGA3dCmdLogicOpsStretchBlt; /* SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdLogicOpsColorFill {
/*
* All LogicOps surfaces are one-level
* surfaces so mipmap & face should always
* be zero.
*/
SVGA3dSurfaceImageId dst;
uint32 color;
SVGA3dLogicOp logicOp;
/* Followed by variable number of SVGA3dRect structures. */
}
#include "vmware_pack_end.h"
SVGA3dCmdLogicOpsColorFill; /* SVGA_3D_CMD_LOGICOPS_COLORFILL */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdLogicOpsAlphaBlend {
/*
* All LogicOps surfaces are one-level
* surfaces so mipmap & face should always
* be zero.
*/
SVGA3dSurfaceImageId src;
SVGA3dSurfaceImageId dst;
uint32 alphaVal;
uint32 flags;
SVGA3dBox srcBox;
SVGA3dBox dstBox;
}
#include "vmware_pack_end.h"
SVGA3dCmdLogicOpsAlphaBlend; /* SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
#define SVGA3D_CLEARTYPE_INVALID_GAMMA_INDEX 0xFFFFFFFF
#define SVGA3D_CLEARTYPE_GAMMA_WIDTH 512
#define SVGA3D_CLEARTYPE_GAMMA_HEIGHT 16
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdLogicOpsClearTypeBlend {
/*
* All LogicOps surfaces are one-level
* surfaces so mipmap & face should always
* be zero.
*/
SVGA3dSurfaceImageId tmp;
SVGA3dSurfaceImageId dst;
SVGA3dSurfaceImageId gammaSurf;
SVGA3dSurfaceImageId alphaSurf;
uint32 gamma;
uint32 color;
uint32 color2;
int32 alphaOffsetX;
int32 alphaOffsetY;
/* Followed by variable number of SVGA3dBox structures */
}
#include "vmware_pack_end.h"
SVGA3dCmdLogicOpsClearTypeBlend; /* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
/*
* Guest-backed objects definitions.
*/
typedef
#include "vmware_pack_begin.h"
struct {
SVGAMobFormat ptDepth;
uint32 sizeInBytes;
PPN64 base;
}
#include "vmware_pack_end.h"
SVGAOTableMobEntry;
#define SVGA3D_OTABLE_MOB_ENTRY_SIZE (sizeof(SVGAOTableMobEntry))
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dSurfaceFormat format;
SVGA3dSurfaceFlags surfaceFlags;
uint32 numMipLevels;
uint32 multisampleCount;
SVGA3dTextureFilter autogenFilter;
SVGA3dSize size;
SVGAMobId mobid;
uint32 arraySize;
uint32 mobPitch;
uint32 pad[5];
}
#include "vmware_pack_end.h"
SVGAOTableSurfaceEntry;
#define SVGA3D_OTABLE_SURFACE_ENTRY_SIZE (sizeof(SVGAOTableSurfaceEntry))
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGAMobId mobid;
}
#include "vmware_pack_end.h"
SVGAOTableContextEntry;
#define SVGA3D_OTABLE_CONTEXT_ENTRY_SIZE (sizeof(SVGAOTableContextEntry))
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dShaderType type;
uint32 sizeInBytes;
uint32 offsetInBytes;
SVGAMobId mobid;
}
#include "vmware_pack_end.h"
SVGAOTableShaderEntry;
#define SVGA3D_OTABLE_SHADER_ENTRY_SIZE (sizeof(SVGAOTableShaderEntry))
#define SVGA_STFLAG_PRIMARY (1 << 0)
typedef uint32 SVGAScreenTargetFlags;
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dSurfaceImageId image;
uint32 width;
uint32 height;
int32 xRoot;
int32 yRoot;
SVGAScreenTargetFlags flags;
uint32 dpi;
uint32 pad[7];
}
#include "vmware_pack_end.h"
SVGAOTableScreenTargetEntry;
#define SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE \
(sizeof(SVGAOTableScreenTargetEntry))
typedef
#include "vmware_pack_begin.h"
struct {
float value[4];
}
#include "vmware_pack_end.h"
SVGA3dShaderConstFloat;
typedef
#include "vmware_pack_begin.h"
struct {
int32 value[4];
}
#include "vmware_pack_end.h"
SVGA3dShaderConstInt;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 value;
}
#include "vmware_pack_end.h"
SVGA3dShaderConstBool;
typedef
#include "vmware_pack_begin.h"
struct {
uint16 streamOffset;
uint8 stream;
uint8 type;
uint8 methodUsage;
uint8 usageIndex;
}
#include "vmware_pack_end.h"
SVGAGBVertexElement;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 sid;
uint16 stride;
uint32 offset;
}
#include "vmware_pack_end.h"
SVGAGBVertexStream;
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dRect viewport;
SVGA3dRect scissorRect;
SVGA3dZRange zRange;
SVGA3dSurfaceImageId renderTargets[SVGA3D_RT_MAX];
SVGAGBVertexElement decl1[4];
uint32 renderStates[SVGA3D_RS_MAX];
SVGAGBVertexElement decl2[18];
uint32 pad0[2];
struct {
SVGA3dFace face;
SVGA3dMaterial material;
} material;
float clipPlanes[SVGA3D_NUM_CLIPPLANES][4];
float matrices[SVGA3D_TRANSFORM_MAX][16];
SVGA3dBool lightEnabled[SVGA3D_NUM_LIGHTS];
SVGA3dLightData lightData[SVGA3D_NUM_LIGHTS];
/*
* Shaders currently bound
*/
uint32 shaders[SVGA3D_NUM_SHADERTYPE_PREDX];
SVGAGBVertexElement decl3[10];
uint32 pad1[3];
uint32 occQueryActive;
uint32 occQueryValue;
/*
* Int/Bool Shader constants
*/
SVGA3dShaderConstInt pShaderIValues[SVGA3D_CONSTINTREG_MAX];
SVGA3dShaderConstInt vShaderIValues[SVGA3D_CONSTINTREG_MAX];
uint16 pShaderBValues;
uint16 vShaderBValues;
SVGAGBVertexStream streams[SVGA3D_MAX_VERTEX_ARRAYS];
SVGA3dVertexDivisor divisors[SVGA3D_MAX_VERTEX_ARRAYS];
uint32 numVertexDecls;
uint32 numVertexStreams;
uint32 numVertexDivisors;
uint32 pad2[30];
/*
* Texture Stages
*
* SVGA3D_TS_INVALID through SVGA3D_TS_CONSTANT are in the
* textureStages array.
* SVGA3D_TS_COLOR_KEY is in tsColorKey.
*/
uint32 tsColorKey[SVGA3D_NUM_TEXTURE_UNITS];
uint32 textureStages[SVGA3D_NUM_TEXTURE_UNITS][SVGA3D_TS_CONSTANT + 1];
uint32 tsColorKeyEnable[SVGA3D_NUM_TEXTURE_UNITS];
/*
* Float Shader constants.
*/
SVGA3dShaderConstFloat pShaderFValues[SVGA3D_CONSTREG_MAX];
SVGA3dShaderConstFloat vShaderFValues[SVGA3D_CONSTREG_MAX];
}
#include "vmware_pack_end.h"
SVGAGBContextData;
#define SVGA3D_CONTEXT_DATA_SIZE (sizeof(SVGAGBContextData))
/*
* SVGA3dCmdSetOTableBase --
*
* This command allows the guest to specify the base PPN of the
* specified object table.
*/
typedef
#include "vmware_pack_begin.h"
struct {
SVGAOTableType type;
PPN baseAddress;
uint32 sizeInBytes;
uint32 validSizeInBytes;
SVGAMobFormat ptDepth;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetOTableBase; /* SVGA_3D_CMD_SET_OTABLE_BASE */
typedef
#include "vmware_pack_begin.h"
struct {
SVGAOTableType type;
PPN64 baseAddress;
uint32 sizeInBytes;
uint32 validSizeInBytes;
SVGAMobFormat ptDepth;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetOTableBase64; /* SVGA_3D_CMD_SET_OTABLE_BASE64 */
typedef
#include "vmware_pack_begin.h"
struct {
SVGAOTableType type;
}
#include "vmware_pack_end.h"
SVGA3dCmdReadbackOTable; /* SVGA_3D_CMD_READBACK_OTABLE */
/*
* Define a memory object (Mob) in the OTable.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDefineGBMob {
SVGAMobId mobid;
SVGAMobFormat ptDepth;
PPN base;
uint32 sizeInBytes;
}
#include "vmware_pack_end.h"
SVGA3dCmdDefineGBMob; /* SVGA_3D_CMD_DEFINE_GB_MOB */
/*
* Destroys an object in the OTable.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDestroyGBMob {
SVGAMobId mobid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDestroyGBMob; /* SVGA_3D_CMD_DESTROY_GB_MOB */
/*
* Define a memory object (Mob) in the OTable with a PPN64 base.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDefineGBMob64 {
SVGAMobId mobid;
SVGAMobFormat ptDepth;
PPN64 base;
uint32 sizeInBytes;
}
#include "vmware_pack_end.h"
SVGA3dCmdDefineGBMob64; /* SVGA_3D_CMD_DEFINE_GB_MOB64 */
/*
* Redefine an object in the OTable with PPN64 base.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdRedefineGBMob64 {
SVGAMobId mobid;
SVGAMobFormat ptDepth;
PPN64 base;
uint32 sizeInBytes;
}
#include "vmware_pack_end.h"
SVGA3dCmdRedefineGBMob64; /* SVGA_3D_CMD_REDEFINE_GB_MOB64 */
/*
* Notification that the page tables have been modified.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdUpdateGBMobMapping {
SVGAMobId mobid;
}
#include "vmware_pack_end.h"
SVGA3dCmdUpdateGBMobMapping; /* SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING */
/*
* Define a guest-backed surface.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDefineGBSurface {
uint32 sid;
SVGA3dSurfaceFlags surfaceFlags;
SVGA3dSurfaceFormat format;
uint32 numMipLevels;
uint32 multisampleCount;
SVGA3dTextureFilter autogenFilter;
SVGA3dSize size;
}
#include "vmware_pack_end.h"
SVGA3dCmdDefineGBSurface; /* SVGA_3D_CMD_DEFINE_GB_SURFACE */
/*
* Destroy a guest-backed surface.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDestroyGBSurface {
uint32 sid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDestroyGBSurface; /* SVGA_3D_CMD_DESTROY_GB_SURFACE */
/*
* Bind a guest-backed surface to a mob.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdBindGBSurface {
uint32 sid;
SVGAMobId mobid;
}
#include "vmware_pack_end.h"
SVGA3dCmdBindGBSurface; /* SVGA_3D_CMD_BIND_GB_SURFACE */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdBindGBSurfaceWithPitch {
uint32 sid;
SVGAMobId mobid;
uint32 baseLevelPitch;
}
#include "vmware_pack_end.h"
SVGA3dCmdBindGBSurfaceWithPitch; /* SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH */
/*
* Conditionally bind a mob to a guest-backed surface if testMobid
* matches the currently bound mob. Optionally issue a
* readback/update on the surface while it is still bound to the old
* mobid if the mobid is changed by this command.
*/
#define SVGA3D_COND_BIND_GB_SURFACE_FLAG_READBACK (1 << 0)
#define SVGA3D_COND_BIND_GB_SURFACE_FLAG_UPDATE (1 << 1)
typedef
#include "vmware_pack_begin.h"
struct{
uint32 sid;
SVGAMobId testMobid;
SVGAMobId mobid;
uint32 flags;
}
#include "vmware_pack_end.h"
SVGA3dCmdCondBindGBSurface; /* SVGA_3D_CMD_COND_BIND_GB_SURFACE */
/*
* Update an image in a guest-backed surface.
* (Inform the device that the guest-contents have been updated.)
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdUpdateGBImage {
SVGA3dSurfaceImageId image;
SVGA3dBox box;
}
#include "vmware_pack_end.h"
SVGA3dCmdUpdateGBImage; /* SVGA_3D_CMD_UPDATE_GB_IMAGE */
/*
* Update an entire guest-backed surface.
* (Inform the device that the guest-contents have been updated.)
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdUpdateGBSurface {
uint32 sid;
}
#include "vmware_pack_end.h"
SVGA3dCmdUpdateGBSurface; /* SVGA_3D_CMD_UPDATE_GB_SURFACE */
/*
* Readback an image in a guest-backed surface.
* (Request the device to flush the dirty contents into the guest.)
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdReadbackGBImage {
SVGA3dSurfaceImageId image;
}
#include "vmware_pack_end.h"
SVGA3dCmdReadbackGBImage; /* SVGA_3D_CMD_READBACK_GB_IMAGE */
/*
* Readback an entire guest-backed surface.
* (Request the device to flush the dirty contents into the guest.)
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdReadbackGBSurface {
uint32 sid;
}
#include "vmware_pack_end.h"
SVGA3dCmdReadbackGBSurface; /* SVGA_3D_CMD_READBACK_GB_SURFACE */
/*
* Readback a sub rect of an image in a guest-backed surface. After
* issuing this command the driver is required to issue an update call
* of the same region before issuing any other commands that reference
* this surface or rendering is not guaranteed.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdReadbackGBImagePartial {
SVGA3dSurfaceImageId image;
SVGA3dBox box;
uint32 invertBox;
}
#include "vmware_pack_end.h"
SVGA3dCmdReadbackGBImagePartial; /* SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL */
/*
* Invalidate an image in a guest-backed surface.
* (Notify the device that the contents can be lost.)
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdInvalidateGBImage {
SVGA3dSurfaceImageId image;
}
#include "vmware_pack_end.h"
SVGA3dCmdInvalidateGBImage; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE */
/*
* Invalidate an entire guest-backed surface.
* (Notify the device that the contents if all images can be lost.)
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdInvalidateGBSurface {
uint32 sid;
}
#include "vmware_pack_end.h"
SVGA3dCmdInvalidateGBSurface; /* SVGA_3D_CMD_INVALIDATE_GB_SURFACE */
/*
* Invalidate a sub rect of an image in a guest-backed surface. After
* issuing this command the driver is required to issue an update call
* of the same region before issuing any other commands that reference
* this surface or rendering is not guaranteed.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdInvalidateGBImagePartial {
SVGA3dSurfaceImageId image;
SVGA3dBox box;
uint32 invertBox;
}
#include "vmware_pack_end.h"
SVGA3dCmdInvalidateGBImagePartial; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL */
/*
* Define a guest-backed context.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDefineGBContext {
uint32 cid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDefineGBContext; /* SVGA_3D_CMD_DEFINE_GB_CONTEXT */
/*
* Destroy a guest-backed context.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDestroyGBContext {
uint32 cid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDestroyGBContext; /* SVGA_3D_CMD_DESTROY_GB_CONTEXT */
/*
* Bind a guest-backed context.
*
* validContents should be set to 0 for new contexts,
* and 1 if this is an old context which is getting paged
* back on to the device.
*
* For new contexts, it is recommended that the driver
* issue commands to initialize all interesting state
* prior to rendering.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdBindGBContext {
uint32 cid;
SVGAMobId mobid;
uint32 validContents;
}
#include "vmware_pack_end.h"
SVGA3dCmdBindGBContext; /* SVGA_3D_CMD_BIND_GB_CONTEXT */
/*
* Readback a guest-backed context.
* (Request that the device flush the contents back into guest memory.)
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdReadbackGBContext {
uint32 cid;
}
#include "vmware_pack_end.h"
SVGA3dCmdReadbackGBContext; /* SVGA_3D_CMD_READBACK_GB_CONTEXT */
/*
* Invalidate a guest-backed context.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdInvalidateGBContext {
uint32 cid;
}
#include "vmware_pack_end.h"
SVGA3dCmdInvalidateGBContext; /* SVGA_3D_CMD_INVALIDATE_GB_CONTEXT */
/*
* Define a guest-backed shader.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDefineGBShader {
uint32 shid;
SVGA3dShaderType type;
uint32 sizeInBytes;
}
#include "vmware_pack_end.h"
SVGA3dCmdDefineGBShader; /* SVGA_3D_CMD_DEFINE_GB_SHADER */
/*
* Bind a guest-backed shader.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdBindGBShader {
uint32 shid;
SVGAMobId mobid;
uint32 offsetInBytes;
}
#include "vmware_pack_end.h"
SVGA3dCmdBindGBShader; /* SVGA_3D_CMD_BIND_GB_SHADER */
/*
* Destroy a guest-backed shader.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDestroyGBShader {
uint32 shid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDestroyGBShader; /* SVGA_3D_CMD_DESTROY_GB_SHADER */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint32 regStart;
SVGA3dShaderType shaderType;
SVGA3dShaderConstType constType;
/*
* Followed by a variable number of shader constants.
*
* Note that FLOAT and INT constants are 4-dwords in length, while
* BOOL constants are 1-dword in length.
*/
}
#include "vmware_pack_end.h"
SVGA3dCmdSetGBShaderConstInline; /* SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dQueryType type;
}
#include "vmware_pack_end.h"
SVGA3dCmdBeginGBQuery; /* SVGA_3D_CMD_BEGIN_GB_QUERY */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dQueryType type;
SVGAMobId mobid;
uint32 offset;
}
#include "vmware_pack_end.h"
SVGA3dCmdEndGBQuery; /* SVGA_3D_CMD_END_GB_QUERY */
/*
* SVGA_3D_CMD_WAIT_FOR_GB_QUERY --
*
* The semantics of this command are identical to the
* SVGA_3D_CMD_WAIT_FOR_QUERY except that the results are written
* to a Mob instead of a GMR.
*/
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dQueryType type;
SVGAMobId mobid;
uint32 offset;
}
#include "vmware_pack_end.h"
SVGA3dCmdWaitForGBQuery; /* SVGA_3D_CMD_WAIT_FOR_GB_QUERY */
typedef
#include "vmware_pack_begin.h"
struct {
SVGAMobId mobid;
uint32 mustBeZero;
uint32 initialized;
}
#include "vmware_pack_end.h"
SVGA3dCmdEnableGart; /* SVGA_3D_CMD_ENABLE_GART */
typedef
#include "vmware_pack_begin.h"
struct {
SVGAMobId mobid;
uint32 gartOffset;
}
#include "vmware_pack_end.h"
SVGA3dCmdMapMobIntoGart; /* SVGA_3D_CMD_MAP_MOB_INTO_GART */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 gartOffset;
uint32 numPages;
}
#include "vmware_pack_end.h"
SVGA3dCmdUnmapGartRange; /* SVGA_3D_CMD_UNMAP_GART_RANGE */
/*
* Screen Targets
*/
typedef
#include "vmware_pack_begin.h"
struct {
uint32 stid;
uint32 width;
uint32 height;
int32 xRoot;
int32 yRoot;
SVGAScreenTargetFlags flags;
/*
* The physical DPI that the guest expects this screen displayed at.
*
* Guests which are not DPI-aware should set this to zero.
*/
uint32 dpi;
}
#include "vmware_pack_end.h"
SVGA3dCmdDefineGBScreenTarget; /* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 stid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDestroyGBScreenTarget; /* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 stid;
SVGA3dSurfaceImageId image;
}
#include "vmware_pack_end.h"
SVGA3dCmdBindGBScreenTarget; /* SVGA_3D_CMD_BIND_GB_SCREENTARGET */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 stid;
SVGA3dRect rect;
}
#include "vmware_pack_end.h"
SVGA3dCmdUpdateGBScreenTarget; /* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdGBScreenDMA {
uint32 screenId;
uint32 dead;
SVGAMobId destMobID;
uint32 destPitch;
SVGAMobId changeMapMobID;
}
#include "vmware_pack_end.h"
SVGA3dCmdGBScreenDMA; /* SVGA_3D_CMD_GB_SCREEN_DMA */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 value;
uint32 mobId;
uint32 mobOffset;
}
#include "vmware_pack_end.h"
SVGA3dCmdGBMobFence; /* SVGA_3D_CMD_GB_MOB_FENCE*/
#endif /* _SVGA3D_CMD_H_ */
drivers/gpu/drm/vmwgfx/device_include/svga3d_devcaps.h 0 → 100644
View file @ 8ce75f8a
/**********************************************************
* Copyright 1998-2015 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
/*
* svga3d_devcaps.h --
*
* SVGA 3d caps definitions
*/
#ifndef _SVGA3D_DEVCAPS_H_
#define _SVGA3D_DEVCAPS_H_
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#define INCLUDE_ALLOW_VMCORE
#include "includeCheck.h"
/*
* 3D Hardware Version
*
* The hardware version is stored in the SVGA_FIFO_3D_HWVERSION fifo
* register. Is set by the host and read by the guest. This lets
* us make new guest drivers which are backwards-compatible with old
* SVGA hardware revisions. It does not let us support old guest
* drivers. Good enough for now.
*
*/
#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16)
#define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF)
typedef enum {
SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1),
SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2),
SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3),
SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1),
SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4),
SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0),
SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1),
SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1,
} SVGA3dHardwareVersion;
/*
* DevCap indexes.
*/
typedef enum {
SVGA3D_DEVCAP_INVALID = ((uint32)-1),
SVGA3D_DEVCAP_3D = 0,
SVGA3D_DEVCAP_MAX_LIGHTS = 1,
/*
* SVGA3D_DEVCAP_MAX_TEXTURES reflects the maximum number of
* fixed-function texture units available. Each of these units
* work in both FFP and Shader modes, and they support texture
* transforms and texture coordinates. The host may have additional
* texture image units that are only usable with shaders.
*/
SVGA3D_DEVCAP_MAX_TEXTURES = 2,
SVGA3D_DEVCAP_MAX_CLIP_PLANES = 3,
SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = 4,
SVGA3D_DEVCAP_VERTEX_SHADER = 5,
SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = 6,
SVGA3D_DEVCAP_FRAGMENT_SHADER = 7,
SVGA3D_DEVCAP_MAX_RENDER_TARGETS = 8,
SVGA3D_DEVCAP_S23E8_TEXTURES = 9,
SVGA3D_DEVCAP_S10E5_TEXTURES = 10,
SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = 11,
SVGA3D_DEVCAP_D16_BUFFER_FORMAT = 12,
SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = 13,
SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = 14,
SVGA3D_DEVCAP_QUERY_TYPES = 15,
SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = 16,
SVGA3D_DEVCAP_MAX_POINT_SIZE = 17,
SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = 18,
SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = 19,
SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = 20,
SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = 21,
SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = 22,
SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = 23,
SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = 24,
SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = 25,
SVGA3D_DEVCAP_MAX_VERTEX_INDEX = 26,
SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = 27,
SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = 28,
SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = 29,
SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = 30,
SVGA3D_DEVCAP_TEXTURE_OPS = 31,
SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = 32,
SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = 33,
SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = 34,
SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = 35,
SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = 36,
SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = 37,
SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = 38,
SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = 39,
SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = 40,
SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = 41,
SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = 42,
SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = 43,
SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = 44,
SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = 45,
SVGA3D_DEVCAP_SURFACEFMT_DXT1 = 46,
SVGA3D_DEVCAP_SURFACEFMT_DXT2 = 47,
SVGA3D_DEVCAP_SURFACEFMT_DXT3 = 48,
SVGA3D_DEVCAP_SURFACEFMT_DXT4 = 49,
SVGA3D_DEVCAP_SURFACEFMT_DXT5 = 50,
SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = 51,
SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = 52,
SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = 53,
SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = 54,
SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = 55,
SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = 56,
SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = 57,
SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = 58,
SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = 59,
SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = 60,
SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = 61,
/*
* There is a hole in our devcap definitions for
* historical reasons.
*
* Define a constant just for completeness.
*/
SVGA3D_DEVCAP_MISSING62 = 62,
SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = 63,
/*
* Note that MAX_SIMULTANEOUS_RENDER_TARGETS is a maximum count of color
* render targets. This does not include the depth or stencil targets.
*/
SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = 64,
SVGA3D_DEVCAP_SURFACEFMT_V16U16 = 65,
SVGA3D_DEVCAP_SURFACEFMT_G16R16 = 66,
SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = 67,
SVGA3D_DEVCAP_SURFACEFMT_UYVY = 68,
SVGA3D_DEVCAP_SURFACEFMT_YUY2 = 69,
SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = 70,
SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = 71,
SVGA3D_DEVCAP_ALPHATOCOVERAGE = 72,
SVGA3D_DEVCAP_SUPERSAMPLE = 73,
SVGA3D_DEVCAP_AUTOGENMIPMAPS = 74,
SVGA3D_DEVCAP_SURFACEFMT_NV12 = 75,
SVGA3D_DEVCAP_SURFACEFMT_AYUV = 76,
/*
* This is the maximum number of SVGA context IDs that the guest
* can define using SVGA_3D_CMD_CONTEXT_DEFINE.
*/
SVGA3D_DEVCAP_MAX_CONTEXT_IDS = 77,
/*
* This is the maximum number of SVGA surface IDs that the guest
* can define using SVGA_3D_CMD_SURFACE_DEFINE*.
*/
SVGA3D_DEVCAP_MAX_SURFACE_IDS = 78,
SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = 79,
SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = 80,
SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = 81,
SVGA3D_DEVCAP_SURFACEFMT_ATI1 = 82,
SVGA3D_DEVCAP_SURFACEFMT_ATI2 = 83,
/*
* Deprecated.
*/
SVGA3D_DEVCAP_DEAD1 = 84,
/*
* This contains several SVGA_3D_CAPS_VIDEO_DECODE elements
* ored together, one for every type of video decoding supported.
*/
SVGA3D_DEVCAP_VIDEO_DECODE = 85,
/*
* This contains several SVGA_3D_CAPS_VIDEO_PROCESS elements
* ored together, one for every type of video processing supported.
*/
SVGA3D_DEVCAP_VIDEO_PROCESS = 86,
SVGA3D_DEVCAP_LINE_AA = 87, /* boolean */
SVGA3D_DEVCAP_LINE_STIPPLE = 88, /* boolean */
SVGA3D_DEVCAP_MAX_LINE_WIDTH = 89, /* float */
SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH = 90, /* float */
SVGA3D_DEVCAP_SURFACEFMT_YV12 = 91,
/*
* Does the host support the SVGA logic ops commands?
*/
SVGA3D_DEVCAP_LOGICOPS = 92,
/*
* Are TS_CONSTANT, TS_COLOR_KEY, and TS_COLOR_KEY_ENABLE supported?
*/
SVGA3D_DEVCAP_TS_COLOR_KEY = 93, /* boolean */
/*
* Deprecated.
*/
SVGA3D_DEVCAP_DEAD2 = 94,
/*
* Does the device support the DX commands?
*/
SVGA3D_DEVCAP_DX = 95,
/*
* What is the maximum size of a texture array?
*
* (Even if this cap is zero, cubemaps are still allowed.)
*/
SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE = 96,
/*
* What is the maximum number of vertex buffers that can
* be used in the DXContext inputAssembly?
*/
SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS = 97,
/*
* What is the maximum number of constant buffers
* that can be expected to work correctly with a
* DX context?
*/
SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS = 98,
/*
* Does the device support provoking vertex control?
* If zero, the first vertex will always be the provoking vertex.
*/
SVGA3D_DEVCAP_DX_PROVOKING_VERTEX = 99,
SVGA3D_DEVCAP_DXFMT_X8R8G8B8 = 100,
SVGA3D_DEVCAP_DXFMT_A8R8G8B8 = 101,
SVGA3D_DEVCAP_DXFMT_R5G6B5 = 102,
SVGA3D_DEVCAP_DXFMT_X1R5G5B5 = 103,
SVGA3D_DEVCAP_DXFMT_A1R5G5B5 = 104,
SVGA3D_DEVCAP_DXFMT_A4R4G4B4 = 105,
SVGA3D_DEVCAP_DXFMT_Z_D32 = 106,
SVGA3D_DEVCAP_DXFMT_Z_D16 = 107,
SVGA3D_DEVCAP_DXFMT_Z_D24S8 = 108,
SVGA3D_DEVCAP_DXFMT_Z_D15S1 = 109,
SVGA3D_DEVCAP_DXFMT_LUMINANCE8 = 110,
SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4 = 111,
SVGA3D_DEVCAP_DXFMT_LUMINANCE16 = 112,
SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8 = 113,
SVGA3D_DEVCAP_DXFMT_DXT1 = 114,
SVGA3D_DEVCAP_DXFMT_DXT2 = 115,
SVGA3D_DEVCAP_DXFMT_DXT3 = 116,
SVGA3D_DEVCAP_DXFMT_DXT4 = 117,
SVGA3D_DEVCAP_DXFMT_DXT5 = 118,
SVGA3D_DEVCAP_DXFMT_BUMPU8V8 = 119,
SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5 = 120,
SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8 = 121,
SVGA3D_DEVCAP_DXFMT_BUMPL8V8U8 = 122,
SVGA3D_DEVCAP_DXFMT_ARGB_S10E5 = 123,
SVGA3D_DEVCAP_DXFMT_ARGB_S23E8 = 124,
SVGA3D_DEVCAP_DXFMT_A2R10G10B10 = 125,
SVGA3D_DEVCAP_DXFMT_V8U8 = 126,
SVGA3D_DEVCAP_DXFMT_Q8W8V8U8 = 127,
SVGA3D_DEVCAP_DXFMT_CxV8U8 = 128,
SVGA3D_DEVCAP_DXFMT_X8L8V8U8 = 129,
SVGA3D_DEVCAP_DXFMT_A2W10V10U10 = 130,
SVGA3D_DEVCAP_DXFMT_ALPHA8 = 131,
SVGA3D_DEVCAP_DXFMT_R_S10E5 = 132,
SVGA3D_DEVCAP_DXFMT_R_S23E8 = 133,
SVGA3D_DEVCAP_DXFMT_RG_S10E5 = 134,
SVGA3D_DEVCAP_DXFMT_RG_S23E8 = 135,
SVGA3D_DEVCAP_DXFMT_BUFFER = 136,
SVGA3D_DEVCAP_DXFMT_Z_D24X8 = 137,
SVGA3D_DEVCAP_DXFMT_V16U16 = 138,
SVGA3D_DEVCAP_DXFMT_G16R16 = 139,
SVGA3D_DEVCAP_DXFMT_A16B16G16R16 = 140,
SVGA3D_DEVCAP_DXFMT_UYVY = 141,
SVGA3D_DEVCAP_DXFMT_YUY2 = 142,
SVGA3D_DEVCAP_DXFMT_NV12 = 143,
SVGA3D_DEVCAP_DXFMT_AYUV = 144,
SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS = 145,
SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT = 146,
SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT = 147,
SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS = 148,
SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT = 149,
SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT = 150,
SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT = 151,
SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS = 152,
SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT = 153,
SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM = 154,
SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT = 155,
SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS = 156,
SVGA3D_DEVCAP_DXFMT_R32G32_UINT = 157,
SVGA3D_DEVCAP_DXFMT_R32G32_SINT = 158,
SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS = 159,
SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT = 160,
SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24_TYPELESS = 161,
SVGA3D_DEVCAP_DXFMT_X32_TYPELESS_G8X24_UINT = 162,
SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS = 163,
SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT = 164,
SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT = 165,
SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS = 166,
SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM = 167,
SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB = 168,
SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT = 169,
SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT = 170,
SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS = 171,
SVGA3D_DEVCAP_DXFMT_R16G16_UINT = 172,
SVGA3D_DEVCAP_DXFMT_R16G16_SINT = 173,
SVGA3D_DEVCAP_DXFMT_R32_TYPELESS = 174,
SVGA3D_DEVCAP_DXFMT_D32_FLOAT = 175,
SVGA3D_DEVCAP_DXFMT_R32_UINT = 176,
SVGA3D_DEVCAP_DXFMT_R32_SINT = 177,
SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS = 178,
SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT = 179,
SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8_TYPELESS = 180,
SVGA3D_DEVCAP_DXFMT_X24_TYPELESS_G8_UINT = 181,
SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS = 182,
SVGA3D_DEVCAP_DXFMT_R8G8_UNORM = 183,
SVGA3D_DEVCAP_DXFMT_R8G8_UINT = 184,
SVGA3D_DEVCAP_DXFMT_R8G8_SINT = 185,
SVGA3D_DEVCAP_DXFMT_R16_TYPELESS = 186,
SVGA3D_DEVCAP_DXFMT_R16_UNORM = 187,
SVGA3D_DEVCAP_DXFMT_R16_UINT = 188,
SVGA3D_DEVCAP_DXFMT_R16_SNORM = 189,
SVGA3D_DEVCAP_DXFMT_R16_SINT = 190,
SVGA3D_DEVCAP_DXFMT_R8_TYPELESS = 191,
SVGA3D_DEVCAP_DXFMT_R8_UNORM = 192,
SVGA3D_DEVCAP_DXFMT_R8_UINT = 193,
SVGA3D_DEVCAP_DXFMT_R8_SNORM = 194,
SVGA3D_DEVCAP_DXFMT_R8_SINT = 195,
SVGA3D_DEVCAP_DXFMT_P8 = 196,
SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP = 197,
SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM = 198,
SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM = 199,
SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS = 200,
SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB = 201,
SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS = 202,
SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB = 203,
SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS = 204,
SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB = 205,
SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS = 206,
SVGA3D_DEVCAP_DXFMT_ATI1 = 207,
SVGA3D_DEVCAP_DXFMT_BC4_SNORM = 208,
SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS = 209,
SVGA3D_DEVCAP_DXFMT_ATI2 = 210,
SVGA3D_DEVCAP_DXFMT_BC5_SNORM = 211,
SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM = 212,
SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS = 213,
SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB = 214,
SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS = 215,
SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB = 216,
SVGA3D_DEVCAP_DXFMT_Z_DF16 = 217,
SVGA3D_DEVCAP_DXFMT_Z_DF24 = 218,
SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT = 219,
SVGA3D_DEVCAP_DXFMT_YV12 = 220,
SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT = 221,
SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT = 222,
SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM = 223,
SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT = 224,
SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM = 225,
SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM = 226,
SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT = 227,
SVGA3D_DEVCAP_DXFMT_R16G16_UNORM = 228,
SVGA3D_DEVCAP_DXFMT_R16G16_SNORM = 229,
SVGA3D_DEVCAP_DXFMT_R32_FLOAT = 230,
SVGA3D_DEVCAP_DXFMT_R8G8_SNORM = 231,
SVGA3D_DEVCAP_DXFMT_R16_FLOAT = 232,
SVGA3D_DEVCAP_DXFMT_D16_UNORM = 233,
SVGA3D_DEVCAP_DXFMT_A8_UNORM = 234,
SVGA3D_DEVCAP_DXFMT_BC1_UNORM = 235,
SVGA3D_DEVCAP_DXFMT_BC2_UNORM = 236,
SVGA3D_DEVCAP_DXFMT_BC3_UNORM = 237,
SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM = 238,
SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM = 239,
SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM = 240,
SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM = 241,
SVGA3D_DEVCAP_DXFMT_BC4_UNORM = 242,
SVGA3D_DEVCAP_DXFMT_BC5_UNORM = 243,
SVGA3D_DEVCAP_MAX /* This must be the last index. */
} SVGA3dDevCapIndex;
/*
* Bit definitions for DXFMT devcaps
*
*
* SUPPORTED: Can the format be defined?
* SHADER_SAMPLE: Can the format be sampled from a shader?
* COLOR_RENDERTARGET: Can the format be a color render target?
* DEPTH_RENDERTARGET: Can the format be a depth render target?
* BLENDABLE: Is the format blendable?
* MIPS: Does the format support mip levels?
* ARRAY: Does the format support texture arrays?
* VOLUME: Does the format support having volume?
* MULTISAMPLE_2: Does the format support 2x multisample?
* MULTISAMPLE_4: Does the format support 4x multisample?
* MULTISAMPLE_8: Does the format support 8x multisample?
*/
#define SVGA3D_DXFMT_SUPPORTED (1 << 0)
#define SVGA3D_DXFMT_SHADER_SAMPLE (1 << 1)
#define SVGA3D_DXFMT_COLOR_RENDERTARGET (1 << 2)
#define SVGA3D_DXFMT_DEPTH_RENDERTARGET (1 << 3)
#define SVGA3D_DXFMT_BLENDABLE (1 << 4)
#define SVGA3D_DXFMT_MIPS (1 << 5)
#define SVGA3D_DXFMT_ARRAY (1 << 6)
#define SVGA3D_DXFMT_VOLUME (1 << 7)
#define SVGA3D_DXFMT_DX_VERTEX_BUFFER (1 << 8)
#define SVGADX_DXFMT_MULTISAMPLE_2 (1 << 9)
#define SVGADX_DXFMT_MULTISAMPLE_4 (1 << 10)
#define SVGADX_DXFMT_MULTISAMPLE_8 (1 << 11)
#define SVGADX_DXFMT_MAX (1 << 12)
/*
* Convenience mask for any multisample capability.
*
* The multisample bits imply both load and render capability.
*/
#define SVGA3D_DXFMT_MULTISAMPLE ( \
SVGADX_DXFMT_MULTISAMPLE_2 | \
SVGADX_DXFMT_MULTISAMPLE_4 | \
SVGADX_DXFMT_MULTISAMPLE_8 )
typedef union {
Bool b;
uint32 u;
int32 i;
float f;
} SVGA3dDevCapResult;
#endif /* _SVGA3D_DEVCAPS_H_ */
drivers/gpu/drm/vmwgfx/device_include/svga3d_dx.h 0 → 100644
View file @ 8ce75f8a
/**********************************************************
* Copyright 2012-2015 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
/*
* svga3d_dx.h --
*
* SVGA 3d hardware definitions for DX10 support.
*/
#ifndef _SVGA3D_DX_H_
#define _SVGA3D_DX_H_
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#define INCLUDE_ALLOW_VMCORE
#include "includeCheck.h"
#include "svga3d_limits.h"
#define SVGA3D_INPUT_MIN 0
#define SVGA3D_INPUT_PER_VERTEX_DATA 0
#define SVGA3D_INPUT_PER_INSTANCE_DATA 1
#define SVGA3D_INPUT_MAX 2
typedef uint32 SVGA3dInputClassification;
#define SVGA3D_RESOURCE_TYPE_MIN 1
#define SVGA3D_RESOURCE_BUFFER 1
#define SVGA3D_RESOURCE_TEXTURE1D 2
#define SVGA3D_RESOURCE_TEXTURE2D 3
#define SVGA3D_RESOURCE_TEXTURE3D 4
#define SVGA3D_RESOURCE_TEXTURECUBE 5
#define SVGA3D_RESOURCE_TYPE_DX10_MAX 6
#define SVGA3D_RESOURCE_BUFFEREX 6
#define SVGA3D_RESOURCE_TYPE_MAX 7
typedef uint32 SVGA3dResourceType;
#define SVGA3D_DEPTH_WRITE_MASK_ZERO 0
#define SVGA3D_DEPTH_WRITE_MASK_ALL 1
typedef uint8 SVGA3dDepthWriteMask;
#define SVGA3D_FILTER_MIP_LINEAR (1 << 0)
#define SVGA3D_FILTER_MAG_LINEAR (1 << 2)
#define SVGA3D_FILTER_MIN_LINEAR (1 << 4)
#define SVGA3D_FILTER_ANISOTROPIC (1 << 6)
#define SVGA3D_FILTER_COMPARE (1 << 7)
typedef uint32 SVGA3dFilter;
#define SVGA3D_CULL_INVALID 0
#define SVGA3D_CULL_MIN 1
#define SVGA3D_CULL_NONE 1
#define SVGA3D_CULL_FRONT 2
#define SVGA3D_CULL_BACK 3
#define SVGA3D_CULL_MAX 4
typedef uint8 SVGA3dCullMode;
#define SVGA3D_COMPARISON_INVALID 0
#define SVGA3D_COMPARISON_MIN 1
#define SVGA3D_COMPARISON_NEVER 1
#define SVGA3D_COMPARISON_LESS 2
#define SVGA3D_COMPARISON_EQUAL 3
#define SVGA3D_COMPARISON_LESS_EQUAL 4
#define SVGA3D_COMPARISON_GREATER 5
#define SVGA3D_COMPARISON_NOT_EQUAL 6
#define SVGA3D_COMPARISON_GREATER_EQUAL 7
#define SVGA3D_COMPARISON_ALWAYS 8
#define SVGA3D_COMPARISON_MAX 9
typedef uint8 SVGA3dComparisonFunc;
#define SVGA3D_DX_MAX_VERTEXBUFFERS 32
#define SVGA3D_DX_MAX_SOTARGETS 4
#define SVGA3D_DX_MAX_SRVIEWS 128
#define SVGA3D_DX_MAX_CONSTBUFFERS 16
#define SVGA3D_DX_MAX_SAMPLERS 16
/* Id limits */
static const uint32 SVGA3dBlendObjectCountPerContext = 4096;
static const uint32 SVGA3dDepthStencilObjectCountPerContext = 4096;
typedef uint32 SVGA3dSurfaceId;
typedef uint32 SVGA3dShaderResourceViewId;
typedef uint32 SVGA3dRenderTargetViewId;
typedef uint32 SVGA3dDepthStencilViewId;
typedef uint32 SVGA3dShaderId;
typedef uint32 SVGA3dElementLayoutId;
typedef uint32 SVGA3dSamplerId;
typedef uint32 SVGA3dBlendStateId;
typedef uint32 SVGA3dDepthStencilStateId;
typedef uint32 SVGA3dRasterizerStateId;
typedef uint32 SVGA3dQueryId;
typedef uint32 SVGA3dStreamOutputId;
typedef union {
struct {
float r;
float g;
float b;
float a;
};
float value[4];
} SVGA3dRGBAFloat;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGAMobId mobid;
}
#include "vmware_pack_end.h"
SVGAOTableDXContextEntry;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDefineContext {
uint32 cid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDefineContext; /* SVGA_3D_CMD_DX_DEFINE_CONTEXT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDestroyContext {
uint32 cid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDestroyContext; /* SVGA_3D_CMD_DX_DESTROY_CONTEXT */
/*
* Bind a DX context.
*
* validContents should be set to 0 for new contexts,
* and 1 if this is an old context which is getting paged
* back on to the device.
*
* For new contexts, it is recommended that the driver
* issue commands to initialize all interesting state
* prior to rendering.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXBindContext {
uint32 cid;
SVGAMobId mobid;
uint32 validContents;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXBindContext; /* SVGA_3D_CMD_DX_BIND_CONTEXT */
/*
* Readback a DX context.
* (Request that the device flush the contents back into guest memory.)
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXReadbackContext {
uint32 cid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXReadbackContext; /* SVGA_3D_CMD_DX_READBACK_CONTEXT */
/*
* Invalidate a guest-backed context.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXInvalidateContext {
uint32 cid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXInvalidateContext; /* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dReplyFormatData {
uint32 formatSupport;
uint32 msaa2xQualityLevels:5;
uint32 msaa4xQualityLevels:5;
uint32 msaa8xQualityLevels:5;
uint32 msaa16xQualityLevels:5;
uint32 msaa32xQualityLevels:5;
uint32 pad:7;
}
#include "vmware_pack_end.h"
SVGA3dReplyFormatData;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetSingleConstantBuffer {
uint32 slot;
SVGA3dShaderType type;
SVGA3dSurfaceId sid;
uint32 offsetInBytes;
uint32 sizeInBytes;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetSingleConstantBuffer;
/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetShaderResources {
uint32 startView;
SVGA3dShaderType type;
/*
* Followed by a variable number of SVGA3dShaderResourceViewId's.
*/
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetShaderResources; /* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetShader {
SVGA3dShaderId shaderId;
SVGA3dShaderType type;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetShader; /* SVGA_3D_CMD_DX_SET_SHADER */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetSamplers {
uint32 startSampler;
SVGA3dShaderType type;
/*
* Followed by a variable number of SVGA3dSamplerId's.
*/
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetSamplers; /* SVGA_3D_CMD_DX_SET_SAMPLERS */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDraw {
uint32 vertexCount;
uint32 startVertexLocation;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDraw; /* SVGA_3D_CMD_DX_DRAW */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDrawIndexed {
uint32 indexCount;
uint32 startIndexLocation;
int32 baseVertexLocation;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDrawIndexed; /* SVGA_3D_CMD_DX_DRAW_INDEXED */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDrawInstanced {
uint32 vertexCountPerInstance;
uint32 instanceCount;
uint32 startVertexLocation;
uint32 startInstanceLocation;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDrawInstanced; /* SVGA_3D_CMD_DX_DRAW_INSTANCED */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDrawIndexedInstanced {
uint32 indexCountPerInstance;
uint32 instanceCount;
uint32 startIndexLocation;
int32 baseVertexLocation;
uint32 startInstanceLocation;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDrawIndexedInstanced; /* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDrawAuto {
uint32 pad0;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDrawAuto; /* SVGA_3D_CMD_DX_DRAW_AUTO */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetInputLayout {
SVGA3dElementLayoutId elementLayoutId;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetInputLayout; /* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dVertexBuffer {
SVGA3dSurfaceId sid;
uint32 stride;
uint32 offset;
}
#include "vmware_pack_end.h"
SVGA3dVertexBuffer;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetVertexBuffers {
uint32 startBuffer;
/* Followed by a variable number of SVGA3dVertexBuffer's. */
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetVertexBuffers; /* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetIndexBuffer {
SVGA3dSurfaceId sid;
SVGA3dSurfaceFormat format;
uint32 offset;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetIndexBuffer; /* SVGA_3D_CMD_DX_SET_INDEX_BUFFER */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetTopology {
SVGA3dPrimitiveType topology;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetTopology; /* SVGA_3D_CMD_DX_SET_TOPOLOGY */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetRenderTargets {
SVGA3dDepthStencilViewId depthStencilViewId;
/* Followed by a variable number of SVGA3dRenderTargetViewId's. */
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetRenderTargets; /* SVGA_3D_CMD_DX_SET_RENDERTARGETS */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetBlendState {
SVGA3dBlendStateId blendId;
float blendFactor[4];
uint32 sampleMask;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetBlendState; /* SVGA_3D_CMD_DX_SET_BLEND_STATE */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetDepthStencilState {
SVGA3dDepthStencilStateId depthStencilId;
uint32 stencilRef;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetDepthStencilState; /* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetRasterizerState {
SVGA3dRasterizerStateId rasterizerId;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetRasterizerState; /* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE */
#define SVGA3D_DXQUERY_FLAG_PREDICATEHINT (1 << 0)
typedef uint32 SVGA3dDXQueryFlags;
/*
* The SVGADXQueryDeviceState and SVGADXQueryDeviceBits are used by the device
* to track query state transitions, but are not intended to be used by the
* driver.
*/
#define SVGADX_QDSTATE_INVALID ((uint8)-1) /* Query has no state */
#define SVGADX_QDSTATE_MIN 0
#define SVGADX_QDSTATE_IDLE 0 /* Query hasn't started yet */
#define SVGADX_QDSTATE_ACTIVE 1 /* Query is actively gathering data */
#define SVGADX_QDSTATE_PENDING 2 /* Query is waiting for results */
#define SVGADX_QDSTATE_FINISHED 3 /* Query has completed */
#define SVGADX_QDSTATE_MAX 4
typedef uint8 SVGADXQueryDeviceState;
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dQueryTypeUint8 type;
uint16 pad0;
SVGADXQueryDeviceState state;
SVGA3dDXQueryFlags flags;
SVGAMobId mobid;
uint32 offset;
}
#include "vmware_pack_end.h"
SVGACOTableDXQueryEntry;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDefineQuery {
SVGA3dQueryId queryId;
SVGA3dQueryType type;
SVGA3dDXQueryFlags flags;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDefineQuery; /* SVGA_3D_CMD_DX_DEFINE_QUERY */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDestroyQuery {
SVGA3dQueryId queryId;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDestroyQuery; /* SVGA_3D_CMD_DX_DESTROY_QUERY */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXBindQuery {
SVGA3dQueryId queryId;
SVGAMobId mobid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXBindQuery; /* SVGA_3D_CMD_DX_BIND_QUERY */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetQueryOffset {
SVGA3dQueryId queryId;
uint32 mobOffset;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetQueryOffset; /* SVGA_3D_CMD_DX_SET_QUERY_OFFSET */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXBeginQuery {
SVGA3dQueryId queryId;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXBeginQuery; /* SVGA_3D_CMD_DX_QUERY_BEGIN */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXEndQuery {
SVGA3dQueryId queryId;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXEndQuery; /* SVGA_3D_CMD_DX_QUERY_END */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXReadbackQuery {
SVGA3dQueryId queryId;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXReadbackQuery; /* SVGA_3D_CMD_DX_READBACK_QUERY */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXMoveQuery {
SVGA3dQueryId queryId;
SVGAMobId mobid;
uint32 mobOffset;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXMoveQuery; /* SVGA_3D_CMD_DX_MOVE_QUERY */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXBindAllQuery {
uint32 cid;
SVGAMobId mobid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXBindAllQuery; /* SVGA_3D_CMD_DX_BIND_ALL_QUERY */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXReadbackAllQuery {
uint32 cid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXReadbackAllQuery; /* SVGA_3D_CMD_DX_READBACK_ALL_QUERY */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetPredication {
SVGA3dQueryId queryId;
uint32 predicateValue;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetPredication; /* SVGA_3D_CMD_DX_SET_PREDICATION */
typedef
#include "vmware_pack_begin.h"
struct MKS3dDXSOState {
uint32 offset; /* Starting offset */
uint32 intOffset; /* Internal offset */
uint32 vertexCount; /* vertices written */
uint32 sizeInBytes; /* max bytes to write */
}
#include "vmware_pack_end.h"
SVGA3dDXSOState;
/* Set the offset field to this value to append SO values to the buffer */
#define SVGA3D_DX_SO_OFFSET_APPEND ((uint32) ~0u)
typedef
#include "vmware_pack_begin.h"
struct SVGA3dSoTarget {
SVGA3dSurfaceId sid;
uint32 offset;
uint32 sizeInBytes;
}
#include "vmware_pack_end.h"
SVGA3dSoTarget;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetSOTargets {
uint32 pad0;
/* Followed by a variable number of SVGA3dSOTarget's. */
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetSOTargets; /* SVGA_3D_CMD_DX_SET_SOTARGETS */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dViewport
{
float x;
float y;
float width;
float height;
float minDepth;
float maxDepth;
}
#include "vmware_pack_end.h"
SVGA3dViewport;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetViewports {
uint32 pad0;
/* Followed by a variable number of SVGA3dViewport's. */
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetViewports; /* SVGA_3D_CMD_DX_SET_VIEWPORTS */
#define SVGA3D_DX_MAX_VIEWPORTS 16
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetScissorRects {
uint32 pad0;
/* Followed by a variable number of SVGASignedRect's. */
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetScissorRects; /* SVGA_3D_CMD_DX_SET_SCISSORRECTS */
#define SVGA3D_DX_MAX_SCISSORRECTS 16
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXClearRenderTargetView {
SVGA3dRenderTargetViewId renderTargetViewId;
SVGA3dRGBAFloat rgba;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXClearRenderTargetView; /* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXClearDepthStencilView {
uint16 flags;
uint16 stencil;
SVGA3dDepthStencilViewId depthStencilViewId;
float depth;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXClearDepthStencilView; /* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXPredCopyRegion {
SVGA3dSurfaceId dstSid;
uint32 dstSubResource;
SVGA3dSurfaceId srcSid;
uint32 srcSubResource;
SVGA3dCopyBox box;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXPredCopyRegion;
/* SVGA_3D_CMD_DX_PRED_COPY_REGION */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXPredCopy {
SVGA3dSurfaceId dstSid;
SVGA3dSurfaceId srcSid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXPredCopy; /* SVGA_3D_CMD_DX_PRED_COPY */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXBufferCopy {
SVGA3dSurfaceId dest;
SVGA3dSurfaceId src;
uint32 destX;
uint32 srcX;
uint32 width;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXBufferCopy;
/* SVGA_3D_CMD_DX_BUFFER_COPY */
typedef uint32 SVGA3dDXStretchBltMode;
#define SVGADX_STRETCHBLT_LINEAR (1 << 0)
#define SVGADX_STRETCHBLT_FORCE_SRC_SRGB (1 << 1)
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXStretchBlt {
SVGA3dSurfaceId srcSid;
uint32 srcSubResource;
SVGA3dSurfaceId dstSid;
uint32 destSubResource;
SVGA3dBox boxSrc;
SVGA3dBox boxDest;
SVGA3dDXStretchBltMode mode;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXStretchBlt; /* SVGA_3D_CMD_DX_STRETCHBLT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXGenMips {
SVGA3dShaderResourceViewId shaderResourceViewId;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXGenMips; /* SVGA_3D_CMD_DX_GENMIPS */
/*
* Defines a resource/DX surface. Resources share the surfaceId namespace.
*
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDefineGBSurface_v2 {
uint32 sid;
SVGA3dSurfaceFlags surfaceFlags;
SVGA3dSurfaceFormat format;
uint32 numMipLevels;
uint32 multisampleCount;
SVGA3dTextureFilter autogenFilter;
SVGA3dSize size;
uint32 arraySize;
uint32 pad;
}
#include "vmware_pack_end.h"
SVGA3dCmdDefineGBSurface_v2; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 */
/*
* Update a sub-resource in a guest-backed resource.
* (Inform the device that the guest-contents have been updated.)
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXUpdateSubResource {
SVGA3dSurfaceId sid;
uint32 subResource;
SVGA3dBox box;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXUpdateSubResource; /* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE */
/*
* Readback a subresource in a guest-backed resource.
* (Request the device to flush the dirty contents into the guest.)
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXReadbackSubResource {
SVGA3dSurfaceId sid;
uint32 subResource;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXReadbackSubResource; /* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE */
/*
* Invalidate an image in a guest-backed surface.
* (Notify the device that the contents can be lost.)
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXInvalidateSubResource {
SVGA3dSurfaceId sid;
uint32 subResource;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXInvalidateSubResource; /* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE */
/*
* Raw byte wise transfer from a buffer surface into another surface
* of the requested box.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXTransferFromBuffer {
SVGA3dSurfaceId srcSid;
uint32 srcOffset;
uint32 srcPitch;
uint32 srcSlicePitch;
SVGA3dSurfaceId destSid;
uint32 destSubResource;
SVGA3dBox destBox;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXTransferFromBuffer; /* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER */
/*
* Raw byte wise transfer from a buffer surface into another surface
* of the requested box. Supported if SVGA3D_DEVCAP_DXCONTEXT is set.
* The context is implied from the command buffer header.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXPredTransferFromBuffer {
SVGA3dSurfaceId srcSid;
uint32 srcOffset;
uint32 srcPitch;
uint32 srcSlicePitch;
SVGA3dSurfaceId destSid;
uint32 destSubResource;
SVGA3dBox destBox;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXPredTransferFromBuffer;
/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSurfaceCopyAndReadback {
SVGA3dSurfaceId srcSid;
SVGA3dSurfaceId destSid;
SVGA3dCopyBox box;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSurfaceCopyAndReadback;
/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK */
typedef
#include "vmware_pack_begin.h"
struct {
union {
struct {
uint32 firstElement;
uint32 numElements;
uint32 pad0;
uint32 pad1;
} buffer;
struct {
uint32 mostDetailedMip;
uint32 firstArraySlice;
uint32 mipLevels;
uint32 arraySize;
} tex;
struct {
uint32 firstElement;
uint32 numElements;
uint32 flags;
uint32 pad0;
} bufferex;
};
}
#include "vmware_pack_end.h"
SVGA3dShaderResourceViewDesc;
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dSurfaceId sid;
SVGA3dSurfaceFormat format;
SVGA3dResourceType resourceDimension;
SVGA3dShaderResourceViewDesc desc;
uint32 pad;
}
#include "vmware_pack_end.h"
SVGACOTableDXSRViewEntry;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDefineShaderResourceView {
SVGA3dShaderResourceViewId shaderResourceViewId;
SVGA3dSurfaceId sid;
SVGA3dSurfaceFormat format;
SVGA3dResourceType resourceDimension;
SVGA3dShaderResourceViewDesc desc;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDefineShaderResourceView;
/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDestroyShaderResourceView {
SVGA3dShaderResourceViewId shaderResourceViewId;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDestroyShaderResourceView;
/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dRenderTargetViewDesc {
union {
struct {
uint32 firstElement;
uint32 numElements;
} buffer;
struct {
uint32 mipSlice;
uint32 firstArraySlice;
uint32 arraySize;
} tex; /* 1d, 2d, cube */
struct {
uint32 mipSlice;
uint32 firstW;
uint32 wSize;
} tex3D;
};
}
#include "vmware_pack_end.h"
SVGA3dRenderTargetViewDesc;
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dSurfaceId sid;
SVGA3dSurfaceFormat format;
SVGA3dResourceType resourceDimension;
SVGA3dRenderTargetViewDesc desc;
uint32 pad[2];
}
#include "vmware_pack_end.h"
SVGACOTableDXRTViewEntry;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDefineRenderTargetView {
SVGA3dRenderTargetViewId renderTargetViewId;
SVGA3dSurfaceId sid;
SVGA3dSurfaceFormat format;
SVGA3dResourceType resourceDimension;
SVGA3dRenderTargetViewDesc desc;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDefineRenderTargetView;
/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDestroyRenderTargetView {
SVGA3dRenderTargetViewId renderTargetViewId;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDestroyRenderTargetView;
/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW */
/*
*/
#define SVGA3D_DXDSVIEW_CREATE_READ_ONLY_DEPTH 0x01
#define SVGA3D_DXDSVIEW_CREATE_READ_ONLY_STENCIL 0x02
#define SVGA3D_DXDSVIEW_CREATE_FLAG_MASK 0x03
typedef uint8 SVGA3DCreateDSViewFlags;
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dSurfaceId sid;
SVGA3dSurfaceFormat format;
SVGA3dResourceType resourceDimension;
uint32 mipSlice;
uint32 firstArraySlice;
uint32 arraySize;
SVGA3DCreateDSViewFlags flags;
uint8 pad0;
uint16 pad1;
uint32 pad2;
}
#include "vmware_pack_end.h"
SVGACOTableDXDSViewEntry;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDefineDepthStencilView {
SVGA3dDepthStencilViewId depthStencilViewId;
SVGA3dSurfaceId sid;
SVGA3dSurfaceFormat format;
SVGA3dResourceType resourceDimension;
uint32 mipSlice;
uint32 firstArraySlice;
uint32 arraySize;
SVGA3DCreateDSViewFlags flags;
uint8 pad0;
uint16 pad1;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDefineDepthStencilView;
/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDestroyDepthStencilView {
SVGA3dDepthStencilViewId depthStencilViewId;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDestroyDepthStencilView;
/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dInputElementDesc {
uint32 inputSlot;
uint32 alignedByteOffset;
SVGA3dSurfaceFormat format;
SVGA3dInputClassification inputSlotClass;
uint32 instanceDataStepRate;
uint32 inputRegister;
}
#include "vmware_pack_end.h"
SVGA3dInputElementDesc;
typedef
#include "vmware_pack_begin.h"
struct {
/*
* XXX: How many of these can there be?
*/
uint32 elid;
uint32 numDescs;
SVGA3dInputElementDesc desc[32];
uint32 pad[62];
}
#include "vmware_pack_end.h"
SVGACOTableDXElementLayoutEntry;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDefineElementLayout {
SVGA3dElementLayoutId elementLayoutId;
/* Followed by a variable number of SVGA3dInputElementDesc's. */
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDefineElementLayout;
/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDestroyElementLayout {
SVGA3dElementLayoutId elementLayoutId;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDestroyElementLayout;
/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT */
#define SVGA3D_DX_MAX_RENDER_TARGETS 8
typedef
#include "vmware_pack_begin.h"
struct SVGA3dDXBlendStatePerRT {
uint8 blendEnable;
uint8 srcBlend;
uint8 destBlend;
uint8 blendOp;
uint8 srcBlendAlpha;
uint8 destBlendAlpha;
uint8 blendOpAlpha;
uint8 renderTargetWriteMask;
uint8 logicOpEnable;
uint8 logicOp;
uint16 pad0;
}
#include "vmware_pack_end.h"
SVGA3dDXBlendStatePerRT;
typedef
#include "vmware_pack_begin.h"
struct {
uint8 alphaToCoverageEnable;
uint8 independentBlendEnable;
uint16 pad0;
SVGA3dDXBlendStatePerRT perRT[SVGA3D_MAX_RENDER_TARGETS];
uint32 pad1[7];
}
#include "vmware_pack_end.h"
SVGACOTableDXBlendStateEntry;
/*
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDefineBlendState {
SVGA3dBlendStateId blendId;
uint8 alphaToCoverageEnable;
uint8 independentBlendEnable;
uint16 pad0;
SVGA3dDXBlendStatePerRT perRT[SVGA3D_MAX_RENDER_TARGETS];
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDefineBlendState; /* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDestroyBlendState {
SVGA3dBlendStateId blendId;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDestroyBlendState; /* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE */
typedef
#include "vmware_pack_begin.h"
struct {
uint8 depthEnable;
SVGA3dDepthWriteMask depthWriteMask;
SVGA3dComparisonFunc depthFunc;
uint8 stencilEnable;
uint8 frontEnable;
uint8 backEnable;
uint8 stencilReadMask;
uint8 stencilWriteMask;
uint8 frontStencilFailOp;
uint8 frontStencilDepthFailOp;
uint8 frontStencilPassOp;
SVGA3dComparisonFunc frontStencilFunc;
uint8 backStencilFailOp;
uint8 backStencilDepthFailOp;
uint8 backStencilPassOp;
SVGA3dComparisonFunc backStencilFunc;
}
#include "vmware_pack_end.h"
SVGACOTableDXDepthStencilEntry;
/*
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDefineDepthStencilState {
SVGA3dDepthStencilStateId depthStencilId;
uint8 depthEnable;
SVGA3dDepthWriteMask depthWriteMask;
SVGA3dComparisonFunc depthFunc;
uint8 stencilEnable;
uint8 frontEnable;
uint8 backEnable;
uint8 stencilReadMask;
uint8 stencilWriteMask;
uint8 frontStencilFailOp;
uint8 frontStencilDepthFailOp;
uint8 frontStencilPassOp;
SVGA3dComparisonFunc frontStencilFunc;
uint8 backStencilFailOp;
uint8 backStencilDepthFailOp;
uint8 backStencilPassOp;
SVGA3dComparisonFunc backStencilFunc;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDefineDepthStencilState;
/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDestroyDepthStencilState {
SVGA3dDepthStencilStateId depthStencilId;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDestroyDepthStencilState;
/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE */
typedef
#include "vmware_pack_begin.h"
struct {
uint8 fillMode;
SVGA3dCullMode cullMode;
uint8 frontCounterClockwise;
uint8 provokingVertexLast;
int32 depthBias;
float depthBiasClamp;
float slopeScaledDepthBias;
uint8 depthClipEnable;
uint8 scissorEnable;
uint8 multisampleEnable;
uint8 antialiasedLineEnable;
float lineWidth;
uint8 lineStippleEnable;
uint8 lineStippleFactor;
uint16 lineStipplePattern;
uint32 forcedSampleCount;
}
#include "vmware_pack_end.h"
SVGACOTableDXRasterizerStateEntry;
/*
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDefineRasterizerState {
SVGA3dRasterizerStateId rasterizerId;
uint8 fillMode;
SVGA3dCullMode cullMode;
uint8 frontCounterClockwise;
uint8 provokingVertexLast;
int32 depthBias;
float depthBiasClamp;
float slopeScaledDepthBias;
uint8 depthClipEnable;
uint8 scissorEnable;
uint8 multisampleEnable;
uint8 antialiasedLineEnable;
float lineWidth;
uint8 lineStippleEnable;
uint8 lineStippleFactor;
uint16 lineStipplePattern;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDefineRasterizerState;
/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDestroyRasterizerState {
SVGA3dRasterizerStateId rasterizerId;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDestroyRasterizerState;
/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE */
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dFilter filter;
uint8 addressU;
uint8 addressV;
uint8 addressW;
uint8 pad0;
float mipLODBias;
uint8 maxAnisotropy;
SVGA3dComparisonFunc comparisonFunc;
uint16 pad1;
SVGA3dRGBAFloat borderColor;
float minLOD;
float maxLOD;
uint32 pad2[6];
}
#include "vmware_pack_end.h"
SVGACOTableDXSamplerEntry;
/*
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDefineSamplerState {
SVGA3dSamplerId samplerId;
SVGA3dFilter filter;
uint8 addressU;
uint8 addressV;
uint8 addressW;
uint8 pad0;
float mipLODBias;
uint8 maxAnisotropy;
SVGA3dComparisonFunc comparisonFunc;
uint16 pad1;
SVGA3dRGBAFloat borderColor;
float minLOD;
float maxLOD;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDefineSamplerState; /* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDestroySamplerState {
SVGA3dSamplerId samplerId;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDestroySamplerState; /* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE */
/*
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dSignatureEntry {
uint8 systemValue;
uint8 reg; /* register is a reserved word */
uint16 mask;
uint8 registerComponentType;
uint8 minPrecision;
uint16 pad0;
}
#include "vmware_pack_end.h"
SVGA3dSignatureEntry;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDefineShader {
SVGA3dShaderId shaderId;
SVGA3dShaderType type;
uint32 sizeInBytes; /* Number of bytes of shader text. */
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDefineShader; /* SVGA_3D_CMD_DX_DEFINE_SHADER */
typedef
#include "vmware_pack_begin.h"
struct SVGACOTableDXShaderEntry {
SVGA3dShaderType type;
uint32 sizeInBytes;
uint32 offsetInBytes;
SVGAMobId mobid;
uint32 numInputSignatureEntries;
uint32 numOutputSignatureEntries;
uint32 numPatchConstantSignatureEntries;
uint32 pad;
}
#include "vmware_pack_end.h"
SVGACOTableDXShaderEntry;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDestroyShader {
SVGA3dShaderId shaderId;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDestroyShader; /* SVGA_3D_CMD_DX_DESTROY_SHADER */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXBindShader {
uint32 cid;
uint32 shid;
SVGAMobId mobid;
uint32 offsetInBytes;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXBindShader; /* SVGA_3D_CMD_DX_BIND_SHADER */
/*
* The maximum number of streamout decl's in each streamout entry.
*/
#define SVGA3D_MAX_STREAMOUT_DECLS 64
typedef
#include "vmware_pack_begin.h"
struct SVGA3dStreamOutputDeclarationEntry {
uint32 outputSlot;
uint32 registerIndex;
uint8 registerMask;
uint8 pad0;
uint16 pad1;
uint32 stream;
}
#include "vmware_pack_end.h"
SVGA3dStreamOutputDeclarationEntry;
typedef
#include "vmware_pack_begin.h"
struct SVGAOTableStreamOutputEntry {
uint32 numOutputStreamEntries;
SVGA3dStreamOutputDeclarationEntry decl[SVGA3D_MAX_STREAMOUT_DECLS];
uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS];
uint32 rasterizedStream;
uint32 pad[250];
}
#include "vmware_pack_end.h"
SVGACOTableDXStreamOutputEntry;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDefineStreamOutput {
SVGA3dStreamOutputId soid;
uint32 numOutputStreamEntries;
SVGA3dStreamOutputDeclarationEntry decl[SVGA3D_MAX_STREAMOUT_DECLS];
uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS];
uint32 rasterizedStream;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDefineStreamOutput; /* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXDestroyStreamOutput {
SVGA3dStreamOutputId soid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXDestroyStreamOutput; /* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetStreamOutput {
SVGA3dStreamOutputId soid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetStreamOutput; /* SVGA_3D_CMD_DX_SET_STREAMOUTPUT */
typedef
#include "vmware_pack_begin.h"
struct {
uint64 value;
uint32 mobId;
uint32 mobOffset;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXMobFence64; /* SVGA_3D_CMD_DX_MOB_FENCE_64 */
/*
* SVGA3dCmdSetCOTable --
*
* This command allows the guest to bind a mob to a context-object table.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXSetCOTable {
uint32 cid;
uint32 mobid;
SVGACOTableType type;
uint32 validSizeInBytes;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXSetCOTable; /* SVGA_3D_CMD_DX_SET_COTABLE */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXReadbackCOTable {
uint32 cid;
SVGACOTableType type;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXReadbackCOTable; /* SVGA_3D_CMD_DX_READBACK_COTABLE */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCOTableData {
uint32 mobid;
}
#include "vmware_pack_end.h"
SVGA3dCOTableData;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dBufferBinding {
uint32 bufferId;
uint32 stride;
uint32 offset;
}
#include "vmware_pack_end.h"
SVGA3dBufferBinding;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dConstantBufferBinding {
uint32 sid;
uint32 offsetInBytes;
uint32 sizeInBytes;
}
#include "vmware_pack_end.h"
SVGA3dConstantBufferBinding;
typedef
#include "vmware_pack_begin.h"
struct SVGADXInputAssemblyMobFormat {
uint32 layoutId;
SVGA3dBufferBinding vertexBuffers[SVGA3D_DX_MAX_VERTEXBUFFERS];
uint32 indexBufferSid;
uint32 pad;
uint32 indexBufferOffset;
uint32 indexBufferFormat;
uint32 topology;
}
#include "vmware_pack_end.h"
SVGADXInputAssemblyMobFormat;
typedef
#include "vmware_pack_begin.h"
struct SVGADXContextMobFormat {
SVGADXInputAssemblyMobFormat inputAssembly;
struct {
uint32 blendStateId;
uint32 blendFactor[4];
uint32 sampleMask;
uint32 depthStencilStateId;
uint32 stencilRef;
uint32 rasterizerStateId;
uint32 depthStencilViewId;
uint32 renderTargetViewIds[SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS];
uint32 unorderedAccessViewIds[SVGA3D_MAX_UAVIEWS];
} renderState;
struct {
uint32 targets[SVGA3D_DX_MAX_SOTARGETS];
uint32 soid;
} streamOut;
uint32 pad0[11];
uint8 numViewports;
uint8 numScissorRects;
uint16 pad1[1];
uint32 pad2[3];
SVGA3dViewport viewports[SVGA3D_DX_MAX_VIEWPORTS];
uint32 pad3[32];
SVGASignedRect scissorRects[SVGA3D_DX_MAX_SCISSORRECTS];
uint32 pad4[64];
struct {
uint32 queryID;
uint32 value;
} predication;
uint32 pad5[2];
struct {
uint32 shaderId;
SVGA3dConstantBufferBinding constantBuffers[SVGA3D_DX_MAX_CONSTBUFFERS];
uint32 shaderResources[SVGA3D_DX_MAX_SRVIEWS];
uint32 samplers[SVGA3D_DX_MAX_SAMPLERS];
} shaderState[SVGA3D_NUM_SHADERTYPE];
uint32 pad6[26];
SVGA3dQueryId queryID[SVGA3D_MAX_QUERY];
SVGA3dCOTableData cotables[SVGA_COTABLE_MAX];
uint32 pad7[381];
}
#include "vmware_pack_end.h"
SVGADXContextMobFormat;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDXTempSetContext {
uint32 dxcid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDXTempSetContext; /* SVGA_3D_CMD_DX_TEMP_SET_CONTEXT */
#endif /* _SVGA3D_DX_H_ */
drivers/gpu/drm/vmwgfx/device_include/svga3d_limits.h 0 → 100644
View file @ 8ce75f8a
/**********************************************************
* Copyright 2007-2015 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
/*
* svga3d_limits.h --
*
* SVGA 3d hardware limits
*/
#ifndef _SVGA3D_LIMITS_H_
#define _SVGA3D_LIMITS_H_
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#define INCLUDE_ALLOW_VMCORE
#include "includeCheck.h"
#define SVGA3D_NUM_CLIPPLANES 6
#define SVGA3D_MAX_RENDER_TARGETS 8
#define SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS (SVGA3D_MAX_RENDER_TARGETS)
#define SVGA3D_MAX_UAVIEWS 8
#define SVGA3D_MAX_CONTEXT_IDS 256
#define SVGA3D_MAX_SURFACE_IDS (32 * 1024)
/*
* Maximum ID a shader can be assigned on a given context.
*/
#define SVGA3D_MAX_SHADERIDS 5000
/*
* Maximum number of shaders of a given type that can be defined
* (including all contexts).
*/
#define SVGA3D_MAX_SIMULTANEOUS_SHADERS 20000
#define SVGA3D_NUM_TEXTURE_UNITS 32
#define SVGA3D_NUM_LIGHTS 8
/*
* Maximum size in dwords of shader text the SVGA device will allow.
* Currently 8 MB.
*/
#define SVGA3D_MAX_SHADER_MEMORY (8 * 1024 * 1024 / sizeof(uint32))
#define SVGA3D_MAX_CLIP_PLANES 6
/*
* This is the limit to the number of fixed-function texture
* transforms and texture coordinates we can support. It does *not*
* correspond to the number of texture image units (samplers) we
* support!
*/
#define SVGA3D_MAX_TEXTURE_COORDS 8
/*
* Number of faces in a cubemap.
*/
#define SVGA3D_MAX_SURFACE_FACES 6
/*
* Maximum number of array indexes in a GB surface (with DX enabled).
*/
#define SVGA3D_MAX_SURFACE_ARRAYSIZE 512
/*
* The maximum number of vertex arrays we're guaranteed to support in
* SVGA_3D_CMD_DRAWPRIMITIVES.
*/
#define SVGA3D_MAX_VERTEX_ARRAYS 32
/*
* The maximum number of primitive ranges we're guaranteed to support
* in SVGA_3D_CMD_DRAWPRIMITIVES.
*/
#define SVGA3D_MAX_DRAW_PRIMITIVE_RANGES 32
#endif /* _SVGA3D_LIMITS_H_ */
drivers/gpu/drm/vmwgfx/device_include/svga3d_reg.h 0 → 100644
View file @ 8ce75f8a
/**********************************************************
* Copyright 1998-2015 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
/*
* svga3d_reg.h --
*
* SVGA 3d hardware definitions
*/
#ifndef _SVGA3D_REG_H_
#define _SVGA3D_REG_H_
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#define INCLUDE_ALLOW_VMCORE
#include "includeCheck.h"
#include "svga_reg.h"
#include "svga3d_types.h"
#include "svga3d_limits.h"
#include "svga3d_cmd.h"
#include "svga3d_dx.h"
#include "svga3d_devcaps.h"
#endif /* _SVGA3D_REG_H_ */
drivers/gpu/drm/vmwgfx/svga3d_surfacedefs.h → drivers/gpu/drm/vmwgfx/device_include/svga3d_surfacedefs.h
View file @ 8ce75f8a
/**************************************************************************
*
* Copyright © 2008-2012 VMware, Inc., Palo Alto, CA., USA
* Copyright © 2008-2015 VMware, Inc., Palo Alto, CA., USA
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
......@@ -38,11 +38,8 @@
#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
#define max_t(type, x, y) ((x) > (y) ? (x) : (y))
#define min_t(type, x, y) ((x) < (y) ? (x) : (y))
#define surf_size_struct SVGA3dSize
#define u32 uint32
#define u64 uint64_t
#define U32_MAX ((u32)~0U)
#endif /* __KERNEL__ */
......@@ -174,541 +171,778 @@ enum svga3d_block_desc {
* 4. Bit depth of the pixel data.
* 5. Channel bit depths and masks (if applicable).
*/
#define SVGA3D_CHANNEL_DEF(type) \
struct { \
union { \
type blue; \
type u; \
type uv_video; \
type u_video; \
}; \
union { \
type green; \
type v; \
type stencil; \
type v_video; \
}; \
union { \
type red; \
type w; \
type luminance; \
type y; \
type depth; \
type data; \
}; \
union { \
type alpha; \
type q; \
type exp; \
}; \
}
struct svga3d_channel_def {
union {
u8 blue;
u8 u;
u8 uv_video;
u8 u_video;
};
union {
u8 green;
u8 v;
u8 stencil;
u8 v_video;
};
union {
u8 red;
u8 w;
u8 luminance;
u8 y;
u8 depth;
u8 data;
};
union {
u8 alpha;
u8 q;
u8 exp;
};
};
struct svga3d_surface_desc {
SVGA3dSurfaceFormat format;
enum svga3d_block_desc block_desc;
surf_size_struct block_size;
u32 bytes_per_block;
u32 pitch_bytes_per_block;
struct {
u32 total;
SVGA3D_CHANNEL_DEF(uint8);
} bit_depth;
struct {
SVGA3D_CHANNEL_DEF(uint8);
} bit_offset;
u32 total_bit_depth;
struct svga3d_channel_def bit_depth;
struct svga3d_channel_def bit_offset;
};
static const struct svga3d_surface_desc svga3d_surface_descs[] = {
{SVGA3DBLOCKDESC_NONE,
{1, 1, 1}, 0, 0, {0, {{0}, {0}, {0}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_FORMAT_INVALID */
{SVGA3DBLOCKDESC_RGB,
{1, 1, 1}, 4, 4, {24, {{8}, {8}, {8}, {0} } },
{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_X8R8G8B8 */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_A8R8G8B8 */
{SVGA3DBLOCKDESC_RGB,
{1, 1, 1}, 2, 2, {16, {{5}, {6}, {5}, {0} } },
{{{0}, {5}, {11}, {0} } } }, /* SVGA3D_R5G6B5 */
{SVGA3DBLOCKDESC_RGB,
{1, 1, 1}, 2, 2, {15, {{5}, {5}, {5}, {0} } },
{{{0}, {5}, {10}, {0} } } }, /* SVGA3D_X1R5G5B5 */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 2, 2, {16, {{5}, {5}, {5}, {1} } },
{{{0}, {5}, {10}, {15} } } }, /* SVGA3D_A1R5G5B5 */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 2, 2, {16, {{4}, {4}, {4}, {4} } },
{{{0}, {4}, {8}, {12} } } }, /* SVGA3D_A4R4G4B4 */
{SVGA3DBLOCKDESC_DEPTH,
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_Z_D32 */
{SVGA3DBLOCKDESC_DEPTH,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_Z_D16 */
{SVGA3DBLOCKDESC_DS,
{1, 1, 1}, 4, 4, {32, {{0}, {8}, {24}, {0} } },
{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_Z_D24S8 */
{SVGA3DBLOCKDESC_DS,
{1, 1, 1}, 2, 2, {16, {{0}, {1}, {15}, {0} } },
{{{0}, {15}, {0}, {0} } } }, /* SVGA3D_Z_D15S1 */
{SVGA3DBLOCKDESC_LUMINANCE,
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_LUMINANCE8 */
{SVGA3DBLOCKDESC_LA,
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {4}, {4} } },
{{{0}, {0}, {0}, {4} } } }, /* SVGA3D_LUMINANCE4_ALPHA4 */
{SVGA3DBLOCKDESC_LUMINANCE,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_LUMINANCE16 */
{SVGA3DBLOCKDESC_LA,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {8}, {8} } },
{{{0}, {0}, {0}, {8} } } }, /* SVGA3D_LUMINANCE8_ALPHA8 */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_DXT1 */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_DXT2 */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_DXT3 */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_DXT4 */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_DXT5 */
{SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {8}, {8} } },
{{{0}, {0}, {0}, {8} } } }, /* SVGA3D_BUMPU8V8 */
{SVGA3DBLOCKDESC_UVL,
{1, 1, 1}, 2, 2, {16, {{5}, {5}, {6}, {0} } },
{{{11}, {6}, {0}, {0} } } }, /* SVGA3D_BUMPL6V5U5 */
{SVGA3DBLOCKDESC_UVL,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {0} } },
{{{16}, {8}, {0}, {0} } } }, /* SVGA3D_BUMPX8L8V8U8 */
{SVGA3DBLOCKDESC_UVL,
{1, 1, 1}, 3, 3, {24, {{8}, {8}, {8}, {0} } },
{{{16}, {8}, {0}, {0} } } }, /* SVGA3D_BUMPL8V8U8 */
{SVGA3DBLOCKDESC_RGBA_FP,
{1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
{{{32}, {16}, {0}, {48} } } }, /* SVGA3D_ARGB_S10E5 */
{SVGA3DBLOCKDESC_RGBA_FP,
{1, 1, 1}, 16, 16, {128, {{32}, {32}, {32}, {32} } },
{{{64}, {32}, {0}, {96} } } }, /* SVGA3D_ARGB_S23E8 */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4, {32, {{10}, {10}, {10}, {2} } },
{{{0}, {10}, {20}, {30} } } }, /* SVGA3D_A2R10G10B10 */
{SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 2, 2, {16, {{8}, {8}, {0}, {0} } },
{{{8}, {0}, {0}, {0} } } }, /* SVGA3D_V8U8 */
{SVGA3DBLOCKDESC_UVWQ,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
{{{24}, {16}, {8}, {0} } } }, /* SVGA3D_Q8W8V8U8 */
{SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 2, 2, {16, {{8}, {8}, {0}, {0} } },
{{{8}, {0}, {0}, {0} } } }, /* SVGA3D_CxV8U8 */
{SVGA3DBLOCKDESC_UVL,
{1, 1, 1}, 4, 4, {24, {{8}, {8}, {8}, {0} } },
{{{16}, {8}, {0}, {0} } } }, /* SVGA3D_X8L8V8U8 */
{SVGA3DBLOCKDESC_UVWA,
{1, 1, 1}, 4, 4, {32, {{10}, {10}, {10}, {2} } },
{{{0}, {10}, {20}, {30} } } }, /* SVGA3D_A2W10V10U10 */
{SVGA3DBLOCKDESC_ALPHA,
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {0}, {8} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_ALPHA8 */
{SVGA3DBLOCKDESC_R_FP,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R_S10E5 */
{SVGA3DBLOCKDESC_R_FP,
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R_S23E8 */
{SVGA3DBLOCKDESC_RG_FP,
{1, 1, 1}, 4, 4, {32, {{0}, {16}, {16}, {0} } },
{{{0}, {16}, {0}, {0} } } }, /* SVGA3D_RG_S10E5 */
{SVGA3DBLOCKDESC_RG_FP,
{1, 1, 1}, 8, 8, {64, {{0}, {32}, {32}, {0} } },
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_RG_S23E8 */
{SVGA3DBLOCKDESC_BUFFER,
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BUFFER */
{SVGA3DBLOCKDESC_DEPTH,
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {24}, {0} } },
{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_Z_D24X8 */
{SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 4, 4, {32, {{16}, {16}, {0}, {0} } },
{{{16}, {0}, {0}, {0} } } }, /* SVGA3D_V16U16 */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 4, 4, {32, {{0}, {16}, {16}, {0} } },
{{{0}, {0}, {16}, {0} } } }, /* SVGA3D_G16R16 */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
{{{32}, {16}, {0}, {48} } } }, /* SVGA3D_A16B16G16R16 */
{SVGA3DBLOCKDESC_YUV,
{1, 1, 1}, 2, 2, {16, {{8}, {0}, {8}, {0} } },
{{{0}, {0}, {8}, {0} } } }, /* SVGA3D_UYVY */
{SVGA3DBLOCKDESC_YUV,
{1, 1, 1}, 2, 2, {16, {{8}, {0}, {8}, {0} } },
{{{8}, {0}, {0}, {0} } } }, /* SVGA3D_YUY2 */
{SVGA3DBLOCKDESC_NV12,
{2, 2, 1}, 6, 2, {48, {{0}, {0}, {48}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_NV12 */
{SVGA3DBLOCKDESC_AYUV,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_AYUV */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 16, 16, {128, {{32}, {32}, {32}, {32} } },
{{{64}, {32}, {0}, {96} } } }, /* SVGA3D_R32G32B32A32_TYPELESS */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 16, 16, {128, {{32}, {32}, {32}, {32} } },
{{{64}, {32}, {0}, {96} } } }, /* SVGA3D_R32G32B32A32_UINT */
{SVGA3DBLOCKDESC_UVWQ,
{1, 1, 1}, 16, 16, {128, {{32}, {32}, {32}, {32} } },
{{{64}, {32}, {0}, {96} } } }, /* SVGA3D_R32G32B32A32_SINT */
{SVGA3DBLOCKDESC_RGB,
{1, 1, 1}, 12, 12, {96, {{32}, {32}, {32}, {0} } },
{{{64}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32B32_TYPELESS */
{SVGA3DBLOCKDESC_RGB_FP,
{1, 1, 1}, 12, 12, {96, {{32}, {32}, {32}, {0} } },
{{{64}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32B32_FLOAT */
{SVGA3DBLOCKDESC_RGB,
{1, 1, 1}, 12, 12, {96, {{32}, {32}, {32}, {0} } },
{{{64}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32B32_UINT */
{SVGA3DBLOCKDESC_UVW,
{1, 1, 1}, 12, 12, {96, {{32}, {32}, {32}, {0} } },
{{{64}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32B32_SINT */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
{{{32}, {16}, {0}, {48} } } }, /* SVGA3D_R16G16B16A16_TYPELESS */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
{{{32}, {16}, {0}, {48} } } }, /* SVGA3D_R16G16B16A16_UINT */
{SVGA3DBLOCKDESC_UVWQ,
{1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
{{{32}, {16}, {0}, {48} } } }, /* SVGA3D_R16G16B16A16_SNORM */
{SVGA3DBLOCKDESC_UVWQ,
{1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
{{{32}, {16}, {0}, {48} } } }, /* SVGA3D_R16G16B16A16_SINT */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 8, 8, {64, {{0}, {32}, {32}, {0} } },
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32_TYPELESS */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 8, 8, {64, {{0}, {32}, {32}, {0} } },
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32_UINT */
{SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 8, 8, {64, {{0}, {32}, {32}, {0} } },
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32_SINT */
{SVGA3D_FORMAT_INVALID, SVGA3DBLOCKDESC_NONE,
{1, 1, 1}, 0, 0,
0, {{0}, {0}, {0}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_X8R8G8B8, SVGA3DBLOCKDESC_RGB,
{1, 1, 1}, 4, 4,
24, {{8}, {8}, {8}, {0}},
{{0}, {8}, {16}, {24}}},
{SVGA3D_A8R8G8B8, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4,
32, {{8}, {8}, {8}, {8}},
{{0}, {8}, {16}, {24}}},
{SVGA3D_R5G6B5, SVGA3DBLOCKDESC_RGB,
{1, 1, 1}, 2, 2,
16, {{5}, {6}, {5}, {0}},
{{0}, {5}, {11}, {0}}},
{SVGA3D_X1R5G5B5, SVGA3DBLOCKDESC_RGB,
{1, 1, 1}, 2, 2,
15, {{5}, {5}, {5}, {0}},
{{0}, {5}, {10}, {0}}},
{SVGA3D_A1R5G5B5, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 2, 2,
16, {{5}, {5}, {5}, {1}},
{{0}, {5}, {10}, {15}}},
{SVGA3D_A4R4G4B4, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 2, 2,
16, {{4}, {4}, {4}, {4}},
{{0}, {4}, {8}, {12}}},
{SVGA3D_Z_D32, SVGA3DBLOCKDESC_DEPTH,
{1, 1, 1}, 4, 4,
32, {{0}, {0}, {32}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_Z_D16, SVGA3DBLOCKDESC_DEPTH,
{1, 1, 1}, 2, 2,
16, {{0}, {0}, {16}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_Z_D24S8, SVGA3DBLOCKDESC_DS,
{1, 1, 1}, 4, 4,
32, {{0}, {8}, {24}, {0}},
{{0}, {24}, {0}, {0}}},
{SVGA3D_Z_D15S1, SVGA3DBLOCKDESC_DS,
{1, 1, 1}, 2, 2,
16, {{0}, {1}, {15}, {0}},
{{0}, {15}, {0}, {0}}},
{SVGA3D_LUMINANCE8, SVGA3DBLOCKDESC_LUMINANCE,
{1, 1, 1}, 1, 1,
8, {{0}, {0}, {8}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_LUMINANCE4_ALPHA4, SVGA3DBLOCKDESC_LA,
{1 , 1, 1}, 1, 1,
8, {{0}, {0}, {4}, {4}},
{{0}, {0}, {0}, {4}}},
{SVGA3D_LUMINANCE16, SVGA3DBLOCKDESC_LUMINANCE,
{1, 1, 1}, 2, 2,
16, {{0}, {0}, {16}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_LUMINANCE8_ALPHA8, SVGA3DBLOCKDESC_LA,
{1, 1, 1}, 2, 2,
16, {{0}, {0}, {8}, {8}},
{{0}, {0}, {0}, {8}}},
{SVGA3D_DXT1, SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 8, 8,
64, {{0}, {0}, {64}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_DXT2, SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16,
128, {{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_DXT3, SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16,
128, {{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_DXT4, SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16,
128, {{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_DXT5, SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16,
128, {{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_BUMPU8V8, SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 2, 2,
16, {{0}, {0}, {8}, {8}},
{{0}, {0}, {0}, {8}}},
{SVGA3D_BUMPL6V5U5, SVGA3DBLOCKDESC_UVL,
{1, 1, 1}, 2, 2,
16, {{5}, {5}, {6}, {0}},
{{11}, {6}, {0}, {0}}},
{SVGA3D_BUMPX8L8V8U8, SVGA3DBLOCKDESC_UVL,
{1, 1, 1}, 4, 4,
32, {{8}, {8}, {8}, {0}},
{{16}, {8}, {0}, {0}}},
{SVGA3D_BUMPL8V8U8, SVGA3DBLOCKDESC_UVL,
{1, 1, 1}, 3, 3,
24, {{8}, {8}, {8}, {0}},
{{16}, {8}, {0}, {0}}},
{SVGA3D_ARGB_S10E5, SVGA3DBLOCKDESC_RGBA_FP,
{1, 1, 1}, 8, 8,
64, {{16}, {16}, {16}, {16}},
{{32}, {16}, {0}, {48}}},
{SVGA3D_ARGB_S23E8, SVGA3DBLOCKDESC_RGBA_FP,
{1, 1, 1}, 16, 16,
128, {{32}, {32}, {32}, {32}},
{{64}, {32}, {0}, {96}}},
{SVGA3D_A2R10G10B10, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4,
32, {{10}, {10}, {10}, {2}},
{{0}, {10}, {20}, {30}}},
{SVGA3D_V8U8, SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 2, 2,
16, {{8}, {8}, {0}, {0}},
{{8}, {0}, {0}, {0}}},
{SVGA3D_Q8W8V8U8, SVGA3DBLOCKDESC_UVWQ,
{1, 1, 1}, 4, 4,
32, {{8}, {8}, {8}, {8}},
{{24}, {16}, {8}, {0}}},
{SVGA3D_CxV8U8, SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 2, 2,
16, {{8}, {8}, {0}, {0}},
{{8}, {0}, {0}, {0}}},
{SVGA3D_X8L8V8U8, SVGA3DBLOCKDESC_UVL,
{1, 1, 1}, 4, 4,
24, {{8}, {8}, {8}, {0}},
{{16}, {8}, {0}, {0}}},
{SVGA3D_A2W10V10U10, SVGA3DBLOCKDESC_UVWA,
{1, 1, 1}, 4, 4,
32, {{10}, {10}, {10}, {2}},
{{0}, {10}, {20}, {30}}},
{SVGA3D_ALPHA8, SVGA3DBLOCKDESC_ALPHA,
{1, 1, 1}, 1, 1,
8, {{0}, {0}, {0}, {8}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_R_S10E5, SVGA3DBLOCKDESC_R_FP,
{1, 1, 1}, 2, 2,
16, {{0}, {0}, {16}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_R_S23E8, SVGA3DBLOCKDESC_R_FP,
{1, 1, 1}, 4, 4,
32, {{0}, {0}, {32}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_RG_S10E5, SVGA3DBLOCKDESC_RG_FP,
{1, 1, 1}, 4, 4,
32, {{0}, {16}, {16}, {0}},
{{0}, {16}, {0}, {0}}},
{SVGA3D_RG_S23E8, SVGA3DBLOCKDESC_RG_FP,
{1, 1, 1}, 8, 8,
64, {{0}, {32}, {32}, {0}},
{{0}, {32}, {0}, {0}}},
{SVGA3D_BUFFER, SVGA3DBLOCKDESC_BUFFER,
{1, 1, 1}, 1, 1,
8, {{0}, {0}, {8}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_Z_D24X8, SVGA3DBLOCKDESC_DEPTH,
{1, 1, 1}, 4, 4,
32, {{0}, {0}, {24}, {0}},
{{0}, {24}, {0}, {0}}},
{SVGA3D_V16U16, SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 4, 4,
32, {{16}, {16}, {0}, {0}},
{{16}, {0}, {0}, {0}}},
{SVGA3D_G16R16, SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 4, 4,
32, {{0}, {16}, {16}, {0}},
{{0}, {0}, {16}, {0}}},
{SVGA3D_A16B16G16R16, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 8, 8,
64, {{16}, {16}, {16}, {16}},
{{32}, {16}, {0}, {48}}},
{SVGA3D_UYVY, SVGA3DBLOCKDESC_YUV,
{1, 1, 1}, 2, 2,
16, {{8}, {0}, {8}, {0}},
{{0}, {0}, {8}, {0}}},
{SVGA3D_YUY2, SVGA3DBLOCKDESC_YUV,
{1, 1, 1}, 2, 2,
16, {{8}, {0}, {8}, {0}},
{{8}, {0}, {0}, {0}}},
{SVGA3D_NV12, SVGA3DBLOCKDESC_NV12,
{2, 2, 1}, 6, 2,
48, {{0}, {0}, {48}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_AYUV, SVGA3DBLOCKDESC_AYUV,
{1, 1, 1}, 4, 4,
32, {{8}, {8}, {8}, {8}},
{{0}, {8}, {16}, {24}}},
{SVGA3D_R32G32B32A32_TYPELESS, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 16, 16,
128, {{32}, {32}, {32}, {32}},
{{64}, {32}, {0}, {96}}},
{SVGA3D_R32G32B32A32_UINT, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 16, 16,
128, {{32}, {32}, {32}, {32}},
{{64}, {32}, {0}, {96}}},
{SVGA3D_R32G32B32A32_SINT, SVGA3DBLOCKDESC_UVWQ,
{1, 1, 1}, 16, 16,
128, {{32}, {32}, {32}, {32}},
{{64}, {32}, {0}, {96}}},
{SVGA3D_R32G32B32_TYPELESS, SVGA3DBLOCKDESC_RGB,
{1, 1, 1}, 12, 12,
96, {{32}, {32}, {32}, {0}},
{{64}, {32}, {0}, {0}}},
{SVGA3D_R32G32B32_FLOAT, SVGA3DBLOCKDESC_RGB_FP,
{1, 1, 1}, 12, 12,
96, {{32}, {32}, {32}, {0}},
{{64}, {32}, {0}, {0}}},
{SVGA3D_R32G32B32_UINT, SVGA3DBLOCKDESC_RGB,
{1, 1, 1}, 12, 12,
96, {{32}, {32}, {32}, {0}},
{{64}, {32}, {0}, {0}}},
{SVGA3D_R32G32B32_SINT, SVGA3DBLOCKDESC_UVW,
{1, 1, 1}, 12, 12,
96, {{32}, {32}, {32}, {0}},
{{64}, {32}, {0}, {0}}},
{SVGA3D_R16G16B16A16_TYPELESS, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 8, 8,
64, {{16}, {16}, {16}, {16}},
{{32}, {16}, {0}, {48}}},
{SVGA3D_R16G16B16A16_UINT, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 8, 8,
64, {{16}, {16}, {16}, {16}},
{{32}, {16}, {0}, {48}}},
{SVGA3D_R16G16B16A16_SNORM, SVGA3DBLOCKDESC_UVWQ,
{1, 1, 1}, 8, 8,
64, {{16}, {16}, {16}, {16}},
{{32}, {16}, {0}, {48}}},
{SVGA3D_R16G16B16A16_SINT, SVGA3DBLOCKDESC_UVWQ,
{1, 1, 1}, 8, 8,
64, {{16}, {16}, {16}, {16}},
{{32}, {16}, {0}, {48}}},
{SVGA3D_R32G32_TYPELESS, SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 8, 8,
64, {{0}, {32}, {32}, {0}},
{{0}, {32}, {0}, {0}}},
{SVGA3D_R32G32_UINT, SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 8, 8,
64, {{0}, {32}, {32}, {0}},
{{0}, {32}, {0}, {0}}},
{SVGA3D_R32G32_SINT, SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 8, 8,
64, {{0}, {32}, {32}, {0}},
{{0}, {32}, {0}, {0}}},
{SVGA3D_R32G8X24_TYPELESS, SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 8, 8,
64, {{0}, {8}, {32}, {0}},
{{0}, {32}, {0}, {0}}},
{SVGA3D_D32_FLOAT_S8X24_UINT, SVGA3DBLOCKDESC_DS,
{1, 1, 1}, 8, 8,
64, {{0}, {8}, {32}, {0}},
{{0}, {32}, {0}, {0}}},
{SVGA3D_R32_FLOAT_X8X24_TYPELESS, SVGA3DBLOCKDESC_R_FP,
{1, 1, 1}, 8, 8,
64, {{0}, {0}, {32}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_X32_TYPELESS_G8X24_UINT, SVGA3DBLOCKDESC_GREEN,
{1, 1, 1}, 8, 8,
64, {{0}, {8}, {0}, {0}},
{{0}, {32}, {0}, {0}}},
{SVGA3D_R10G10B10A2_TYPELESS, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4,
32, {{10}, {10}, {10}, {2}},
{{0}, {10}, {20}, {30}}},
{SVGA3D_R10G10B10A2_UINT, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4,
32, {{10}, {10}, {10}, {2}},
{{0}, {10}, {20}, {30}}},
{SVGA3D_R11G11B10_FLOAT, SVGA3DBLOCKDESC_RGB_FP,
{1, 1, 1}, 4, 4,
32, {{10}, {11}, {11}, {0}},
{{0}, {10}, {21}, {0}}},
{SVGA3D_R8G8B8A8_TYPELESS, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4,
32, {{8}, {8}, {8}, {8}},
{{16}, {8}, {0}, {24}}},
{SVGA3D_R8G8B8A8_UNORM, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4,
32, {{8}, {8}, {8}, {8}},
{{16}, {8}, {0}, {24}}},
{SVGA3D_R8G8B8A8_UNORM_SRGB, SVGA3DBLOCKDESC_RGBA_SRGB,
{1, 1, 1}, 4, 4,
32, {{8}, {8}, {8}, {8}},
{{16}, {8}, {0}, {24}}},
{SVGA3D_R8G8B8A8_UINT, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4,
32, {{8}, {8}, {8}, {8}},
{{16}, {8}, {0}, {24}}},
{SVGA3D_R8G8B8A8_SINT, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4,
32, {{8}, {8}, {8}, {8}},
{{16}, {8}, {0}, {24}}},
{SVGA3D_R16G16_TYPELESS, SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 4, 4,
32, {{0}, {16}, {16}, {0}},
{{0}, {16}, {0}, {0}}},
{SVGA3D_R16G16_UINT, SVGA3DBLOCKDESC_RG_FP,
{1, 1, 1}, 4, 4,
32, {{0}, {16}, {16}, {0}},
{{0}, {16}, {0}, {0}}},
{SVGA3D_R16G16_SINT, SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 4, 4,
32, {{0}, {16}, {16}, {0}},
{{0}, {16}, {0}, {0}}},
{SVGA3D_R32_TYPELESS, SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 4, 4,
32, {{0}, {0}, {32}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_D32_FLOAT, SVGA3DBLOCKDESC_DEPTH,
{1, 1, 1}, 4, 4,
32, {{0}, {0}, {32}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_R32_UINT, SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 4, 4,
32, {{0}, {0}, {32}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_R32_SINT, SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 4, 4,
32, {{0}, {0}, {32}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_R24G8_TYPELESS, SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 4, 4,
32, {{0}, {8}, {24}, {0}},
{{0}, {24}, {0}, {0}}},
{SVGA3D_D24_UNORM_S8_UINT, SVGA3DBLOCKDESC_DS,
{1, 1, 1}, 4, 4,
32, {{0}, {8}, {24}, {0}},
{{0}, {24}, {0}, {0}}},
{SVGA3D_R24_UNORM_X8_TYPELESS, SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 4, 4,
32, {{0}, {0}, {24}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_X24_TYPELESS_G8_UINT, SVGA3DBLOCKDESC_GREEN,
{1, 1, 1}, 4, 4,
32, {{0}, {8}, {0}, {0}},
{{0}, {24}, {0}, {0}}},
{SVGA3D_R8G8_TYPELESS, SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 2, 2,
16, {{0}, {8}, {8}, {0}},
{{0}, {8}, {0}, {0}}},
{SVGA3D_R8G8_UNORM, SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 2, 2,
16, {{0}, {8}, {8}, {0}},
{{0}, {8}, {0}, {0}}},
{SVGA3D_R8G8_UINT, SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 2, 2,
16, {{0}, {8}, {8}, {0}},
{{0}, {8}, {0}, {0}}},
{SVGA3D_R8G8_SINT, SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 2, 2,
16, {{0}, {8}, {8}, {0}},
{{0}, {8}, {0}, {0}}},
{SVGA3D_R16_TYPELESS, SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 2, 2,
16, {{0}, {0}, {16}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_R16_UNORM, SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 2, 2,
16, {{0}, {0}, {16}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_R16_UINT, SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 2, 2,
16, {{0}, {0}, {16}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_R16_SNORM, SVGA3DBLOCKDESC_U,
{1, 1, 1}, 2, 2,
16, {{0}, {0}, {16}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_R16_SINT, SVGA3DBLOCKDESC_U,
{1, 1, 1}, 2, 2,
16, {{0}, {0}, {16}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_R8_TYPELESS, SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 1, 1,
8, {{0}, {0}, {8}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_R8_UNORM, SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 1, 1,
8, {{0}, {0}, {8}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_R8_UINT, SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 1, 1,
8, {{0}, {0}, {8}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_R8_SNORM, SVGA3DBLOCKDESC_U,
{1, 1, 1}, 1, 1,
8, {{0}, {0}, {8}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_R8_SINT, SVGA3DBLOCKDESC_U,
{1, 1, 1}, 1, 1,
8, {{0}, {0}, {8}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_P8, SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 1, 1,
8, {{0}, {0}, {8}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_R9G9B9E5_SHAREDEXP, SVGA3DBLOCKDESC_RGBE,
{1, 1, 1}, 4, 4,
32, {{9}, {9}, {9}, {5}},
{{18}, {9}, {0}, {27}}},
{SVGA3D_R8G8_B8G8_UNORM, SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 2, 2,
16, {{0}, {8}, {8}, {0}},
{{0}, {8}, {0}, {0}}},
{SVGA3D_G8R8_G8B8_UNORM, SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 2, 2,
16, {{0}, {8}, {8}, {0}},
{{0}, {8}, {0}, {0}}},
{SVGA3D_BC1_TYPELESS, SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 8, 8,
64, {{0}, {0}, {64}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_BC1_UNORM_SRGB, SVGA3DBLOCKDESC_COMPRESSED_SRGB,
{4, 4, 1}, 8, 8,
64, {{0}, {0}, {64}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_BC2_TYPELESS, SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16,
128, {{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_BC2_UNORM_SRGB, SVGA3DBLOCKDESC_COMPRESSED_SRGB,
{4, 4, 1}, 16, 16,
128, {{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_BC3_TYPELESS, SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16,
128, {{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_BC3_UNORM_SRGB, SVGA3DBLOCKDESC_COMPRESSED_SRGB,
{4, 4, 1}, 16, 16,
128, {{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_BC4_TYPELESS, SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 8, 8,
64, {{0}, {0}, {64}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_ATI1, SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 8, 8,
64, {{0}, {0}, {64}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_BC4_SNORM, SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 8, 8,
64, {{0}, {0}, {64}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_BC5_TYPELESS, SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16,
128, {{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_ATI2, SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16,
128, {{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_BC5_SNORM, SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16,
128, {{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_R10G10B10_XR_BIAS_A2_UNORM, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4,
32, {{10}, {10}, {10}, {2}},
{{0}, {10}, {20}, {30}}},
{SVGA3D_B8G8R8A8_TYPELESS, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4,
32, {{8}, {8}, {8}, {8}},
{{0}, {8}, {16}, {24}}},
{SVGA3D_B8G8R8A8_UNORM_SRGB, SVGA3DBLOCKDESC_RGBA_SRGB,
{1, 1, 1}, 4, 4,
32, {{8}, {8}, {8}, {8}},
{{0}, {8}, {16}, {24}}},
{SVGA3D_B8G8R8X8_TYPELESS, SVGA3DBLOCKDESC_RGB,
{1, 1, 1}, 4, 4,
24, {{8}, {8}, {8}, {0}},
{{0}, {8}, {16}, {24}}},
{SVGA3D_B8G8R8X8_UNORM_SRGB, SVGA3DBLOCKDESC_RGB_SRGB,
{1, 1, 1}, 4, 4,
24, {{8}, {8}, {8}, {0}},
{{0}, {8}, {16}, {24}}},
{SVGA3D_Z_DF16, SVGA3DBLOCKDESC_DEPTH,
{1, 1, 1}, 2, 2,
16, {{0}, {0}, {16}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_Z_DF24, SVGA3DBLOCKDESC_DEPTH,
{1, 1, 1}, 4, 4,
32, {{0}, {8}, {24}, {0}},
{{0}, {24}, {0}, {0}}},
{SVGA3D_Z_D24S8_INT, SVGA3DBLOCKDESC_DS,
{1, 1, 1}, 4, 4,
32, {{0}, {8}, {24}, {0}},
{{0}, {24}, {0}, {0}}},
{SVGA3D_YV12, SVGA3DBLOCKDESC_YV12,
{2, 2, 1}, 6, 2,
48, {{0}, {0}, {48}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_R32G32B32A32_FLOAT, SVGA3DBLOCKDESC_RGBA_FP,
{1, 1, 1}, 16, 16,
128, {{32}, {32}, {32}, {32}},
{{64}, {32}, {0}, {96}}},
{SVGA3D_R16G16B16A16_FLOAT, SVGA3DBLOCKDESC_RGBA_FP,
{1, 1, 1}, 8, 8,
64, {{16}, {16}, {16}, {16}},
{{32}, {16}, {0}, {48}}},
{SVGA3D_R16G16B16A16_UNORM, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 8, 8,
64, {{16}, {16}, {16}, {16}},
{{32}, {16}, {0}, {48}}},
{SVGA3D_R32G32_FLOAT, SVGA3DBLOCKDESC_RG_FP,
{1, 1, 1}, 8, 8,
64, {{0}, {32}, {32}, {0}},
{{0}, {32}, {0}, {0}}},
{SVGA3D_R10G10B10A2_UNORM, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4,
32, {{10}, {10}, {10}, {2}},
{{0}, {10}, {20}, {30}}},
{SVGA3D_R8G8B8A8_SNORM, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4,
32, {{8}, {8}, {8}, {8}},
{{24}, {16}, {8}, {0}}},
{SVGA3D_R16G16_FLOAT, SVGA3DBLOCKDESC_RG_FP,
{1, 1, 1}, 4, 4,
32, {{0}, {16}, {16}, {0}},
{{0}, {16}, {0}, {0}}},
{SVGA3D_R16G16_UNORM, SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 4, 4,
32, {{0}, {16}, {16}, {0}},
{{0}, {0}, {16}, {0}}},
{SVGA3D_R16G16_SNORM, SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 4, 4,
32, {{16}, {16}, {0}, {0}},
{{16}, {0}, {0}, {0}}},
{SVGA3D_R32_FLOAT, SVGA3DBLOCKDESC_R_FP,
{1, 1, 1}, 4, 4,
32, {{0}, {0}, {32}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_R8G8_SNORM, SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 2, 2,
16, {{8}, {8}, {0}, {0}},
{{8}, {0}, {0}, {0}}},
{SVGA3D_R16_FLOAT, SVGA3DBLOCKDESC_R_FP,
{1, 1, 1}, 2, 2,
16, {{0}, {0}, {16}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_D16_UNORM, SVGA3DBLOCKDESC_DEPTH,
{1, 1, 1}, 2, 2,
16, {{0}, {0}, {16}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_A8_UNORM, SVGA3DBLOCKDESC_ALPHA,
{1, 1, 1}, 1, 1,
8, {{0}, {0}, {0}, {8}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_BC1_UNORM, SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 8, 8,
64, {{0}, {0}, {64}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_BC2_UNORM, SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16,
128, {{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_BC3_UNORM, SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16,
128, {{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_B5G6R5_UNORM, SVGA3DBLOCKDESC_RGB,
{1, 1, 1}, 2, 2,
16, {{5}, {6}, {5}, {0}},
{{0}, {5}, {11}, {0}}},
{SVGA3D_B5G5R5A1_UNORM, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 2, 2,
16, {{5}, {5}, {5}, {1}},
{{0}, {5}, {10}, {15}}},
{SVGA3D_B8G8R8A8_UNORM, SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4,
32, {{8}, {8}, {8}, {8}},
{{0}, {8}, {16}, {24}}},
{SVGA3D_B8G8R8X8_UNORM, SVGA3DBLOCKDESC_RGB,
{1, 1, 1}, 4, 4,
24, {{8}, {8}, {8}, {0}},
{{0}, {8}, {16}, {24}}},
{SVGA3D_BC4_UNORM, SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 8, 8,
64, {{0}, {0}, {64}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3D_BC5_UNORM, SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16,
128, {{0}, {0}, {128}, {0}},
{{0}, {0}, {0}, {0}}},
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 8, 8, {64, {{0}, {8}, {32}, {0} } },
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_R32G8X24_TYPELESS */
{SVGA3DBLOCKDESC_DS,
{1, 1, 1}, 8, 8, {64, {{0}, {8}, {32}, {0} } },
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_D32_FLOAT_S8X24_UINT */
{SVGA3DBLOCKDESC_R_FP,
{1, 1, 1}, 8, 8, {64, {{0}, {0}, {32}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R32_FLOAT_X8_X24_TYPELESS */
{SVGA3DBLOCKDESC_GREEN,
{1, 1, 1}, 8, 8, {64, {{0}, {8}, {0}, {0} } },
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_X32_TYPELESS_G8X24_UINT */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4, {32, {{10}, {10}, {10}, {2} } },
{{{0}, {10}, {20}, {30} } } }, /* SVGA3D_R10G10B10A2_TYPELESS */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4, {32, {{10}, {10}, {10}, {2} } },
{{{0}, {10}, {20}, {30} } } }, /* SVGA3D_R10G10B10A2_UINT */
{SVGA3DBLOCKDESC_RGB_FP,
{1, 1, 1}, 4, 4, {32, {{10}, {11}, {11}, {0} } },
{{{0}, {10}, {21}, {0} } } }, /* SVGA3D_R11G11B10_FLOAT */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
{{{16}, {8}, {0}, {24} } } }, /* SVGA3D_R8G8B8A8_TYPELESS */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
{{{16}, {8}, {0}, {24} } } }, /* SVGA3D_R8G8B8A8_UNORM */
{SVGA3DBLOCKDESC_RGBA_SRGB,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
{{{16}, {8}, {0}, {24} } } }, /* SVGA3D_R8G8B8A8_UNORM_SRGB */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
{{{16}, {8}, {0}, {24} } } }, /* SVGA3D_R8G8B8A8_UINT */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
{{{16}, {8}, {0}, {24} } } }, /* SVGA3D_R8G8B8A8_SINT */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 4, 4, {32, {{0}, {16}, {16}, {0} } },
{{{0}, {16}, {0}, {0} } } }, /* SVGA3D_R16G16_TYPELESS */
{SVGA3DBLOCKDESC_RG_FP,
{1, 1, 1}, 4, 4, {32, {{0}, {16}, {16}, {0} } },
{{{0}, {16}, {0}, {0} } } }, /* SVGA3D_R16G16_UINT */
{SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 4, 4, {32, {{0}, {16}, {16}, {0} } },
{{{0}, {16}, {0}, {0} } } }, /* SVGA3D_R16G16_SINT */
{SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R32_TYPELESS */
{SVGA3DBLOCKDESC_DEPTH,
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_D32_FLOAT */
{SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R32_UINT */
{SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R32_SINT */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 4, 4, {32, {{0}, {8}, {24}, {0} } },
{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_R24G8_TYPELESS */
{SVGA3DBLOCKDESC_DS,
{1, 1, 1}, 4, 4, {32, {{0}, {8}, {24}, {0} } },
{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_D24_UNORM_S8_UINT */
{SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {24}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R24_UNORM_X8_TYPELESS */
{SVGA3DBLOCKDESC_GREEN,
{1, 1, 1}, 4, 4, {32, {{0}, {8}, {0}, {0} } },
{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_X24_TYPELESS_G8_UINT */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
{{{0}, {8}, {0}, {0} } } }, /* SVGA3D_R8G8_TYPELESS */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
{{{0}, {8}, {0}, {0} } } }, /* SVGA3D_R8G8_UNORM */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
{{{0}, {8}, {0}, {0} } } }, /* SVGA3D_R8G8_UINT */
{SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
{{{0}, {8}, {0}, {0} } } }, /* SVGA3D_R8G8_SINT */
{SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R16_TYPELESS */
{SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R16_UNORM */
{SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R16_UINT */
{SVGA3DBLOCKDESC_U,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R16_SNORM */
{SVGA3DBLOCKDESC_U,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R16_SINT */
{SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R8_TYPELESS */
{SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R8_UNORM */
{SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R8_UINT */
{SVGA3DBLOCKDESC_U,
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R8_SNORM */
{SVGA3DBLOCKDESC_U,
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R8_SINT */
{SVGA3DBLOCKDESC_NONE,
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_P8 */
{SVGA3DBLOCKDESC_RGBE,
{1, 1, 1}, 4, 4, {32, {{9}, {9}, {9}, {5} } },
{{{18}, {9}, {0}, {27} } } }, /* SVGA3D_R9G9B9E5_SHAREDEXP */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
{{{0}, {8}, {0}, {0} } } }, /* SVGA3D_R8G8_B8G8_UNORM */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
{{{0}, {8}, {0}, {0} } } }, /* SVGA3D_G8R8_G8B8_UNORM */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC1_TYPELESS */
{SVGA3DBLOCKDESC_COMPRESSED_SRGB,
{4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC1_UNORM_SRGB */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC2_TYPELESS */
{SVGA3DBLOCKDESC_COMPRESSED_SRGB,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC2_UNORM_SRGB */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC3_TYPELESS */
{SVGA3DBLOCKDESC_COMPRESSED_SRGB,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC3_UNORM_SRGB */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC4_TYPELESS */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC4_UNORM */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC4_SNORM */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC5_TYPELESS */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC5_UNORM */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC5_SNORM */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4, {32, {{10}, {10}, {10}, {2} } },
{{{0}, {10}, {20}, {30} } } }, /* SVGA3D_R10G10B10_XR_BIAS_A2_UNORM */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_B8G8R8A8_TYPELESS */
{SVGA3DBLOCKDESC_RGBA_SRGB,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_B8G8R8A8_UNORM_SRGB */
{SVGA3DBLOCKDESC_RGB,
{1, 1, 1}, 4, 4, {24, {{8}, {8}, {8}, {0} } },
{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_B8G8R8X8_TYPELESS */
{SVGA3DBLOCKDESC_RGB_SRGB,
{1, 1, 1}, 4, 4, {24, {{8}, {8}, {8}, {0} } },
{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_B8G8R8X8_UNORM_SRGB */
{SVGA3DBLOCKDESC_DEPTH,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_Z_DF16 */
{SVGA3DBLOCKDESC_DS,
{1, 1, 1}, 4, 4, {32, {{0}, {8}, {24}, {0} } },
{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_Z_DF24 */
{SVGA3DBLOCKDESC_DS,
{1, 1, 1}, 4, 4, {32, {{0}, {8}, {24}, {0} } },
{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_Z_D24S8_INT */
};
static inline u32 clamped_umul32(u32 a, u32 b)
{
u64 tmp = (u64) a*b;
return (tmp > (u64) U32_MAX) ? U32_MAX : tmp;
uint64_t tmp = (uint64_t) a*b;
return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp;
}
static inline const struct svga3d_surface_desc *
......@@ -834,10 +1068,10 @@ static inline u32
svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format,
surf_size_struct base_level_size,
u32 num_mip_levels,
bool cubemap)
u32 num_layers)
{
const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format);
u64 total_size = 0;
u32 total_size = 0;
u32 mip;
for (mip = 0; mip < num_mip_levels; mip++) {
......@@ -847,10 +1081,7 @@ svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format,
&size, 0);
}
if (cubemap)
total_size *= SVGA3D_MAX_SURFACE_FACES;
return (u32) min_t(u64, total_size, (u64) U32_MAX);
return total_size * num_layers;
}
......
drivers/gpu/drm/vmwgfx/svga3d_reg.h → drivers/gpu/drm/vmwgfx/device_include/svga3d_types.h
View file @ 8ce75f8a
/**********************************************************
* Copyright 1998-2014 VMware, Inc. All rights reserved.
* Copyright 2012-2015 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
......@@ -24,72 +24,101 @@
**********************************************************/
/*
* svga3d_reg.h --
* svga3d_types.h --
*
* SVGA 3D hardware definitions
* SVGA 3d hardware definitions for basic types
*/
#ifndef _SVGA3D_REG_H_
#define _SVGA3D_REG_H_
#ifndef _SVGA3D_TYPES_H_
#define _SVGA3D_TYPES_H_
#include "svga_reg.h"
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#define INCLUDE_ALLOW_VMCORE
typedef uint32 PPN;
typedef u64 PPN64;
#include "includeCheck.h"
/*
* 3D Hardware Version
*
* The hardware version is stored in the SVGA_FIFO_3D_HWVERSION fifo
* register. Is set by the host and read by the guest. This lets
* us make new guest drivers which are backwards-compatible with old
* SVGA hardware revisions. It does not let us support old guest
* drivers. Good enough for now.
*
* Generic Types
*/
#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16)
#define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF)
#define SVGA3D_INVALID_ID ((uint32)-1)
typedef enum {
SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1),
SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2),
SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3),
SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1),
SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4),
SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0),
SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1),
SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1,
} SVGA3dHardwareVersion;
typedef uint32 SVGA3dBool; /* 32-bit Bool definition */
typedef uint32 SVGA3dColor; /* a, r, g, b */
/*
* Generic Types
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCopyRect {
uint32 x;
uint32 y;
uint32 w;
uint32 h;
uint32 srcx;
uint32 srcy;
}
#include "vmware_pack_end.h"
SVGA3dCopyRect;
typedef uint32 SVGA3dBool; /* 32-bit Bool definition */
#define SVGA3D_NUM_CLIPPLANES 6
#define SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS 8
#define SVGA3D_MAX_CONTEXT_IDS 256
#define SVGA3D_MAX_SURFACE_IDS (32 * 1024)
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCopyBox {
uint32 x;
uint32 y;
uint32 z;
uint32 w;
uint32 h;
uint32 d;
uint32 srcx;
uint32 srcy;
uint32 srcz;
}
#include "vmware_pack_end.h"
SVGA3dCopyBox;
#define SVGA3D_NUM_TEXTURE_UNITS 32
#define SVGA3D_NUM_LIGHTS 8
typedef
#include "vmware_pack_begin.h"
struct SVGA3dRect {
uint32 x;
uint32 y;
uint32 w;
uint32 h;
}
#include "vmware_pack_end.h"
SVGA3dRect;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 x;
uint32 y;
uint32 z;
uint32 w;
uint32 h;
uint32 d;
}
#include "vmware_pack_end.h"
SVGA3dBox;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 x;
uint32 y;
uint32 z;
}
#include "vmware_pack_end.h"
SVGA3dPoint;
/*
* Surface formats.
*
* If you modify this list, be sure to keep GLUtil.c in sync. It
* includes the internal format definition of each surface in
* GLUtil_ConvertSurfaceFormat, and it contains a table of
* human-readable names in GLUtil_GetFormatName.
*/
typedef enum SVGA3dSurfaceFormat {
SVGA3D_FORMAT_MIN = 0,
SVGA3D_FORMAT_INVALID = 0,
SVGA3D_X8R8G8B8 = 1,
SVGA3D_FORMAT_MIN = 1,
SVGA3D_A8R8G8B8 = 2,
SVGA3D_R5G6B5 = 3,
......@@ -160,7 +189,6 @@ typedef enum SVGA3dSurfaceFormat {
SVGA3D_AYUV = 45,
SVGA3D_R32G32B32A32_TYPELESS = 46,
SVGA3D_R32G32B32A32_FLOAT = 25,
SVGA3D_R32G32B32A32_UINT = 47,
SVGA3D_R32G32B32A32_SINT = 48,
SVGA3D_R32G32B32_TYPELESS = 49,
......@@ -168,13 +196,10 @@ typedef enum SVGA3dSurfaceFormat {
SVGA3D_R32G32B32_UINT = 51,
SVGA3D_R32G32B32_SINT = 52,
SVGA3D_R16G16B16A16_TYPELESS = 53,
SVGA3D_R16G16B16A16_FLOAT = 24,
SVGA3D_R16G16B16A16_UNORM = 41,
SVGA3D_R16G16B16A16_UINT = 54,
SVGA3D_R16G16B16A16_SNORM = 55,
SVGA3D_R16G16B16A16_SINT = 56,
SVGA3D_R32G32_TYPELESS = 57,
SVGA3D_R32G32_FLOAT = 36,
SVGA3D_R32G32_UINT = 58,
SVGA3D_R32G32_SINT = 59,
SVGA3D_R32G8X24_TYPELESS = 60,
......@@ -182,24 +207,18 @@ typedef enum SVGA3dSurfaceFormat {
SVGA3D_R32_FLOAT_X8X24_TYPELESS = 62,
SVGA3D_X32_TYPELESS_G8X24_UINT = 63,
SVGA3D_R10G10B10A2_TYPELESS = 64,
SVGA3D_R10G10B10A2_UNORM = 26,
SVGA3D_R10G10B10A2_UINT = 65,
SVGA3D_R11G11B10_FLOAT = 66,
SVGA3D_R8G8B8A8_TYPELESS = 67,
SVGA3D_R8G8B8A8_UNORM = 68,
SVGA3D_R8G8B8A8_UNORM_SRGB = 69,
SVGA3D_R8G8B8A8_UINT = 70,
SVGA3D_R8G8B8A8_SNORM = 28,
SVGA3D_R8G8B8A8_SINT = 71,
SVGA3D_R16G16_TYPELESS = 72,
SVGA3D_R16G16_FLOAT = 35,
SVGA3D_R16G16_UNORM = 40,
SVGA3D_R16G16_UINT = 73,
SVGA3D_R16G16_SNORM = 39,
SVGA3D_R16G16_SINT = 74,
SVGA3D_R32_TYPELESS = 75,
SVGA3D_D32_FLOAT = 76,
SVGA3D_R32_FLOAT = 34,
SVGA3D_R32_UINT = 77,
SVGA3D_R32_SINT = 78,
SVGA3D_R24G8_TYPELESS = 79,
......@@ -209,11 +228,8 @@ typedef enum SVGA3dSurfaceFormat {
SVGA3D_R8G8_TYPELESS = 83,
SVGA3D_R8G8_UNORM = 84,
SVGA3D_R8G8_UINT = 85,
SVGA3D_R8G8_SNORM = 27,
SVGA3D_R8G8_SINT = 86,
SVGA3D_R16_TYPELESS = 87,
SVGA3D_R16_FLOAT = 33,
SVGA3D_D16_UNORM = 8,
SVGA3D_R16_UNORM = 88,
SVGA3D_R16_UINT = 89,
SVGA3D_R16_SNORM = 90,
......@@ -223,37 +239,29 @@ typedef enum SVGA3dSurfaceFormat {
SVGA3D_R8_UINT = 94,
SVGA3D_R8_SNORM = 95,
SVGA3D_R8_SINT = 96,
SVGA3D_A8_UNORM = 32,
SVGA3D_P8 = 97,
SVGA3D_R9G9B9E5_SHAREDEXP = 98,
SVGA3D_R8G8_B8G8_UNORM = 99,
SVGA3D_G8R8_G8B8_UNORM = 100,
SVGA3D_BC1_TYPELESS = 101,
SVGA3D_BC1_UNORM = 15,
SVGA3D_BC1_UNORM_SRGB = 102,
SVGA3D_BC2_TYPELESS = 103,
SVGA3D_BC2_UNORM = 17,
SVGA3D_BC2_UNORM_SRGB = 104,
SVGA3D_BC3_TYPELESS = 105,
SVGA3D_BC3_UNORM = 19,
SVGA3D_BC3_UNORM_SRGB = 106,
SVGA3D_BC4_TYPELESS = 107,
SVGA3D_BC4_UNORM = 108,
SVGA3D_ATI1 = 108, /* DX9-specific BC4_UNORM */
SVGA3D_BC4_SNORM = 109,
SVGA3D_BC5_TYPELESS = 110,
SVGA3D_BC5_UNORM = 111,
SVGA3D_ATI2 = 111, /* DX9-specific BC5_UNORM */
SVGA3D_BC5_SNORM = 112,
SVGA3D_B5G6R5_UNORM = 3,
SVGA3D_B5G5R5A1_UNORM = 5,
SVGA3D_B8G8R8A8_UNORM = 2,
SVGA3D_B8G8R8X8_UNORM = 1,
SVGA3D_R10G10B10_XR_BIAS_A2_UNORM = 113,
SVGA3D_B8G8R8A8_TYPELESS = 114,
SVGA3D_B8G8R8A8_UNORM_SRGB = 115,
SVGA3D_B8G8R8X8_TYPELESS = 116,
SVGA3D_B8G8R8X8_UNORM_SRGB = 117,
/* Advanced D3D9 depth formats. */
/* Advanced depth formats. */
SVGA3D_Z_DF16 = 118,
SVGA3D_Z_DF24 = 119,
SVGA3D_Z_D24S8_INT = 120,
......@@ -261,17 +269,185 @@ typedef enum SVGA3dSurfaceFormat {
/* Planar video formats. */
SVGA3D_YV12 = 121,
SVGA3D_FORMAT_MAX = 122,
SVGA3D_R32G32B32A32_FLOAT = 122,
SVGA3D_R16G16B16A16_FLOAT = 123,
SVGA3D_R16G16B16A16_UNORM = 124,
SVGA3D_R32G32_FLOAT = 125,
SVGA3D_R10G10B10A2_UNORM = 126,
SVGA3D_R8G8B8A8_SNORM = 127,
SVGA3D_R16G16_FLOAT = 128,
SVGA3D_R16G16_UNORM = 129,
SVGA3D_R16G16_SNORM = 130,
SVGA3D_R32_FLOAT = 131,
SVGA3D_R8G8_SNORM = 132,
SVGA3D_R16_FLOAT = 133,
SVGA3D_D16_UNORM = 134,
SVGA3D_A8_UNORM = 135,
SVGA3D_BC1_UNORM = 136,
SVGA3D_BC2_UNORM = 137,
SVGA3D_BC3_UNORM = 138,
SVGA3D_B5G6R5_UNORM = 139,
SVGA3D_B5G5R5A1_UNORM = 140,
SVGA3D_B8G8R8A8_UNORM = 141,
SVGA3D_B8G8R8X8_UNORM = 142,
SVGA3D_BC4_UNORM = 143,
SVGA3D_BC5_UNORM = 144,
SVGA3D_FORMAT_MAX
} SVGA3dSurfaceFormat;
typedef uint32 SVGA3dColor; /* a, r, g, b */
typedef enum SVGA3dSurfaceFlags {
SVGA3D_SURFACE_CUBEMAP = (1 << 0),
/*
* HINT flags are not enforced by the device but are useful for
* performance.
*/
SVGA3D_SURFACE_HINT_STATIC = (1 << 1),
SVGA3D_SURFACE_HINT_DYNAMIC = (1 << 2),
SVGA3D_SURFACE_HINT_INDEXBUFFER = (1 << 3),
SVGA3D_SURFACE_HINT_VERTEXBUFFER = (1 << 4),
SVGA3D_SURFACE_HINT_TEXTURE = (1 << 5),
SVGA3D_SURFACE_HINT_RENDERTARGET = (1 << 6),
SVGA3D_SURFACE_HINT_DEPTHSTENCIL = (1 << 7),
SVGA3D_SURFACE_HINT_WRITEONLY = (1 << 8),
SVGA3D_SURFACE_MASKABLE_ANTIALIAS = (1 << 9),
SVGA3D_SURFACE_AUTOGENMIPMAPS = (1 << 10),
SVGA3D_SURFACE_DECODE_RENDERTARGET = (1 << 11),
/*
* Is this surface using a base-level pitch for it's mob backing?
*
* This flag is not intended to be set by guest-drivers, but is instead
* set by the device when the surface is bound to a mob with a specified
* pitch.
*/
SVGA3D_SURFACE_MOB_PITCH = (1 << 12),
SVGA3D_SURFACE_INACTIVE = (1 << 13),
SVGA3D_SURFACE_HINT_RT_LOCKABLE = (1 << 14),
SVGA3D_SURFACE_VOLUME = (1 << 15),
/*
* Required to be set on a surface to bind it to a screen target.
*/
SVGA3D_SURFACE_SCREENTARGET = (1 << 16),
/*
* Align images in the guest-backing mob to 16-bytes.
*/
SVGA3D_SURFACE_ALIGN16 = (1 << 17),
SVGA3D_SURFACE_1D = (1 << 18),
SVGA3D_SURFACE_ARRAY = (1 << 19),
/*
* Bind flags.
* These are enforced for any surface defined with DefineGBSurface_v2.
*/
SVGA3D_SURFACE_BIND_VERTEX_BUFFER = (1 << 20),
SVGA3D_SURFACE_BIND_INDEX_BUFFER = (1 << 21),
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER = (1 << 22),
SVGA3D_SURFACE_BIND_SHADER_RESOURCE = (1 << 23),
SVGA3D_SURFACE_BIND_RENDER_TARGET = (1 << 24),
SVGA3D_SURFACE_BIND_DEPTH_STENCIL = (1 << 25),
SVGA3D_SURFACE_BIND_STREAM_OUTPUT = (1 << 26),
/*
* A note on staging flags:
*
* The STAGING flags notes that the surface will not be used directly by the
* drawing pipeline, i.e. that it will not be bound to any bind point.
* Staging surfaces may be used by copy operations to move data in and out
* of other surfaces.
*
* The HINT_INDIRECT_UPDATE flag suggests that the surface will receive
* updates indirectly, i.e. the surface will not be updated directly, but
* will receive copies from staging surfaces.
*/
SVGA3D_SURFACE_STAGING_UPLOAD = (1 << 27),
SVGA3D_SURFACE_STAGING_DOWNLOAD = (1 << 28),
SVGA3D_SURFACE_HINT_INDIRECT_UPDATE = (1 << 29),
/*
* Setting this flag allow this surface to be used with the
* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER command. It is only valid for
* buffer surfaces, an no bind flags are allowed to be set on surfaces
* with this flag.
*/
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER = (1 << 30),
/*
* Marker for the last defined bit.
*/
SVGA3D_SURFACE_FLAG_MAX = (1 << 31),
} SVGA3dSurfaceFlags;
#define SVGA3D_SURFACE_HB_DISALLOWED_MASK \
( SVGA3D_SURFACE_MOB_PITCH | \
SVGA3D_SURFACE_SCREENTARGET | \
SVGA3D_SURFACE_ALIGN16 | \
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
SVGA3D_SURFACE_STAGING_UPLOAD | \
SVGA3D_SURFACE_STAGING_DOWNLOAD | \
SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER \
)
#define SVGA3D_SURFACE_2D_DISALLOWED_MASK \
( SVGA3D_SURFACE_CUBEMAP | \
SVGA3D_SURFACE_MASKABLE_ANTIALIAS | \
SVGA3D_SURFACE_AUTOGENMIPMAPS | \
SVGA3D_SURFACE_DECODE_RENDERTARGET | \
SVGA3D_SURFACE_VOLUME | \
SVGA3D_SURFACE_1D | \
SVGA3D_SURFACE_ARRAY | \
SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER \
)
#define SVGA3D_SURFACE_SCREENTARGET_DISALLOWED_MASK \
( SVGA3D_SURFACE_CUBEMAP | \
SVGA3D_SURFACE_AUTOGENMIPMAPS | \
SVGA3D_SURFACE_DECODE_RENDERTARGET | \
SVGA3D_SURFACE_VOLUME | \
SVGA3D_SURFACE_1D | \
SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
SVGA3D_SURFACE_INACTIVE | \
SVGA3D_SURFACE_STAGING_UPLOAD | \
SVGA3D_SURFACE_STAGING_DOWNLOAD | \
SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER \
)
#define SVGA3D_SURFACE_DX_ONLY_MASK \
( SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER \
#define SVGA3D_SURFACE_STAGING_MASK \
( SVGA3D_SURFACE_STAGING_UPLOAD | \
SVGA3D_SURFACE_STAGING_DOWNLOAD \
)
#define SVGA3D_SURFACE_BIND_MASK \
( SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
SVGA3D_SURFACE_BIND_SHADER_RESOURCE | \
SVGA3D_SURFACE_BIND_RENDER_TARGET | \
SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
SVGA3D_SURFACE_BIND_STREAM_OUTPUT \
)
/*
* These match the D3DFORMAT_OP definitions used by Direct3D. We need
* them so that we can query the host for what the supported surface
* operations are (when we're using the D3D backend, in particular),
* and so we can send those operations to the guest.
*/
typedef enum {
SVGA3DFORMAT_OP_TEXTURE = 0x00000001,
SVGA3DFORMAT_OP_VOLUMETEXTURE = 0x00000002,
......@@ -348,8 +524,8 @@ typedef enum {
SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB = 0x00080000,
/*
* Indicated that this format can be written as an SRGB target (meaning that the
* pixel pipe will DE-linearize data on output to format)
* Indicated that this format can be written as an SRGB target
* (meaning that the pixel pipe will DE-linearize data on output to format)
*/
SVGA3DFORMAT_OP_SRGBWRITE = 0x00100000,
......@@ -370,14 +546,41 @@ typedef enum {
SVGA3DFORMAT_OP_VERTEXTEXTURE = 0x00800000,
/*
* Indicates that this format supports neither texture coordinate wrap
* modes, nor mipmapping
* Indicates that this format supports neither texture coordinate
* wrap modes, nor mipmapping.
*/
SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP = 0x01000000
} SVGA3dFormatOp;
/*
* This structure is a conversion of SVGA3DFORMAT_OP_*.
#define SVGA3D_FORMAT_POSITIVE \
(SVGA3DFORMAT_OP_TEXTURE | \
SVGA3DFORMAT_OP_VOLUMETEXTURE | \
SVGA3DFORMAT_OP_CUBETEXTURE | \
SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET | \
SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET | \
SVGA3DFORMAT_OP_ZSTENCIL | \
SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH | \
SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET | \
SVGA3DFORMAT_OP_DISPLAYMODE | \
SVGA3DFORMAT_OP_3DACCELERATION | \
SVGA3DFORMAT_OP_PIXELSIZE | \
SVGA3DFORMAT_OP_CONVERT_TO_ARGB | \
SVGA3DFORMAT_OP_OFFSCREENPLAIN | \
SVGA3DFORMAT_OP_SRGBREAD | \
SVGA3DFORMAT_OP_BUMPMAP | \
SVGA3DFORMAT_OP_DMAP | \
SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB | \
SVGA3DFORMAT_OP_SRGBWRITE | \
SVGA3DFORMAT_OP_AUTOGENMIPMAP | \
SVGA3DFORMAT_OP_VERTEXTEXTURE)
#define SVGA3D_FORMAT_NEGATIVE \
(SVGA3DFORMAT_OP_NOFILTER | \
SVGA3DFORMAT_OP_NOALPHABLEND | \
SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP)
/*
* This structure is a conversion of SVGA3DFORMAT_OP_*
* Entries must be located at the same position.
*/
typedef union {
......@@ -418,6 +621,7 @@ typedef union {
typedef enum {
SVGA3D_RS_INVALID = 0,
SVGA3D_RS_MIN = 1,
SVGA3D_RS_ZENABLE = 1, /* SVGA3dBool */
SVGA3D_RS_ZWRITEENABLE = 2, /* SVGA3dBool */
SVGA3D_RS_ALPHATESTENABLE = 3, /* SVGA3dBool */
......@@ -526,8 +730,7 @@ typedef enum {
SVGA3D_RS_DSTBLENDALPHA = 95, /* SVGA3dBlendOp */
SVGA3D_RS_BLENDEQUATIONALPHA = 96, /* SVGA3dBlendEquation */
SVGA3D_RS_TRANSPARENCYANTIALIAS = 97, /* SVGA3dTransparencyAntialiasType */
SVGA3D_RS_LINEAA = 98, /* SVGA3dBool */
SVGA3D_RS_LINEWIDTH = 99, /* float */
SVGA3D_RS_LINEWIDTH = 98, /* float */
SVGA3D_RS_MAX
} SVGA3dRenderStateName;
......@@ -542,10 +745,12 @@ typedef enum {
SVGA3D_VERTEXMATERIAL_NONE = 0, /* Use the value in the current material */
SVGA3D_VERTEXMATERIAL_DIFFUSE = 1, /* Use the value in the diffuse component */
SVGA3D_VERTEXMATERIAL_SPECULAR = 2, /* Use the value in the specular component */
SVGA3D_VERTEXMATERIAL_MAX = 3,
} SVGA3dVertexMaterial;
typedef enum {
SVGA3D_FILLMODE_INVALID = 0,
SVGA3D_FILLMODE_MIN = 1,
SVGA3D_FILLMODE_POINT = 1,
SVGA3D_FILLMODE_LINE = 2,
SVGA3D_FILLMODE_FILL = 3,
......@@ -554,13 +759,16 @@ typedef enum {
typedef
#include "vmware_pack_begin.h"
union {
struct {
uint16 mode; /* SVGA3dFillModeType */
uint16 face; /* SVGA3dFace */
};
uint32 uintValue;
} SVGA3dFillMode;
}
#include "vmware_pack_end.h"
SVGA3dFillMode;
typedef enum {
SVGA3D_SHADEMODE_INVALID = 0,
......@@ -571,34 +779,45 @@ typedef enum {
} SVGA3dShadeMode;
typedef
#include "vmware_pack_begin.h"
union {
struct {
uint16 repeat;
uint16 pattern;
};
uint32 uintValue;
} SVGA3dLinePattern;
}
#include "vmware_pack_end.h"
SVGA3dLinePattern;
typedef enum {
SVGA3D_BLENDOP_INVALID = 0,
SVGA3D_BLENDOP_ZERO = 1,
SVGA3D_BLENDOP_ONE = 2,
SVGA3D_BLENDOP_SRCCOLOR = 3,
SVGA3D_BLENDOP_INVSRCCOLOR = 4,
SVGA3D_BLENDOP_SRCALPHA = 5,
SVGA3D_BLENDOP_INVSRCALPHA = 6,
SVGA3D_BLENDOP_DESTALPHA = 7,
SVGA3D_BLENDOP_INVDESTALPHA = 8,
SVGA3D_BLENDOP_DESTCOLOR = 9,
SVGA3D_BLENDOP_INVDESTCOLOR = 10,
SVGA3D_BLENDOP_SRCALPHASAT = 11,
SVGA3D_BLENDOP_BLENDFACTOR = 12,
SVGA3D_BLENDOP_INVBLENDFACTOR = 13,
SVGA3D_BLENDOP_INVALID = 0,
SVGA3D_BLENDOP_MIN = 1,
SVGA3D_BLENDOP_ZERO = 1,
SVGA3D_BLENDOP_ONE = 2,
SVGA3D_BLENDOP_SRCCOLOR = 3,
SVGA3D_BLENDOP_INVSRCCOLOR = 4,
SVGA3D_BLENDOP_SRCALPHA = 5,
SVGA3D_BLENDOP_INVSRCALPHA = 6,
SVGA3D_BLENDOP_DESTALPHA = 7,
SVGA3D_BLENDOP_INVDESTALPHA = 8,
SVGA3D_BLENDOP_DESTCOLOR = 9,
SVGA3D_BLENDOP_INVDESTCOLOR = 10,
SVGA3D_BLENDOP_SRCALPHASAT = 11,
SVGA3D_BLENDOP_BLENDFACTOR = 12,
SVGA3D_BLENDOP_INVBLENDFACTOR = 13,
SVGA3D_BLENDOP_SRC1COLOR = 14,
SVGA3D_BLENDOP_INVSRC1COLOR = 15,
SVGA3D_BLENDOP_SRC1ALPHA = 16,
SVGA3D_BLENDOP_INVSRC1ALPHA = 17,
SVGA3D_BLENDOP_BLENDFACTORALPHA = 18,
SVGA3D_BLENDOP_INVBLENDFACTORALPHA = 19,
SVGA3D_BLENDOP_MAX
} SVGA3dBlendOp;
typedef enum {
SVGA3D_BLENDEQ_INVALID = 0,
SVGA3D_BLENDEQ_MIN = 1,
SVGA3D_BLENDEQ_ADD = 1,
SVGA3D_BLENDEQ_SUBTRACT = 2,
SVGA3D_BLENDEQ_REVSUBTRACT = 3,
......@@ -607,6 +826,27 @@ typedef enum {
SVGA3D_BLENDEQ_MAX
} SVGA3dBlendEquation;
typedef enum {
SVGA3D_DX11_LOGICOP_MIN = 0,
SVGA3D_DX11_LOGICOP_CLEAR = 0,
SVGA3D_DX11_LOGICOP_SET = 1,
SVGA3D_DX11_LOGICOP_COPY = 2,
SVGA3D_DX11_LOGICOP_COPY_INVERTED = 3,
SVGA3D_DX11_LOGICOP_NOOP = 4,
SVGA3D_DX11_LOGICOP_INVERT = 5,
SVGA3D_DX11_LOGICOP_AND = 6,
SVGA3D_DX11_LOGICOP_NAND = 7,
SVGA3D_DX11_LOGICOP_OR = 8,
SVGA3D_DX11_LOGICOP_NOR = 9,
SVGA3D_DX11_LOGICOP_XOR = 10,
SVGA3D_DX11_LOGICOP_EQUIV = 11,
SVGA3D_DX11_LOGICOP_AND_REVERSE = 12,
SVGA3D_DX11_LOGICOP_AND_INVERTED = 13,
SVGA3D_DX11_LOGICOP_OR_REVERSE = 14,
SVGA3D_DX11_LOGICOP_OR_INVERTED = 15,
SVGA3D_DX11_LOGICOP_MAX
} SVGA3dDX11LogicOp;
typedef enum {
SVGA3D_FRONTWINDING_INVALID = 0,
SVGA3D_FRONTWINDING_CW = 1,
......@@ -617,6 +857,7 @@ typedef enum {
typedef enum {
SVGA3D_FACE_INVALID = 0,
SVGA3D_FACE_NONE = 1,
SVGA3D_FACE_MIN = 1,
SVGA3D_FACE_FRONT = 2,
SVGA3D_FACE_BACK = 3,
SVGA3D_FACE_FRONT_BACK = 4,
......@@ -678,6 +919,7 @@ typedef enum {
typedef enum {
SVGA3D_STENCILOP_INVALID = 0,
SVGA3D_STENCILOP_MIN = 1,
SVGA3D_STENCILOP_KEEP = 1,
SVGA3D_STENCILOP_ZERO = 2,
SVGA3D_STENCILOP_REPLACE = 3,
......@@ -701,11 +943,19 @@ typedef enum {
typedef enum {
SVGA3D_CLEAR_COLOR = 0x1,
SVGA3D_CLEAR_DEPTH = 0x2,
SVGA3D_CLEAR_STENCIL = 0x4
SVGA3D_CLEAR_STENCIL = 0x4,
/*
* Hint only, must be used together with SVGA3D_CLEAR_COLOR. If
* SVGA3D_CLEAR_DEPTH or SVGA3D_CLEAR_STENCIL bit is set, this
* bit will be ignored.
*/
SVGA3D_CLEAR_COLORFILL = 0x8
} SVGA3dClearFlag;
typedef enum {
SVGA3D_RT_DEPTH = 0,
SVGA3D_RT_MIN = 0,
SVGA3D_RT_STENCIL = 1,
SVGA3D_RT_COLOR0 = 2,
SVGA3D_RT_COLOR1 = 3,
......@@ -722,6 +972,7 @@ typedef enum {
#define SVGA3D_MAX_RT_COLOR (SVGA3D_RT_COLOR7 - SVGA3D_RT_COLOR0 + 1)
typedef
#include "vmware_pack_begin.h"
union {
struct {
uint32 red : 1;
......@@ -730,13 +981,16 @@ union {
uint32 alpha : 1;
};
uint32 uintValue;
} SVGA3dColorMask;
}
#include "vmware_pack_end.h"
SVGA3dColorMask;
typedef enum {
SVGA3D_VBLEND_DISABLE = 0,
SVGA3D_VBLEND_1WEIGHT = 1,
SVGA3D_VBLEND_2WEIGHT = 2,
SVGA3D_VBLEND_3WEIGHT = 3,
SVGA3D_VBLEND_MAX = 4,
} SVGA3dVertexBlendFlags;
typedef enum {
......@@ -754,6 +1008,7 @@ typedef enum {
typedef enum {
SVGA3D_TS_INVALID = 0,
SVGA3D_TS_MIN = 1,
SVGA3D_TS_BIND_TEXTURE = 1, /* SVGA3dSurfaceId */
SVGA3D_TS_COLOROP = 2, /* SVGA3dTextureCombiner */
SVGA3D_TS_COLORARG1 = 3, /* SVGA3dTextureArgData */
......@@ -793,6 +1048,10 @@ typedef enum {
SVGA3D_TS_BUMPENVLOFFSET = 27, /* float */
SVGA3D_TS_COLORARG0 = 28, /* SVGA3dTextureArgData */
SVGA3D_TS_ALPHAARG0 = 29, /* SVGA3dTextureArgData */
SVGA3D_TS_PREGB_MAX = 30, /* Max value before GBObjects */
SVGA3D_TS_CONSTANT = 30, /* SVGA3dColor */
SVGA3D_TS_COLOR_KEY_ENABLE = 31, /* SVGA3dBool */
SVGA3D_TS_COLOR_KEY = 32, /* SVGA3dColor */
SVGA3D_TS_MAX
} SVGA3dTextureStateName;
......@@ -831,6 +1090,7 @@ typedef enum {
typedef enum {
SVGA3D_TEX_ADDRESS_INVALID = 0,
SVGA3D_TEX_ADDRESS_MIN = 1,
SVGA3D_TEX_ADDRESS_WRAP = 1,
SVGA3D_TEX_ADDRESS_MIRROR = 2,
SVGA3D_TEX_ADDRESS_CLAMP = 3,
......@@ -846,6 +1106,7 @@ typedef enum {
*/
typedef enum {
SVGA3D_TEX_FILTER_NONE = 0,
SVGA3D_TEX_FILTER_MIN = 0,
SVGA3D_TEX_FILTER_NEAREST = 1,
SVGA3D_TEX_FILTER_LINEAR = 2,
SVGA3D_TEX_FILTER_ANISOTROPIC = 3,
......@@ -879,11 +1140,12 @@ typedef enum {
*/
typedef enum {
SVGA3D_TA_INVALID = 0,
SVGA3D_TA_CONSTANT = 1,
SVGA3D_TA_TFACTOR = 1,
SVGA3D_TA_PREVIOUS = 2,
SVGA3D_TA_DIFFUSE = 3,
SVGA3D_TA_TEXTURE = 4,
SVGA3D_TA_SPECULAR = 5,
SVGA3D_TA_CONSTANT = 6,
SVGA3D_TA_MAX
} SVGA3dTextureArgData;
......@@ -896,17 +1158,6 @@ typedef enum {
SVGA3D_TM_ONE_MINUS = (2 << SVGA3D_TM_MASK_LEN),
} SVGA3dTextureArgModifier;
#define SVGA3D_INVALID_ID ((uint32)-1)
#define SVGA3D_MAX_CLIP_PLANES 6
/*
* This is the limit to the number of fixed-function texture
* transforms and texture coordinates we can support. It does *not*
* correspond to the number of texture image units (samplers) we
* support!
*/
#define SVGA3D_MAX_TEXTURE_COORDS 8
/*
* Vertex declarations
*
......@@ -920,19 +1171,19 @@ typedef enum {
typedef enum {
SVGA3D_DECLUSAGE_POSITION = 0,
SVGA3D_DECLUSAGE_BLENDWEIGHT, /* 1 */
SVGA3D_DECLUSAGE_BLENDINDICES, /* 2 */
SVGA3D_DECLUSAGE_NORMAL, /* 3 */
SVGA3D_DECLUSAGE_PSIZE, /* 4 */
SVGA3D_DECLUSAGE_TEXCOORD, /* 5 */
SVGA3D_DECLUSAGE_TANGENT, /* 6 */
SVGA3D_DECLUSAGE_BINORMAL, /* 7 */
SVGA3D_DECLUSAGE_TESSFACTOR, /* 8 */
SVGA3D_DECLUSAGE_POSITIONT, /* 9 */
SVGA3D_DECLUSAGE_COLOR, /* 10 */
SVGA3D_DECLUSAGE_FOG, /* 11 */
SVGA3D_DECLUSAGE_DEPTH, /* 12 */
SVGA3D_DECLUSAGE_SAMPLE, /* 13 */
SVGA3D_DECLUSAGE_BLENDWEIGHT,
SVGA3D_DECLUSAGE_BLENDINDICES,
SVGA3D_DECLUSAGE_NORMAL,
SVGA3D_DECLUSAGE_PSIZE,
SVGA3D_DECLUSAGE_TEXCOORD,
SVGA3D_DECLUSAGE_TANGENT,
SVGA3D_DECLUSAGE_BINORMAL,
SVGA3D_DECLUSAGE_TESSFACTOR,
SVGA3D_DECLUSAGE_POSITIONT,
SVGA3D_DECLUSAGE_COLOR,
SVGA3D_DECLUSAGE_FOG,
SVGA3D_DECLUSAGE_DEPTH,
SVGA3D_DECLUSAGE_SAMPLE,
SVGA3D_DECLUSAGE_MAX
} SVGA3dDeclUsage;
......@@ -943,7 +1194,8 @@ typedef enum {
SVGA3D_DECLMETHOD_CROSSUV, /* Normal */
SVGA3D_DECLMETHOD_UV,
SVGA3D_DECLMETHOD_LOOKUP, /* Lookup a displacement map */
SVGA3D_DECLMETHOD_LOOKUPPRESAMPLED, /* Lookup a pre-sampled displacement map */
SVGA3D_DECLMETHOD_LOOKUPPRESAMPLED, /* Lookup a pre-sampled displacement */
/* map */
} SVGA3dDeclMethod;
typedef enum {
......@@ -996,13 +1248,25 @@ typedef union {
} SVGA3dVertexDivisor;
typedef enum {
/*
* SVGA3D_PRIMITIVE_INVALID is a valid primitive type.
*
* List MIN second so debuggers will think INVALID is
* the correct name.
*/
SVGA3D_PRIMITIVE_INVALID = 0,
SVGA3D_PRIMITIVE_MIN = 0,
SVGA3D_PRIMITIVE_TRIANGLELIST = 1,
SVGA3D_PRIMITIVE_POINTLIST = 2,
SVGA3D_PRIMITIVE_LINELIST = 3,
SVGA3D_PRIMITIVE_LINESTRIP = 4,
SVGA3D_PRIMITIVE_TRIANGLESTRIP = 5,
SVGA3D_PRIMITIVE_TRIANGLEFAN = 6,
SVGA3D_PRIMITIVE_LINELIST_ADJ = 7,
SVGA3D_PRIMITIVE_PREDX_MAX = 7,
SVGA3D_PRIMITIVE_LINESTRIP_ADJ = 8,
SVGA3D_PRIMITIVE_TRIANGLELIST_ADJ = 9,
SVGA3D_PRIMITIVE_TRIANGLESTRIP_ADJ = 10,
SVGA3D_PRIMITIVE_MAX
} SVGA3dPrimitiveType;
......@@ -1016,6 +1280,7 @@ typedef enum {
typedef enum {
SVGA3D_TRANSFORM_INVALID = 0,
SVGA3D_TRANSFORM_WORLD = 1,
SVGA3D_TRANSFORM_MIN = 1,
SVGA3D_TRANSFORM_VIEW = 2,
SVGA3D_TRANSFORM_PROJECTION = 3,
SVGA3D_TRANSFORM_TEXTURE0 = 4,
......@@ -1034,6 +1299,7 @@ typedef enum {
typedef enum {
SVGA3D_LIGHTTYPE_INVALID = 0,
SVGA3D_LIGHTTYPE_MIN = 1,
SVGA3D_LIGHTTYPE_POINT = 1,
SVGA3D_LIGHTTYPE_SPOT1 = 2, /* 1-cone, in degrees */
SVGA3D_LIGHTTYPE_SPOT2 = 3, /* 2-cone, in radians */
......@@ -1055,20 +1321,38 @@ typedef enum {
SVGA3D_SHADERTYPE_MIN = 1,
SVGA3D_SHADERTYPE_VS = 1,
SVGA3D_SHADERTYPE_PS = 2,
SVGA3D_SHADERTYPE_MAX = 3,
SVGA3D_SHADERTYPE_PREDX_MAX = 3,
SVGA3D_SHADERTYPE_GS = 3,
SVGA3D_SHADERTYPE_DX10_MAX = 4,
SVGA3D_SHADERTYPE_HS = 4,
SVGA3D_SHADERTYPE_DS = 5,
SVGA3D_SHADERTYPE_CS = 6,
SVGA3D_SHADERTYPE_MAX = 7
} SVGA3dShaderType;
#define SVGA3D_NUM_SHADERTYPE (SVGA3D_SHADERTYPE_MAX - SVGA3D_SHADERTYPE_MIN)
#define SVGA3D_NUM_SHADERTYPE_PREDX \
(SVGA3D_SHADERTYPE_PREDX_MAX - SVGA3D_SHADERTYPE_MIN)
#define SVGA3D_NUM_SHADERTYPE_DX10 \
(SVGA3D_SHADERTYPE_DX10_MAX - SVGA3D_SHADERTYPE_MIN)
#define SVGA3D_NUM_SHADERTYPE \
(SVGA3D_SHADERTYPE_MAX - SVGA3D_SHADERTYPE_MIN)
typedef enum {
SVGA3D_CONST_TYPE_MIN = 0,
SVGA3D_CONST_TYPE_FLOAT = 0,
SVGA3D_CONST_TYPE_INT = 1,
SVGA3D_CONST_TYPE_BOOL = 2,
SVGA3D_CONST_TYPE_MAX
SVGA3D_CONST_TYPE_MAX = 3,
} SVGA3dShaderConstType;
#define SVGA3D_MAX_SURFACE_FACES 6
/*
* Register limits for shader consts.
*/
#define SVGA3D_CONSTREG_MAX 256
#define SVGA3D_CONSTINTREG_MAX 16
#define SVGA3D_CONSTBOOLREG_MAX 16
typedef enum {
SVGA3D_STRETCH_BLT_POINT = 0,
......@@ -1077,178 +1361,187 @@ typedef enum {
} SVGA3dStretchBltMode;
typedef enum {
SVGA3D_QUERYTYPE_INVALID = ((uint8)-1),
SVGA3D_QUERYTYPE_MIN = 0,
SVGA3D_QUERYTYPE_OCCLUSION = 0,
SVGA3D_QUERYTYPE_TIMESTAMP = 1,
SVGA3D_QUERYTYPE_TIMESTAMPDISJOINT = 2,
SVGA3D_QUERYTYPE_PIPELINESTATS = 3,
SVGA3D_QUERYTYPE_OCCLUSIONPREDICATE = 4,
SVGA3D_QUERYTYPE_STREAMOUTPUTSTATS = 5,
SVGA3D_QUERYTYPE_STREAMOVERFLOWPREDICATE = 6,
SVGA3D_QUERYTYPE_OCCLUSION64 = 7,
SVGA3D_QUERYTYPE_EVENT = 8,
SVGA3D_QUERYTYPE_DX10_MAX = 9,
SVGA3D_QUERYTYPE_SOSTATS_STREAM0 = 9,
SVGA3D_QUERYTYPE_SOSTATS_STREAM1 = 10,
SVGA3D_QUERYTYPE_SOSTATS_STREAM2 = 11,
SVGA3D_QUERYTYPE_SOSTATS_STREAM3 = 12,
SVGA3D_QUERYTYPE_SOP_STREAM0 = 13,
SVGA3D_QUERYTYPE_SOP_STREAM1 = 14,
SVGA3D_QUERYTYPE_SOP_STREAM2 = 15,
SVGA3D_QUERYTYPE_SOP_STREAM3 = 16,
SVGA3D_QUERYTYPE_MAX
} SVGA3dQueryType;
typedef enum {
SVGA3D_QUERYSTATE_PENDING = 0, /* Waiting on the host (set by guest) */
SVGA3D_QUERYSTATE_SUCCEEDED = 1, /* Completed successfully (set by host) */
SVGA3D_QUERYSTATE_FAILED = 2, /* Completed unsuccessfully (set by host) */
SVGA3D_QUERYSTATE_NEW = 3, /* Never submitted (For guest use only) */
} SVGA3dQueryState;
typedef uint8 SVGA3dQueryTypeUint8;
typedef enum {
SVGA3D_WRITE_HOST_VRAM = 1,
SVGA3D_READ_HOST_VRAM = 2,
} SVGA3dTransferType;
#define SVGA3D_NUM_QUERYTYPE (SVGA3D_QUERYTYPE_MAX - SVGA3D_QUERYTYPE_MIN)
/*
* The maximum number of vertex arrays we're guaranteed to support in
* SVGA_3D_CMD_DRAWPRIMITIVES.
* This is the maximum number of queries per context that can be active
* simultaneously between a beginQuery and endQuery.
*/
#define SVGA3D_MAX_VERTEX_ARRAYS 32
#define SVGA3D_MAX_QUERY 64
/*
* The maximum number of primitive ranges we're guaranteed to support
* in SVGA_3D_CMD_DRAWPRIMITIVES.
* Query result buffer formats
*/
#define SVGA3D_MAX_DRAW_PRIMITIVE_RANGES 32
typedef
#include "vmware_pack_begin.h"
struct {
uint32 samplesRendered;
}
#include "vmware_pack_end.h"
SVGADXOcclusionQueryResult;
/*
* Identifiers for commands in the command FIFO.
*
* IDs between 1000 and 1039 (inclusive) were used by obsolete versions of
* the SVGA3D protocol and remain reserved; they should not be used in the
* future.
*
* IDs between 1040 and 1999 (inclusive) are available for use by the
* current SVGA3D protocol.
*
* FIFO clients other than SVGA3D should stay below 1000, or at 2000
* and up.
*/
typedef
#include "vmware_pack_begin.h"
struct {
uint32 passed;
}
#include "vmware_pack_end.h"
SVGADXEventQueryResult;
typedef
#include "vmware_pack_begin.h"
struct {
uint64 timestamp;
}
#include "vmware_pack_end.h"
SVGADXTimestampQueryResult;
typedef
#include "vmware_pack_begin.h"
struct {
uint64 realFrequency;
uint32 disjoint;
}
#include "vmware_pack_end.h"
SVGADXTimestampDisjointQueryResult;
typedef
#include "vmware_pack_begin.h"
struct {
uint64 inputAssemblyVertices;
uint64 inputAssemblyPrimitives;
uint64 vertexShaderInvocations;
uint64 geometryShaderInvocations;
uint64 geometryShaderPrimitives;
uint64 clipperInvocations;
uint64 clipperPrimitives;
uint64 pixelShaderInvocations;
uint64 hullShaderInvocations;
uint64 domainShaderInvocations;
uint64 computeShaderInvocations;
}
#include "vmware_pack_end.h"
SVGADXPipelineStatisticsQueryResult;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 anySamplesRendered;
}
#include "vmware_pack_end.h"
SVGADXOcclusionPredicateQueryResult;
typedef
#include "vmware_pack_begin.h"
struct {
uint64 numPrimitivesWritten;
uint64 numPrimitivesRequired;
}
#include "vmware_pack_end.h"
SVGADXStreamOutStatisticsQueryResult;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 overflowed;
}
#include "vmware_pack_end.h"
SVGADXStreamOutPredicateQueryResult;
#define SVGA_3D_CMD_LEGACY_BASE 1000
#define SVGA_3D_CMD_BASE 1040
#define SVGA_3D_CMD_SURFACE_DEFINE SVGA_3D_CMD_BASE + 0 /* Deprecated */
#define SVGA_3D_CMD_SURFACE_DESTROY SVGA_3D_CMD_BASE + 1
#define SVGA_3D_CMD_SURFACE_COPY SVGA_3D_CMD_BASE + 2
#define SVGA_3D_CMD_SURFACE_STRETCHBLT SVGA_3D_CMD_BASE + 3
#define SVGA_3D_CMD_SURFACE_DMA SVGA_3D_CMD_BASE + 4
#define SVGA_3D_CMD_CONTEXT_DEFINE SVGA_3D_CMD_BASE + 5
#define SVGA_3D_CMD_CONTEXT_DESTROY SVGA_3D_CMD_BASE + 6
#define SVGA_3D_CMD_SETTRANSFORM SVGA_3D_CMD_BASE + 7
#define SVGA_3D_CMD_SETZRANGE SVGA_3D_CMD_BASE + 8
#define SVGA_3D_CMD_SETRENDERSTATE SVGA_3D_CMD_BASE + 9
#define SVGA_3D_CMD_SETRENDERTARGET SVGA_3D_CMD_BASE + 10
#define SVGA_3D_CMD_SETTEXTURESTATE SVGA_3D_CMD_BASE + 11
#define SVGA_3D_CMD_SETMATERIAL SVGA_3D_CMD_BASE + 12
#define SVGA_3D_CMD_SETLIGHTDATA SVGA_3D_CMD_BASE + 13
#define SVGA_3D_CMD_SETLIGHTENABLED SVGA_3D_CMD_BASE + 14
#define SVGA_3D_CMD_SETVIEWPORT SVGA_3D_CMD_BASE + 15
#define SVGA_3D_CMD_SETCLIPPLANE SVGA_3D_CMD_BASE + 16
#define SVGA_3D_CMD_CLEAR SVGA_3D_CMD_BASE + 17
#define SVGA_3D_CMD_PRESENT SVGA_3D_CMD_BASE + 18 /* Deprecated */
#define SVGA_3D_CMD_SHADER_DEFINE SVGA_3D_CMD_BASE + 19
#define SVGA_3D_CMD_SHADER_DESTROY SVGA_3D_CMD_BASE + 20
#define SVGA_3D_CMD_SET_SHADER SVGA_3D_CMD_BASE + 21
#define SVGA_3D_CMD_SET_SHADER_CONST SVGA_3D_CMD_BASE + 22
#define SVGA_3D_CMD_DRAW_PRIMITIVES SVGA_3D_CMD_BASE + 23
#define SVGA_3D_CMD_SETSCISSORRECT SVGA_3D_CMD_BASE + 24
#define SVGA_3D_CMD_BEGIN_QUERY SVGA_3D_CMD_BASE + 25
#define SVGA_3D_CMD_END_QUERY SVGA_3D_CMD_BASE + 26
#define SVGA_3D_CMD_WAIT_FOR_QUERY SVGA_3D_CMD_BASE + 27
#define SVGA_3D_CMD_PRESENT_READBACK SVGA_3D_CMD_BASE + 28 /* Deprecated */
#define SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN SVGA_3D_CMD_BASE + 29
#define SVGA_3D_CMD_SURFACE_DEFINE_V2 SVGA_3D_CMD_BASE + 30
#define SVGA_3D_CMD_GENERATE_MIPMAPS SVGA_3D_CMD_BASE + 31
#define SVGA_3D_CMD_ACTIVATE_SURFACE SVGA_3D_CMD_BASE + 40
#define SVGA_3D_CMD_DEACTIVATE_SURFACE SVGA_3D_CMD_BASE + 41
#define SVGA_3D_CMD_SCREEN_DMA 1082
#define SVGA_3D_CMD_SET_UNITY_SURFACE_COOKIE 1083
#define SVGA_3D_CMD_OPEN_CONTEXT_SURFACE 1084
#define SVGA_3D_CMD_LOGICOPS_BITBLT 1085
#define SVGA_3D_CMD_LOGICOPS_TRANSBLT 1086
#define SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1087
#define SVGA_3D_CMD_LOGICOPS_COLORFILL 1088
#define SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1089
#define SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1090
#define SVGA_3D_CMD_SET_OTABLE_BASE 1091
#define SVGA_3D_CMD_READBACK_OTABLE 1092
#define SVGA_3D_CMD_DEFINE_GB_MOB 1093
#define SVGA_3D_CMD_DESTROY_GB_MOB 1094
#define SVGA_3D_CMD_REDEFINE_GB_MOB 1095
#define SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING 1096
#define SVGA_3D_CMD_DEFINE_GB_SURFACE 1097
#define SVGA_3D_CMD_DESTROY_GB_SURFACE 1098
#define SVGA_3D_CMD_BIND_GB_SURFACE 1099
#define SVGA_3D_CMD_COND_BIND_GB_SURFACE 1100
#define SVGA_3D_CMD_UPDATE_GB_IMAGE 1101
#define SVGA_3D_CMD_UPDATE_GB_SURFACE 1102
#define SVGA_3D_CMD_READBACK_GB_IMAGE 1103
#define SVGA_3D_CMD_READBACK_GB_SURFACE 1104
#define SVGA_3D_CMD_INVALIDATE_GB_IMAGE 1105
#define SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106
#define SVGA_3D_CMD_DEFINE_GB_CONTEXT 1107
#define SVGA_3D_CMD_DESTROY_GB_CONTEXT 1108
#define SVGA_3D_CMD_BIND_GB_CONTEXT 1109
#define SVGA_3D_CMD_READBACK_GB_CONTEXT 1110
#define SVGA_3D_CMD_INVALIDATE_GB_CONTEXT 1111
#define SVGA_3D_CMD_DEFINE_GB_SHADER 1112
#define SVGA_3D_CMD_DESTROY_GB_SHADER 1113
#define SVGA_3D_CMD_BIND_GB_SHADER 1114
#define SVGA_3D_CMD_SET_OTABLE_BASE64 1115
#define SVGA_3D_CMD_BEGIN_GB_QUERY 1116
#define SVGA_3D_CMD_END_GB_QUERY 1117
#define SVGA_3D_CMD_WAIT_FOR_GB_QUERY 1118
#define SVGA_3D_CMD_NOP 1119
#define SVGA_3D_CMD_ENABLE_GART 1120
#define SVGA_3D_CMD_DISABLE_GART 1121
#define SVGA_3D_CMD_MAP_MOB_INTO_GART 1122
#define SVGA_3D_CMD_UNMAP_GART_RANGE 1123
#define SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124
#define SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125
#define SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126
#define SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127
#define SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL 1128
#define SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL 1129
#define SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE 1130
#define SVGA_3D_CMD_GB_SCREEN_DMA 1131
#define SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH 1132
#define SVGA_3D_CMD_GB_MOB_FENCE 1133
#define SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134
#define SVGA_3D_CMD_DEFINE_GB_MOB64 1135
#define SVGA_3D_CMD_REDEFINE_GB_MOB64 1136
#define SVGA_3D_CMD_NOP_ERROR 1137
#define SVGA_3D_CMD_RESERVED1 1138
#define SVGA_3D_CMD_RESERVED2 1139
#define SVGA_3D_CMD_RESERVED3 1140
#define SVGA_3D_CMD_RESERVED4 1141
#define SVGA_3D_CMD_RESERVED5 1142
#define SVGA_3D_CMD_MAX 1142
#define SVGA_3D_CMD_FUTURE_MAX 3000
typedef
#include "vmware_pack_begin.h"
struct {
uint64 samplesRendered;
}
#include "vmware_pack_end.h"
SVGADXOcclusion64QueryResult;
/*
* Common substructures used in multiple FIFO commands:
* SVGADXQueryResultUnion is not intended for use in the protocol, but is
* very helpful when working with queries generically.
*/
typedef
#include "vmware_pack_begin.h"
union SVGADXQueryResultUnion {
SVGADXOcclusionQueryResult occ;
SVGADXEventQueryResult event;
SVGADXTimestampQueryResult ts;
SVGADXTimestampDisjointQueryResult tsDisjoint;
SVGADXPipelineStatisticsQueryResult pipelineStats;
SVGADXOcclusionPredicateQueryResult occPred;
SVGADXStreamOutStatisticsQueryResult soStats;
SVGADXStreamOutPredicateQueryResult soPred;
SVGADXOcclusion64QueryResult occ64;
}
#include "vmware_pack_end.h"
SVGADXQueryResultUnion;
typedef enum {
SVGA3D_QUERYSTATE_PENDING = 0, /* Query is not finished yet */
SVGA3D_QUERYSTATE_SUCCEEDED = 1, /* Completed successfully */
SVGA3D_QUERYSTATE_FAILED = 2, /* Completed unsuccessfully */
SVGA3D_QUERYSTATE_NEW = 3, /* Never submitted (guest only) */
} SVGA3dQueryState;
typedef enum {
SVGA3D_WRITE_HOST_VRAM = 1,
SVGA3D_READ_HOST_VRAM = 2,
} SVGA3dTransferType;
typedef struct {
typedef enum {
SVGA3D_LOGICOP_INVALID = 0,
SVGA3D_LOGICOP_MIN = 1,
SVGA3D_LOGICOP_COPY = 1,
SVGA3D_LOGICOP_NOT = 2,
SVGA3D_LOGICOP_AND = 3,
SVGA3D_LOGICOP_OR = 4,
SVGA3D_LOGICOP_XOR = 5,
SVGA3D_LOGICOP_NXOR = 6,
SVGA3D_LOGICOP_ROP3MIN = 30, /* 7-29 are reserved for future logic ops. */
SVGA3D_LOGICOP_ROP3MAX = (SVGA3D_LOGICOP_ROP3MIN + 255),
SVGA3D_LOGICOP_MAX = (SVGA3D_LOGICOP_ROP3MAX + 1),
} SVGA3dLogicOp;
typedef
#include "vmware_pack_begin.h"
struct {
union {
struct {
uint16 function; /* SVGA3dFogFunction */
uint8 type; /* SVGA3dFogType */
uint8 base; /* SVGA3dFogBase */
uint16 function; /* SVGA3dFogFunction */
uint8 type; /* SVGA3dFogType */
uint8 base; /* SVGA3dFogBase */
};
uint32 uintValue;
};
} SVGA3dFogMode;
}
#include "vmware_pack_end.h"
SVGA3dFogMode;
/*
* Uniquely identify one image (a 1D/2D/3D array) from a surface. This
......@@ -1256,1420 +1549,85 @@ typedef struct {
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dSurfaceImageId {
uint32 sid;
uint32 face;
uint32 mipmap;
} SVGA3dSurfaceImageId;
typedef
struct SVGA3dGuestImage {
SVGAGuestPtr ptr;
/*
* A note on interpretation of pitch: This value of pitch is the
* number of bytes between vertically adjacent image
* blocks. Normally this is the number of bytes between the first
* pixel of two adjacent scanlines. With compressed textures,
* however, this may represent the number of bytes between
* compression blocks rather than between rows of pixels.
*
* XXX: Compressed textures currently must be tightly packed in guest memory.
*
* If the image is 1-dimensional, pitch is ignored.
*
* If 'pitch' is zero, the SVGA3D device calculates a pitch value
* assuming each row of blocks is tightly packed.
*/
uint32 pitch;
} SVGA3dGuestImage;
/*
* FIFO command format definitions:
*/
/*
* The data size header following cmdNum for every 3d command
*/
typedef
struct {
uint32 id;
uint32 size;
} SVGA3dCmdHeader;
/*
* A surface is a hierarchy of host VRAM surfaces: 1D, 2D, or 3D, with
* optional mipmaps and cube faces.
*/
}
#include "vmware_pack_end.h"
SVGA3dSurfaceImageId;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 width;
uint32 height;
uint32 depth;
} SVGA3dSize;
}
#include "vmware_pack_end.h"
SVGA3dSize;
/*
* Guest-backed objects definitions.
*/
typedef enum {
SVGA3D_SURFACE_CUBEMAP = (1 << 0),
/*
* HINT flags are not enforced by the device but are useful for
* performance.
*/
SVGA3D_SURFACE_HINT_STATIC = (1 << 1),
SVGA3D_SURFACE_HINT_DYNAMIC = (1 << 2),
SVGA3D_SURFACE_HINT_INDEXBUFFER = (1 << 3),
SVGA3D_SURFACE_HINT_VERTEXBUFFER = (1 << 4),
SVGA3D_SURFACE_HINT_TEXTURE = (1 << 5),
SVGA3D_SURFACE_HINT_RENDERTARGET = (1 << 6),
SVGA3D_SURFACE_HINT_DEPTHSTENCIL = (1 << 7),
SVGA3D_SURFACE_HINT_WRITEONLY = (1 << 8),
SVGA3D_SURFACE_MASKABLE_ANTIALIAS = (1 << 9),
SVGA3D_SURFACE_AUTOGENMIPMAPS = (1 << 10),
SVGA3D_SURFACE_DECODE_RENDERTARGET = (1 << 11),
/*
* Is this surface using a base-level pitch for it's mob backing?
*
* This flag is not intended to be set by guest-drivers, but is instead
* set by the device when the surface is bound to a mob with a specified
* pitch.
*/
SVGA3D_SURFACE_MOB_PITCH = (1 << 12),
SVGA_OTABLE_MOB = 0,
SVGA_OTABLE_MIN = 0,
SVGA_OTABLE_SURFACE = 1,
SVGA_OTABLE_CONTEXT = 2,
SVGA_OTABLE_SHADER = 3,
SVGA_OTABLE_SCREENTARGET = 4,
SVGA3D_SURFACE_INACTIVE = (1 << 13),
SVGA3D_SURFACE_HINT_RT_LOCKABLE = (1 << 14),
SVGA3D_SURFACE_VOLUME = (1 << 15),
SVGA_OTABLE_DX9_MAX = 5,
/*
* Required to be set on a surface to bind it to a screen target.
*/
SVGA3D_SURFACE_SCREENTARGET = (1 << 16),
SVGA_OTABLE_DXCONTEXT = 5,
SVGA_OTABLE_MAX = 6
} SVGAOTableType;
/*
* Align images in the guest-backing mob to 16-bytes.
*/
SVGA3D_SURFACE_ALIGN16 = (1 << 17),
/*
* Deprecated.
*/
#define SVGA_OTABLE_COUNT 4
SVGA3D_SURFACE_1D = (1 << 18),
SVGA3D_SURFACE_ARRAY = (1 << 19),
/*
* Bind flags.
* These are enforced for any surface defined with DefineGBSurface_v2.
*/
SVGA3D_SURFACE_BIND_VERTEX_BUFFER = (1 << 20),
SVGA3D_SURFACE_BIND_INDEX_BUFFER = (1 << 21),
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER = (1 << 22),
SVGA3D_SURFACE_BIND_SHADER_RESOURCE = (1 << 23),
SVGA3D_SURFACE_BIND_RENDER_TARGET = (1 << 24),
SVGA3D_SURFACE_BIND_DEPTH_STENCIL = (1 << 25),
SVGA3D_SURFACE_BIND_STREAM_OUTPUT = (1 << 26),
/*
* Marker for the last defined bit.
*/
SVGA3D_SURFACE_FLAG_MAX = (1 << 27),
} SVGA3dSurfaceFlags;
typedef
struct {
uint32 numMipLevels;
} SVGA3dSurfaceFace;
typedef
struct {
uint32 sid;
SVGA3dSurfaceFlags surfaceFlags;
SVGA3dSurfaceFormat format;
/*
* If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
* structures must have the same value of numMipLevels field.
* Otherwise, all but the first SVGA3dSurfaceFace structures must have the
* numMipLevels set to 0.
*/
SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
/*
* Followed by an SVGA3dSize structure for each mip level in each face.
*
* A note on surface sizes: Sizes are always specified in pixels,
* even if the true surface size is not a multiple of the minimum
* block size of the surface's format. For example, a 3x3x1 DXT1
* compressed texture would actually be stored as a 4x4x1 image in
* memory.
*/
} SVGA3dCmdDefineSurface; /* SVGA_3D_CMD_SURFACE_DEFINE */
typedef
struct {
uint32 sid;
SVGA3dSurfaceFlags surfaceFlags;
SVGA3dSurfaceFormat format;
/*
* If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
* structures must have the same value of numMipLevels field.
* Otherwise, all but the first SVGA3dSurfaceFace structures must have the
* numMipLevels set to 0.
*/
SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
uint32 multisampleCount;
SVGA3dTextureFilter autogenFilter;
/*
* Followed by an SVGA3dSize structure for each mip level in each face.
*
* A note on surface sizes: Sizes are always specified in pixels,
* even if the true surface size is not a multiple of the minimum
* block size of the surface's format. For example, a 3x3x1 DXT1
* compressed texture would actually be stored as a 4x4x1 image in
* memory.
*/
} SVGA3dCmdDefineSurface_v2; /* SVGA_3D_CMD_SURFACE_DEFINE_V2 */
typedef
struct {
uint32 sid;
} SVGA3dCmdDestroySurface; /* SVGA_3D_CMD_SURFACE_DESTROY */
typedef
struct {
uint32 cid;
} SVGA3dCmdDefineContext; /* SVGA_3D_CMD_CONTEXT_DEFINE */
typedef
struct {
uint32 cid;
} SVGA3dCmdDestroyContext; /* SVGA_3D_CMD_CONTEXT_DESTROY */
typedef
struct {
uint32 cid;
SVGA3dClearFlag clearFlag;
uint32 color;
float depth;
uint32 stencil;
/* Followed by variable number of SVGA3dRect structures */
} SVGA3dCmdClear; /* SVGA_3D_CMD_CLEAR */
typedef
struct SVGA3dCopyRect {
uint32 x;
uint32 y;
uint32 w;
uint32 h;
uint32 srcx;
uint32 srcy;
} SVGA3dCopyRect;
typedef
struct SVGA3dCopyBox {
uint32 x;
uint32 y;
uint32 z;
uint32 w;
uint32 h;
uint32 d;
uint32 srcx;
uint32 srcy;
uint32 srcz;
} SVGA3dCopyBox;
typedef
struct {
uint32 x;
uint32 y;
uint32 w;
uint32 h;
} SVGA3dRect;
typedef
struct {
uint32 x;
uint32 y;
uint32 z;
uint32 w;
uint32 h;
uint32 d;
} SVGA3dBox;
typedef
struct {
uint32 x;
uint32 y;
uint32 z;
} SVGA3dPoint;
typedef
struct {
SVGA3dLightType type;
SVGA3dBool inWorldSpace;
float diffuse[4];
float specular[4];
float ambient[4];
float position[4];
float direction[4];
float range;
float falloff;
float attenuation0;
float attenuation1;
float attenuation2;
float theta;
float phi;
} SVGA3dLightData;
typedef
struct {
uint32 sid;
/* Followed by variable number of SVGA3dCopyRect structures */
} SVGA3dCmdPresent; /* SVGA_3D_CMD_PRESENT */
typedef
struct {
SVGA3dRenderStateName state;
union {
uint32 uintValue;
float floatValue;
};
} SVGA3dRenderState;
typedef
struct {
uint32 cid;
/* Followed by variable number of SVGA3dRenderState structures */
} SVGA3dCmdSetRenderState; /* SVGA_3D_CMD_SETRENDERSTATE */
typedef
struct {
uint32 cid;
SVGA3dRenderTargetType type;
SVGA3dSurfaceImageId target;
} SVGA3dCmdSetRenderTarget; /* SVGA_3D_CMD_SETRENDERTARGET */
typedef
struct {
SVGA3dSurfaceImageId src;
SVGA3dSurfaceImageId dest;
/* Followed by variable number of SVGA3dCopyBox structures */
} SVGA3dCmdSurfaceCopy; /* SVGA_3D_CMD_SURFACE_COPY */
typedef
struct {
SVGA3dSurfaceImageId src;
SVGA3dSurfaceImageId dest;
SVGA3dBox boxSrc;
SVGA3dBox boxDest;
SVGA3dStretchBltMode mode;
} SVGA3dCmdSurfaceStretchBlt; /* SVGA_3D_CMD_SURFACE_STRETCHBLT */
typedef
struct {
/*
* If the discard flag is present in a surface DMA operation, the host may
* discard the contents of the current mipmap level and face of the target
* surface before applying the surface DMA contents.
*/
uint32 discard : 1;
/*
* If the unsynchronized flag is present, the host may perform this upload
* without syncing to pending reads on this surface.
*/
uint32 unsynchronized : 1;
/*
* Guests *MUST* set the reserved bits to 0 before submitting the command
* suffix as future flags may occupy these bits.
*/
uint32 reserved : 30;
} SVGA3dSurfaceDMAFlags;
typedef
struct {
SVGA3dGuestImage guest;
SVGA3dSurfaceImageId host;
SVGA3dTransferType transfer;
/*
* Followed by variable number of SVGA3dCopyBox structures. For consistency
* in all clipping logic and coordinate translation, we define the
* "source" in each copyBox as the guest image and the
* "destination" as the host image, regardless of transfer
* direction.
*
* For efficiency, the SVGA3D device is free to copy more data than
* specified. For example, it may round copy boxes outwards such
* that they lie on particular alignment boundaries.
*/
} SVGA3dCmdSurfaceDMA; /* SVGA_3D_CMD_SURFACE_DMA */
/*
* SVGA3dCmdSurfaceDMASuffix --
*
* This is a command suffix that will appear after a SurfaceDMA command in
* the FIFO. It contains some extra information that hosts may use to
* optimize performance or protect the guest. This suffix exists to preserve
* backwards compatibility while also allowing for new functionality to be
* implemented.
*/
typedef
struct {
uint32 suffixSize;
/*
* The maximum offset is used to determine the maximum offset from the
* guestPtr base address that will be accessed or written to during this
* surfaceDMA. If the suffix is supported, the host will respect this
* boundary while performing surface DMAs.
*
* Defaults to MAX_UINT32
*/
uint32 maximumOffset;
/*
* A set of flags that describes optimizations that the host may perform
* while performing this surface DMA operation. The guest should never rely
* on behaviour that is different when these flags are set for correctness.
*
* Defaults to 0
*/
SVGA3dSurfaceDMAFlags flags;
} SVGA3dCmdSurfaceDMASuffix;
/*
* SVGA_3D_CMD_DRAW_PRIMITIVES --
*
* This command is the SVGA3D device's generic drawing entry point.
* It can draw multiple ranges of primitives, optionally using an
* index buffer, using an arbitrary collection of vertex buffers.
*
* Each SVGA3dVertexDecl defines a distinct vertex array to bind
* during this draw call. The declarations specify which surface
* the vertex data lives in, what that vertex data is used for,
* and how to interpret it.
*
* Each SVGA3dPrimitiveRange defines a collection of primitives
* to render using the same vertex arrays. An index buffer is
* optional.
*/
typedef
struct {
/*
* A range hint is an optional specification for the range of indices
* in an SVGA3dArray that will be used. If 'last' is zero, it is assumed
* that the entire array will be used.
*
* These are only hints. The SVGA3D device may use them for
* performance optimization if possible, but it's also allowed to
* ignore these values.
*/
uint32 first;
uint32 last;
} SVGA3dArrayRangeHint;
typedef
struct {
/*
* Define the origin and shape of a vertex or index array. Both
* 'offset' and 'stride' are in bytes. The provided surface will be
* reinterpreted as a flat array of bytes in the same format used
* by surface DMA operations. To avoid unnecessary conversions, the
* surface should be created with the SVGA3D_BUFFER format.
*
* Index 0 in the array starts 'offset' bytes into the surface.
* Index 1 begins at byte 'offset + stride', etc. Array indices may
* not be negative.
*/
uint32 surfaceId;
uint32 offset;
uint32 stride;
} SVGA3dArray;
typedef
struct {
/*
* Describe a vertex array's data type, and define how it is to be
* used by the fixed function pipeline or the vertex shader. It
* isn't useful to have two VertexDecls with the same
* VertexArrayIdentity in one draw call.
*/
SVGA3dDeclType type;
SVGA3dDeclMethod method;
SVGA3dDeclUsage usage;
uint32 usageIndex;
} SVGA3dVertexArrayIdentity;
typedef
struct {
SVGA3dVertexArrayIdentity identity;
SVGA3dArray array;
SVGA3dArrayRangeHint rangeHint;
} SVGA3dVertexDecl;
typedef
struct {
/*
* Define a group of primitives to render, from sequential indices.
*
* The value of 'primitiveType' and 'primitiveCount' imply the
* total number of vertices that will be rendered.
*/
SVGA3dPrimitiveType primType;
uint32 primitiveCount;
/*
* Optional index buffer. If indexArray.surfaceId is
* SVGA3D_INVALID_ID, we render without an index buffer. Rendering
* without an index buffer is identical to rendering with an index
* buffer containing the sequence [0, 1, 2, 3, ...].
*
* If an index buffer is in use, indexWidth specifies the width in
* bytes of each index value. It must be less than or equal to
* indexArray.stride.
*
* (Currently, the SVGA3D device requires index buffers to be tightly
* packed. In other words, indexWidth == indexArray.stride)
*/
SVGA3dArray indexArray;
uint32 indexWidth;
/*
* Optional index bias. This number is added to all indices from
* indexArray before they are used as vertex array indices. This
* can be used in multiple ways:
*
* - When not using an indexArray, this bias can be used to
* specify where in the vertex arrays to begin rendering.
*
* - A positive number here is equivalent to increasing the
* offset in each vertex array.
*
* - A negative number can be used to render using a small
* vertex array and an index buffer that contains large
* values. This may be used by some applications that
* crop a vertex buffer without modifying their index
* buffer.
*
* Note that rendering with a negative bias value may be slower and
* use more memory than rendering with a positive or zero bias.
*/
int32 indexBias;
} SVGA3dPrimitiveRange;
typedef
struct {
uint32 cid;
uint32 numVertexDecls;
uint32 numRanges;
/*
* There are two variable size arrays after the
* SVGA3dCmdDrawPrimitives structure. In order,
* they are:
*
* 1. SVGA3dVertexDecl, quantity 'numVertexDecls', but no more than
* SVGA3D_MAX_VERTEX_ARRAYS;
* 2. SVGA3dPrimitiveRange, quantity 'numRanges', but no more than
* SVGA3D_MAX_DRAW_PRIMITIVE_RANGES;
* 3. Optionally, SVGA3dVertexDivisor, quantity 'numVertexDecls' (contains
* the frequency divisor for the corresponding vertex decl).
*/
} SVGA3dCmdDrawPrimitives; /* SVGA_3D_CMD_DRAWPRIMITIVES */
typedef
struct {
uint32 stage;
SVGA3dTextureStateName name;
union {
uint32 value;
float floatValue;
};
} SVGA3dTextureState;
typedef
struct {
uint32 cid;
/* Followed by variable number of SVGA3dTextureState structures */
} SVGA3dCmdSetTextureState; /* SVGA_3D_CMD_SETTEXTURESTATE */
typedef
struct {
uint32 cid;
SVGA3dTransformType type;
float matrix[16];
} SVGA3dCmdSetTransform; /* SVGA_3D_CMD_SETTRANSFORM */
typedef
struct {
float min;
float max;
} SVGA3dZRange;
typedef
struct {
uint32 cid;
SVGA3dZRange zRange;
} SVGA3dCmdSetZRange; /* SVGA_3D_CMD_SETZRANGE */
typedef
struct {
float diffuse[4];
float ambient[4];
float specular[4];
float emissive[4];
float shininess;
} SVGA3dMaterial;
typedef
struct {
uint32 cid;
SVGA3dFace face;
SVGA3dMaterial material;
} SVGA3dCmdSetMaterial; /* SVGA_3D_CMD_SETMATERIAL */
typedef
struct {
uint32 cid;
uint32 index;
SVGA3dLightData data;
} SVGA3dCmdSetLightData; /* SVGA_3D_CMD_SETLIGHTDATA */
typedef
struct {
uint32 cid;
uint32 index;
uint32 enabled;
} SVGA3dCmdSetLightEnabled; /* SVGA_3D_CMD_SETLIGHTENABLED */
typedef
struct {
uint32 cid;
SVGA3dRect rect;
} SVGA3dCmdSetViewport; /* SVGA_3D_CMD_SETVIEWPORT */
typedef
struct {
uint32 cid;
SVGA3dRect rect;
} SVGA3dCmdSetScissorRect; /* SVGA_3D_CMD_SETSCISSORRECT */
typedef
struct {
uint32 cid;
uint32 index;
float plane[4];
} SVGA3dCmdSetClipPlane; /* SVGA_3D_CMD_SETCLIPPLANE */
typedef
struct {
uint32 cid;
uint32 shid;
SVGA3dShaderType type;
/* Followed by variable number of DWORDs for shader bycode */
} SVGA3dCmdDefineShader; /* SVGA_3D_CMD_SHADER_DEFINE */
typedef
struct {
uint32 cid;
uint32 shid;
SVGA3dShaderType type;
} SVGA3dCmdDestroyShader; /* SVGA_3D_CMD_SHADER_DESTROY */
typedef
struct {
uint32 cid;
uint32 reg; /* register number */
SVGA3dShaderType type;
SVGA3dShaderConstType ctype;
uint32 values[4];
} SVGA3dCmdSetShaderConst; /* SVGA_3D_CMD_SET_SHADER_CONST */
typedef
struct {
uint32 cid;
SVGA3dShaderType type;
uint32 shid;
} SVGA3dCmdSetShader; /* SVGA_3D_CMD_SET_SHADER */
typedef
struct {
uint32 cid;
SVGA3dQueryType type;
} SVGA3dCmdBeginQuery; /* SVGA_3D_CMD_BEGIN_QUERY */
typedef
struct {
uint32 cid;
SVGA3dQueryType type;
SVGAGuestPtr guestResult; /* Points to an SVGA3dQueryResult structure */
} SVGA3dCmdEndQuery; /* SVGA_3D_CMD_END_QUERY */
typedef
struct {
uint32 cid; /* Same parameters passed to END_QUERY */
SVGA3dQueryType type;
SVGAGuestPtr guestResult;
} SVGA3dCmdWaitForQuery; /* SVGA_3D_CMD_WAIT_FOR_QUERY */
typedef
struct {
uint32 totalSize; /* Set by guest before query is ended. */
SVGA3dQueryState state; /* Set by host or guest. See SVGA3dQueryState. */
union { /* Set by host on exit from PENDING state */
uint32 result32;
};
} SVGA3dQueryResult;
/*
* SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN --
*
* This is a blit from an SVGA3D surface to a Screen Object. Just
* like GMR-to-screen blits, this blit may be directed at a
* specific screen or to the virtual coordinate space.
*
* The blit copies from a rectangular region of an SVGA3D surface
* image to a rectangular region of a screen or screens.
*
* This command takes an optional variable-length list of clipping
* rectangles after the body of the command. If no rectangles are
* specified, there is no clipping region. The entire destRect is
* drawn to. If one or more rectangles are included, they describe
* a clipping region. The clip rectangle coordinates are measured
* relative to the top-left corner of destRect.
*
* This clipping region serves multiple purposes:
*
* - It can be used to perform an irregularly shaped blit more
* efficiently than by issuing many separate blit commands.
*
* - It is equivalent to allowing blits with non-integer
* source coordinates. You could blit just one half-pixel
* of a source, for example, by specifying a larger
* destination rectangle than you need, then removing
* part of it using a clip rectangle.
*
* Availability:
* SVGA_FIFO_CAP_SCREEN_OBJECT
*
* Limitations:
*
* - Currently, no backend supports blits from a mipmap or face
* other than the first one.
*/
typedef
struct {
SVGA3dSurfaceImageId srcImage;
SVGASignedRect srcRect;
uint32 destScreenId; /* Screen ID or SVGA_ID_INVALID for virt. coords */
SVGASignedRect destRect; /* Supports scaling if src/rest different size */
/* Clipping: zero or more SVGASignedRects follow */
} SVGA3dCmdBlitSurfaceToScreen; /* SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN */
typedef
struct {
uint32 sid;
SVGA3dTextureFilter filter;
} SVGA3dCmdGenerateMipmaps; /* SVGA_3D_CMD_GENERATE_MIPMAPS */
/*
* Guest-backed surface definitions.
*/
typedef enum {
SVGA_COTABLE_MIN = 0,
SVGA_COTABLE_RTVIEW = 0,
SVGA_COTABLE_DSVIEW = 1,
SVGA_COTABLE_SRVIEW = 2,
SVGA_COTABLE_ELEMENTLAYOUT = 3,
SVGA_COTABLE_BLENDSTATE = 4,
SVGA_COTABLE_DEPTHSTENCIL = 5,
SVGA_COTABLE_RASTERIZERSTATE = 6,
SVGA_COTABLE_SAMPLER = 7,
SVGA_COTABLE_STREAMOUTPUT = 8,
SVGA_COTABLE_DXQUERY = 9,
SVGA_COTABLE_DXSHADER = 10,
SVGA_COTABLE_DX10_MAX = 11,
SVGA_COTABLE_UAVIEW = 11,
SVGA_COTABLE_MAX
} SVGACOTableType;
/*
* The largest size (number of entries) allowed in a COTable.
*/
#define SVGA_COTABLE_MAX_IDS (MAX_UINT16 - 2)
typedef enum SVGAMobFormat {
SVGA3D_MOBFMT_INVALID = SVGA3D_INVALID_ID,
SVGA3D_MOBFMT_PTDEPTH_0 = 0,
SVGA3D_MOBFMT_PTDEPTH_1 = 1,
SVGA3D_MOBFMT_PTDEPTH_2 = 2,
SVGA3D_MOBFMT_RANGE = 3,
SVGA3D_MOBFMT_INVALID = SVGA3D_INVALID_ID,
SVGA3D_MOBFMT_PTDEPTH_0 = 0,
SVGA3D_MOBFMT_MIN = 0,
SVGA3D_MOBFMT_PTDEPTH_1 = 1,
SVGA3D_MOBFMT_PTDEPTH_2 = 2,
SVGA3D_MOBFMT_RANGE = 3,
SVGA3D_MOBFMT_PTDEPTH64_0 = 4,
SVGA3D_MOBFMT_PTDEPTH64_1 = 5,
SVGA3D_MOBFMT_PTDEPTH64_2 = 6,
SVGA3D_MOBFMT_PREDX_MAX = 7,
SVGA3D_MOBFMT_EMPTY = 7,
SVGA3D_MOBFMT_MAX,
} SVGAMobFormat;
/*
* Sizes of opaque types.
*/
#define SVGA3D_OTABLE_MOB_ENTRY_SIZE 16
#define SVGA3D_OTABLE_CONTEXT_ENTRY_SIZE 8
#define SVGA3D_OTABLE_SURFACE_ENTRY_SIZE 64
#define SVGA3D_OTABLE_SHADER_ENTRY_SIZE 16
#define SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE 64
#define SVGA3D_CONTEXT_DATA_SIZE 16384
/*
* SVGA3dCmdSetOTableBase --
*
* This command allows the guest to specify the base PPN of the
* specified object table.
*/
typedef enum {
SVGA_OTABLE_MOB = 0,
SVGA_OTABLE_MIN = 0,
SVGA_OTABLE_SURFACE = 1,
SVGA_OTABLE_CONTEXT = 2,
SVGA_OTABLE_SHADER = 3,
SVGA_OTABLE_SCREEN_TARGET = 4,
SVGA_OTABLE_DX9_MAX = 5,
SVGA_OTABLE_MAX = 8
} SVGAOTableType;
typedef
struct {
SVGAOTableType type;
PPN baseAddress;
uint32 sizeInBytes;
uint32 validSizeInBytes;
SVGAMobFormat ptDepth;
} __packed
SVGA3dCmdSetOTableBase; /* SVGA_3D_CMD_SET_OTABLE_BASE */
typedef
struct {
SVGAOTableType type;
PPN64 baseAddress;
uint32 sizeInBytes;
uint32 validSizeInBytes;
SVGAMobFormat ptDepth;
} __packed
SVGA3dCmdSetOTableBase64; /* SVGA_3D_CMD_SET_OTABLE_BASE64 */
typedef
struct {
SVGAOTableType type;
} __packed
SVGA3dCmdReadbackOTable; /* SVGA_3D_CMD_READBACK_OTABLE */
/*
* Define a memory object (Mob) in the OTable.
*/
typedef
struct SVGA3dCmdDefineGBMob {
SVGAMobId mobid;
SVGAMobFormat ptDepth;
PPN base;
uint32 sizeInBytes;
} __packed
SVGA3dCmdDefineGBMob; /* SVGA_3D_CMD_DEFINE_GB_MOB */
/*
* Destroys an object in the OTable.
*/
typedef
struct SVGA3dCmdDestroyGBMob {
SVGAMobId mobid;
} __packed
SVGA3dCmdDestroyGBMob; /* SVGA_3D_CMD_DESTROY_GB_MOB */
/*
* Redefine an object in the OTable.
*/
typedef
struct SVGA3dCmdRedefineGBMob {
SVGAMobId mobid;
SVGAMobFormat ptDepth;
PPN base;
uint32 sizeInBytes;
} __packed
SVGA3dCmdRedefineGBMob; /* SVGA_3D_CMD_REDEFINE_GB_MOB */
/*
* Define a memory object (Mob) in the OTable with a PPN64 base.
*/
typedef
struct SVGA3dCmdDefineGBMob64 {
SVGAMobId mobid;
SVGAMobFormat ptDepth;
PPN64 base;
uint32 sizeInBytes;
} __packed
SVGA3dCmdDefineGBMob64; /* SVGA_3D_CMD_DEFINE_GB_MOB64 */
/*
* Redefine an object in the OTable with PPN64 base.
*/
typedef
struct SVGA3dCmdRedefineGBMob64 {
SVGAMobId mobid;
SVGAMobFormat ptDepth;
PPN64 base;
uint32 sizeInBytes;
} __packed
SVGA3dCmdRedefineGBMob64; /* SVGA_3D_CMD_REDEFINE_GB_MOB64 */
/*
* Notification that the page tables have been modified.
*/
typedef
struct SVGA3dCmdUpdateGBMobMapping {
SVGAMobId mobid;
} __packed
SVGA3dCmdUpdateGBMobMapping; /* SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING */
/*
* Define a guest-backed surface.
*/
typedef
struct SVGA3dCmdDefineGBSurface {
uint32 sid;
SVGA3dSurfaceFlags surfaceFlags;
SVGA3dSurfaceFormat format;
uint32 numMipLevels;
uint32 multisampleCount;
SVGA3dTextureFilter autogenFilter;
SVGA3dSize size;
} __packed
SVGA3dCmdDefineGBSurface; /* SVGA_3D_CMD_DEFINE_GB_SURFACE */
/*
* Destroy a guest-backed surface.
*/
typedef
struct SVGA3dCmdDestroyGBSurface {
uint32 sid;
} __packed
SVGA3dCmdDestroyGBSurface; /* SVGA_3D_CMD_DESTROY_GB_SURFACE */
/*
* Bind a guest-backed surface to an object.
*/
typedef
struct SVGA3dCmdBindGBSurface {
uint32 sid;
SVGAMobId mobid;
} __packed
SVGA3dCmdBindGBSurface; /* SVGA_3D_CMD_BIND_GB_SURFACE */
/*
* Conditionally bind a mob to a guest backed surface if testMobid
* matches the currently bound mob. Optionally issue a readback on
* the surface while it is still bound to the old mobid if the mobid
* is changed by this command.
*/
#define SVGA3D_COND_BIND_GB_SURFACE_FLAG_READBACK (1 << 0)
typedef
struct{
uint32 sid;
SVGAMobId testMobid;
SVGAMobId mobid;
uint32 flags;
} __packed
SVGA3dCmdCondBindGBSurface; /* SVGA_3D_CMD_COND_BIND_GB_SURFACE */
/*
* Update an image in a guest-backed surface.
* (Inform the device that the guest-contents have been updated.)
*/
typedef
struct SVGA3dCmdUpdateGBImage {
SVGA3dSurfaceImageId image;
SVGA3dBox box;
} __packed
SVGA3dCmdUpdateGBImage; /* SVGA_3D_CMD_UPDATE_GB_IMAGE */
/*
* Update an entire guest-backed surface.
* (Inform the device that the guest-contents have been updated.)
*/
typedef
struct SVGA3dCmdUpdateGBSurface {
uint32 sid;
} __packed
SVGA3dCmdUpdateGBSurface; /* SVGA_3D_CMD_UPDATE_GB_SURFACE */
/*
* Readback an image in a guest-backed surface.
* (Request the device to flush the dirty contents into the guest.)
*/
typedef
struct SVGA3dCmdReadbackGBImage {
SVGA3dSurfaceImageId image;
} __packed
SVGA3dCmdReadbackGBImage; /* SVGA_3D_CMD_READBACK_GB_IMAGE*/
/*
* Readback an entire guest-backed surface.
* (Request the device to flush the dirty contents into the guest.)
*/
typedef
struct SVGA3dCmdReadbackGBSurface {
uint32 sid;
} __packed
SVGA3dCmdReadbackGBSurface; /* SVGA_3D_CMD_READBACK_GB_SURFACE */
/*
* Readback a sub rect of an image in a guest-backed surface. After
* issuing this command the driver is required to issue an update call
* of the same region before issuing any other commands that reference
* this surface or rendering is not guaranteed.
*/
typedef
struct SVGA3dCmdReadbackGBImagePartial {
SVGA3dSurfaceImageId image;
SVGA3dBox box;
uint32 invertBox;
} __packed
SVGA3dCmdReadbackGBImagePartial; /* SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL */
/*
* Invalidate an image in a guest-backed surface.
* (Notify the device that the contents can be lost.)
*/
typedef
struct SVGA3dCmdInvalidateGBImage {
SVGA3dSurfaceImageId image;
} __packed
SVGA3dCmdInvalidateGBImage; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE */
/*
* Invalidate an entire guest-backed surface.
* (Notify the device that the contents if all images can be lost.)
*/
typedef
struct SVGA3dCmdInvalidateGBSurface {
uint32 sid;
} __packed
SVGA3dCmdInvalidateGBSurface; /* SVGA_3D_CMD_INVALIDATE_GB_SURFACE */
/*
* Invalidate a sub rect of an image in a guest-backed surface. After
* issuing this command the driver is required to issue an update call
* of the same region before issuing any other commands that reference
* this surface or rendering is not guaranteed.
*/
typedef
struct SVGA3dCmdInvalidateGBImagePartial {
SVGA3dSurfaceImageId image;
SVGA3dBox box;
uint32 invertBox;
} __packed
SVGA3dCmdInvalidateGBImagePartial; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL */
/*
* Define a guest-backed context.
*/
typedef
struct SVGA3dCmdDefineGBContext {
uint32 cid;
} __packed
SVGA3dCmdDefineGBContext; /* SVGA_3D_CMD_DEFINE_GB_CONTEXT */
/*
* Destroy a guest-backed context.
*/
typedef
struct SVGA3dCmdDestroyGBContext {
uint32 cid;
} __packed
SVGA3dCmdDestroyGBContext; /* SVGA_3D_CMD_DESTROY_GB_CONTEXT */
/*
* Bind a guest-backed context.
*
* validContents should be set to 0 for new contexts,
* and 1 if this is an old context which is getting paged
* back on to the device.
*
* For new contexts, it is recommended that the driver
* issue commands to initialize all interesting state
* prior to rendering.
*/
typedef
struct SVGA3dCmdBindGBContext {
uint32 cid;
SVGAMobId mobid;
uint32 validContents;
} __packed
SVGA3dCmdBindGBContext; /* SVGA_3D_CMD_BIND_GB_CONTEXT */
/*
* Readback a guest-backed context.
* (Request that the device flush the contents back into guest memory.)
*/
typedef
struct SVGA3dCmdReadbackGBContext {
uint32 cid;
} __packed
SVGA3dCmdReadbackGBContext; /* SVGA_3D_CMD_READBACK_GB_CONTEXT */
/*
* Invalidate a guest-backed context.
*/
typedef
struct SVGA3dCmdInvalidateGBContext {
uint32 cid;
} __packed
SVGA3dCmdInvalidateGBContext; /* SVGA_3D_CMD_INVALIDATE_GB_CONTEXT */
/*
* Define a guest-backed shader.
*/
typedef
struct SVGA3dCmdDefineGBShader {
uint32 shid;
SVGA3dShaderType type;
uint32 sizeInBytes;
} __packed
SVGA3dCmdDefineGBShader; /* SVGA_3D_CMD_DEFINE_GB_SHADER */
/*
* Bind a guest-backed shader.
*/
typedef struct SVGA3dCmdBindGBShader {
uint32 shid;
SVGAMobId mobid;
uint32 offsetInBytes;
} __packed
SVGA3dCmdBindGBShader; /* SVGA_3D_CMD_BIND_GB_SHADER */
/*
* Destroy a guest-backed shader.
*/
typedef struct SVGA3dCmdDestroyGBShader {
uint32 shid;
} __packed
SVGA3dCmdDestroyGBShader; /* SVGA_3D_CMD_DESTROY_GB_SHADER */
typedef
struct {
uint32 cid;
uint32 regStart;
SVGA3dShaderType shaderType;
SVGA3dShaderConstType constType;
/*
* Followed by a variable number of shader constants.
*
* Note that FLOAT and INT constants are 4-dwords in length, while
* BOOL constants are 1-dword in length.
*/
} __packed
SVGA3dCmdSetGBShaderConstInline;
/* SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE */
typedef
struct {
uint32 cid;
SVGA3dQueryType type;
} __packed
SVGA3dCmdBeginGBQuery; /* SVGA_3D_CMD_BEGIN_GB_QUERY */
typedef
struct {
uint32 cid;
SVGA3dQueryType type;
SVGAMobId mobid;
uint32 offset;
} __packed
SVGA3dCmdEndGBQuery; /* SVGA_3D_CMD_END_GB_QUERY */
/*
* SVGA_3D_CMD_WAIT_FOR_GB_QUERY --
*
* The semantics of this command are identical to the
* SVGA_3D_CMD_WAIT_FOR_QUERY except that the results are written
* to a Mob instead of a GMR.
*/
typedef
struct {
uint32 cid;
SVGA3dQueryType type;
SVGAMobId mobid;
uint32 offset;
} __packed
SVGA3dCmdWaitForGBQuery; /* SVGA_3D_CMD_WAIT_FOR_GB_QUERY */
typedef
struct {
SVGAMobId mobid;
uint32 fbOffset;
uint32 initalized;
} __packed
SVGA3dCmdEnableGart; /* SVGA_3D_CMD_ENABLE_GART */
typedef
struct {
SVGAMobId mobid;
uint32 gartOffset;
} __packed
SVGA3dCmdMapMobIntoGart; /* SVGA_3D_CMD_MAP_MOB_INTO_GART */
typedef
struct {
uint32 gartOffset;
uint32 numPages;
} __packed
SVGA3dCmdUnmapGartRange; /* SVGA_3D_CMD_UNMAP_GART_RANGE */
/*
* Screen Targets
*/
#define SVGA_STFLAG_PRIMARY (1 << 0)
typedef
struct {
uint32 stid;
uint32 width;
uint32 height;
int32 xRoot;
int32 yRoot;
uint32 flags;
uint32 dpi;
} __packed
SVGA3dCmdDefineGBScreenTarget; /* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET */
typedef
struct {
uint32 stid;
} __packed
SVGA3dCmdDestroyGBScreenTarget; /* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET */
typedef
struct {
uint32 stid;
SVGA3dSurfaceImageId image;
} __packed
SVGA3dCmdBindGBScreenTarget; /* SVGA_3D_CMD_BIND_GB_SCREENTARGET */
typedef
struct {
uint32 stid;
SVGA3dRect rect;
} __packed
SVGA3dCmdUpdateGBScreenTarget; /* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET */
/*
* Capability query index.
*
* Notes:
*
* 1. SVGA3D_DEVCAP_MAX_TEXTURES reflects the maximum number of
* fixed-function texture units available. Each of these units
* work in both FFP and Shader modes, and they support texture
* transforms and texture coordinates. The host may have additional
* texture image units that are only usable with shaders.
*
* 2. The BUFFER_FORMAT capabilities are deprecated, and they always
* return TRUE. Even on physical hardware that does not support
* these formats natively, the SVGA3D device will provide an emulation
* which should be invisible to the guest OS.
*
* In general, the SVGA3D device should support any operation on
* any surface format, it just may perform some of these
* operations in software depending on the capabilities of the
* available physical hardware.
*
* XXX: In the future, we will add capabilities that describe in
* detail what formats are supported in hardware for what kinds
* of operations.
*/
typedef enum {
SVGA3D_DEVCAP_3D = 0,
SVGA3D_DEVCAP_MAX_LIGHTS = 1,
SVGA3D_DEVCAP_MAX_TEXTURES = 2, /* See note (1) */
SVGA3D_DEVCAP_MAX_CLIP_PLANES = 3,
SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = 4,
SVGA3D_DEVCAP_VERTEX_SHADER = 5,
SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = 6,
SVGA3D_DEVCAP_FRAGMENT_SHADER = 7,
SVGA3D_DEVCAP_MAX_RENDER_TARGETS = 8,
SVGA3D_DEVCAP_S23E8_TEXTURES = 9,
SVGA3D_DEVCAP_S10E5_TEXTURES = 10,
SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = 11,
SVGA3D_DEVCAP_D16_BUFFER_FORMAT = 12, /* See note (2) */
SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = 13, /* See note (2) */
SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = 14, /* See note (2) */
SVGA3D_DEVCAP_QUERY_TYPES = 15,
SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = 16,
SVGA3D_DEVCAP_MAX_POINT_SIZE = 17,
SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = 18,
SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = 19,
SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = 20,
SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = 21,
SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = 22,
SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = 23,
SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = 24,
SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = 25,
SVGA3D_DEVCAP_MAX_VERTEX_INDEX = 26,
SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = 27,
SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = 28,
SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = 29,
SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = 30,
SVGA3D_DEVCAP_TEXTURE_OPS = 31,
SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = 32,
SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = 33,
SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = 34,
SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = 35,
SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = 36,
SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = 37,
SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = 38,
SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = 39,
SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = 40,
SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = 41,
SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = 42,
SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = 43,
SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = 44,
SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = 45,
SVGA3D_DEVCAP_SURFACEFMT_DXT1 = 46,
SVGA3D_DEVCAP_SURFACEFMT_DXT2 = 47,
SVGA3D_DEVCAP_SURFACEFMT_DXT3 = 48,
SVGA3D_DEVCAP_SURFACEFMT_DXT4 = 49,
SVGA3D_DEVCAP_SURFACEFMT_DXT5 = 50,
SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = 51,
SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = 52,
SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = 53,
SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = 54,
SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = 55,
SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = 56,
SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = 57,
SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = 58,
SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = 59,
SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = 60,
SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = 61,
SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = 63,
/*
* Note that MAX_SIMULTANEOUS_RENDER_TARGETS is a maximum count of color
* render targets. This does no include the depth or stencil targets.
*/
SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = 64,
SVGA3D_DEVCAP_SURFACEFMT_V16U16 = 65,
SVGA3D_DEVCAP_SURFACEFMT_G16R16 = 66,
SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = 67,
SVGA3D_DEVCAP_SURFACEFMT_UYVY = 68,
SVGA3D_DEVCAP_SURFACEFMT_YUY2 = 69,
SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = 70,
SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = 71,
SVGA3D_DEVCAP_ALPHATOCOVERAGE = 72,
SVGA3D_DEVCAP_SUPERSAMPLE = 73,
SVGA3D_DEVCAP_AUTOGENMIPMAPS = 74,
SVGA3D_DEVCAP_SURFACEFMT_NV12 = 75,
SVGA3D_DEVCAP_SURFACEFMT_AYUV = 76,
/*
* This is the maximum number of SVGA context IDs that the guest
* can define using SVGA_3D_CMD_CONTEXT_DEFINE.
*/
SVGA3D_DEVCAP_MAX_CONTEXT_IDS = 77,
/*
* This is the maximum number of SVGA surface IDs that the guest
* can define using SVGA_3D_CMD_SURFACE_DEFINE*.
*/
SVGA3D_DEVCAP_MAX_SURFACE_IDS = 78,
SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = 79,
SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = 80,
SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = 81,
SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = 82,
SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = 83,
/*
* Deprecated.
*/
SVGA3D_DEVCAP_VGPU10 = 84,
/*
* This contains several SVGA_3D_CAPS_VIDEO_DECODE elements
* ored together, one for every type of video decoding supported.
*/
SVGA3D_DEVCAP_VIDEO_DECODE = 85,
/*
* This contains several SVGA_3D_CAPS_VIDEO_PROCESS elements
* ored together, one for every type of video processing supported.
*/
SVGA3D_DEVCAP_VIDEO_PROCESS = 86,
SVGA3D_DEVCAP_LINE_AA = 87, /* boolean */
SVGA3D_DEVCAP_LINE_STIPPLE = 88, /* boolean */
SVGA3D_DEVCAP_MAX_LINE_WIDTH = 89, /* float */
SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH = 90, /* float */
SVGA3D_DEVCAP_SURFACEFMT_YV12 = 91,
/*
* Does the host support the SVGA logic ops commands?
*/
SVGA3D_DEVCAP_LOGICOPS = 92,
/*
* What support does the host have for screen targets?
*
* See the SVGA3D_SCREENTARGET_CAP bits below.
*/
SVGA3D_DEVCAP_SCREENTARGETS = 93,
SVGA3D_DEVCAP_MAX /* This must be the last index. */
} SVGA3dDevCapIndex;
typedef union {
Bool b;
uint32 u;
int32 i;
float f;
} SVGA3dDevCapResult;
typedef enum {
SVGA3DCAPS_RECORD_UNKNOWN = 0,
SVGA3DCAPS_RECORD_DEVCAPS_MIN = 0x100,
SVGA3DCAPS_RECORD_DEVCAPS = 0x100,
SVGA3DCAPS_RECORD_DEVCAPS_MAX = 0x1ff,
} SVGA3dCapsRecordType;
typedef
struct SVGA3dCapsRecordHeader {
uint32 length;
SVGA3dCapsRecordType type;
}
SVGA3dCapsRecordHeader;
typedef
struct SVGA3dCapsRecord {
SVGA3dCapsRecordHeader header;
uint32 data[1];
}
SVGA3dCapsRecord;
typedef uint32 SVGA3dCapPair[2];
#define SVGA3D_MOB_EMPTY_BASE 1
#endif /* _SVGA3D_REG_H_ */
#endif /* _SVGA3D_TYPES_H_ */
drivers/gpu/drm/vmwgfx/svga_escape.h → drivers/gpu/drm/vmwgfx/device_include/svga_escape.h
View file @ 8ce75f8a
/**********************************************************
* Copyright 2007-2009 VMware, Inc. All rights reserved.
* Copyright 2007-2015 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
......
drivers/gpu/drm/vmwgfx/svga_overlay.h → drivers/gpu/drm/vmwgfx/device_include/svga_overlay.h
View file @ 8ce75f8a
/**********************************************************
* Copyright 2007-2009 VMware, Inc. All rights reserved.
* Copyright 2007-2015 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
......@@ -152,19 +152,17 @@ VMwareVideoGetAttributes(const SVGAOverlayFormat format, /* IN */
switch (format) {
case VMWARE_FOURCC_YV12:
*height = (*height + 1) & ~1;
*size = (*width + 3) & ~3;
*size = (*width) * (*height);
if (pitches) {
pitches[0] = *size;
pitches[0] = *width;
}
*size *= *height;
if (offsets) {
offsets[1] = *size;
}
tmp = ((*width >> 1) + 3) & ~3;
tmp = *width >> 1;
if (pitches) {
pitches[1] = pitches[2] = tmp;
......
drivers/gpu/drm/vmwgfx/svga_reg.h → drivers/gpu/drm/vmwgfx/device_include/svga_reg.h
View file @ 8ce75f8a
/**********************************************************
* Copyright 1998-2009 VMware, Inc. All rights reserved.
* Copyright 1998-2015 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
......@@ -31,20 +31,38 @@
#ifndef _SVGA_REG_H_
#define _SVGA_REG_H_
#include <linux/pci_ids.h>
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#define INCLUDE_ALLOW_VMCORE
#include "includeCheck.h"
#include "svga_types.h"
/*
* PCI device IDs.
* SVGA_REG_ENABLE bit definitions.
*/
#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
typedef enum {
SVGA_REG_ENABLE_DISABLE = 0,
SVGA_REG_ENABLE_ENABLE = (1 << 0),
SVGA_REG_ENABLE_HIDE = (1 << 1),
} SvgaRegEnable;
typedef uint32 SVGAMobId;
/*
* SVGA_REG_ENABLE bit definitions.
* Arbitrary and meaningless limits. Please ignore these when writing
* new drivers.
*/
#define SVGA_REG_ENABLE_DISABLE 0
#define SVGA_REG_ENABLE_ENABLE 1
#define SVGA_REG_ENABLE_HIDE 2
#define SVGA_REG_ENABLE_ENABLE_HIDE (SVGA_REG_ENABLE_ENABLE |\
SVGA_REG_ENABLE_HIDE)
#define SVGA_MAX_WIDTH 2560
#define SVGA_MAX_HEIGHT 1600
#define SVGA_MAX_BITS_PER_PIXEL 32
#define SVGA_MAX_DEPTH 24
#define SVGA_MAX_DISPLAYS 10
/*
* Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned
......@@ -57,14 +75,9 @@
#define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 /* Put the cursor back in the framebuffer so the user can see it */
/*
* The maximum framebuffer size that can traced for e.g. guests in VESA mode.
* The changeMap in the monitor is proportional to this number. Therefore, we'd
* like to keep it as small as possible to reduce monitor overhead (using
* SVGA_VRAM_MAX_SIZE for this increases the size of the shared area by over
* 4k!).
*
* NB: For compatibility reasons, this value must be greater than 0xff0000.
* See bug 335072.
* The maximum framebuffer size that can traced for guests unless the
* SVGA_CAP_GBOBJECTS is set in SVGA_REG_CAPABILITIES. In that case
* the full framebuffer can be traced independent of this limit.
*/
#define SVGA_FB_MAX_TRACEABLE_SIZE 0x1000000
......@@ -133,6 +146,7 @@ enum {
SVGA_REG_FB_SIZE = 16,
/* ID 0 implementation only had the above registers, then the palette */
SVGA_REG_ID_0_TOP = 17,
SVGA_REG_CAPABILITIES = 17,
SVGA_REG_MEM_START = 18, /* (Deprecated) */
......@@ -173,7 +187,7 @@ enum {
SVGA_REG_COMMAND_LOW = 48, /* Lower 32 bits and submits commands */
SVGA_REG_COMMAND_HIGH = 49, /* Upper 32 bits of command buffer PA */
SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50, /* Max primary memory */
SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Suggested limit on mob mem */
SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Sugested limit on mob mem */
SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */
SVGA_REG_CMD_PREPEND_LOW = 53,
SVGA_REG_CMD_PREPEND_HIGH = 54,
......@@ -184,7 +198,6 @@ enum {
SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
/* Next 768 (== 256*3) registers exist for colormap */
SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS
/* Base of scratch registers */
/* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage:
......@@ -192,7 +205,6 @@ enum {
the use of the current SVGA driver. */
};
/*
* Guest memory regions (GMRs):
*
......@@ -290,16 +302,22 @@ enum {
#define SVGA_GMR_FRAMEBUFFER ((uint32) -2) /* Guest Framebuffer (GFB) */
typedef
#include "vmware_pack_begin.h"
struct SVGAGuestMemDescriptor {
uint32 ppn;
uint32 numPages;
} SVGAGuestMemDescriptor;
}
#include "vmware_pack_end.h"
SVGAGuestMemDescriptor;
typedef
#include "vmware_pack_begin.h"
struct SVGAGuestPtr {
uint32 gmrId;
uint32 offset;
} SVGAGuestPtr;
}
#include "vmware_pack_end.h"
SVGAGuestPtr;
/*
* Register based command buffers --
......@@ -356,9 +374,9 @@ struct SVGAGuestPtr {
* what it will set to.
*/
#define SVGA_CB_MAX_SIZE (512 * 1024) // 512 KB
#define SVGA_CB_MAX_SIZE (512 * 1024) /* 512 KB */
#define SVGA_CB_MAX_QUEUED_PER_CONTEXT 32
#define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) // 32 KB
#define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) /* 32 KB */
#define SVGA_CB_CONTEXT_MASK 0x3f
typedef enum {
......@@ -431,9 +449,10 @@ typedef enum {
} SVGACBFlags;
typedef
#include "vmware_pack_begin.h"
struct {
volatile SVGACBStatus status; /* Modified by device. */
volatile uint32 errorOffset; /* Modified by device. */
volatile SVGACBStatus status;
volatile uint32 errorOffset;
uint64 id;
SVGACBFlags flags;
uint32 length;
......@@ -444,13 +463,11 @@ struct {
uint32 mobOffset;
} mob;
} ptr;
uint32 offset; /* Valid if CMD_BUFFERS_2 cap set, must be zero otherwise,
* modified by device.
*/
uint32 offset; /* Valid if CMD_BUFFERS_2 cap set, must be zero otherwise */
uint32 dxContext; /* Valid if DX_CONTEXT flag set, must be zero otherwise */
uint32 mustBeZero[6];
}
__attribute__((__packed__))
#include "vmware_pack_end.h"
SVGACBHeader;
typedef enum {
......@@ -458,9 +475,9 @@ typedef enum {
SVGA_DC_CMD_START_STOP_CONTEXT = 1,
SVGA_DC_CMD_PREEMPT = 2,
SVGA_DC_CMD_MAX = 3,
SVGA_DC_CMD_FORCE_UINT = MAX_UINT32,
} SVGADeviceContextCmdId;
typedef struct {
uint32 enable;
SVGACBContext context;
......@@ -485,7 +502,6 @@ typedef struct {
uint32 ignoreIDZero;
} SVGADCCmdPreempt;
/*
* SVGAGMRImageFormat --
*
......@@ -506,13 +522,12 @@ typedef struct {
*
*/
typedef
struct SVGAGMRImageFormat {
typedef struct SVGAGMRImageFormat {
union {
struct {
uint32 bitsPerPixel : 8;
uint32 colorDepth : 8;
uint32 reserved : 16; /* Must be zero */
uint32 reserved : 16; /* Must be zero */
};
uint32 value;
......@@ -520,6 +535,7 @@ struct SVGAGMRImageFormat {
} SVGAGMRImageFormat;
typedef
#include "vmware_pack_begin.h"
struct SVGAGuestImage {
SVGAGuestPtr ptr;
......@@ -539,7 +555,9 @@ struct SVGAGuestImage {
* assuming each row of blocks is tightly packed.
*/
uint32 pitch;
} SVGAGuestImage;
}
#include "vmware_pack_end.h"
SVGAGuestImage;
/*
* SVGAColorBGRX --
......@@ -549,14 +567,13 @@ struct SVGAGuestImage {
* GMRFB state.
*/
typedef
struct SVGAColorBGRX {
typedef struct SVGAColorBGRX {
union {
struct {
uint32 b : 8;
uint32 g : 8;
uint32 r : 8;
uint32 x : 8; /* Unused */
uint32 x : 8; /* Unused */
};
uint32 value;
......@@ -578,26 +595,49 @@ struct SVGAColorBGRX {
*/
typedef
struct SVGASignedRect {
#include "vmware_pack_begin.h"
struct {
int32 left;
int32 top;
int32 right;
int32 bottom;
} SVGASignedRect;
}
#include "vmware_pack_end.h"
SVGASignedRect;
typedef
struct SVGASignedPoint {
#include "vmware_pack_begin.h"
struct {
int32 x;
int32 y;
} SVGASignedPoint;
}
#include "vmware_pack_end.h"
SVGASignedPoint;
/*
* Capabilities
* SVGA Device Capabilities
*
* Note the holes in the bitfield. Missing bits have been deprecated,
* and must not be reused. Those capabilities will never be reported
* by new versions of the SVGA device.
* Note the holes in the bitfield. Missing bits have been deprecated,
* and must not be reused. Those capabilities will never be reported
* by new versions of the SVGA device.
*
* XXX: Add longer descriptions for each capability, including a list
* of the new features that each capability provides.
*
* SVGA_CAP_IRQMASK --
* Provides device interrupts. Adds device register SVGA_REG_IRQMASK
* to set interrupt mask and direct I/O port SVGA_IRQSTATUS_PORT to
* set/clear pending interrupts.
*
* SVGA_CAP_GMR --
* Provides synchronous mapping of guest memory regions (GMR).
* Adds device registers SVGA_REG_GMR_ID, SVGA_REG_GMR_DESCRIPTOR,
* SVGA_REG_GMR_MAX_IDS, and SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH.
*
* SVGA_CAP_TRACES --
* Allows framebuffer trace-based updates even when FIFO is enabled.
* Adds device register SVGA_REG_TRACES.
*
* SVGA_CAP_GMR2 --
* Provides asynchronous commands to define and remap guest memory
......@@ -607,21 +647,39 @@ struct SVGASignedPoint {
* SVGA_CAP_SCREEN_OBJECT_2 --
* Allow screen object support, and require backing stores from the
* guest for each screen object.
*
* SVGA_CAP_COMMAND_BUFFERS --
* Enable register based command buffer submission.
*
* SVGA_CAP_DEAD1 --
* This cap was incorrectly used by old drivers and should not be
* reused.
*
* SVGA_CAP_CMD_BUFFERS_2 --
* Enable support for the prepend command buffer submision
* registers. SVGA_REG_CMD_PREPEND_LOW and
* SVGA_REG_CMD_PREPEND_HIGH.
*
* SVGA_CAP_GBOBJECTS --
* Enable guest-backed objects and surfaces.
*
* SVGA_CAP_CMD_BUFFERS_3 --
* Enable support for command buffers in a mob.
*/
#define SVGA_CAP_NONE 0x00000000
#define SVGA_CAP_RECT_COPY 0x00000002
#define SVGA_CAP_CURSOR 0x00000020
#define SVGA_CAP_CURSOR_BYPASS 0x00000040 /* Legacy (Use Cursor Bypass 3 instead) */
#define SVGA_CAP_CURSOR_BYPASS_2 0x00000080 /* Legacy (Use Cursor Bypass 3 instead) */
#define SVGA_CAP_CURSOR_BYPASS 0x00000040
#define SVGA_CAP_CURSOR_BYPASS_2 0x00000080
#define SVGA_CAP_8BIT_EMULATION 0x00000100
#define SVGA_CAP_ALPHA_CURSOR 0x00000200
#define SVGA_CAP_3D 0x00004000
#define SVGA_CAP_EXTENDED_FIFO 0x00008000
#define SVGA_CAP_MULTIMON 0x00010000 /* Legacy multi-monitor support */
#define SVGA_CAP_MULTIMON 0x00010000
#define SVGA_CAP_PITCHLOCK 0x00020000
#define SVGA_CAP_IRQMASK 0x00040000
#define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000 /* Legacy multi-monitor support */
#define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000
#define SVGA_CAP_GMR 0x00100000
#define SVGA_CAP_TRACES 0x00200000
#define SVGA_CAP_GMR2 0x00400000
......@@ -630,7 +688,33 @@ struct SVGASignedPoint {
#define SVGA_CAP_DEAD1 0x02000000
#define SVGA_CAP_CMD_BUFFERS_2 0x04000000
#define SVGA_CAP_GBOBJECTS 0x08000000
#define SVGA_CAP_CMD_BUFFERS_3 0x10000000
#define SVGA_CAP_DX 0x10000000
#define SVGA_CAP_CMD_RESERVED 0x80000000
/*
* The Guest can optionally read some SVGA device capabilities through
* the backdoor with command BDOOR_CMD_GET_SVGA_CAPABILITIES before
* the SVGA device is initialized. The type of capability the guest
* is requesting from the SVGABackdoorCapType enum should be placed in
* the upper 16 bits of the backdoor command id (ECX). On success the
* the value of EBX will be set to BDOOR_MAGIC and EAX will be set to
* the requested capability. If the command is not supported then EBX
* will be left unchanged and EAX will be set to -1. Because it is
* possible that -1 is the value of the requested cap the correct way
* to check if the command was successful is to check if EBX was changed
* to BDOOR_MAGIC making sure to initialize the register to something
* else first.
*/
typedef enum {
SVGABackdoorCapDeviceCaps = 0,
SVGABackdoorCapFifoCaps = 1,
SVGABackdoorCap3dHWVersion = 2,
SVGABackdoorCapMax = 3,
} SVGABackdoorCapType;
/*
* FIFO register indices.
......@@ -1070,7 +1154,8 @@ enum {
SVGA_VIDEO_PITCH_2,
SVGA_VIDEO_PITCH_3,
SVGA_VIDEO_DATA_GMRID, /* Optional, defaults to SVGA_GMR_FRAMEBUFFER */
SVGA_VIDEO_DST_SCREEN_ID, /* Optional, defaults to virtual coords (SVGA_ID_INVALID) */
SVGA_VIDEO_DST_SCREEN_ID, /* Optional, defaults to virtual coords */
/* (SVGA_ID_INVALID) */
SVGA_VIDEO_NUM_REGS
};
......@@ -1083,7 +1168,9 @@ enum {
* video frame to be displayed.
*/
typedef struct SVGAOverlayUnit {
typedef
#include "vmware_pack_begin.h"
struct SVGAOverlayUnit {
uint32 enabled;
uint32 flags;
uint32 dataOffset;
......@@ -1103,7 +1190,27 @@ typedef struct SVGAOverlayUnit {
uint32 pitches[3];
uint32 dataGMRId;
uint32 dstScreenId;
} SVGAOverlayUnit;
}
#include "vmware_pack_end.h"
SVGAOverlayUnit;
/*
* Guest display topology
*
* XXX: This structure is not part of the SVGA device's interface, and
* doesn't really belong here.
*/
#define SVGA_INVALID_DISPLAY_ID ((uint32)-1)
typedef struct SVGADisplayTopology {
uint16 displayId;
uint16 isPrimary;
uint32 width;
uint32 height;
uint32 positionX;
uint32 positionY;
} SVGADisplayTopology;
/*
......@@ -1138,10 +1245,10 @@ typedef struct SVGAOverlayUnit {
* value of zero means no cloning should happen.
*/
#define SVGA_SCREEN_MUST_BE_SET (1 << 0) /* Must be set or results undefined */
#define SVGA_SCREEN_MUST_BE_SET (1 << 0)
#define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET /* Deprecated */
#define SVGA_SCREEN_IS_PRIMARY (1 << 1) /* Guest considers this screen to be 'primary' */
#define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2) /* Guest is running a fullscreen app here */
#define SVGA_SCREEN_IS_PRIMARY (1 << 1)
#define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2)
/*
* Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When the screen is
......@@ -1164,7 +1271,8 @@ typedef struct SVGAOverlayUnit {
#define SVGA_SCREEN_BLANKING (1 << 4)
typedef
struct SVGAScreenObject {
#include "vmware_pack_begin.h"
struct {
uint32 structSize; /* sizeof(SVGAScreenObject) */
uint32 id;
uint32 flags;
......@@ -1182,8 +1290,17 @@ struct SVGAScreenObject {
* with SVGA_FIFO_CAP_SCREEN_OBJECT.
*/
SVGAGuestImage backingStore;
/*
* The cloneCount field is treated as a hint from the guest that
* the user wants this display to be cloned, cloneCount times.
*
* A value of zero means no cloning should happen.
*/
uint32 cloneCount;
} SVGAScreenObject;
}
#include "vmware_pack_end.h"
SVGAScreenObject;
/*
......@@ -1196,7 +1313,7 @@ struct SVGAScreenObject {
* Note the holes in the command ID numbers: These commands have been
* deprecated, and the old IDs must not be reused.
*
* Command IDs from 1000 to 1999 are reserved for use by the SVGA3D
* Command IDs from 1000 to 2999 are reserved for use by the SVGA3D
* protocol.
*
* Each command's parameters are described by the comments and
......@@ -1207,6 +1324,7 @@ typedef enum {
SVGA_CMD_INVALID_CMD = 0,
SVGA_CMD_UPDATE = 1,
SVGA_CMD_RECT_COPY = 3,
SVGA_CMD_RECT_ROP_COPY = 14,
SVGA_CMD_DEFINE_CURSOR = 19,
SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
SVGA_CMD_UPDATE_VERBOSE = 25,
......@@ -1222,9 +1340,14 @@ typedef enum {
SVGA_CMD_ANNOTATION_COPY = 40,
SVGA_CMD_DEFINE_GMR2 = 41,
SVGA_CMD_REMAP_GMR2 = 42,
SVGA_CMD_DEAD = 43,
SVGA_CMD_DEAD_2 = 44,
SVGA_CMD_NOP = 45,
SVGA_CMD_NOP_ERROR = 46,
SVGA_CMD_MAX
} SVGAFifoCmdId;
#define SVGA_CMD_MAX_DATASIZE (256 * 1024)
#define SVGA_CMD_MAX_ARGS 64
......@@ -1257,12 +1380,15 @@ typedef enum {
*/
typedef
struct SVGAFifoCmdUpdate {
#include "vmware_pack_begin.h"
struct {
uint32 x;
uint32 y;
uint32 width;
uint32 height;
} SVGAFifoCmdUpdate;
}
#include "vmware_pack_end.h"
SVGAFifoCmdUpdate;
/*
......@@ -1276,14 +1402,44 @@ struct SVGAFifoCmdUpdate {
*/
typedef
struct SVGAFifoCmdRectCopy {
#include "vmware_pack_begin.h"
struct {
uint32 srcX;
uint32 srcY;
uint32 destX;
uint32 destY;
uint32 width;
uint32 height;
}
#include "vmware_pack_end.h"
SVGAFifoCmdRectCopy;
/*
* SVGA_CMD_RECT_ROP_COPY --
*
* Perform a rectangular DMA transfer from one area of the GFB to
* another, and copy the result to any screens which intersect it.
* The value of ROP may only be SVGA_ROP_COPY, and this command is
* only supported for backwards compatibility reasons.
*
* Availability:
* SVGA_CAP_RECT_COPY
*/
typedef
#include "vmware_pack_begin.h"
struct {
uint32 srcX;
uint32 srcY;
uint32 destX;
uint32 destY;
uint32 width;
uint32 height;
} SVGAFifoCmdRectCopy;
uint32 rop;
}
#include "vmware_pack_end.h"
SVGAFifoCmdRectRopCopy;
/*
......@@ -1300,7 +1456,8 @@ struct SVGAFifoCmdRectCopy {
*/
typedef
struct SVGAFifoCmdDefineCursor {
#include "vmware_pack_begin.h"
struct {
uint32 id; /* Reserved, must be zero. */
uint32 hotspotX;
uint32 hotspotY;
......@@ -1312,7 +1469,9 @@ struct SVGAFifoCmdDefineCursor {
* Followed by scanline data for AND mask, then XOR mask.
* Each scanline is padded to a 32-bit boundary.
*/
} SVGAFifoCmdDefineCursor;
}
#include "vmware_pack_end.h"
SVGAFifoCmdDefineCursor;
/*
......@@ -1329,14 +1488,17 @@ struct SVGAFifoCmdDefineCursor {
*/
typedef
struct SVGAFifoCmdDefineAlphaCursor {
#include "vmware_pack_begin.h"
struct {
uint32 id; /* Reserved, must be zero. */
uint32 hotspotX;
uint32 hotspotY;
uint32 width;
uint32 height;
/* Followed by scanline data */
} SVGAFifoCmdDefineAlphaCursor;
}
#include "vmware_pack_end.h"
SVGAFifoCmdDefineAlphaCursor;
/*
......@@ -1352,13 +1514,16 @@ struct SVGAFifoCmdDefineAlphaCursor {
*/
typedef
struct SVGAFifoCmdUpdateVerbose {
#include "vmware_pack_begin.h"
struct {
uint32 x;
uint32 y;
uint32 width;
uint32 height;
uint32 reason;
} SVGAFifoCmdUpdateVerbose;
}
#include "vmware_pack_end.h"
SVGAFifoCmdUpdateVerbose;
/*
......@@ -1377,14 +1542,17 @@ struct SVGAFifoCmdUpdateVerbose {
#define SVGA_ROP_COPY 0x03
typedef
struct SVGAFifoCmdFrontRopFill {
#include "vmware_pack_begin.h"
struct {
uint32 color; /* In the same format as the GFB */
uint32 x;
uint32 y;
uint32 width;
uint32 height;
uint32 rop; /* Must be SVGA_ROP_COPY */
} SVGAFifoCmdFrontRopFill;
}
#include "vmware_pack_end.h"
SVGAFifoCmdFrontRopFill;
/*
......@@ -1403,9 +1571,12 @@ struct SVGAFifoCmdFrontRopFill {
*/
typedef
#include "vmware_pack_begin.h"
struct {
uint32 fence;
} SVGAFifoCmdFence;
}
#include "vmware_pack_end.h"
SVGAFifoCmdFence;
/*
......@@ -1420,11 +1591,14 @@ struct {
*/
typedef
struct SVGAFifoCmdEscape {
#include "vmware_pack_begin.h"
struct {
uint32 nsid;
uint32 size;
/* followed by 'size' bytes of data */
} SVGAFifoCmdEscape;
}
#include "vmware_pack_end.h"
SVGAFifoCmdEscape;
/*
......@@ -1454,9 +1628,12 @@ struct SVGAFifoCmdEscape {
*/
typedef
#include "vmware_pack_begin.h"
struct {
SVGAScreenObject screen; /* Variable-length according to version */
} SVGAFifoCmdDefineScreen;
}
#include "vmware_pack_end.h"
SVGAFifoCmdDefineScreen;
/*
......@@ -1470,9 +1647,12 @@ struct {
*/
typedef
#include "vmware_pack_begin.h"
struct {
uint32 screenId;
} SVGAFifoCmdDestroyScreen;
}
#include "vmware_pack_end.h"
SVGAFifoCmdDestroyScreen;
/*
......@@ -1523,11 +1703,14 @@ struct {
*/
typedef
#include "vmware_pack_begin.h"
struct {
SVGAGuestPtr ptr;
uint32 bytesPerLine;
SVGAGMRImageFormat format;
} SVGAFifoCmdDefineGMRFB;
}
#include "vmware_pack_end.h"
SVGAFifoCmdDefineGMRFB;
/*
......@@ -1535,19 +1718,10 @@ struct {
*
* This is a guest-to-host blit. It performs a DMA operation to
* copy a rectangular region of pixels from the current GMRFB to
* one or more Screen Objects.
* a ScreenObject.
*
* The destination coordinate may be specified relative to a
* screen's origin (if a screen ID is specified) or relative to the
* virtual coordinate system's origin (if the screen ID is
* SVGA_ID_INVALID). The actual destination may span zero or more
* screens, in the case of a virtual destination rect or a rect
* which extends off the edge of the specified screen.
*
* This command writes to the screen's "base layer": the underlying
* framebuffer which exists below any cursor or video overlays. No
* action is necessary to explicitly hide or update any overlays
* which exist on top of the updated region.
* screen's origin. The provided screen ID must be valid.
*
* The SVGA device is guaranteed to finish reading from the GMRFB
* by the time any subsequent FENCE commands are reached.
......@@ -1560,46 +1734,27 @@ struct {
*/
typedef
#include "vmware_pack_begin.h"
struct {
SVGASignedPoint srcOrigin;
SVGASignedRect destRect;
uint32 destScreenId;
} SVGAFifoCmdBlitGMRFBToScreen;
}
#include "vmware_pack_end.h"
SVGAFifoCmdBlitGMRFBToScreen;
/*
* SVGA_CMD_BLIT_SCREEN_TO_GMRFB --
*
* This is a host-to-guest blit. It performs a DMA operation to
* copy a rectangular region of pixels from a single Screen Object
* copy a rectangular region of pixels from a single ScreenObject
* back to the current GMRFB.
*
* Usage note: This command should be used rarely. It will
* typically be inefficient, but it is necessary for some types of
* synchronization between 3D (GPU) and 2D (CPU) rendering into
* overlapping areas of a screen.
*
* The source coordinate is specified relative to a screen's
* origin. The provided screen ID must be valid. If any parameters
* origin. The provided screen ID must be valid. If any parameters
* are invalid, the resulting pixel values are undefined.
*
* This command reads the screen's "base layer". Overlays like
* video and cursor are not included, but any data which was sent
* using a blit-to-screen primitive will be available, no matter
* whether the data's original source was the GMRFB or the 3D
* acceleration hardware.
*
* Note that our guest-to-host blits and host-to-guest blits aren't
* symmetric in their current implementation. While the parameters
* are identical, host-to-guest blits are a lot less featureful.
* They do not support clipping: If the source parameters don't
* fully fit within a screen, the blit fails. They must originate
* from exactly one screen. Virtual coordinates are not directly
* supported.
*
* Host-to-guest blits do support the same set of GMRFB formats
* offered by guest-to-host blits.
*
* The SVGA device is guaranteed to finish writing to the GMRFB by
* the time any subsequent FENCE commands are reached.
*
......@@ -1608,77 +1763,57 @@ struct {
*/
typedef
#include "vmware_pack_begin.h"
struct {
SVGASignedPoint destOrigin;
SVGASignedRect srcRect;
uint32 srcScreenId;
} SVGAFifoCmdBlitScreenToGMRFB;
}
#include "vmware_pack_end.h"
SVGAFifoCmdBlitScreenToGMRFB;
/*
* SVGA_CMD_ANNOTATION_FILL --
*
* This is a blit annotation. This command stores a small piece of
* device state which is consumed by the next blit-to-screen
* command. The state is only cleared by commands which are
* specifically documented as consuming an annotation. Other
* commands (such as ESCAPEs for debugging) may intervene between
* the annotation and its associated blit.
*
* This annotation is a promise about the contents of the next
* blit: The video driver is guaranteeing that all pixels in that
* blit will have the same value, specified here as a color in
* SVGAColorBGRX format.
*
* The SVGA device can still render the blit correctly even if it
* ignores this annotation, but the annotation may allow it to
* perform the blit more efficiently, for example by ignoring the
* source data and performing a fill in hardware.
*
* This annotation is most important for performance when the
* user's display is being remoted over a network connection.
* The annotation commands have been deprecated, should not be used
* by new drivers. They used to provide performance hints to the SVGA
* device about the content of screen updates, but newer SVGA devices
* ignore these.
*
* Availability:
* SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
*/
typedef
#include "vmware_pack_begin.h"
struct {
SVGAColorBGRX color;
} SVGAFifoCmdAnnotationFill;
}
#include "vmware_pack_end.h"
SVGAFifoCmdAnnotationFill;
/*
* SVGA_CMD_ANNOTATION_COPY --
*
* This is a blit annotation. See SVGA_CMD_ANNOTATION_FILL for more
* information about annotations.
*
* This annotation is a promise about the contents of the next
* blit: The video driver is guaranteeing that all pixels in that
* blit will have the same value as those which already exist at an
* identically-sized region on the same or a different screen.
*
* Note that the source pixels for the COPY in this annotation are
* sampled before applying the anqnotation's associated blit. They
* are allowed to overlap with the blit's destination pixels.
*
* The copy source rectangle is specified the same way as the blit
* destination: it can be a rectangle which spans zero or more
* screens, specified relative to either a screen or to the virtual
* coordinate system's origin. If the source rectangle includes
* pixels which are not from exactly one screen, the results are
* undefined.
* The annotation commands have been deprecated, should not be used
* by new drivers. They used to provide performance hints to the SVGA
* device about the content of screen updates, but newer SVGA devices
* ignore these.
*
* Availability:
* SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
*/
typedef
#include "vmware_pack_begin.h"
struct {
SVGASignedPoint srcOrigin;
uint32 srcScreenId;
} SVGAFifoCmdAnnotationCopy;
}
#include "vmware_pack_end.h"
SVGAFifoCmdAnnotationCopy;
/*
......@@ -1691,10 +1826,13 @@ struct {
*/
typedef
#include "vmware_pack_begin.h"
struct {
uint32 gmrId;
uint32 numPages;
} SVGAFifoCmdDefineGMR2;
}
#include "vmware_pack_end.h"
SVGAFifoCmdDefineGMR2;
/*
......@@ -1733,6 +1871,7 @@ typedef enum {
} SVGARemapGMR2Flags;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 gmrId;
SVGARemapGMR2Flags flags;
......@@ -1746,6 +1885,52 @@ struct {
* (according to flag SVGA_REMAP_GMR2_PPN64) follows. If flag
* SVGA_REMAP_GMR2_SINGLE_PPN is set, array contains a single entry.
*/
} SVGAFifoCmdRemapGMR2;
}
#include "vmware_pack_end.h"
SVGAFifoCmdRemapGMR2;
/*
* Size of SVGA device memory such as frame buffer and FIFO.
*/
#define SVGA_VRAM_MIN_SIZE (4 * 640 * 480) /* bytes */
#define SVGA_VRAM_MIN_SIZE_3D (16 * 1024 * 1024)
#define SVGA_VRAM_MAX_SIZE (128 * 1024 * 1024)
#define SVGA_MEMORY_SIZE_MAX (1024 * 1024 * 1024)
#define SVGA_FIFO_SIZE_MAX (2 * 1024 * 1024)
#define SVGA_GRAPHICS_MEMORY_KB_MIN (32 * 1024)
#define SVGA_GRAPHICS_MEMORY_KB_MAX (2 * 1024 * 1024)
#define SVGA_GRAPHICS_MEMORY_KB_DEFAULT (256 * 1024)
#define SVGA_VRAM_SIZE_W2K (64 * 1024 * 1024) /* 64 MB */
/*
* To simplify autoDetect display configuration, support a minimum of
* two 1920x1200 monitors, 32bpp, side-by-side, optionally rotated:
* numDisplays = 2
* maxWidth = numDisplay * 1920 = 3840
* maxHeight = rotated width of single monitor = 1920
* vramSize = maxWidth * maxHeight * 4 = 29491200
*/
#define SVGA_VRAM_SIZE_AUTODETECT (32 * 1024 * 1024)
#if defined(VMX86_SERVER)
#define SVGA_VRAM_SIZE (4 * 1024 * 1024)
#define SVGA_VRAM_SIZE_3D (64 * 1024 * 1024)
#define SVGA_FIFO_SIZE (256 * 1024)
#define SVGA_FIFO_SIZE_3D (516 * 1024)
#define SVGA_MEMORY_SIZE_DEFAULT (160 * 1024 * 1024)
#define SVGA_AUTODETECT_DEFAULT FALSE
#else
#define SVGA_VRAM_SIZE (16 * 1024 * 1024)
#define SVGA_VRAM_SIZE_3D SVGA_VRAM_MAX_SIZE
#define SVGA_FIFO_SIZE (2 * 1024 * 1024)
#define SVGA_FIFO_SIZE_3D SVGA_FIFO_SIZE
#define SVGA_MEMORY_SIZE_DEFAULT (768 * 1024 * 1024)
#define SVGA_AUTODETECT_DEFAULT TRUE
#endif
#define SVGA_FIFO_SIZE_GBOBJECTS (256 * 1024)
#define SVGA_VRAM_SIZE_GBOBJECTS (4 * 1024 * 1024)
#endif
drivers/gpu/drm/vmwgfx/device_include/svga_types.h 0 → 100644
View file @ 8ce75f8a
/**********************************************************
* Copyright 2015 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
#ifndef _VM_BASIC_TYPES_H_
#define _VM_BASIC_TYPES_H_
#include <linux/kernel.h>
typedef u32 uint32;
typedef s32 int32;
typedef u64 uint64;
typedef u16 uint16;
typedef s16 int16;
typedef u8 uint8;
typedef s8 int8;
typedef uint64 PA;
typedef uint32 PPN;
typedef uint64 PPN64;
typedef bool Bool;
#define MAX_UINT32 U32_MAX
#define MAX_UINT16 U16_MAX
#endif
drivers/gpu/drm/vmwgfx/device_include/vm_basic_types.h 0 → 100644
View file @ 8ce75f8a
#ifndef _VM_BASIC_TYPES_H_
#define _VM_BASIC_TYPES_H_
#include <linux/kernel.h>
typedef u32 uint32;
typedef s32 int32;
typedef u64 uint64;
typedef u16 uint16;
typedef s16 int16;
typedef u8 uint8;
typedef s8 int8;
typedef uint64 PA;
typedef uint32 PPN;
typedef uint64 PPN64;
typedef bool Bool;
#define MAX_UINT32 U32_MAX
#endif
drivers/gpu/drm/vmwgfx/device_include/vmware_pack_begin.h 0 → 100644
View file @ 8ce75f8a
/**********************************************************
* Copyright 2015 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
#include <linux/compiler.h>
drivers/gpu/drm/vmwgfx/device_include/vmware_pack_end.h 0 → 100644
View file @ 8ce75f8a
/**********************************************************
* Copyright 2015 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
__packed
drivers/gpu/drm/vmwgfx/svga_types.h deleted 100644 → 0
View file @ 5101020c
/**************************************************************************
*
* Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
/**
* Silly typedefs for the svga headers. Currently the headers are shared
* between all components that talk to svga. And as such the headers are
* are in a completely different style and use weird defines.
*
* This file lets all the ugly be prefixed with svga*.
*/
#ifndef _SVGA_TYPES_H_
#define _SVGA_TYPES_H_
typedef uint16_t uint16;
typedef uint32_t uint32;
typedef uint8_t uint8;
typedef int32_t int32;
typedef uint64_t uint64;
typedef bool Bool;
typedef uint64 PA;
typedef uint32 SVGAMobId;
#endif
drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c
View file @ 8ce75f8a
......@@ -1139,7 +1139,7 @@ int vmw_cmdbuf_set_pool_size(struct vmw_cmdbuf_man *man,
* actually call into the already enabled manager, when
* binding the MOB.
*/
if (!(dev_priv->capabilities & SVGA_CAP_CMD_BUFFERS_3))
if (!(dev_priv->capabilities & SVGA_CAP_DX))
return -ENOMEM;
ret = ttm_bo_create(&dev_priv->bdev, size, ttm_bo_type_device,
......
drivers/gpu/drm/vmwgfx/vmwgfx_context.c
View file @ 8ce75f8a
......@@ -696,7 +696,7 @@ int vmw_context_binding_add(struct vmw_ctx_binding_state *cbs,
break;
case vmw_ctx_binding_shader:
if (unlikely((unsigned)bi->i1.shader_type >=
SVGA3D_SHADERTYPE_MAX)) {
SVGA3D_SHADERTYPE_PREDX_MAX)) {
DRM_ERROR("Illegal shader type %u.\n",
(unsigned) bi->i1.shader_type);
return -EINVAL;
......
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
View file @ 8ce75f8a
......@@ -278,8 +278,8 @@ static void vmw_print_capabilities(uint32_t capabilities)
DRM_INFO(" Command Buffers 2.\n");
if (capabilities & SVGA_CAP_GBOBJECTS)
DRM_INFO(" Guest Backed Resources.\n");
if (capabilities & SVGA_CAP_CMD_BUFFERS_3)
DRM_INFO(" Command Buffers 3.\n");
if (capabilities & SVGA_CAP_DX)
DRM_INFO(" DX Features.\n");
}
/**
......@@ -1264,7 +1264,8 @@ static void __vmw_svga_disable(struct vmw_private *dev_priv)
if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
vmw_write(dev_priv, SVGA_REG_ENABLE,
SVGA_REG_ENABLE_ENABLE_HIDE);
SVGA_REG_ENABLE_HIDE |
SVGA_REG_ENABLE_ENABLE);
}
spin_unlock(&dev_priv->svga_lock);
}
......@@ -1282,11 +1283,12 @@ void vmw_svga_disable(struct vmw_private *dev_priv)
spin_lock(&dev_priv->svga_lock);
if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
vmw_write(dev_priv, SVGA_REG_ENABLE,
SVGA_REG_ENABLE_ENABLE_HIDE);
spin_unlock(&dev_priv->svga_lock);
if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM))
DRM_ERROR("Failed evicting VRAM buffers.\n");
vmw_write(dev_priv, SVGA_REG_ENABLE,
SVGA_REG_ENABLE_HIDE |
SVGA_REG_ENABLE_ENABLE);
} else
spin_unlock(&dev_priv->svga_lock);
ttm_write_unlock(&dev_priv->reservation_sem);
......
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
View file @ 8ce75f8a
......@@ -328,7 +328,7 @@ struct vmw_ctx_binding_state {
struct list_head list;
struct vmw_ctx_binding render_targets[SVGA3D_RT_MAX];
struct vmw_ctx_binding texture_units[SVGA3D_NUM_TEXTURE_UNITS];
struct vmw_ctx_binding shaders[SVGA3D_SHADERTYPE_MAX];
struct vmw_ctx_binding shaders[SVGA3D_SHADERTYPE_PREDX_MAX];
};
......
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
View file @ 8ce75f8a
......@@ -1981,8 +1981,6 @@ static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = {
false, false, true),
VMW_CMD_DEF(SVGA_3D_CMD_DESTROY_GB_MOB, &vmw_cmd_invalid,
false, false, true),
VMW_CMD_DEF(SVGA_3D_CMD_REDEFINE_GB_MOB, &vmw_cmd_invalid,
false, false, true),
VMW_CMD_DEF(SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING, &vmw_cmd_invalid,
false, false, true),
VMW_CMD_DEF(SVGA_3D_CMD_DEFINE_GB_SURFACE, &vmw_cmd_invalid,
......
drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
View file @ 8ce75f8a
......@@ -119,7 +119,8 @@ int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE_HIDE);
vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE |
SVGA_REG_ENABLE_HIDE);
vmw_write(dev_priv, SVGA_REG_TRACES, 0);
min = 4;
......
drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
View file @ 8ce75f8a
......@@ -28,6 +28,7 @@
#include "vmwgfx_drv.h"
#include <drm/vmwgfx_drm.h>
#include "vmwgfx_kms.h"
#include "device_include/svga3d_caps.h"
struct svga_3d_compat_cap {
SVGA3dCapsRecordHeader header;
......
drivers/gpu/drm/vmwgfx/vmwgfx_mob.c
View file @ 8ce75f8a
......@@ -253,7 +253,7 @@ int vmw_otables_setup(struct vmw_private *dev_priv)
VMWGFX_NUM_GB_CONTEXT * SVGA3D_OTABLE_CONTEXT_ENTRY_SIZE;
otables[SVGA_OTABLE_SHADER].size =
VMWGFX_NUM_GB_SHADER * SVGA3D_OTABLE_SHADER_ENTRY_SIZE;
otables[SVGA_OTABLE_SCREEN_TARGET].size =
otables[SVGA_OTABLE_SCREENTARGET].size =
VMWGFX_NUM_GB_SCREEN_TARGET *
SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE;
......
drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
View file @ 8ce75f8a
......@@ -31,8 +31,8 @@
#include <drm/ttm/ttm_placement.h>
#include "svga_overlay.h"
#include "svga_escape.h"
#include "device_include/svga_overlay.h"
#include "device_include/svga_escape.h"
#define VMW_MAX_NUM_STREAMS 1
#define VMW_OVERLAY_CAP_MASK (SVGA_FIFO_CAP_VIDEO | SVGA_FIFO_CAP_ESCAPE)
......
drivers/gpu/drm/vmwgfx/vmwgfx_reg.h
View file @ 8ce75f8a
......@@ -50,8 +50,6 @@ struct svga_fifo_cmd_fence {
#define SVGA_SYNC_GENERIC 1
#define SVGA_SYNC_FIFOFULL 2
#include "svga_types.h"
#include "svga3d_reg.h"
#include "device_include/svga3d_reg.h"
#endif
drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
View file @ 8ce75f8a
......@@ -26,7 +26,7 @@
******************************************************************************/
#include "vmwgfx_kms.h"
#include "svga3d_surfacedefs.h"
#include "device_include/svga3d_surfacedefs.h"
#include <drm/drm_plane_helper.h>
#define vmw_crtc_to_stdu(x) \
......
drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
View file @ 8ce75f8a
......@@ -28,7 +28,7 @@
#include "vmwgfx_drv.h"
#include "vmwgfx_resource_priv.h"
#include <ttm/ttm_placement.h>
#include "svga3d_surfacedefs.h"
#include "device_include/svga3d_surfacedefs.h"
/**
* struct vmw_user_surface - User-space visible surface resource
......
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