Skip to content

L
linux
Commit 8e00ee40 authored by Andrew Morton's avatar Andrew Morton Committed by Linus Torvalds
Browse files
Options

[PATCH] sn: Debug clean up in pcibr_dvr.c 

From: Pat Gefre <pfg@sgi.com>

Debug clean up in pcibr_dvr.c
parent 5501e738
Show whitespace changes
Inline Side-by-side
Showing with 122 additions and 129 deletions
arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c
View file @ 8e00ee40
......@@ -25,13 +25,9 @@
* -pcibr_debug_mask is the mask of the different types of debugging
* you want to enable. See sys/PCI/pcibr_private.h
* -pcibr_debug_module is the module you want to trace. By default
* all modules are trace. For IP35 this value has the format of
* something like "001c10". For IP27 this value is a node number,
* i.e. "1", "2"... For IP30 this is undefined and should be set to
* 'all'.
* -pcibr_debug_widget is the widget you want to trace. For IP27
* the widget isn't exposed in the hwpath so use the xio slot num.
* i.e. for 'io2' set pcibr_debug_widget to "2".
* all modules are trace. The format is something like "001c10".
* -pcibr_debug_widget is the widget you want to trace. For TIO
* based bricks use the corelet id.
* -pcibr_debug_slot is the pci slot you want to trace.
*/
uint32_t pcibr_debug_mask = 0x0; /* 0x00000000 to disable */
......@@ -39,23 +35,6 @@ char *pcibr_debug_module = "all"; /* 'all' for all modules */
int pcibr_debug_widget = -1; /* '-1' for all widgets */
int pcibr_debug_slot = -1; /* '-1' for all slots */
/*
* Macros related to the Lucent USS 302/312 usb timeout workaround. It
* appears that if the lucent part can get into a retry loop if it sees a
* DAC on the bus during a pio read retry. The loop is broken after about
* 1ms, so we need to set up bridges holding this part to allow at least
* 1ms for pio.
*/
#define USS302_TIMEOUT_WAR
#ifdef USS302_TIMEOUT_WAR
#define LUCENT_USBHC_VENDOR_ID_NUM 0x11c1
#define LUCENT_USBHC302_DEVICE_ID_NUM 0x5801
#define LUCENT_USBHC312_DEVICE_ID_NUM 0x5802
#define USS302_BRIDGE_TIMEOUT_HLD 4
#endif
/* kbrick widgetnum-to-bus layout */
int p_busnum[MAX_PORT_NUM] = { /* widget# */
0, 0, 0, 0, 0, 0, 0, 0, /* 0x0 - 0x7 */
......@@ -68,6 +47,24 @@ int p_busnum[MAX_PORT_NUM] = { /* widget# */
3, /* 0xf */
};
char *pci_space[] = {"NONE",
"ROM",
"IO",
"",
"MEM",
"MEM32",
"MEM64",
"CFG",
"WIN0",
"WIN1",
"WIN2",
"WIN3",
"WIN4",
"WIN5",
"",
"BAD"};
#if PCIBR_SOFT_LIST
pcibr_list_p pcibr_list = 0;
#endif
......@@ -400,6 +397,11 @@ pcibr_try_set_device(pcibr_soft_t pcibr_soft,
}
}
/* PIC BRINGUP WAR (PV# 878674): Don't allow 64bit PIO accesses */
if (IS_PIC_SOFT(pcibr_soft) && (flags & PCIBR_64BIT) &&
PCIBR_WAR_ENABLED(PV878674, pcibr_soft)) {
new &= ~(1ull << 22);
}
chg = old ^ new; /* what are we changing, */
chg &= xmask; /* of the interesting bits */
......@@ -450,6 +452,8 @@ pcibr_try_set_device(pcibr_soft_t pcibr_soft,
*/
if (bad) {
pcibr_unlock(pcibr_soft, s);
PCIBR_DEBUG((PCIBR_DEBUG_DEVREG, pcibr_soft->bs_vhdl,
"pcibr_try_set_device: mod blocked by 0x%x\n", bad));
return bad;
}
}
......@@ -477,7 +481,8 @@ pcibr_try_set_device(pcibr_soft_t pcibr_soft,
bridge->b_wid_tflush; /* wait until Bridge PIO complete */
pcibr_unlock(pcibr_soft, s);
printk("pcibr_try_set_device: Device(%d): %x\n", slot, new);
PCIBR_DEBUG((PCIBR_DEBUG_DEVREG, pcibr_soft->bs_vhdl,
"pcibr_try_set_device: Device(%d): 0x%x\n", slot, new));
return 0;
}
......@@ -680,7 +685,7 @@ pcibr_device_unregister(vertex_hdl_t pconn_vhdl)
pcibr_soft_t pcibr_soft;
bridge_t *bridge;
int count_vchan0, count_vchan1;
unsigned s;
unsigned long s;
int error_call;
int error = 0;
......@@ -1803,7 +1808,6 @@ pcibr_detach(vertex_hdl_t xconn)
pciio_device_info_unregister(pcibr_vhdl,
&(pcibr_soft->bs_noslot_info->f_c));
/* spin_lock_destroy(&pcibr_soft->bs_lock); */
kfree(pcibr_soft->bs_name);
/* Disconnect the error interrupt and free the xtalk resources
......@@ -1900,7 +1904,6 @@ pcibr_addr_pci_to_xio(vertex_hdl_t pconn_vhdl,
iopaddr_t mbase; /* base of devio(x) mapped area on PCI */
size_t msize; /* size of devio(x) mapped area on PCI */
size_t mmask; /* addr bits stored in Device(x) */
char tmp_str[512];
unsigned long s;
......@@ -2097,18 +2100,12 @@ pcibr_addr_pci_to_xio(vertex_hdl_t pconn_vhdl,
if (bar != -1)
pcibr_info->f_window[bar].w_devio_index = win;
/*
* The kernel only allows functions to have so many variable args,
* attempting to call PCIBR_DEBUG_ALWAYS() with more than 5 printk
* arguments fails so sprintf() it into a temporary string.
*/
if (pcibr_debug_mask & PCIBR_DEBUG_PIOMAP) {
sprintf(tmp_str, "pcibr_addr_pci_to_xio: map to [%lx..%lx] for "
"slot %d allocates DevIO(%d) Device(%d) set to %lx\n",
(unsigned long)pci_addr, (unsigned long)(pci_addr + req_size - 1),
(unsigned int)slot, win, win, (unsigned long)devreg);
PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pconn_vhdl, "%s", tmp_str));
}
PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pconn_vhdl,
"pcibr_addr_pci_to_xio: map to space %s [0x%lx..0x%lx] "
"for slot %d allocates DevIO(%d) Device(%d) set to %lx\n",
pci_space[space], pci_addr, pci_addr + req_size - 1,
slot, win, win, devreg));
goto done;
} /* endif DevIO(x) not pointed */
mbase = pcibr_soft->bs_slot[win].bss_devio.bssd_base;
......@@ -2136,9 +2133,10 @@ pcibr_addr_pci_to_xio(vertex_hdl_t pconn_vhdl,
if (bar != -1)
pcibr_info->f_window[bar].w_devio_index = win;
if (pcibr_debug_mask & PCIBR_DEBUG_PIOMAP) {
PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pconn_vhdl, "%s", tmp_str));
}
PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pconn_vhdl,
"pcibr_addr_pci_to_xio: map to space %s [0x%lx..0x%lx] "
"for slot %d uses DevIO(%d)\n", pci_space[space],
pci_addr, pci_addr + req_size - 1, slot, win));
goto done;
}
......@@ -2194,17 +2192,6 @@ pcibr_addr_pci_to_xio(vertex_hdl_t pconn_vhdl,
*/
xio_addr = XIO_NOWHERE;
break;
/* Bridge Hardware Bug WAR #482741:
* The 4G area that maps directly from
* XIO space to PCI I/O space is busted
* until Bridge Rev D.
*/
if ((pcibr_soft->bs_rev_num > BRIDGE_PART_REV_C) &&
((pci_addr + BRIDGE_PCI_IO_BASE + req_size - 1) <=
BRIDGE_PCI_IO_LIMIT))
xio_addr = pci_addr + BRIDGE_PCI_IO_BASE;
break;
}
/* Check that "Direct PIO" byteswapping matches,
......@@ -2230,9 +2217,13 @@ pcibr_addr_pci_to_xio(vertex_hdl_t pconn_vhdl,
if (bfn == bfo) { /* we already match. */
;
} else if (bfo != 0) { /* we have a conflict. */
if (pcibr_debug_mask & PCIBR_DEBUG_PIOMAP) {
PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pconn_vhdl, "%s", tmp_str));
}
PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pconn_vhdl,
"pcibr_addr_pci_to_xio: swap conflict in %s, "
"was%s%s, want%s%s\n", pci_space[space],
bfo & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
bfo & PCIIO_WORD_VALUES ? " WORD_VALUES" : "",
bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : ""));
xio_addr = XIO_NOWHERE;
} else { /* OK to make the change. */
picreg_t octl, nctl;
......@@ -2244,9 +2235,11 @@ pcibr_addr_pci_to_xio(vertex_hdl_t pconn_vhdl,
bridge->b_wid_control = nctl;
*bfp = bfn; /* record the assignment */
if (pcibr_debug_mask & PCIBR_DEBUG_PIOMAP) {
PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pconn_vhdl, "%s", tmp_str));
}
PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pconn_vhdl,
"pcibr_addr_pci_to_xio: swap for %s set to%s%s\n",
pci_space[space],
bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : ""));
}
}
done:
......@@ -2358,7 +2351,7 @@ pcibr_piomap_alloc(vertex_hdl_t pconn_vhdl,
}
PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pconn_vhdl,
"pcibr_piomap_alloc: map=0x%x\n", pcibr_piomap));
"pcibr_piomap_alloc: map=0x%lx\n", pcibr_piomap));
return pcibr_piomap;
}
......@@ -2368,7 +2361,7 @@ void
pcibr_piomap_free(pcibr_piomap_t pcibr_piomap)
{
PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pcibr_piomap->bp_dev,
"pcibr_piomap_free: map=0x%x\n", pcibr_piomap));
"pcibr_piomap_free: map=0x%lx\n", pcibr_piomap));
xtalk_piomap_free(pcibr_piomap->bp_xtalk_pio);
pcibr_piomap->bp_xtalk_pio = 0;
......@@ -2387,7 +2380,7 @@ pcibr_piomap_addr(pcibr_piomap_t pcibr_piomap,
pci_addr - pcibr_piomap->bp_pciaddr,
req_size);
PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pcibr_piomap->bp_dev,
"pcibr_piomap_free: map=0x%x, addr=0x%x\n",
"pcibr_piomap_addr: map=0x%lx, addr=0x%lx\n",
pcibr_piomap, addr));
return(addr);
......@@ -2398,7 +2391,7 @@ void
pcibr_piomap_done(pcibr_piomap_t pcibr_piomap)
{
PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pcibr_piomap->bp_dev,
"pcibr_piomap_done: map=0x%x\n", pcibr_piomap));
"pcibr_piomap_done: map=0x%lx\n", pcibr_piomap));
xtalk_piomap_done(pcibr_piomap->bp_xtalk_pio);
}
......@@ -2429,7 +2422,7 @@ pcibr_piotrans_addr(vertex_hdl_t pconn_vhdl,
addr = xtalk_piotrans_addr(xconn_vhdl, 0, xio_addr, req_size, flags & PIOMAP_FLAGS);
PCIBR_DEBUG((PCIBR_DEBUG_PIODIR, pconn_vhdl,
"pcibr_piotrans_addr: xio_addr=0x%x, addr=0x%x\n",
"pcibr_piotrans_addr: xio_addr=0x%lx, addr=0x%lx\n",
xio_addr, addr));
return(addr);
}
......@@ -2473,7 +2466,8 @@ pcibr_piospace_alloc(vertex_hdl_t pconn_vhdl,
/*
* First look if a previously allocated chunk exists.
*/
if ((piosp = pcibr_info->f_piospace)) {
piosp = pcibr_info->f_piospace;
if (piosp) {
/*
* Look through the list for a right sized free chunk.
*/
......@@ -2547,7 +2541,7 @@ pcibr_piospace_alloc(vertex_hdl_t pconn_vhdl,
pcibr_unlock(pcibr_soft, s);
PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pconn_vhdl,
"pcibr_piospace_alloc: piosp=0x%x\n", piosp));
"pcibr_piospace_alloc: piosp=0x%lx\n", piosp));
return start_addr;
}
......@@ -2603,7 +2597,7 @@ pcibr_piospace_free(vertex_hdl_t pconn_vhdl,
pcibr_unlock(pcibr_soft, s);
PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pconn_vhdl,
"pcibr_piospace_free: piosp=0x%x\n", piosp));
"pcibr_piospace_free: piosp=0x%lx\n", piosp));
return;
}
......@@ -2715,6 +2709,7 @@ pcibr_dmamap_alloc(vertex_hdl_t pconn_vhdl,
int ate_count;
int ate_index;
int vchan = VCHAN0;
unsigned long s;
/* merge in forced flags */
flags |= pcibr_soft->bs_dma_flags;
......@@ -2723,7 +2718,9 @@ pcibr_dmamap_alloc(vertex_hdl_t pconn_vhdl,
* On SNIA64, these maps are pre-allocated because pcibr_dmamap_alloc()
* can be called within an interrupt thread.
*/
s = pcibr_lock(pcibr_soft);
pcibr_dmamap = (pcibr_dmamap_t)get_free_pciio_dmamap(pcibr_soft->bs_vhdl);
pcibr_unlock(pcibr_soft, s);
if (!pcibr_dmamap)
return 0;
......@@ -2782,7 +2779,7 @@ pcibr_dmamap_alloc(vertex_hdl_t pconn_vhdl,
}
}
PCIBR_DEBUG((PCIBR_DEBUG_DMAMAP | PCIBR_DEBUG_DMADIR, pconn_vhdl,
"pcibr_dmamap_alloc: using direct64, map=0x%x\n",
"pcibr_dmamap_alloc: using direct64, map=0x%lx\n",
pcibr_dmamap));
return pcibr_dmamap;
}
......@@ -2813,7 +2810,7 @@ pcibr_dmamap_alloc(vertex_hdl_t pconn_vhdl,
* is outside the direct32 range.
*/
PCIBR_DEBUG((PCIBR_DEBUG_DMAMAP | PCIBR_DEBUG_DMADIR, pconn_vhdl,
"pcibr_dmamap_alloc: using direct32, map=0x%x\n",
"pcibr_dmamap_alloc: using direct32, map=0x%lx\n",
pcibr_dmamap));
pcibr_dmamap->bd_flags = flags;
pcibr_dmamap->bd_xio_addr = pcibr_soft->bs_dir_xbase;
......@@ -2857,16 +2854,14 @@ pcibr_dmamap_alloc(vertex_hdl_t pconn_vhdl,
PCIBR_DEBUG((PCIBR_DEBUG_DMAMAP, pconn_vhdl,
"pcibr_dmamap_alloc: using PMU, ate_index=%d, "
"pcibr_dmamap=0x%x\n", ate_index, pcibr_dmamap));
"pcibr_dmamap=0x%lx\n", ate_index, pcibr_dmamap));
ate_proto = pcibr_flags_to_ate(flags);
pcibr_dmamap->bd_flags = flags;
pcibr_dmamap->bd_pci_addr =
PCI32_MAPPED_BASE + IOPGSIZE * ate_index;
/*
* for xbridge the byte-swap bit == bit 29 of PCI address
*/
if (flags & PCIIO_BYTE_STREAM)
ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
/*
......@@ -2947,7 +2942,7 @@ pcibr_dmamap_free(pcibr_dmamap_t pcibr_dmamap)
}
PCIBR_DEBUG((PCIBR_DEBUG_DMAMAP, pcibr_dmamap->bd_dev,
"pcibr_dmamap_free: pcibr_dmamap=0x%x\n", pcibr_dmamap));
"pcibr_dmamap_free: pcibr_dmamap=0x%lx\n", pcibr_dmamap));
free_pciio_dmamap(pcibr_dmamap);
}
......@@ -2990,16 +2985,8 @@ pcibr_addr_xio_to_pci(pcibr_soft_t soft,
return pci_addr;
}
} else {
if ((xio_addr >= BRIDGE_PCI_MEM32_BASE) &&
(xio_lim <= BRIDGE_PCI_MEM32_LIMIT)) {
pci_addr = xio_addr - BRIDGE_PCI_MEM32_BASE;
return pci_addr;
}
if ((xio_addr >= BRIDGE_PCI_MEM64_BASE) &&
(xio_lim <= BRIDGE_PCI_MEM64_LIMIT)) {
pci_addr = xio_addr - BRIDGE_PCI_MEM64_BASE;
return pci_addr;
}
printk("pcibr_addr_xio_to_pci(): unknown bridge type");
return (iopaddr_t)0;
}
for (slot = soft->bs_min_slot; slot < PCIBR_NUM_SLOTS(soft); ++slot)
if ((xio_addr >= PCIBR_BRIDGE_DEVIO(soft, slot)) &&
......@@ -3073,8 +3060,8 @@ pcibr_dmamap_addr(pcibr_dmamap_t pcibr_dmamap,
PCIBR_DEBUG((PCIBR_DEBUG_DMAMAP | PCIBR_DEBUG_DMADIR,
pcibr_dmamap->bd_dev,
"pcibr_dmamap_addr: (direct64): wanted paddr [0x%x..0x%x] "
"XIO port 0x%x offset 0x%x, returning PCI 0x%x\n",
"pcibr_dmamap_addr: (direct64): wanted paddr [0x%lx..0x%lx] "
"XIO port 0x%x offset 0x%lx, returning PCI 0x%lx\n",
paddr, paddr + req_size - 1, xio_port, xio_addr, pci_addr));
} else if (flags & PCIIO_FIXED) {
......@@ -3098,8 +3085,8 @@ pcibr_dmamap_addr(pcibr_dmamap_t pcibr_dmamap,
PCIBR_DEBUG((PCIBR_DEBUG_DMAMAP | PCIBR_DEBUG_DMADIR,
pcibr_dmamap->bd_dev,
"pcibr_dmamap_addr (direct32): wanted paddr [0x%x..0x%x] "
"XIO port 0x%x offset 0x%x, returning PCI 0x%x\n",
"pcibr_dmamap_addr (direct32): wanted paddr [0x%lx..0x%lx] "
"XIO port 0x%x offset 0x%lx, returning PCI 0x%lx\n",
paddr, paddr + req_size - 1, xio_port, xio_addr, pci_addr));
} else {
......@@ -3146,7 +3133,7 @@ pcibr_dmamap_addr(pcibr_dmamap_t pcibr_dmamap,
bridge->b_wid_tflush; /* wait until Bridge PIO complete */
PCIBR_DEBUG((PCIBR_DEBUG_DMAMAP, pcibr_dmamap->bd_dev,
"pcibr_dmamap_addr (PMU) : wanted paddr "
"[0x%x..0x%x] returning PCI 0x%x\n",
"[0x%lx..0x%lx] returning PCI 0x%lx\n",
paddr, paddr + req_size - 1, pci_addr));
} else {
......@@ -3160,7 +3147,7 @@ pcibr_dmamap_addr(pcibr_dmamap_t pcibr_dmamap,
*/
PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DMAMAP, pcibr_dmamap->bd_dev,
"pcibr_dmamap_addr (PMU) : wanted paddr "
"[0x%x..0x%x] ate_count 0x%x bd_ate_count 0x%x "
"[0x%lx..0x%lx] ate_count 0x%x bd_ate_count 0x%x "
"ATE's required > number allocated\n",
paddr, paddr + req_size - 1,
ate_count, pcibr_dmamap->bd_ate_count));
......@@ -3191,7 +3178,7 @@ pcibr_dmamap_done(pcibr_dmamap_t pcibr_dmamap)
xtalk_dmamap_done(pcibr_dmamap->bd_xtalk);
PCIBR_DEBUG((PCIBR_DEBUG_DMAMAP, pcibr_dmamap->bd_dev,
"pcibr_dmamap_done: pcibr_dmamap=0x%x\n", pcibr_dmamap));
"pcibr_dmamap_done: pcibr_dmamap=0x%lx\n", pcibr_dmamap));
}
......@@ -3242,8 +3229,8 @@ pcibr_dmatrans_addr(vertex_hdl_t pconn_vhdl,
flags & DMAMAP_FLAGS);
if (!xio_addr) {
PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DMADIR, pconn_vhdl,
"pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], "
"xtalk_dmatrans_addr failed with 0x%x\n",
"pcibr_dmatrans_addr: wanted paddr [0x%lx..0x%lx], "
"xtalk_dmatrans_addr failed with 0x%lx\n",
paddr, paddr + req_size - 1, xio_addr));
return 0;
}
......@@ -3253,7 +3240,7 @@ pcibr_dmatrans_addr(vertex_hdl_t pconn_vhdl,
if (XIO_PACKED(xio_addr)) {
if (xio_addr == XIO_NOWHERE) {
PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DMADIR, pconn_vhdl,
"pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], "
"pcibr_dmatrans_addr: wanted paddr [0x%lx..0x%lx], "
"xtalk_dmatrans_addr failed with XIO_NOWHERE\n",
paddr, paddr + req_size - 1));
return 0;
......@@ -3274,8 +3261,8 @@ pcibr_dmatrans_addr(vertex_hdl_t pconn_vhdl,
if (xio_port == pcibr_soft->bs_xid) {
pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, req_size);
PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl,
"pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], "
"xio_port=0x%x, pci_addr=0x%x\n",
"pcibr_dmatrans_addr: wanted paddr [0x%lx..0x%lx], "
"xio_port=0x%x, pci_addr=0x%lx\n",
paddr, paddr + req_size - 1, xio_port, pci_addr));
return pci_addr;
}
......@@ -3329,19 +3316,16 @@ pcibr_dmatrans_addr(vertex_hdl_t pconn_vhdl,
min_rrbs - have_rrbs);
}
}
#if HWG_PERF_CHECK
if (xio_addr != 0x20000000)
#endif
PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl,
"pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], "
"xio_port=0x%x, direct64: pci_addr=0x%x, "
"pcibr_dmatrans_addr: wanted paddr [0x%lx..0x%lx], "
"xio_port=0x%x, direct64: pci_addr=0x%lx, "
"new flags: 0x%x\n", paddr, paddr + req_size - 1,
xio_addr, pci_addr, (uint64_t) flags));
return (pci_addr);
}
PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl,
"pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], "
"pcibr_dmatrans_addr: wanted paddr [0x%lx..0x%lx], "
"xio_port=0x%x, Unable to set direct64 Device(x) bits\n",
paddr, paddr + req_size - 1, xio_addr));
......@@ -3352,6 +3336,11 @@ pcibr_dmatrans_addr(vertex_hdl_t pconn_vhdl,
/* our flags conflict with Device(x). try direct32*/
flags = flags & ~(PCIIO_DMA_A64 | PCIBR_VCHAN0);
} else {
/* BUS in PCI-X mode only supports 64-bit direct mapping */
if (IS_PCIX(pcibr_soft)) {
return 0;
}
}
/* Try to satisfy the request with the 32-bit direct
* map. This can fail if the configuration bits in
......@@ -3370,7 +3359,7 @@ pcibr_dmatrans_addr(vertex_hdl_t pconn_vhdl,
(endoff > map_size)) {
PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl,
"pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], "
"pcibr_dmatrans_addr: wanted paddr [0x%lx..0x%lx], "
"xio_port=0x%x, xio region outside direct32 target\n",
paddr, paddr + req_size - 1, xio_addr));
} else {
......@@ -3381,8 +3370,8 @@ pcibr_dmatrans_addr(vertex_hdl_t pconn_vhdl,
pci_addr |= offset;
PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl,
"pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], "
"xio_port=0x%x, direct32: pci_addr=0x%x\n",
"pcibr_dmatrans_addr: wanted paddr [0x%lx..0x%lx],"
" xio_port=0x%x, direct32: pci_addr=0x%lx\n",
paddr, paddr + req_size - 1, xio_addr, pci_addr));
return (pci_addr);
......@@ -3408,12 +3397,9 @@ pcibr_dmatrans_addr(vertex_hdl_t pconn_vhdl,
vchan, min_rrbs - have_rrbs);
}
}
#if HWG_PERF_CHECK
if (xio_addr != 0x20000000)
#endif
PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl,
"pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], "
"xio_port=0x%x, direct32: pci_addr=0x%x, "
"pcibr_dmatrans_addr: wanted paddr [0x%lx..0x%lx],"
" xio_port=0x%x, direct32: pci_addr=0x%lx, "
"new flags: 0x%x\n", paddr, paddr + req_size - 1,
xio_addr, pci_addr, (uint64_t) flags));
......@@ -3422,14 +3408,14 @@ pcibr_dmatrans_addr(vertex_hdl_t pconn_vhdl,
/* our flags conflict with Device(x).
*/
PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl,
"pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], "
"pcibr_dmatrans_addr: wanted paddr [0x%lx..0x%lx], "
"xio_port=0x%x, Unable to set direct32 Device(x) bits\n",
paddr, paddr + req_size - 1, xio_port));
}
}
PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl,
"pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], "
"pcibr_dmatrans_addr: wanted paddr [0x%lx..0x%lx], "
"xio_port=0x%x, No acceptable PCI address found\n",
paddr, paddr + req_size - 1, xio_port));
......@@ -3693,7 +3679,10 @@ pcibr_device_flags_set(vertex_hdl_t pconn_vhdl,
bridge->b_wid_tflush; /* wait until Bridge PIO complete */
}
pcibr_unlock(pcibr_soft, s);
printk("pcibr_device_flags_set: Device(%d): %x\n", pciio_slot, devreg);
PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DEVREG, pconn_vhdl,
"pcibr_device_flags_set: Device(%d): 0x%x\n",
pciio_slot, devreg));
}
return (1);
}
......@@ -3818,23 +3807,26 @@ pcibr_debug(uint32_t type, vertex_hdl_t vhdl, char *format, ...)
if (strcmp(module, pcibr_debug_module)) {
/* use a copy */
(void)strcpy(copy_of_hwpath, hwpath);
cp = strstr(copy_of_hwpath, "/module/");
cp = strstr(copy_of_hwpath, "/" EDGE_LBL_MODULE "/");
if (cp) {
cp += strlen("/module");
cp += strlen("/" EDGE_LBL_MODULE "/");
module = strsep(&cp, "/");
}
}
if (pcibr_debug_widget != -1) {
cp = strstr(hwpath, "/xtalk/");
cp = strstr(hwpath, "/" EDGE_LBL_XTALK "/");
if (cp) {
cp += strlen("/xtalk/");
cp += strlen("/" EDGE_LBL_XTALK "/");
widget = simple_strtoul(cp, NULL, 0);
}
}
if (pcibr_debug_slot != -1) {
cp = strstr(hwpath, "/pci/");
cp = strstr(hwpath, "/" EDGE_LBL_PCIX_0 "/");
if (!cp) {
cp = strstr(hwpath, "/" EDGE_LBL_PCIX_1 "/");
}
if (cp) {
cp += strlen("/pci/");
cp += strlen("/" EDGE_LBL_PCIX_0 "/");
slot = simple_strtoul(cp, NULL, 0);
}
}
......
include/asm-ia64/sn/pci/pcibr_private.h
View file @ 8e00ee40
......@@ -300,7 +300,8 @@ struct pcibr_intr_wrap_s {
*/
#define PV854697 (~0) /* PIC: write 64bit regs as 64bits. permanent */
#define PV854827 (~0) /* PIC: fake widget 0xf presence bit. permanent */
#define PV855271 (1 << 1) /* PIC: PIC: use virt chan iff 64-bit device. */
#define PV855271 (1 << 1) /* PIC: use virt chan iff 64-bit device. */
#define PV878674 (~0) /* PIC: Dont allow 64bit PIOs. permanent */
#define PV855272 (1 << 1) /* PIC: runaway interrupt WAR */
#define PV856155 (1 << 1) /* PIC: arbitration WAR */
#define PV856864 (1 << 1) /* PIC: lower timeout to free TNUMs quicker */
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7