Commit 8fc06ebc authored by Xingyue Tao's avatar Xingyue Tao Committed by Alex Deucher

drm/amd/display: Only limit VSR downscaling when actually downscaling

Signed-off-by: default avatarXingyue Tao <xingyue.tao@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent eb815442
......@@ -145,18 +145,17 @@ bool dpp_get_optimal_number_of_taps(
else
pixel_width = scl_data->viewport.width;
if (scl_data->viewport.width != scl_data->h_active &&
scl_data->viewport.height != scl_data->v_active) {
/* Some ASICs does not support FP16 scaling, so we reject modes require this*/
if (dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
if (scl_data->viewport.width != scl_data->h_active &&
scl_data->viewport.height != scl_data->v_active &&
dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
scl_data->format == PIXEL_FORMAT_FP16)
return false;
if (dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
if (scl_data->viewport.width > scl_data->h_active &&
dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
return false;
}
/* TODO: add lb check */
......
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