Commit 9034e510 authored by David Mosberger's avatar David Mosberger

Merge tiger.hpl.hp.com:/data1/bk/vanilla/linux-2.5

into tiger.hpl.hp.com:/data1/bk/lia64/to-linus-2.5
parents a8588521 a09f2c11
...@@ -293,7 +293,7 @@ iosapic_set_affinity (unsigned int irq, cpumask_t mask) ...@@ -293,7 +293,7 @@ iosapic_set_affinity (unsigned int irq, cpumask_t mask)
irq &= (~IA64_IRQ_REDIRECTED); irq &= (~IA64_IRQ_REDIRECTED);
vec = irq_to_vector(irq); vec = irq_to_vector(irq);
if (cpus_empty(mask) || vec >= IA64_NUM_VECTORS) if (cpus_empty(mask))
return; return;
dest = cpu_physical_id(first_cpu(mask)); dest = cpu_physical_id(first_cpu(mask));
......
...@@ -445,6 +445,7 @@ setup_frame (int sig, struct k_sigaction *ka, siginfo_t *info, sigset_t *set, ...@@ -445,6 +445,7 @@ setup_frame (int sig, struct k_sigaction *ka, siginfo_t *info, sigset_t *set,
scr->pt.ar_fpsr = FPSR_DEFAULT; /* reset fpsr for signal handler */ scr->pt.ar_fpsr = FPSR_DEFAULT; /* reset fpsr for signal handler */
scr->pt.cr_iip = tramp_addr; scr->pt.cr_iip = tramp_addr;
ia64_psr(&scr->pt)->ri = 0; /* start executing in first slot */ ia64_psr(&scr->pt)->ri = 0; /* start executing in first slot */
ia64_psr(&scr->pt)->be = 0; /* force little-endian byte-order */
/* /*
* Force the interruption function mask to zero. This has no effect when a * Force the interruption function mask to zero. This has no effect when a
* system-call got interrupted by a signal (since, in that case, scr->pt_cr_ifs is * system-call got interrupted by a signal (since, in that case, scr->pt_cr_ifs is
......
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
#include <linux/sched.h> #include <linux/sched.h>
#include <linux/tty.h> #include <linux/tty.h>
#include <linux/vt_kern.h> /* For unblank_screen() */ #include <linux/vt_kern.h> /* For unblank_screen() */
#include <linux/module.h> /* for EXPORT_SYMBOL */
#include <asm/fpswa.h> #include <asm/fpswa.h>
#include <asm/hardirq.h> #include <asm/hardirq.h>
...@@ -47,6 +48,7 @@ register double f30 asm ("f30"); register double f31 asm ("f31"); ...@@ -47,6 +48,7 @@ register double f30 asm ("f30"); register double f31 asm ("f31");
extern spinlock_t timerlist_lock; extern spinlock_t timerlist_lock;
fpswa_interface_t *fpswa_interface; fpswa_interface_t *fpswa_interface;
EXPORT_SYMBOL(fpswa_interface);
void __init void __init
trap_init (void) trap_init (void)
......
...@@ -58,36 +58,6 @@ struct pci_fixup pcibios_fixups[1]; ...@@ -58,36 +58,6 @@ struct pci_fixup pcibios_fixups[1];
((u64)(seg << 24) | (u64)(bus << 16) | \ ((u64)(seg << 24) | (u64)(bus << 16) | \
(u64)(devfn << 8) | (u64)(reg)) (u64)(devfn << 8) | (u64)(reg))
static int
pci_sal_read (int seg, int bus, int devfn, int reg, int len, u32 *value)
{
int result = 0;
u64 data = 0;
if ((seg > 255) || (bus > 255) || (devfn > 255) || (reg > 255))
return -EINVAL;
result = ia64_sal_pci_config_read(PCI_SAL_ADDRESS(seg, bus, devfn, reg), 0, len, &data);
*value = (u32) data;
return result;
}
static int
pci_sal_write (int seg, int bus, int devfn, int reg, int len, u32 value)
{
if ((seg > 255) || (bus > 255) || (devfn > 255) || (reg > 255))
return -EINVAL;
return ia64_sal_pci_config_write(PCI_SAL_ADDRESS(seg, bus, devfn, reg), 0, len, value);
}
static struct pci_raw_ops pci_sal_ops = {
.read = pci_sal_read,
.write = pci_sal_write
};
/* SAL 3.2 adds support for extended config space. */ /* SAL 3.2 adds support for extended config space. */
#define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \ #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
...@@ -95,15 +65,22 @@ static struct pci_raw_ops pci_sal_ops = { ...@@ -95,15 +65,22 @@ static struct pci_raw_ops pci_sal_ops = {
(u64)(devfn << 12) | (u64)(reg)) (u64)(devfn << 12) | (u64)(reg))
static int static int
pci_sal_ext_read (int seg, int bus, int devfn, int reg, int len, u32 *value) pci_sal_read (int seg, int bus, int devfn, int reg, int len, u32 *value)
{ {
u64 addr, mode, data = 0;
int result = 0; int result = 0;
u64 data = 0;
if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) if ((seg > 255) || (bus > 255) || (devfn > 255) || (reg > 4095))
return -EINVAL; return -EINVAL;
result = ia64_sal_pci_config_read(PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg), 1, len, &data); if ((seg | reg) <= 255) {
addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
mode = 0;
} else {
addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
mode = 1;
}
result = ia64_sal_pci_config_read(addr, mode, len, &data);
*value = (u32) data; *value = (u32) data;
...@@ -111,33 +88,29 @@ pci_sal_ext_read (int seg, int bus, int devfn, int reg, int len, u32 *value) ...@@ -111,33 +88,29 @@ pci_sal_ext_read (int seg, int bus, int devfn, int reg, int len, u32 *value)
} }
static int static int
pci_sal_ext_write (int seg, int bus, int devfn, int reg, int len, u32 value) pci_sal_write (int seg, int bus, int devfn, int reg, int len, u32 value)
{ {
u64 addr, mode;
if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
return -EINVAL; return -EINVAL;
return ia64_sal_pci_config_write(PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg), 1, len, value); if ((seg | reg) <= 255) {
} addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
mode = 0;
static struct pci_raw_ops pci_sal_ext_ops = { } else {
.read = pci_sal_ext_read, addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
.write = pci_sal_ext_write mode = 1;
};
struct pci_raw_ops *raw_pci_ops = &pci_sal_ops; /* default to SAL < 3.2 */
static int __init
pci_set_sal_ops (void)
{
if (sal_revision >= SAL_VERSION_CODE(3, 2)) {
printk("Using SAL 3.2 to access PCI config space\n");
raw_pci_ops = &pci_sal_ext_ops;
} }
return 0; return ia64_sal_pci_config_write(addr, mode, len, value);
} }
arch_initcall(pci_set_sal_ops); static struct pci_raw_ops pci_sal_ops = {
.read = pci_sal_read,
.write = pci_sal_write
};
struct pci_raw_ops *raw_pci_ops = &pci_sal_ops;
static int static int
pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
......
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