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Commit 912b330c authored by Dave Airlie's avatar Dave Airlie
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Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into drm-next 

Big ticket items are hdmi support for 8996 (aka snapdragon 820), and
adreno 430 support.  Also one more small uapi addition to support
timestamp queries.

* 'msm-next' of git://people.freedesktop.org/~robclark/linux: (29 commits)
  drm/msm: rename hdmi symbols
  drm/msm/adreno: remove duplicate adreno_hw_init() call
  drm/msm: add timestamp param
  drm/msm: fix small typo
  drm/msm: grab struct_mutex after allocating submit
  drm/msm: reject submit ioctl if no gpu
  drm/msm/adreno: print details in case of a protect fault interrupt
  drm/msm/adreno: get CP_RPTR from register instead of shadow memory
  drm/msm/adreno: add adreno430 power control
  drm/msm/adreno: support for adreno 430.
  drm/msm: update generated headers
  drm/msm/dsi: fix definition of msm_dsi_pll_28nm_8960_init()
  drm/msm/dsi: Parse DSI lanes via DT
  drm/msm/dsi: Drop VDD regulator for MSM8916
  drm/msm/dsi: Remove incorrect warning on host attach
  drm/msm: Free fb helper resources in msm_unload
  drm/msm/mdp: Detach iommu in mdp4_destroy
  drm/msm: make iommu port names const'ier
  drm/msm/mdp: Use atomic helper to set crtc property
  dt-bindings: msm/hdmi: Add HDMI PHY bindings
  ...
parents 42e85606 fcda50c8
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Documentation/devicetree/bindings/display/msm/dsi.txt
View file @ 912b330c
......@@ -44,9 +44,34 @@ Optional properties:
- pinctrl-names: the pin control state names; should contain "default"
- pinctrl-0: the default pinctrl state (active)
- pinctrl-n: the "sleep" pinctrl state
- port: DSI controller output port. This contains one endpoint subnode, with its
remote-endpoint set to the phandle of the connected panel's endpoint.
See Documentation/devicetree/bindings/graph.txt for device graph info.
- port: DSI controller output port, containing one endpoint subnode.
DSI Endpoint properties:
- remote-endpoint: set to phandle of the connected panel's endpoint.
See Documentation/devicetree/bindings/graph.txt for device graph info.
- qcom,data-lane-map: this describes how the logical DSI lanes are mapped
to the physical lanes on the given platform. The value contained in
index n describes what logical data lane is mapped to the physical data
lane n (DATAn, where n lies between 0 and 3).
For example:
qcom,data-lane-map = <3 0 1 2>;
The above mapping describes that the logical data lane DATA3 is mapped to
the physical data lane DATA0, logical DATA0 to physical DATA1, logic DATA1
to phys DATA2 and logic DATA2 to phys DATA3.
There are only a limited number of physical to logical mappings possible:
"0123": Logic 0->Phys 0; Logic 1->Phys 1; Logic 2->Phys 2; Logic 3->Phys 3;
"3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
"2301": Logic 2->Phys 0; Logic 3->Phys 1; Logic 0->Phys 2; Logic 1->Phys 3;
"1230": Logic 1->Phys 0; Logic 2->Phys 1; Logic 3->Phys 2; Logic 0->Phys 3;
"0321": Logic 0->Phys 0; Logic 3->Phys 1; Logic 2->Phys 2; Logic 1->Phys 3;
"1032": Logic 1->Phys 0; Logic 0->Phys 1; Logic 3->Phys 2; Logic 2->Phys 3;
"2103": Logic 2->Phys 0; Logic 1->Phys 1; Logic 0->Phys 2; Logic 3->Phys 3;
"3210": Logic 3->Phys 0; Logic 2->Phys 1; Logic 1->Phys 2; Logic 0->Phys 3;
DSI PHY:
Required properties:
......@@ -131,6 +156,7 @@ Example:
port {
dsi0_out: endpoint {
remote-endpoint = <&panel_in>;
lanes = <0 1 2 3>;
};
};
};
......
Documentation/devicetree/bindings/display/msm/hdmi.txt
View file @ 912b330c
......@@ -11,6 +11,7 @@ Required properties:
- reg: Physical base address and length of the controller's registers
- reg-names: "core_physical"
- interrupts: The interrupt signal from the hdmi block.
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: device clocks
See ../clocks/clock-bindings.txt for details.
- qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin
......@@ -18,6 +19,8 @@ Required properties:
- qcom,hdmi-tx-hpd-gpio: hpd pin
- core-vdda-supply: phandle to supply regulator
- hdmi-mux-supply: phandle to mux regulator
- phys: the phandle for the HDMI PHY device
- phy-names: the name of the corresponding PHY device
Optional properties:
- qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
......@@ -27,15 +30,38 @@ Optional properties:
- pinctrl-0: the default pinctrl state (active)
- pinctrl-1: the "sleep" pinctrl state
HDMI PHY:
Required properties:
- compatible: Could be the following
* "qcom,hdmi-phy-8660"
* "qcom,hdmi-phy-8960"
* "qcom,hdmi-phy-8974"
* "qcom,hdmi-phy-8084"
* "qcom,hdmi-phy-8996"
- #phy-cells: Number of cells in a PHY specifier; Should be 0.
- reg: Physical base address and length of the registers of the PHY sub blocks.
- reg-names: The names of register regions. The following regions are required:
* "hdmi_phy"
* "hdmi_pll"
For HDMI PHY on msm8996, these additional register regions are required:
* "hdmi_tx_l0"
* "hdmi_tx_l1"
* "hdmi_tx_l3"
* "hdmi_tx_l4"
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: device clocks
See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
- core-vdda-supply: phandle to vdda regulator device node
Example:
/ {
...
hdmi: qcom,hdmi-tx-8960@4a00000 {
hdmi: hdmi@4a00000 {
compatible = "qcom,hdmi-tx-8960";
reg-names = "core_physical";
reg = <0x04a00000 0x1000>;
reg = <0x04a00000 0x2f0>;
interrupts = <GIC_SPI 79 0>;
power-domains = <&mmcc MDSS_GDSC>;
clock-names =
......@@ -54,5 +80,21 @@ Example:
pinctrl-names = "default", "sleep";
pinctrl-0 = <&hpd_active &ddc_active &cec_active>;
pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;
phys = <&hdmi_phy>;
phy-names = "hdmi_phy";
};
hdmi_phy: phy@4a00400 {
compatible = "qcom,hdmi-phy-8960";
reg-names = "hdmi_phy",
"hdmi_pll";
reg = <0x4a00400 0x60>,
<0x4a00500 0x100>;
#phy-cells = <0>;
power-domains = <&mmcc MDSS_GDSC>;
clock-names = "slave_iface_clk";
clocks = <&mmcc HDMI_S_AHB_CLK>;
core-vdda-supply = <&pm8921_hdmi_mvs>;
};
};
drivers/gpu/drm/msm/Makefile
View file @ 912b330c
......@@ -12,6 +12,7 @@ msm-y := \
hdmi/hdmi_connector.o \
hdmi/hdmi_hdcp.o \
hdmi/hdmi_i2c.o \
hdmi/hdmi_phy.o \
hdmi/hdmi_phy_8960.o \
hdmi/hdmi_phy_8x60.o \
hdmi/hdmi_phy_8x74.o \
......@@ -52,6 +53,8 @@ msm-y := \
msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o
msm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_pll_8960.o
msm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_phy_8996.o
msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
mdp/mdp4/mdp4_dsi_encoder.o \
......
drivers/gpu/drm/msm/adreno/a2xx.xml.h
View file @ 912b330c
......@@ -9,16 +9,17 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
......
drivers/gpu/drm/msm/adreno/a3xx.xml.h
View file @ 912b330c
......@@ -9,16 +9,17 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
Copyright (C) 2013-2015 by the following authors:
Copyright (C) 2013-2016 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
......@@ -111,10 +112,14 @@ enum a3xx_vtx_fmt {
VFMT_8_8_SNORM = 53,
VFMT_8_8_8_SNORM = 54,
VFMT_8_8_8_8_SNORM = 55,
VFMT_10_10_10_2_UINT = 60,
VFMT_10_10_10_2_UNORM = 61,
VFMT_10_10_10_2_SINT = 62,
VFMT_10_10_10_2_SNORM = 63,
VFMT_10_10_10_2_UINT = 56,
VFMT_10_10_10_2_UNORM = 57,
VFMT_10_10_10_2_SINT = 58,
VFMT_10_10_10_2_SNORM = 59,
VFMT_2_10_10_10_UINT = 60,
VFMT_2_10_10_10_UNORM = 61,
VFMT_2_10_10_10_SINT = 62,
VFMT_2_10_10_10_SNORM = 63,
};
enum a3xx_tex_fmt {
......@@ -138,10 +143,12 @@ enum a3xx_tex_fmt {
TFMT_DXT1 = 36,
TFMT_DXT3 = 37,
TFMT_DXT5 = 38,
TFMT_2_10_10_10_UNORM = 40,
TFMT_10_10_10_2_UNORM = 41,
TFMT_9_9_9_E5_FLOAT = 42,
TFMT_11_11_10_FLOAT = 43,
TFMT_A8_UNORM = 44,
TFMT_L8_UNORM = 45,
TFMT_L8_A8_UNORM = 47,
TFMT_8_UNORM = 48,
TFMT_8_8_UNORM = 49,
......@@ -183,6 +190,8 @@ enum a3xx_tex_fmt {
TFMT_32_SINT = 92,
TFMT_32_32_SINT = 93,
TFMT_32_32_32_32_SINT = 95,
TFMT_2_10_10_10_UINT = 96,
TFMT_10_10_10_2_UINT = 97,
TFMT_ETC2_RG11_SNORM = 112,
TFMT_ETC2_RG11_UNORM = 113,
TFMT_ETC2_R11_SNORM = 114,
......@@ -215,6 +224,9 @@ enum a3xx_color_fmt {
RB_R8_UINT = 14,
RB_R8_SINT = 15,
RB_R10G10B10A2_UNORM = 16,
RB_A2R10G10B10_UNORM = 17,
RB_R10G10B10A2_UINT = 18,
RB_A2R10G10B10_UINT = 19,
RB_A8_UNORM = 20,
RB_R8_UNORM = 21,
RB_R16_FLOAT = 24,
......@@ -244,30 +256,273 @@ enum a3xx_color_fmt {
RB_R32G32B32A32_UINT = 59,
};
enum a3xx_cp_perfcounter_select {
CP_ALWAYS_COUNT = 0,
CP_AHB_PFPTRANS_WAIT = 3,
CP_AHB_NRTTRANS_WAIT = 6,
CP_CSF_NRT_READ_WAIT = 8,
CP_CSF_I1_FIFO_FULL = 9,
CP_CSF_I2_FIFO_FULL = 10,
CP_CSF_ST_FIFO_FULL = 11,
CP_RESERVED_12 = 12,
CP_CSF_RING_ROQ_FULL = 13,
CP_CSF_I1_ROQ_FULL = 14,
CP_CSF_I2_ROQ_FULL = 15,
CP_CSF_ST_ROQ_FULL = 16,
CP_RESERVED_17 = 17,
CP_MIU_TAG_MEM_FULL = 18,
CP_MIU_NRT_WRITE_STALLED = 22,
CP_MIU_NRT_READ_STALLED = 23,
CP_ME_REGS_RB_DONE_FIFO_FULL = 26,
CP_ME_REGS_VS_EVENT_FIFO_FULL = 27,
CP_ME_REGS_PS_EVENT_FIFO_FULL = 28,
CP_ME_REGS_CF_EVENT_FIFO_FULL = 29,
CP_ME_MICRO_RB_STARVED = 30,
CP_AHB_RBBM_DWORD_SENT = 40,
CP_ME_BUSY_CLOCKS = 41,
CP_ME_WAIT_CONTEXT_AVAIL = 42,
CP_PFP_TYPE0_PACKET = 43,
CP_PFP_TYPE3_PACKET = 44,
CP_CSF_RB_WPTR_NEQ_RPTR = 45,
CP_CSF_I1_SIZE_NEQ_ZERO = 46,
CP_CSF_I2_SIZE_NEQ_ZERO = 47,
CP_CSF_RBI1I2_FETCHING = 48,
};
enum a3xx_gras_tse_perfcounter_select {
GRAS_TSEPERF_INPUT_PRIM = 0,
GRAS_TSEPERF_INPUT_NULL_PRIM = 1,
GRAS_TSEPERF_TRIVAL_REJ_PRIM = 2,
GRAS_TSEPERF_CLIPPED_PRIM = 3,
GRAS_TSEPERF_NEW_PRIM = 4,
GRAS_TSEPERF_ZERO_AREA_PRIM = 5,
GRAS_TSEPERF_FACENESS_CULLED_PRIM = 6,
GRAS_TSEPERF_ZERO_PIXEL_PRIM = 7,
GRAS_TSEPERF_OUTPUT_NULL_PRIM = 8,
GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM = 9,
GRAS_TSEPERF_PRE_CLIP_PRIM = 10,
GRAS_TSEPERF_POST_CLIP_PRIM = 11,
GRAS_TSEPERF_WORKING_CYCLES = 12,
GRAS_TSEPERF_PC_STARVE = 13,
GRAS_TSERASPERF_STALL = 14,
};
enum a3xx_gras_ras_perfcounter_select {
GRAS_RASPERF_16X16_TILES = 0,
GRAS_RASPERF_8X8_TILES = 1,
GRAS_RASPERF_4X4_TILES = 2,
GRAS_RASPERF_WORKING_CYCLES = 3,
GRAS_RASPERF_STALL_CYCLES_BY_RB = 4,
GRAS_RASPERF_STALL_CYCLES_BY_VSC = 5,
GRAS_RASPERF_STARVE_CYCLES_BY_TSE = 6,
};
enum a3xx_hlsq_perfcounter_select {
HLSQ_PERF_SP_VS_CONSTANT = 0,
HLSQ_PERF_SP_VS_INSTRUCTIONS = 1,
HLSQ_PERF_SP_FS_CONSTANT = 2,
HLSQ_PERF_SP_FS_INSTRUCTIONS = 3,
HLSQ_PERF_TP_STATE = 4,
HLSQ_PERF_QUADS = 5,
HLSQ_PERF_PIXELS = 6,
HLSQ_PERF_VERTICES = 7,
HLSQ_PERF_FS8_THREADS = 8,
HLSQ_PERF_FS16_THREADS = 9,
HLSQ_PERF_FS32_THREADS = 10,
HLSQ_PERF_VS8_THREADS = 11,
HLSQ_PERF_VS16_THREADS = 12,
HLSQ_PERF_SP_VS_DATA_BYTES = 13,
HLSQ_PERF_SP_FS_DATA_BYTES = 14,
HLSQ_PERF_ACTIVE_CYCLES = 15,
HLSQ_PERF_STALL_CYCLES_SP_STATE = 16,
HLSQ_PERF_STALL_CYCLES_SP_VS = 17,
HLSQ_PERF_STALL_CYCLES_SP_FS = 18,
HLSQ_PERF_STALL_CYCLES_UCHE = 19,
HLSQ_PERF_RBBM_LOAD_CYCLES = 20,
HLSQ_PERF_DI_TO_VS_START_SP0 = 21,
HLSQ_PERF_DI_TO_FS_START_SP0 = 22,
HLSQ_PERF_VS_START_TO_DONE_SP0 = 23,
HLSQ_PERF_FS_START_TO_DONE_SP0 = 24,
HLSQ_PERF_SP_STATE_COPY_CYCLES_VS = 25,
HLSQ_PERF_SP_STATE_COPY_CYCLES_FS = 26,
HLSQ_PERF_UCHE_LATENCY_CYCLES = 27,
HLSQ_PERF_UCHE_LATENCY_COUNT = 28,
};
enum a3xx_pc_perfcounter_select {
PC_PCPERF_VISIBILITY_STREAMS = 0,
PC_PCPERF_TOTAL_INSTANCES = 1,
PC_PCPERF_PRIMITIVES_PC_VPC = 2,
PC_PCPERF_PRIMITIVES_KILLED_BY_VS = 3,
PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS = 4,
PC_PCPERF_DRAWCALLS_KILLED_BY_VS = 5,
PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS = 6,
PC_PCPERF_VERTICES_TO_VFD = 7,
PC_PCPERF_REUSED_VERTICES = 8,
PC_PCPERF_CYCLES_STALLED_BY_VFD = 9,
PC_PCPERF_CYCLES_STALLED_BY_TSE = 10,
PC_PCPERF_CYCLES_STALLED_BY_VBIF = 11,
PC_PCPERF_CYCLES_IS_WORKING = 12,
};
enum a3xx_rb_perfcounter_select {
RB_RBPERF_ACTIVE_CYCLES_ANY = 0,
RB_RBPERF_ACTIVE_CYCLES_ALL = 1,
RB_RBPERF_STARVE_CYCLES_BY_SP = 2,
RB_RBPERF_STARVE_CYCLES_BY_RAS = 3,
RB_RBPERF_STARVE_CYCLES_BY_MARB = 4,
RB_RBPERF_STALL_CYCLES_BY_MARB = 5,
RB_RBPERF_STALL_CYCLES_BY_HLSQ = 6,
RB_RBPERF_RB_MARB_DATA = 7,
RB_RBPERF_SP_RB_QUAD = 8,
RB_RBPERF_RAS_EARLY_Z_QUADS = 9,
RB_RBPERF_GMEM_CH0_READ = 10,
RB_RBPERF_GMEM_CH1_READ = 11,
RB_RBPERF_GMEM_CH0_WRITE = 12,
RB_RBPERF_GMEM_CH1_WRITE = 13,
RB_RBPERF_CP_CONTEXT_DONE = 14,
RB_RBPERF_CP_CACHE_FLUSH = 15,
RB_RBPERF_CP_ZPASS_DONE = 16,
};
enum a3xx_rbbm_perfcounter_select {
RBBM_ALAWYS_ON = 0,
RBBM_VBIF_BUSY = 1,
RBBM_TSE_BUSY = 2,
RBBM_RAS_BUSY = 3,
RBBM_PC_DCALL_BUSY = 4,
RBBM_PC_VSD_BUSY = 5,
RBBM_VFD_BUSY = 6,
RBBM_VPC_BUSY = 7,
RBBM_UCHE_BUSY = 8,
RBBM_VSC_BUSY = 9,
RBBM_HLSQ_BUSY = 10,
RBBM_ANY_RB_BUSY = 11,
RBBM_ANY_TEX_BUSY = 12,
RBBM_ANY_USP_BUSY = 13,
RBBM_ANY_MARB_BUSY = 14,
RBBM_ANY_ARB_BUSY = 15,
RBBM_AHB_STATUS_BUSY = 16,
RBBM_AHB_STATUS_STALLED = 17,
RBBM_AHB_STATUS_TXFR = 18,
RBBM_AHB_STATUS_TXFR_SPLIT = 19,
RBBM_AHB_STATUS_TXFR_ERROR = 20,
RBBM_AHB_STATUS_LONG_STALL = 21,
RBBM_RBBM_STATUS_MASKED = 22,
};
enum a3xx_sp_perfcounter_select {
SP_LM_LOAD_INSTRUCTIONS = 0,
SP_LM_STORE_INSTRUCTIONS = 1,
SP_LM_ATOMICS = 2,
SP_UCHE_LOAD_INSTRUCTIONS = 3,
SP_UCHE_STORE_INSTRUCTIONS = 4,
SP_UCHE_ATOMICS = 5,
SP_VS_TEX_INSTRUCTIONS = 6,
SP_VS_CFLOW_INSTRUCTIONS = 7,
SP_VS_EFU_INSTRUCTIONS = 8,
SP_VS_FULL_ALU_INSTRUCTIONS = 9,
SP_VS_HALF_ALU_INSTRUCTIONS = 10,
SP_FS_TEX_INSTRUCTIONS = 11,
SP_FS_CFLOW_INSTRUCTIONS = 12,
SP_FS_EFU_INSTRUCTIONS = 13,
SP_FS_FULL_ALU_INSTRUCTIONS = 14,
SP0_ICL1_MISSES = 26,
SP_FS_HALF_ALU_INSTRUCTIONS = 15,
SP_FS_BARY_INSTRUCTIONS = 16,
SP_VS_INSTRUCTIONS = 17,
SP_FS_INSTRUCTIONS = 18,
SP_ADDR_LOCK_COUNT = 19,
SP_UCHE_READ_TRANS = 20,
SP_UCHE_WRITE_TRANS = 21,
SP_EXPORT_VPC_TRANS = 22,
SP_EXPORT_RB_TRANS = 23,
SP_PIXELS_KILLED = 24,
SP_ICL1_REQUESTS = 25,
SP_ICL1_MISSES = 26,
SP_ICL0_REQUESTS = 27,
SP_ICL0_MISSES = 28,
SP_ALU_ACTIVE_CYCLES = 29,
SP_EFU_ACTIVE_CYCLES = 30,
SP_STALL_CYCLES_BY_VPC = 31,
SP_STALL_CYCLES_BY_TP = 32,
SP_STALL_CYCLES_BY_UCHE = 33,
SP_STALL_CYCLES_BY_RB = 34,
SP_ACTIVE_CYCLES_ANY = 35,
SP_ACTIVE_CYCLES_ALL = 36,
};
enum a3xx_tp_perfcounter_select {
TPL1_TPPERF_L1_REQUESTS = 0,
TPL1_TPPERF_TP0_L1_REQUESTS = 1,
TPL1_TPPERF_TP0_L1_MISSES = 2,
TPL1_TPPERF_TP1_L1_REQUESTS = 3,
TPL1_TPPERF_TP1_L1_MISSES = 4,
TPL1_TPPERF_TP2_L1_REQUESTS = 5,
TPL1_TPPERF_TP2_L1_MISSES = 6,
TPL1_TPPERF_TP3_L1_REQUESTS = 7,
TPL1_TPPERF_TP3_L1_MISSES = 8,
TPL1_TPPERF_OUTPUT_TEXELS_POINT = 9,
TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR = 10,
TPL1_TPPERF_OUTPUT_TEXELS_MIP = 11,
TPL1_TPPERF_OUTPUT_TEXELS_ANISO = 12,
TPL1_TPPERF_BILINEAR_OPS = 13,
TPL1_TPPERF_QUADSQUADS_OFFSET = 14,
TPL1_TPPERF_QUADQUADS_SHADOW = 15,
TPL1_TPPERF_QUADS_ARRAY = 16,
TPL1_TPPERF_QUADS_PROJECTION = 17,
TPL1_TPPERF_QUADS_GRADIENT = 18,
TPL1_TPPERF_QUADS_1D2D = 19,
TPL1_TPPERF_QUADS_3DCUBE = 20,
TPL1_TPPERF_ZERO_LOD = 21,
TPL1_TPPERF_OUTPUT_TEXELS = 22,
TPL1_TPPERF_ACTIVE_CYCLES_ANY = 23,
TPL1_TPPERF_ACTIVE_CYCLES_ALL = 24,
TPL1_TPPERF_STALL_CYCLES_BY_ARB = 25,
TPL1_TPPERF_LATENCY = 26,
TPL1_TPPERF_LATENCY_TRANS = 27,
};
enum a3xx_rop_code {
ROP_CLEAR = 0,
ROP_NOR = 1,
ROP_AND_INVERTED = 2,
ROP_COPY_INVERTED = 3,
ROP_AND_REVERSE = 4,
ROP_INVERT = 5,
ROP_XOR = 6,
ROP_NAND = 7,
ROP_AND = 8,
ROP_EQUIV = 9,
ROP_NOOP = 10,
ROP_OR_INVERTED = 11,
ROP_COPY = 12,
ROP_OR_REVERSE = 13,
ROP_OR = 14,
ROP_SET = 15,
enum a3xx_vfd_perfcounter_select {
VFD_PERF_UCHE_BYTE_FETCHED = 0,
VFD_PERF_UCHE_TRANS = 1,
VFD_PERF_VPC_BYPASS_COMPONENTS = 2,
VFD_PERF_FETCH_INSTRUCTIONS = 3,
VFD_PERF_DECODE_INSTRUCTIONS = 4,
VFD_PERF_ACTIVE_CYCLES = 5,
VFD_PERF_STALL_CYCLES_UCHE = 6,
VFD_PERF_STALL_CYCLES_HLSQ = 7,
VFD_PERF_STALL_CYCLES_VPC_BYPASS = 8,
VFD_PERF_STALL_CYCLES_VPC_ALLOC = 9,
};
enum a3xx_vpc_perfcounter_select {
VPC_PERF_SP_LM_PRIMITIVES = 0,
VPC_PERF_COMPONENTS_FROM_SP = 1,
VPC_PERF_SP_LM_COMPONENTS = 2,
VPC_PERF_ACTIVE_CYCLES = 3,
VPC_PERF_STALL_CYCLES_LM = 4,
VPC_PERF_STALL_CYCLES_RAS = 5,
};
enum a3xx_uche_perfcounter_select {
UCHE_UCHEPERF_VBIF_READ_BEATS_TP = 0,
UCHE_UCHEPERF_VBIF_READ_BEATS_VFD = 1,
UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ = 2,
UCHE_UCHEPERF_VBIF_READ_BEATS_MARB = 3,
UCHE_UCHEPERF_VBIF_READ_BEATS_SP = 4,
UCHE_UCHEPERF_READ_REQUESTS_TP = 8,
UCHE_UCHEPERF_READ_REQUESTS_VFD = 9,
UCHE_UCHEPERF_READ_REQUESTS_HLSQ = 10,
UCHE_UCHEPERF_READ_REQUESTS_MARB = 11,
UCHE_UCHEPERF_READ_REQUESTS_SP = 12,
UCHE_UCHEPERF_WRITE_REQUESTS_MARB = 13,
UCHE_UCHEPERF_WRITE_REQUESTS_SP = 14,
UCHE_UCHEPERF_TAG_CHECK_FAILS = 15,
UCHE_UCHEPERF_EVICTS = 16,
UCHE_UCHEPERF_FLUSHES = 17,
UCHE_UCHEPERF_VBIF_LATENCY_CYCLES = 18,
UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES = 19,
UCHE_UCHEPERF_ACTIVE_CYCLES = 20,
};
enum a3xx_rb_blend_opcode {
......@@ -1429,15 +1684,23 @@ static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_
#define REG_A3XX_PC_RESTART_INDEX 0x000021ed
#define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200
#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000030
#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
{
return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
}
#define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
#define A3XX_HLSQ_CONTROL_0_REG_COMPUTEMODE 0x00000100
#define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
#define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
#define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK 0x00fff000
#define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT 12
static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC(uint32_t val)
{
return ((val) << A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK;
}
#define A3XX_HLSQ_CONTROL_0_REG_FSONLYTEX 0x02000000
#define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
#define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000
#define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27
......@@ -1451,17 +1714,39 @@ static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
#define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
#define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201
#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040
#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x000000c0
#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
{
return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
}
#define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
#define A3XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
#define A3XX_HLSQ_CONTROL_1_REG_ZWCOORD 0x02000000
#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK 0x00ff0000
#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT 16
static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(uint32_t val)
{
return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK;
}
#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK 0xff000000
#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT 24
static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(uint32_t val)
{
return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK;
}
#define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202
#define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK 0x000003fc
#define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT 2
static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(uint32_t val)
{
return ((val) << A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK;
}
#define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK 0x03fc0000
#define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT 18
static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID(uint32_t val)
{
return ((val) << A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK;
}
#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
......@@ -1478,13 +1763,13 @@ static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
}
#define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204
#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff
#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000003ff
#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
{
return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
}
#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000
#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x001ff000
#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12
static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
{
......@@ -1498,13 +1783,13 @@ static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
}
#define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205
#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff
#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000003ff
#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
{
return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
}
#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000
#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x001ff000
#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12
static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
{
......@@ -1518,13 +1803,13 @@ static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
}
#define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206
#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff
#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x000001ff
#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0
static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
{
return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK;
}
#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000
#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0x01ff0000
#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16
static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
{
......@@ -1532,13 +1817,13 @@ static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
}
#define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207
#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff
#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x000001ff
#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0
static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
{
return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK;
}
#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000
#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0x01ff0000
#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16
static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
{
......@@ -1620,12 +1905,24 @@ static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
}
#define REG_A3XX_VFD_CONTROL_1 0x00002241
#define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff
#define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000000f
#define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
{
return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
}
#define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK 0x000000f0
#define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT 4
static inline uint32_t A3XX_VFD_CONTROL_1_MAXTHRESHOLD(uint32_t val)
{
return ((val) << A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK;
}
#define A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK 0x00000f00
#define A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT 8
static inline uint32_t A3XX_VFD_CONTROL_1_MINTHRESHOLD(uint32_t val)
{
return ((val) << A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK;
}
#define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
#define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
......@@ -2008,24 +2305,19 @@ static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffe
return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK;
}
#define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
#define A3XX_SP_VS_CTRL_REG0_ALUSCHMODE 0x00000008
#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
{
return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
}
#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
{
return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
}
#define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
#define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
static inline uint32_t A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
{
return ((val) << A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK;
}
#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
......@@ -2033,8 +2325,6 @@ static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
}
#define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
#define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
#define A3XX_SP_VS_CTRL_REG0_COMPUTEMODE 0x00800000
#define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000
#define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24
static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val)
......@@ -2075,7 +2365,8 @@ static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
{
return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
}
#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000
#define A3XX_SP_VS_PARAM_REG_POS2DMODE 0x00010000
#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0x01f00000
#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
{
......@@ -2085,24 +2376,26 @@ static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
#define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
#define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
#define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
{
return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK;
}
#define A3XX_SP_VS_OUT_REG_A_HALF 0x00000100
#define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
#define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
{
return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
}
#define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000
#define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
#define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
{
return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK;
}
#define A3XX_SP_VS_OUT_REG_B_HALF 0x01000000
#define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
#define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
......@@ -2113,25 +2406,25 @@ static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x0000007f
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
{
return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
}
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x00007f00
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
{
return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
}
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x007f0000
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
{
return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
}
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0x7f000000
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
{
......@@ -2139,6 +2432,12 @@ static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
}
#define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4
#define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK 0x0000ffff
#define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT 0
static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val)
{
return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK;
}
#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
......@@ -2155,8 +2454,38 @@ static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
#define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5
#define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK 0x000000ff
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0
static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val)
{
return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK;
}
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8
static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val)
{
return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK;
}
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT 24
static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val)
{
return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK;
}
#define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7
#define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK 0x0000001f
#define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT 0
static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val)
{
return ((val) << A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK;
}
#define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK 0xffffffe0
#define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5
static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)
{
return ((val >> 5) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;
}
#define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8
......@@ -2182,24 +2511,22 @@ static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffe
return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK;
}
#define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
#define A3XX_SP_FS_CTRL_REG0_ALUSCHMODE 0x00000008
#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
{
return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
}
#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
{
return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
}
#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
static inline uint32_t A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
{
return ((val) << A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK;
}
#define A3XX_SP_FS_CTRL_REG0_FSBYPASSENABLE 0x00020000
#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP 0x00040000
#define A3XX_SP_FS_CTRL_REG0_OUTORDERED 0x00080000
#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
......@@ -2235,7 +2562,7 @@ static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
{
return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK;
}
#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x3f000000
#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x7f000000
#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24
static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val)
{
......@@ -2243,6 +2570,12 @@ static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val)
}
#define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2
#define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK 0x0000ffff
#define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT 0
static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val)
{
return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK;
}
#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
......@@ -2259,8 +2592,38 @@ static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
#define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3
#define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4
#define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK 0x000000ff
#define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0
static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val)
{
return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK;
}
#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00
#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8
static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val)
{
return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK;
}
#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000
#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT 24
static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val)
{
return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK;
}
#define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5
#define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK 0x0000001f
#define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT 0
static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val)
{
return ((val) << A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK;
}
#define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK 0xffffffe0
#define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5
static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)
{
return ((val >> 5) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;
}
#define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6
......
drivers/gpu/drm/msm/adreno/a4xx.xml.h
View file @ 912b330c
......@@ -9,16 +9,17 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
Copyright (C) 2013-2015 by the following authors:
Copyright (C) 2013-2016 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
......@@ -47,11 +48,13 @@ enum a4xx_color_fmt {
RB4_R8_UNORM = 2,
RB4_R4G4B4A4_UNORM = 8,
RB4_R5G5B5A1_UNORM = 10,
RB4_R5G6R5_UNORM = 14,
RB4_R5G6B5_UNORM = 14,
RB4_R8G8_UNORM = 15,
RB4_R8G8_SNORM = 16,
RB4_R8G8_UINT = 17,
RB4_R8G8_SINT = 18,
RB4_R16_UNORM = 19,
RB4_R16_SNORM = 20,
RB4_R16_FLOAT = 21,
RB4_R16_UINT = 22,
RB4_R16_SINT = 23,
......@@ -63,12 +66,16 @@ enum a4xx_color_fmt {
RB4_R10G10B10A2_UNORM = 31,
RB4_R10G10B10A2_UINT = 34,
RB4_R11G11B10_FLOAT = 39,
RB4_R16G16_UNORM = 40,
RB4_R16G16_SNORM = 41,
RB4_R16G16_FLOAT = 42,
RB4_R16G16_UINT = 43,
RB4_R16G16_SINT = 44,
RB4_R32_FLOAT = 45,
RB4_R32_UINT = 46,
RB4_R32_SINT = 47,
RB4_R16G16B16A16_UNORM = 52,
RB4_R16G16B16A16_SNORM = 53,
RB4_R16G16B16A16_FLOAT = 54,
RB4_R16G16B16A16_UINT = 55,
RB4_R16G16B16A16_SINT = 56,
......@@ -106,6 +113,7 @@ enum a4xx_vtx_fmt {
VFMT4_32_32_FIXED = 10,
VFMT4_32_32_32_FIXED = 11,
VFMT4_32_32_32_32_FIXED = 12,
VFMT4_11_11_10_FLOAT = 13,
VFMT4_16_SINT = 16,
VFMT4_16_16_SINT = 17,
VFMT4_16_16_16_SINT = 18,
......@@ -146,52 +154,76 @@ enum a4xx_vtx_fmt {
VFMT4_8_8_SNORM = 53,
VFMT4_8_8_8_SNORM = 54,
VFMT4_8_8_8_8_SNORM = 55,
VFMT4_10_10_10_2_UINT = 60,
VFMT4_10_10_10_2_UNORM = 61,
VFMT4_10_10_10_2_SINT = 62,
VFMT4_10_10_10_2_SNORM = 63,
VFMT4_10_10_10_2_UINT = 56,
VFMT4_10_10_10_2_UNORM = 57,
VFMT4_10_10_10_2_SINT = 58,
VFMT4_10_10_10_2_SNORM = 59,
VFMT4_2_10_10_10_UINT = 60,
VFMT4_2_10_10_10_UNORM = 61,
VFMT4_2_10_10_10_SINT = 62,
VFMT4_2_10_10_10_SNORM = 63,
};
enum a4xx_tex_fmt {
TFMT4_5_6_5_UNORM = 11,
TFMT4_5_5_5_1_UNORM = 10,
TFMT4_4_4_4_4_UNORM = 8,
TFMT4_X8Z24_UNORM = 71,
TFMT4_10_10_10_2_UNORM = 33,
TFMT4_A8_UNORM = 3,
TFMT4_L8_A8_UNORM = 13,
TFMT4_8_UNORM = 4,
TFMT4_8_8_UNORM = 14,
TFMT4_8_8_8_8_UNORM = 28,
TFMT4_8_SNORM = 5,
TFMT4_8_8_SNORM = 15,
TFMT4_8_8_8_8_SNORM = 29,
TFMT4_8_UINT = 6,
TFMT4_8_8_UINT = 16,
TFMT4_8_8_8_8_UINT = 30,
TFMT4_8_SINT = 7,
TFMT4_4_4_4_4_UNORM = 8,
TFMT4_5_5_5_1_UNORM = 9,
TFMT4_5_6_5_UNORM = 11,
TFMT4_L8_A8_UNORM = 13,
TFMT4_8_8_UNORM = 14,
TFMT4_8_8_SNORM = 15,
TFMT4_8_8_UINT = 16,
TFMT4_8_8_SINT = 17,
TFMT4_8_8_8_8_SINT = 31,
TFMT4_16_UNORM = 18,
TFMT4_16_SNORM = 19,
TFMT4_16_FLOAT = 20,
TFMT4_16_UINT = 21,
TFMT4_16_16_UINT = 41,
TFMT4_16_16_16_16_UINT = 54,
TFMT4_16_SINT = 22,
TFMT4_8_8_8_8_UNORM = 28,
TFMT4_8_8_8_8_SNORM = 29,
TFMT4_8_8_8_8_UINT = 30,
TFMT4_8_8_8_8_SINT = 31,
TFMT4_9_9_9_E5_FLOAT = 32,
TFMT4_10_10_10_2_UNORM = 33,
TFMT4_10_10_10_2_UINT = 34,
TFMT4_11_11_10_FLOAT = 37,
TFMT4_16_16_UNORM = 38,
TFMT4_16_16_SNORM = 39,
TFMT4_16_16_FLOAT = 40,
TFMT4_16_16_UINT = 41,
TFMT4_16_16_SINT = 42,
TFMT4_16_16_16_16_SINT = 55,
TFMT4_32_FLOAT = 43,
TFMT4_32_UINT = 44,
TFMT4_32_32_UINT = 57,
TFMT4_32_32_32_32_UINT = 64,
TFMT4_32_SINT = 45,
TFMT4_32_32_SINT = 58,
TFMT4_32_32_32_32_SINT = 65,
TFMT4_16_FLOAT = 20,
TFMT4_16_16_FLOAT = 40,
TFMT4_16_16_16_16_UNORM = 51,
TFMT4_16_16_16_16_SNORM = 52,
TFMT4_16_16_16_16_FLOAT = 53,
TFMT4_32_FLOAT = 43,
TFMT4_16_16_16_16_UINT = 54,
TFMT4_16_16_16_16_SINT = 55,
TFMT4_32_32_FLOAT = 56,
TFMT4_32_32_UINT = 57,
TFMT4_32_32_SINT = 58,
TFMT4_32_32_32_FLOAT = 59,
TFMT4_32_32_32_UINT = 60,
TFMT4_32_32_32_SINT = 61,
TFMT4_32_32_32_32_FLOAT = 63,
TFMT4_9_9_9_E5_FLOAT = 32,
TFMT4_11_11_10_FLOAT = 37,
TFMT4_32_32_32_32_UINT = 64,
TFMT4_32_32_32_32_SINT = 65,
TFMT4_X8Z24_UNORM = 71,
TFMT4_DXT1 = 86,
TFMT4_DXT3 = 87,
TFMT4_DXT5 = 88,
TFMT4_RGTC1_UNORM = 90,
TFMT4_RGTC1_SNORM = 91,
TFMT4_RGTC2_UNORM = 94,
TFMT4_RGTC2_SNORM = 95,
TFMT4_BPTC_UFLOAT = 97,
TFMT4_BPTC_FLOAT = 98,
TFMT4_BPTC = 99,
TFMT4_ATC_RGB = 100,
TFMT4_ATC_RGBA_EXPLICIT = 101,
TFMT4_ATC_RGBA_INTERPOLATED = 102,
......@@ -240,6 +272,545 @@ enum a4xx_tess_spacing {
EVEN_SPACING = 3,
};
enum a4xx_ccu_perfcounter_select {
CCU_BUSY_CYCLES = 0,
CCU_RB_DEPTH_RETURN_STALL = 2,
CCU_RB_COLOR_RETURN_STALL = 3,
CCU_DEPTH_BLOCKS = 6,
CCU_COLOR_BLOCKS = 7,
CCU_DEPTH_BLOCK_HIT = 8,
CCU_COLOR_BLOCK_HIT = 9,
CCU_DEPTH_FLAG1_COUNT = 10,
CCU_DEPTH_FLAG2_COUNT = 11,
CCU_DEPTH_FLAG3_COUNT = 12,
CCU_DEPTH_FLAG4_COUNT = 13,
CCU_COLOR_FLAG1_COUNT = 14,
CCU_COLOR_FLAG2_COUNT = 15,
CCU_COLOR_FLAG3_COUNT = 16,
CCU_COLOR_FLAG4_COUNT = 17,
CCU_PARTIAL_BLOCK_READ = 18,
};
enum a4xx_cp_perfcounter_select {
CP_ALWAYS_COUNT = 0,
CP_BUSY = 1,
CP_PFP_IDLE = 2,
CP_PFP_BUSY_WORKING = 3,
CP_PFP_STALL_CYCLES_ANY = 4,
CP_PFP_STARVE_CYCLES_ANY = 5,
CP_PFP_STARVED_PER_LOAD_ADDR = 6,
CP_PFP_STALLED_PER_STORE_ADDR = 7,
CP_PFP_PC_PROFILE = 8,
CP_PFP_MATCH_PM4_PKT_PROFILE = 9,
CP_PFP_COND_INDIRECT_DISCARDED = 10,
CP_LONG_RESUMPTIONS = 11,
CP_RESUME_CYCLES = 12,
CP_RESUME_TO_BOUNDARY_CYCLES = 13,
CP_LONG_PREEMPTIONS = 14,
CP_PREEMPT_CYCLES = 15,
CP_PREEMPT_TO_BOUNDARY_CYCLES = 16,
CP_ME_FIFO_EMPTY_PFP_IDLE = 17,
CP_ME_FIFO_EMPTY_PFP_BUSY = 18,
CP_ME_FIFO_NOT_EMPTY_NOT_FULL = 19,
CP_ME_FIFO_FULL_ME_BUSY = 20,
CP_ME_FIFO_FULL_ME_NON_WORKING = 21,
CP_ME_WAITING_FOR_PACKETS = 22,
CP_ME_BUSY_WORKING = 23,
CP_ME_STARVE_CYCLES_ANY = 24,
CP_ME_STARVE_CYCLES_PER_PROFILE = 25,
CP_ME_STALL_CYCLES_PER_PROFILE = 26,
CP_ME_PC_PROFILE = 27,
CP_RCIU_FIFO_EMPTY = 28,
CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL = 29,
CP_RCIU_FIFO_FULL = 30,
CP_RCIU_FIFO_FULL_NO_CONTEXT = 31,
CP_RCIU_FIFO_FULL_AHB_MASTER = 32,
CP_RCIU_FIFO_FULL_OTHER = 33,
CP_AHB_IDLE = 34,
CP_AHB_STALL_ON_GRANT_NO_SPLIT = 35,
CP_AHB_STALL_ON_GRANT_SPLIT = 36,
CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE = 37,
CP_AHB_BUSY_WORKING = 38,
CP_AHB_BUSY_STALL_ON_HRDY = 39,
CP_AHB_BUSY_STALL_ON_HRDY_PROFILE = 40,
};
enum a4xx_gras_ras_perfcounter_select {
RAS_SUPER_TILES = 0,
RAS_8X8_TILES = 1,
RAS_4X4_TILES = 2,
RAS_BUSY_CYCLES = 3,
RAS_STALL_CYCLES_BY_RB = 4,
RAS_STALL_CYCLES_BY_VSC = 5,
RAS_STARVE_CYCLES_BY_TSE = 6,
RAS_SUPERTILE_CYCLES = 7,
RAS_TILE_CYCLES = 8,
RAS_FULLY_COVERED_SUPER_TILES = 9,
RAS_FULLY_COVERED_8X8_TILES = 10,
RAS_4X4_PRIM = 11,
RAS_8X4_4X8_PRIM = 12,
RAS_8X8_PRIM = 13,
};
enum a4xx_gras_tse_perfcounter_select {
TSE_INPUT_PRIM = 0,
TSE_INPUT_NULL_PRIM = 1,
TSE_TRIVAL_REJ_PRIM = 2,
TSE_CLIPPED_PRIM = 3,
TSE_NEW_PRIM = 4,
TSE_ZERO_AREA_PRIM = 5,
TSE_FACENESS_CULLED_PRIM = 6,
TSE_ZERO_PIXEL_PRIM = 7,
TSE_OUTPUT_NULL_PRIM = 8,
TSE_OUTPUT_VISIBLE_PRIM = 9,
TSE_PRE_CLIP_PRIM = 10,
TSE_POST_CLIP_PRIM = 11,
TSE_BUSY_CYCLES = 12,
TSE_PC_STARVE = 13,
TSE_RAS_STALL = 14,
TSE_STALL_BARYPLANE_FIFO_FULL = 15,
TSE_STALL_ZPLANE_FIFO_FULL = 16,
};
enum a4xx_hlsq_perfcounter_select {
HLSQ_SP_VS_STAGE_CONSTANT = 0,
HLSQ_SP_VS_STAGE_INSTRUCTIONS = 1,
HLSQ_SP_FS_STAGE_CONSTANT = 2,
HLSQ_SP_FS_STAGE_INSTRUCTIONS = 3,
HLSQ_TP_STATE = 4,
HLSQ_QUADS = 5,
HLSQ_PIXELS = 6,
HLSQ_VERTICES = 7,
HLSQ_SP_VS_STAGE_DATA_BYTES = 13,
HLSQ_SP_FS_STAGE_DATA_BYTES = 14,
HLSQ_BUSY_CYCLES = 15,
HLSQ_STALL_CYCLES_SP_STATE = 16,
HLSQ_STALL_CYCLES_SP_VS_STAGE = 17,
HLSQ_STALL_CYCLES_SP_FS_STAGE = 18,
HLSQ_STALL_CYCLES_UCHE = 19,
HLSQ_RBBM_LOAD_CYCLES = 20,
HLSQ_DI_TO_VS_START_SP = 21,
HLSQ_DI_TO_FS_START_SP = 22,
HLSQ_VS_STAGE_START_TO_DONE_SP = 23,
HLSQ_FS_STAGE_START_TO_DONE_SP = 24,
HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE = 25,
HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE = 26,
HLSQ_UCHE_LATENCY_CYCLES = 27,
HLSQ_UCHE_LATENCY_COUNT = 28,
HLSQ_STARVE_CYCLES_VFD = 29,
};
enum a4xx_pc_perfcounter_select {
PC_VIS_STREAMS_LOADED = 0,
PC_VPC_PRIMITIVES = 2,
PC_DEAD_PRIM = 3,
PC_LIVE_PRIM = 4,
PC_DEAD_DRAWCALLS = 5,
PC_LIVE_DRAWCALLS = 6,
PC_VERTEX_MISSES = 7,
PC_STALL_CYCLES_VFD = 9,
PC_STALL_CYCLES_TSE = 10,
PC_STALL_CYCLES_UCHE = 11,
PC_WORKING_CYCLES = 12,
PC_IA_VERTICES = 13,
PC_GS_PRIMITIVES = 14,
PC_HS_INVOCATIONS = 15,
PC_DS_INVOCATIONS = 16,
PC_DS_PRIMITIVES = 17,
PC_STARVE_CYCLES_FOR_INDEX = 20,
PC_STARVE_CYCLES_FOR_TESS_FACTOR = 21,
PC_STARVE_CYCLES_FOR_VIZ_STREAM = 22,
PC_STALL_CYCLES_TESS = 23,
PC_STARVE_CYCLES_FOR_POSITION = 24,
PC_MODE0_DRAWCALL = 25,
PC_MODE1_DRAWCALL = 26,
PC_MODE2_DRAWCALL = 27,
PC_MODE3_DRAWCALL = 28,
PC_MODE4_DRAWCALL = 29,
PC_PREDICATED_DEAD_DRAWCALL = 30,
PC_STALL_CYCLES_BY_TSE_ONLY = 31,
PC_STALL_CYCLES_BY_VPC_ONLY = 32,
PC_VPC_POS_DATA_TRANSACTION = 33,
PC_BUSY_CYCLES = 34,
PC_STARVE_CYCLES_DI = 35,
PC_STALL_CYCLES_VPC = 36,
TESS_WORKING_CYCLES = 37,
TESS_NUM_CYCLES_SETUP_WORKING = 38,
TESS_NUM_CYCLES_PTGEN_WORKING = 39,
TESS_NUM_CYCLES_CONNGEN_WORKING = 40,
TESS_BUSY_CYCLES = 41,
TESS_STARVE_CYCLES_PC = 42,
TESS_STALL_CYCLES_PC = 43,
};
enum a4xx_pwr_perfcounter_select {
PWR_CORE_CLOCK_CYCLES = 0,
PWR_BUSY_CLOCK_CYCLES = 1,
};
enum a4xx_rb_perfcounter_select {
RB_BUSY_CYCLES = 0,
RB_BUSY_CYCLES_BINNING = 1,
RB_BUSY_CYCLES_RENDERING = 2,
RB_BUSY_CYCLES_RESOLVE = 3,
RB_STARVE_CYCLES_BY_SP = 4,
RB_STARVE_CYCLES_BY_RAS = 5,
RB_STARVE_CYCLES_BY_MARB = 6,
RB_STALL_CYCLES_BY_MARB = 7,
RB_STALL_CYCLES_BY_HLSQ = 8,
RB_RB_RB_MARB_DATA = 9,
RB_SP_RB_QUAD = 10,
RB_RAS_RB_Z_QUADS = 11,
RB_GMEM_CH0_READ = 12,
RB_GMEM_CH1_READ = 13,
RB_GMEM_CH0_WRITE = 14,
RB_GMEM_CH1_WRITE = 15,
RB_CP_CONTEXT_DONE = 16,
RB_CP_CACHE_FLUSH = 17,
RB_CP_ZPASS_DONE = 18,
RB_STALL_FIFO0_FULL = 19,
RB_STALL_FIFO1_FULL = 20,
RB_STALL_FIFO2_FULL = 21,
RB_STALL_FIFO3_FULL = 22,
RB_RB_HLSQ_TRANSACTIONS = 23,
RB_Z_READ = 24,
RB_Z_WRITE = 25,
RB_C_READ = 26,
RB_C_WRITE = 27,
RB_C_READ_LATENCY = 28,
RB_Z_READ_LATENCY = 29,
RB_STALL_BY_UCHE = 30,
RB_MARB_UCHE_TRANSACTIONS = 31,
RB_CACHE_STALL_MISS = 32,
RB_CACHE_STALL_FIFO_FULL = 33,
RB_8BIT_BLENDER_UNITS_ACTIVE = 34,
RB_16BIT_BLENDER_UNITS_ACTIVE = 35,
RB_SAMPLER_UNITS_ACTIVE = 36,
RB_TOTAL_PASS = 38,
RB_Z_PASS = 39,
RB_Z_FAIL = 40,
RB_S_FAIL = 41,
RB_POWER0 = 42,
RB_POWER1 = 43,
RB_POWER2 = 44,
RB_POWER3 = 45,
RB_POWER4 = 46,
RB_POWER5 = 47,
RB_POWER6 = 48,
RB_POWER7 = 49,
};
enum a4xx_rbbm_perfcounter_select {
RBBM_ALWAYS_ON = 0,
RBBM_VBIF_BUSY = 1,
RBBM_TSE_BUSY = 2,
RBBM_RAS_BUSY = 3,
RBBM_PC_DCALL_BUSY = 4,
RBBM_PC_VSD_BUSY = 5,
RBBM_VFD_BUSY = 6,
RBBM_VPC_BUSY = 7,
RBBM_UCHE_BUSY = 8,
RBBM_VSC_BUSY = 9,
RBBM_HLSQ_BUSY = 10,
RBBM_ANY_RB_BUSY = 11,
RBBM_ANY_TPL1_BUSY = 12,
RBBM_ANY_SP_BUSY = 13,
RBBM_ANY_MARB_BUSY = 14,
RBBM_ANY_ARB_BUSY = 15,
RBBM_AHB_STATUS_BUSY = 16,
RBBM_AHB_STATUS_STALLED = 17,
RBBM_AHB_STATUS_TXFR = 18,
RBBM_AHB_STATUS_TXFR_SPLIT = 19,
RBBM_AHB_STATUS_TXFR_ERROR = 20,
RBBM_AHB_STATUS_LONG_STALL = 21,
RBBM_STATUS_MASKED = 22,
RBBM_CP_BUSY_GFX_CORE_IDLE = 23,
RBBM_TESS_BUSY = 24,
RBBM_COM_BUSY = 25,
RBBM_DCOM_BUSY = 32,
RBBM_ANY_CCU_BUSY = 33,
RBBM_DPM_BUSY = 34,
};
enum a4xx_sp_perfcounter_select {
SP_LM_LOAD_INSTRUCTIONS = 0,
SP_LM_STORE_INSTRUCTIONS = 1,
SP_LM_ATOMICS = 2,
SP_GM_LOAD_INSTRUCTIONS = 3,
SP_GM_STORE_INSTRUCTIONS = 4,
SP_GM_ATOMICS = 5,
SP_VS_STAGE_TEX_INSTRUCTIONS = 6,
SP_VS_STAGE_CFLOW_INSTRUCTIONS = 7,
SP_VS_STAGE_EFU_INSTRUCTIONS = 8,
SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 9,
SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 10,
SP_FS_STAGE_TEX_INSTRUCTIONS = 11,
SP_FS_STAGE_CFLOW_INSTRUCTIONS = 12,
SP_FS_STAGE_EFU_INSTRUCTIONS = 13,
SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 14,
SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 15,
SP_VS_INSTRUCTIONS = 17,
SP_FS_INSTRUCTIONS = 18,
SP_ADDR_LOCK_COUNT = 19,
SP_UCHE_READ_TRANS = 20,
SP_UCHE_WRITE_TRANS = 21,
SP_EXPORT_VPC_TRANS = 22,
SP_EXPORT_RB_TRANS = 23,
SP_PIXELS_KILLED = 24,
SP_ICL1_REQUESTS = 25,
SP_ICL1_MISSES = 26,
SP_ICL0_REQUESTS = 27,
SP_ICL0_MISSES = 28,
SP_ALU_WORKING_CYCLES = 29,
SP_EFU_WORKING_CYCLES = 30,
SP_STALL_CYCLES_BY_VPC = 31,
SP_STALL_CYCLES_BY_TP = 32,
SP_STALL_CYCLES_BY_UCHE = 33,
SP_STALL_CYCLES_BY_RB = 34,
SP_BUSY_CYCLES = 35,
SP_HS_INSTRUCTIONS = 36,
SP_DS_INSTRUCTIONS = 37,
SP_GS_INSTRUCTIONS = 38,
SP_CS_INSTRUCTIONS = 39,
SP_SCHEDULER_NON_WORKING = 40,
SP_WAVE_CONTEXTS = 41,
SP_WAVE_CONTEXT_CYCLES = 42,
SP_POWER0 = 43,
SP_POWER1 = 44,
SP_POWER2 = 45,
SP_POWER3 = 46,
SP_POWER4 = 47,
SP_POWER5 = 48,
SP_POWER6 = 49,
SP_POWER7 = 50,
SP_POWER8 = 51,
SP_POWER9 = 52,
SP_POWER10 = 53,
SP_POWER11 = 54,
SP_POWER12 = 55,
SP_POWER13 = 56,
SP_POWER14 = 57,
SP_POWER15 = 58,
};
enum a4xx_tp_perfcounter_select {
TP_L1_REQUESTS = 0,
TP_L1_MISSES = 1,
TP_QUADS_OFFSET = 8,
TP_QUAD_SHADOW = 9,
TP_QUADS_ARRAY = 10,
TP_QUADS_GRADIENT = 11,
TP_QUADS_1D2D = 12,
TP_QUADS_3DCUBE = 13,
TP_BUSY_CYCLES = 16,
TP_STALL_CYCLES_BY_ARB = 17,
TP_STATE_CACHE_REQUESTS = 20,
TP_STATE_CACHE_MISSES = 21,
TP_POWER0 = 22,
TP_POWER1 = 23,
TP_POWER2 = 24,
TP_POWER3 = 25,
TP_POWER4 = 26,
TP_POWER5 = 27,
TP_POWER6 = 28,
TP_POWER7 = 29,
};
enum a4xx_uche_perfcounter_select {
UCHE_VBIF_READ_BEATS_TP = 0,
UCHE_VBIF_READ_BEATS_VFD = 1,
UCHE_VBIF_READ_BEATS_HLSQ = 2,
UCHE_VBIF_READ_BEATS_MARB = 3,
UCHE_VBIF_READ_BEATS_SP = 4,
UCHE_READ_REQUESTS_TP = 5,
UCHE_READ_REQUESTS_VFD = 6,
UCHE_READ_REQUESTS_HLSQ = 7,
UCHE_READ_REQUESTS_MARB = 8,
UCHE_READ_REQUESTS_SP = 9,
UCHE_WRITE_REQUESTS_MARB = 10,
UCHE_WRITE_REQUESTS_SP = 11,
UCHE_TAG_CHECK_FAILS = 12,
UCHE_EVICTS = 13,
UCHE_FLUSHES = 14,
UCHE_VBIF_LATENCY_CYCLES = 15,
UCHE_VBIF_LATENCY_SAMPLES = 16,
UCHE_BUSY_CYCLES = 17,
UCHE_VBIF_READ_BEATS_PC = 18,
UCHE_READ_REQUESTS_PC = 19,
UCHE_WRITE_REQUESTS_VPC = 20,
UCHE_STALL_BY_VBIF = 21,
UCHE_WRITE_REQUESTS_VSC = 22,
UCHE_POWER0 = 23,
UCHE_POWER1 = 24,
UCHE_POWER2 = 25,
UCHE_POWER3 = 26,
UCHE_POWER4 = 27,
UCHE_POWER5 = 28,
UCHE_POWER6 = 29,
UCHE_POWER7 = 30,
};
enum a4xx_vbif_perfcounter_select {
AXI_READ_REQUESTS_ID_0 = 0,
AXI_READ_REQUESTS_ID_1 = 1,
AXI_READ_REQUESTS_ID_2 = 2,
AXI_READ_REQUESTS_ID_3 = 3,
AXI_READ_REQUESTS_ID_4 = 4,
AXI_READ_REQUESTS_ID_5 = 5,
AXI_READ_REQUESTS_ID_6 = 6,
AXI_READ_REQUESTS_ID_7 = 7,
AXI_READ_REQUESTS_ID_8 = 8,
AXI_READ_REQUESTS_ID_9 = 9,
AXI_READ_REQUESTS_ID_10 = 10,
AXI_READ_REQUESTS_ID_11 = 11,
AXI_READ_REQUESTS_ID_12 = 12,
AXI_READ_REQUESTS_ID_13 = 13,
AXI_READ_REQUESTS_ID_14 = 14,
AXI_READ_REQUESTS_ID_15 = 15,
AXI0_READ_REQUESTS_TOTAL = 16,
AXI1_READ_REQUESTS_TOTAL = 17,
AXI2_READ_REQUESTS_TOTAL = 18,
AXI3_READ_REQUESTS_TOTAL = 19,
AXI_READ_REQUESTS_TOTAL = 20,
AXI_WRITE_REQUESTS_ID_0 = 21,
AXI_WRITE_REQUESTS_ID_1 = 22,
AXI_WRITE_REQUESTS_ID_2 = 23,
AXI_WRITE_REQUESTS_ID_3 = 24,
AXI_WRITE_REQUESTS_ID_4 = 25,
AXI_WRITE_REQUESTS_ID_5 = 26,
AXI_WRITE_REQUESTS_ID_6 = 27,
AXI_WRITE_REQUESTS_ID_7 = 28,
AXI_WRITE_REQUESTS_ID_8 = 29,
AXI_WRITE_REQUESTS_ID_9 = 30,
AXI_WRITE_REQUESTS_ID_10 = 31,
AXI_WRITE_REQUESTS_ID_11 = 32,
AXI_WRITE_REQUESTS_ID_12 = 33,
AXI_WRITE_REQUESTS_ID_13 = 34,
AXI_WRITE_REQUESTS_ID_14 = 35,
AXI_WRITE_REQUESTS_ID_15 = 36,
AXI0_WRITE_REQUESTS_TOTAL = 37,
AXI1_WRITE_REQUESTS_TOTAL = 38,
AXI2_WRITE_REQUESTS_TOTAL = 39,
AXI3_WRITE_REQUESTS_TOTAL = 40,
AXI_WRITE_REQUESTS_TOTAL = 41,
AXI_TOTAL_REQUESTS = 42,
AXI_READ_DATA_BEATS_ID_0 = 43,
AXI_READ_DATA_BEATS_ID_1 = 44,
AXI_READ_DATA_BEATS_ID_2 = 45,
AXI_READ_DATA_BEATS_ID_3 = 46,
AXI_READ_DATA_BEATS_ID_4 = 47,
AXI_READ_DATA_BEATS_ID_5 = 48,
AXI_READ_DATA_BEATS_ID_6 = 49,
AXI_READ_DATA_BEATS_ID_7 = 50,
AXI_READ_DATA_BEATS_ID_8 = 51,
AXI_READ_DATA_BEATS_ID_9 = 52,
AXI_READ_DATA_BEATS_ID_10 = 53,
AXI_READ_DATA_BEATS_ID_11 = 54,
AXI_READ_DATA_BEATS_ID_12 = 55,
AXI_READ_DATA_BEATS_ID_13 = 56,
AXI_READ_DATA_BEATS_ID_14 = 57,
AXI_READ_DATA_BEATS_ID_15 = 58,
AXI0_READ_DATA_BEATS_TOTAL = 59,
AXI1_READ_DATA_BEATS_TOTAL = 60,
AXI2_READ_DATA_BEATS_TOTAL = 61,
AXI3_READ_DATA_BEATS_TOTAL = 62,
AXI_READ_DATA_BEATS_TOTAL = 63,
AXI_WRITE_DATA_BEATS_ID_0 = 64,
AXI_WRITE_DATA_BEATS_ID_1 = 65,
AXI_WRITE_DATA_BEATS_ID_2 = 66,
AXI_WRITE_DATA_BEATS_ID_3 = 67,
AXI_WRITE_DATA_BEATS_ID_4 = 68,
AXI_WRITE_DATA_BEATS_ID_5 = 69,
AXI_WRITE_DATA_BEATS_ID_6 = 70,
AXI_WRITE_DATA_BEATS_ID_7 = 71,
AXI_WRITE_DATA_BEATS_ID_8 = 72,
AXI_WRITE_DATA_BEATS_ID_9 = 73,
AXI_WRITE_DATA_BEATS_ID_10 = 74,
AXI_WRITE_DATA_BEATS_ID_11 = 75,
AXI_WRITE_DATA_BEATS_ID_12 = 76,
AXI_WRITE_DATA_BEATS_ID_13 = 77,
AXI_WRITE_DATA_BEATS_ID_14 = 78,
AXI_WRITE_DATA_BEATS_ID_15 = 79,
AXI0_WRITE_DATA_BEATS_TOTAL = 80,
AXI1_WRITE_DATA_BEATS_TOTAL = 81,
AXI2_WRITE_DATA_BEATS_TOTAL = 82,
AXI3_WRITE_DATA_BEATS_TOTAL = 83,
AXI_WRITE_DATA_BEATS_TOTAL = 84,
AXI_DATA_BEATS_TOTAL = 85,
CYCLES_HELD_OFF_ID_0 = 86,
CYCLES_HELD_OFF_ID_1 = 87,
CYCLES_HELD_OFF_ID_2 = 88,
CYCLES_HELD_OFF_ID_3 = 89,
CYCLES_HELD_OFF_ID_4 = 90,
CYCLES_HELD_OFF_ID_5 = 91,
CYCLES_HELD_OFF_ID_6 = 92,
CYCLES_HELD_OFF_ID_7 = 93,
CYCLES_HELD_OFF_ID_8 = 94,
CYCLES_HELD_OFF_ID_9 = 95,
CYCLES_HELD_OFF_ID_10 = 96,
CYCLES_HELD_OFF_ID_11 = 97,
CYCLES_HELD_OFF_ID_12 = 98,
CYCLES_HELD_OFF_ID_13 = 99,
CYCLES_HELD_OFF_ID_14 = 100,
CYCLES_HELD_OFF_ID_15 = 101,
AXI_READ_REQUEST_HELD_OFF = 102,
AXI_WRITE_REQUEST_HELD_OFF = 103,
AXI_REQUEST_HELD_OFF = 104,
AXI_WRITE_DATA_HELD_OFF = 105,
OCMEM_AXI_READ_REQUEST_HELD_OFF = 106,
OCMEM_AXI_WRITE_REQUEST_HELD_OFF = 107,
OCMEM_AXI_REQUEST_HELD_OFF = 108,
OCMEM_AXI_WRITE_DATA_HELD_OFF = 109,
ELAPSED_CYCLES_DDR = 110,
ELAPSED_CYCLES_OCMEM = 111,
};
enum a4xx_vfd_perfcounter_select {
VFD_UCHE_BYTE_FETCHED = 0,
VFD_UCHE_TRANS = 1,
VFD_FETCH_INSTRUCTIONS = 3,
VFD_BUSY_CYCLES = 5,
VFD_STALL_CYCLES_UCHE = 6,
VFD_STALL_CYCLES_HLSQ = 7,
VFD_STALL_CYCLES_VPC_BYPASS = 8,
VFD_STALL_CYCLES_VPC_ALLOC = 9,
VFD_MODE_0_FIBERS = 13,
VFD_MODE_1_FIBERS = 14,
VFD_MODE_2_FIBERS = 15,
VFD_MODE_3_FIBERS = 16,
VFD_MODE_4_FIBERS = 17,
VFD_BFIFO_STALL = 18,
VFD_NUM_VERTICES_TOTAL = 19,
VFD_PACKER_FULL = 20,
VFD_UCHE_REQUEST_FIFO_FULL = 21,
VFD_STARVE_CYCLES_PC = 22,
VFD_STARVE_CYCLES_UCHE = 23,
};
enum a4xx_vpc_perfcounter_select {
VPC_SP_LM_COMPONENTS = 2,
VPC_SP0_LM_BYTES = 3,
VPC_SP1_LM_BYTES = 4,
VPC_SP2_LM_BYTES = 5,
VPC_SP3_LM_BYTES = 6,
VPC_WORKING_CYCLES = 7,
VPC_STALL_CYCLES_LM = 8,
VPC_STARVE_CYCLES_RAS = 9,
VPC_STREAMOUT_CYCLES = 10,
VPC_UCHE_TRANSACTIONS = 12,
VPC_STALL_CYCLES_UCHE = 13,
VPC_BUSY_CYCLES = 14,
VPC_STARVE_CYCLES_SP = 15,
};
enum a4xx_vsc_perfcounter_select {
VSC_BUSY_CYCLES = 0,
VSC_WORKING_CYCLES = 1,
VSC_STALL_CYCLES_UCHE = 2,
VSC_STARVE_CYCLES_RAS = 3,
VSC_EOT_NUM = 4,
};
enum a4xx_tex_filter {
A4XX_TEX_NEAREST = 0,
A4XX_TEX_LINEAR = 1,
......@@ -326,6 +897,12 @@ static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val)
#define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce
#define REG_A4XX_RB_PERFCTR_CCU_SEL_0 0x00000ccf
#define REG_A4XX_RB_PERFCTR_CCU_SEL_1 0x00000cd0
#define REG_A4XX_RB_PERFCTR_CCU_SEL_2 0x00000cd1
#define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2
#define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
......@@ -400,8 +977,13 @@ static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4
#define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
#define A4XX_RB_MRT_CONTROL_BLEND 0x00000010
#define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020
#define A4XX_RB_MRT_CONTROL_FASTCLEAR 0x00000400
#define A4XX_RB_MRT_CONTROL_B11 0x00000800
#define A4XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000040
#define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00
#define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8
static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
{
return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK;
}
#define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
#define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
......@@ -490,8 +1072,8 @@ static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_r
return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
}
#define REG_A4XX_RB_BLEND_RED 0x000020f3
#define A4XX_RB_BLEND_RED_UINT__MASK 0x00007fff
#define REG_A4XX_RB_BLEND_RED 0x000020f0
#define A4XX_RB_BLEND_RED_UINT__MASK 0x0000ffff
#define A4XX_RB_BLEND_RED_UINT__SHIFT 0
static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)
{
......@@ -504,8 +1086,16 @@ static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
}
#define REG_A4XX_RB_BLEND_GREEN 0x000020f4
#define A4XX_RB_BLEND_GREEN_UINT__MASK 0x00007fff
#define REG_A4XX_RB_BLEND_RED_F32 0x000020f1
#define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff
#define A4XX_RB_BLEND_RED_F32__SHIFT 0
static inline uint32_t A4XX_RB_BLEND_RED_F32(float val)
{
return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK;
}
#define REG_A4XX_RB_BLEND_GREEN 0x000020f2
#define A4XX_RB_BLEND_GREEN_UINT__MASK 0x0000ffff
#define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0
static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)
{
......@@ -518,8 +1108,16 @@ static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
}
#define REG_A4XX_RB_BLEND_BLUE 0x000020f5
#define A4XX_RB_BLEND_BLUE_UINT__MASK 0x00007fff
#define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3
#define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
#define A4XX_RB_BLEND_GREEN_F32__SHIFT 0
static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val)
{
return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK;
}
#define REG_A4XX_RB_BLEND_BLUE 0x000020f4
#define A4XX_RB_BLEND_BLUE_UINT__MASK 0x0000ffff
#define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0
static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)
{
......@@ -532,8 +1130,16 @@ static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
}
#define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5
#define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
#define A4XX_RB_BLEND_BLUE_F32__SHIFT 0
static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val)
{
return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK;
}
#define REG_A4XX_RB_BLEND_ALPHA 0x000020f6
#define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x00007fff
#define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x0000ffff
#define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0
static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)
{
......@@ -546,6 +1152,14 @@ static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
}
#define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7
#define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
#define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0
static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val)
{
return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK;
}
#define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8
#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
......@@ -568,7 +1182,7 @@ static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
{
return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK;
}
#define A4XX_RB_FS_OUTPUT_FAST_CLEAR 0x00000100
#define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND 0x00000100
#define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000
#define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16
static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
......@@ -736,6 +1350,7 @@ static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
}
#define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080
#define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000
#define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000
#define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
#define REG_A4XX_RB_DEPTH_CLEAR 0x00002102
......@@ -996,8 +1611,386 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x
#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d
#define REG_A4XX_RBBM_POWER_CNTL_IP 0x00000098
#define A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE 0x00000001
#define A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON 0x00100000
#define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c
#define REG_A4XX_RBBM_PERFCTR_CP_0_HI 0x0000009d
#define REG_A4XX_RBBM_PERFCTR_CP_1_LO 0x0000009e
#define REG_A4XX_RBBM_PERFCTR_CP_1_HI 0x0000009f
#define REG_A4XX_RBBM_PERFCTR_CP_2_LO 0x000000a0
#define REG_A4XX_RBBM_PERFCTR_CP_2_HI 0x000000a1
#define REG_A4XX_RBBM_PERFCTR_CP_3_LO 0x000000a2
#define REG_A4XX_RBBM_PERFCTR_CP_3_HI 0x000000a3
#define REG_A4XX_RBBM_PERFCTR_CP_4_LO 0x000000a4
#define REG_A4XX_RBBM_PERFCTR_CP_4_HI 0x000000a5
#define REG_A4XX_RBBM_PERFCTR_CP_5_LO 0x000000a6
#define REG_A4XX_RBBM_PERFCTR_CP_5_HI 0x000000a7
#define REG_A4XX_RBBM_PERFCTR_CP_6_LO 0x000000a8
#define REG_A4XX_RBBM_PERFCTR_CP_6_HI 0x000000a9
#define REG_A4XX_RBBM_PERFCTR_CP_7_LO 0x000000aa
#define REG_A4XX_RBBM_PERFCTR_CP_7_HI 0x000000ab
#define REG_A4XX_RBBM_PERFCTR_RBBM_0_LO 0x000000ac
#define REG_A4XX_RBBM_PERFCTR_RBBM_0_HI 0x000000ad
#define REG_A4XX_RBBM_PERFCTR_RBBM_1_LO 0x000000ae
#define REG_A4XX_RBBM_PERFCTR_RBBM_1_HI 0x000000af
#define REG_A4XX_RBBM_PERFCTR_RBBM_2_LO 0x000000b0
#define REG_A4XX_RBBM_PERFCTR_RBBM_2_HI 0x000000b1
#define REG_A4XX_RBBM_PERFCTR_RBBM_3_LO 0x000000b2
#define REG_A4XX_RBBM_PERFCTR_RBBM_3_HI 0x000000b3
#define REG_A4XX_RBBM_PERFCTR_PC_0_LO 0x000000b4
#define REG_A4XX_RBBM_PERFCTR_PC_0_HI 0x000000b5
#define REG_A4XX_RBBM_PERFCTR_PC_1_LO 0x000000b6
#define REG_A4XX_RBBM_PERFCTR_PC_1_HI 0x000000b7
#define REG_A4XX_RBBM_PERFCTR_PC_2_LO 0x000000b8
#define REG_A4XX_RBBM_PERFCTR_PC_2_HI 0x000000b9
#define REG_A4XX_RBBM_PERFCTR_PC_3_LO 0x000000ba
#define REG_A4XX_RBBM_PERFCTR_PC_3_HI 0x000000bb
#define REG_A4XX_RBBM_PERFCTR_PC_4_LO 0x000000bc
#define REG_A4XX_RBBM_PERFCTR_PC_4_HI 0x000000bd
#define REG_A4XX_RBBM_PERFCTR_PC_5_LO 0x000000be
#define REG_A4XX_RBBM_PERFCTR_PC_5_HI 0x000000bf
#define REG_A4XX_RBBM_PERFCTR_PC_6_LO 0x000000c0
#define REG_A4XX_RBBM_PERFCTR_PC_6_HI 0x000000c1
#define REG_A4XX_RBBM_PERFCTR_PC_7_LO 0x000000c2
#define REG_A4XX_RBBM_PERFCTR_PC_7_HI 0x000000c3
#define REG_A4XX_RBBM_PERFCTR_VFD_0_LO 0x000000c4
#define REG_A4XX_RBBM_PERFCTR_VFD_0_HI 0x000000c5
#define REG_A4XX_RBBM_PERFCTR_VFD_1_LO 0x000000c6
#define REG_A4XX_RBBM_PERFCTR_VFD_1_HI 0x000000c7
#define REG_A4XX_RBBM_PERFCTR_VFD_2_LO 0x000000c8
#define REG_A4XX_RBBM_PERFCTR_VFD_2_HI 0x000000c9
#define REG_A4XX_RBBM_PERFCTR_VFD_3_LO 0x000000ca
#define REG_A4XX_RBBM_PERFCTR_VFD_3_HI 0x000000cb
#define REG_A4XX_RBBM_PERFCTR_VFD_4_LO 0x000000cc
#define REG_A4XX_RBBM_PERFCTR_VFD_4_HI 0x000000cd
#define REG_A4XX_RBBM_PERFCTR_VFD_5_LO 0x000000ce
#define REG_A4XX_RBBM_PERFCTR_VFD_5_HI 0x000000cf
#define REG_A4XX_RBBM_PERFCTR_VFD_6_LO 0x000000d0
#define REG_A4XX_RBBM_PERFCTR_VFD_6_HI 0x000000d1
#define REG_A4XX_RBBM_PERFCTR_VFD_7_LO 0x000000d2
#define REG_A4XX_RBBM_PERFCTR_VFD_7_HI 0x000000d3
#define REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000d4
#define REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000d5
#define REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000d6
#define REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000d7
#define REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000d8
#define REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000d9
#define REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000da
#define REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000db
#define REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000dc
#define REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000dd
#define REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000de
#define REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000df
#define REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO 0x000000e0
#define REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI 0x000000e1
#define REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO 0x000000e2
#define REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI 0x000000e3
#define REG_A4XX_RBBM_PERFCTR_VPC_0_LO 0x000000e4
#define REG_A4XX_RBBM_PERFCTR_VPC_0_HI 0x000000e5
#define REG_A4XX_RBBM_PERFCTR_VPC_1_LO 0x000000e6
#define REG_A4XX_RBBM_PERFCTR_VPC_1_HI 0x000000e7
#define REG_A4XX_RBBM_PERFCTR_VPC_2_LO 0x000000e8
#define REG_A4XX_RBBM_PERFCTR_VPC_2_HI 0x000000e9
#define REG_A4XX_RBBM_PERFCTR_VPC_3_LO 0x000000ea
#define REG_A4XX_RBBM_PERFCTR_VPC_3_HI 0x000000eb
#define REG_A4XX_RBBM_PERFCTR_CCU_0_LO 0x000000ec
#define REG_A4XX_RBBM_PERFCTR_CCU_0_HI 0x000000ed
#define REG_A4XX_RBBM_PERFCTR_CCU_1_LO 0x000000ee
#define REG_A4XX_RBBM_PERFCTR_CCU_1_HI 0x000000ef
#define REG_A4XX_RBBM_PERFCTR_CCU_2_LO 0x000000f0
#define REG_A4XX_RBBM_PERFCTR_CCU_2_HI 0x000000f1
#define REG_A4XX_RBBM_PERFCTR_CCU_3_LO 0x000000f2
#define REG_A4XX_RBBM_PERFCTR_CCU_3_HI 0x000000f3
#define REG_A4XX_RBBM_PERFCTR_TSE_0_LO 0x000000f4
#define REG_A4XX_RBBM_PERFCTR_TSE_0_HI 0x000000f5
#define REG_A4XX_RBBM_PERFCTR_TSE_1_LO 0x000000f6
#define REG_A4XX_RBBM_PERFCTR_TSE_1_HI 0x000000f7
#define REG_A4XX_RBBM_PERFCTR_TSE_2_LO 0x000000f8
#define REG_A4XX_RBBM_PERFCTR_TSE_2_HI 0x000000f9
#define REG_A4XX_RBBM_PERFCTR_TSE_3_LO 0x000000fa
#define REG_A4XX_RBBM_PERFCTR_TSE_3_HI 0x000000fb
#define REG_A4XX_RBBM_PERFCTR_RAS_0_LO 0x000000fc
#define REG_A4XX_RBBM_PERFCTR_RAS_0_HI 0x000000fd
#define REG_A4XX_RBBM_PERFCTR_RAS_1_LO 0x000000fe
#define REG_A4XX_RBBM_PERFCTR_RAS_1_HI 0x000000ff
#define REG_A4XX_RBBM_PERFCTR_RAS_2_LO 0x00000100
#define REG_A4XX_RBBM_PERFCTR_RAS_2_HI 0x00000101
#define REG_A4XX_RBBM_PERFCTR_RAS_3_LO 0x00000102
#define REG_A4XX_RBBM_PERFCTR_RAS_3_HI 0x00000103
#define REG_A4XX_RBBM_PERFCTR_UCHE_0_LO 0x00000104
#define REG_A4XX_RBBM_PERFCTR_UCHE_0_HI 0x00000105
#define REG_A4XX_RBBM_PERFCTR_UCHE_1_LO 0x00000106
#define REG_A4XX_RBBM_PERFCTR_UCHE_1_HI 0x00000107
#define REG_A4XX_RBBM_PERFCTR_UCHE_2_LO 0x00000108
#define REG_A4XX_RBBM_PERFCTR_UCHE_2_HI 0x00000109
#define REG_A4XX_RBBM_PERFCTR_UCHE_3_LO 0x0000010a
#define REG_A4XX_RBBM_PERFCTR_UCHE_3_HI 0x0000010b
#define REG_A4XX_RBBM_PERFCTR_UCHE_4_LO 0x0000010c
#define REG_A4XX_RBBM_PERFCTR_UCHE_4_HI 0x0000010d
#define REG_A4XX_RBBM_PERFCTR_UCHE_5_LO 0x0000010e
#define REG_A4XX_RBBM_PERFCTR_UCHE_5_HI 0x0000010f
#define REG_A4XX_RBBM_PERFCTR_UCHE_6_LO 0x00000110
#define REG_A4XX_RBBM_PERFCTR_UCHE_6_HI 0x00000111
#define REG_A4XX_RBBM_PERFCTR_UCHE_7_LO 0x00000112
#define REG_A4XX_RBBM_PERFCTR_UCHE_7_HI 0x00000113
#define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114
#define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115
#define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114
#define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115
#define REG_A4XX_RBBM_PERFCTR_TP_1_LO 0x00000116
#define REG_A4XX_RBBM_PERFCTR_TP_1_HI 0x00000117
#define REG_A4XX_RBBM_PERFCTR_TP_2_LO 0x00000118
#define REG_A4XX_RBBM_PERFCTR_TP_2_HI 0x00000119
#define REG_A4XX_RBBM_PERFCTR_TP_3_LO 0x0000011a
#define REG_A4XX_RBBM_PERFCTR_TP_3_HI 0x0000011b
#define REG_A4XX_RBBM_PERFCTR_TP_4_LO 0x0000011c
#define REG_A4XX_RBBM_PERFCTR_TP_4_HI 0x0000011d
#define REG_A4XX_RBBM_PERFCTR_TP_5_LO 0x0000011e
#define REG_A4XX_RBBM_PERFCTR_TP_5_HI 0x0000011f
#define REG_A4XX_RBBM_PERFCTR_TP_6_LO 0x00000120
#define REG_A4XX_RBBM_PERFCTR_TP_6_HI 0x00000121
#define REG_A4XX_RBBM_PERFCTR_TP_7_LO 0x00000122
#define REG_A4XX_RBBM_PERFCTR_TP_7_HI 0x00000123
#define REG_A4XX_RBBM_PERFCTR_SP_0_LO 0x00000124
#define REG_A4XX_RBBM_PERFCTR_SP_0_HI 0x00000125
#define REG_A4XX_RBBM_PERFCTR_SP_1_LO 0x00000126
#define REG_A4XX_RBBM_PERFCTR_SP_1_HI 0x00000127
#define REG_A4XX_RBBM_PERFCTR_SP_2_LO 0x00000128
#define REG_A4XX_RBBM_PERFCTR_SP_2_HI 0x00000129
#define REG_A4XX_RBBM_PERFCTR_SP_3_LO 0x0000012a
#define REG_A4XX_RBBM_PERFCTR_SP_3_HI 0x0000012b
#define REG_A4XX_RBBM_PERFCTR_SP_4_LO 0x0000012c
#define REG_A4XX_RBBM_PERFCTR_SP_4_HI 0x0000012d
#define REG_A4XX_RBBM_PERFCTR_SP_5_LO 0x0000012e
#define REG_A4XX_RBBM_PERFCTR_SP_5_HI 0x0000012f
#define REG_A4XX_RBBM_PERFCTR_SP_6_LO 0x00000130
#define REG_A4XX_RBBM_PERFCTR_SP_6_HI 0x00000131
#define REG_A4XX_RBBM_PERFCTR_SP_7_LO 0x00000132
#define REG_A4XX_RBBM_PERFCTR_SP_7_HI 0x00000133
#define REG_A4XX_RBBM_PERFCTR_SP_8_LO 0x00000134
#define REG_A4XX_RBBM_PERFCTR_SP_8_HI 0x00000135
#define REG_A4XX_RBBM_PERFCTR_SP_9_LO 0x00000136
#define REG_A4XX_RBBM_PERFCTR_SP_9_HI 0x00000137
#define REG_A4XX_RBBM_PERFCTR_SP_10_LO 0x00000138
#define REG_A4XX_RBBM_PERFCTR_SP_10_HI 0x00000139
#define REG_A4XX_RBBM_PERFCTR_SP_11_LO 0x0000013a
#define REG_A4XX_RBBM_PERFCTR_SP_11_HI 0x0000013b
#define REG_A4XX_RBBM_PERFCTR_RB_0_LO 0x0000013c
#define REG_A4XX_RBBM_PERFCTR_RB_0_HI 0x0000013d
#define REG_A4XX_RBBM_PERFCTR_RB_1_LO 0x0000013e
#define REG_A4XX_RBBM_PERFCTR_RB_1_HI 0x0000013f
#define REG_A4XX_RBBM_PERFCTR_RB_2_LO 0x00000140
#define REG_A4XX_RBBM_PERFCTR_RB_2_HI 0x00000141
#define REG_A4XX_RBBM_PERFCTR_RB_3_LO 0x00000142
#define REG_A4XX_RBBM_PERFCTR_RB_3_HI 0x00000143
#define REG_A4XX_RBBM_PERFCTR_RB_4_LO 0x00000144
#define REG_A4XX_RBBM_PERFCTR_RB_4_HI 0x00000145
#define REG_A4XX_RBBM_PERFCTR_RB_5_LO 0x00000146
#define REG_A4XX_RBBM_PERFCTR_RB_5_HI 0x00000147
#define REG_A4XX_RBBM_PERFCTR_RB_6_LO 0x00000148
#define REG_A4XX_RBBM_PERFCTR_RB_6_HI 0x00000149
#define REG_A4XX_RBBM_PERFCTR_RB_7_LO 0x0000014a
#define REG_A4XX_RBBM_PERFCTR_RB_7_HI 0x0000014b
#define REG_A4XX_RBBM_PERFCTR_VSC_0_LO 0x0000014c
#define REG_A4XX_RBBM_PERFCTR_VSC_0_HI 0x0000014d
#define REG_A4XX_RBBM_PERFCTR_VSC_1_LO 0x0000014e
#define REG_A4XX_RBBM_PERFCTR_VSC_1_HI 0x0000014f
#define REG_A4XX_RBBM_PERFCTR_PWR_0_LO 0x00000166
#define REG_A4XX_RBBM_PERFCTR_PWR_0_HI 0x00000167
#define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
#define REG_A4XX_RBBM_PERFCTR_PWR_1_HI 0x00000169
#define REG_A4XX_RBBM_ALWAYSON_COUNTER_LO 0x0000016e
#define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI 0x0000016f
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; }
static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }
......@@ -1046,6 +2039,10 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { r
static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }
#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x00000099
#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x0000009a
#define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
#define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170
......@@ -1060,6 +2057,14 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0)
#define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175
#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000176
#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000177
#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000178
#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3 0x00000179
#define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a
#define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d
......@@ -1099,6 +2104,11 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0)
#define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f
#define REG_A4XX_RBBM_POWER_STATUS 0x000001b0
#define A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON 0x00100000
#define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2 0x000001b8
#define REG_A4XX_CP_SCRATCH_UMASK 0x00000228
#define REG_A4XX_CP_SCRATCH_ADDR 0x00000229
......@@ -1191,6 +2201,20 @@ static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240
#define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500
#define REG_A4XX_CP_PERFCTR_CP_SEL_1 0x00000501
#define REG_A4XX_CP_PERFCTR_CP_SEL_2 0x00000502
#define REG_A4XX_CP_PERFCTR_CP_SEL_3 0x00000503
#define REG_A4XX_CP_PERFCTR_CP_SEL_4 0x00000504
#define REG_A4XX_CP_PERFCTR_CP_SEL_5 0x00000505
#define REG_A4XX_CP_PERFCTR_CP_SEL_6 0x00000506
#define REG_A4XX_CP_PERFCTR_CP_SEL_7 0x00000507
#define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b
static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; }
......@@ -1201,6 +2225,28 @@ static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578
#define REG_A4XX_SP_MODE_CONTROL 0x00000ec3
#define REG_A4XX_SP_PERFCTR_SP_SEL_0 0x00000ec4
#define REG_A4XX_SP_PERFCTR_SP_SEL_1 0x00000ec5
#define REG_A4XX_SP_PERFCTR_SP_SEL_2 0x00000ec6
#define REG_A4XX_SP_PERFCTR_SP_SEL_3 0x00000ec7
#define REG_A4XX_SP_PERFCTR_SP_SEL_4 0x00000ec8
#define REG_A4XX_SP_PERFCTR_SP_SEL_5 0x00000ec9
#define REG_A4XX_SP_PERFCTR_SP_SEL_6 0x00000eca
#define REG_A4XX_SP_PERFCTR_SP_SEL_7 0x00000ecb
#define REG_A4XX_SP_PERFCTR_SP_SEL_8 0x00000ecc
#define REG_A4XX_SP_PERFCTR_SP_SEL_9 0x00000ecd
#define REG_A4XX_SP_PERFCTR_SP_SEL_10 0x00000ece
#define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf
#define REG_A4XX_SP_SP_CTRL_REG 0x000022c0
......@@ -1699,6 +2745,12 @@ static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
#define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64
#define REG_A4XX_VPC_PERFCTR_VPC_SEL_0 0x00000e65
#define REG_A4XX_VPC_PERFCTR_VPC_SEL_1 0x00000e66
#define REG_A4XX_VPC_PERFCTR_VPC_SEL_2 0x00000e67
#define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68
#define REG_A4XX_VPC_ATTR 0x00002140
......@@ -1811,6 +2863,20 @@ static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0
#define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40
#define REG_A4XX_VFD_PERFCTR_VFD_SEL_0 0x00000e43
#define REG_A4XX_VFD_PERFCTR_VFD_SEL_1 0x00000e44
#define REG_A4XX_VFD_PERFCTR_VFD_SEL_2 0x00000e45
#define REG_A4XX_VFD_PERFCTR_VFD_SEL_3 0x00000e46
#define REG_A4XX_VFD_PERFCTR_VFD_SEL_4 0x00000e47
#define REG_A4XX_VFD_PERFCTR_VFD_SEL_5 0x00000e48
#define REG_A4XX_VFD_PERFCTR_VFD_SEL_6 0x00000e49
#define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a
#define REG_A4XX_VGT_CL_INITIATOR 0x000021d0
......@@ -1967,6 +3033,20 @@ static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
#define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03
#define REG_A4XX_TPL1_PERFCTR_TP_SEL_0 0x00000f04
#define REG_A4XX_TPL1_PERFCTR_TP_SEL_1 0x00000f05
#define REG_A4XX_TPL1_PERFCTR_TP_SEL_2 0x00000f06
#define REG_A4XX_TPL1_PERFCTR_TP_SEL_3 0x00000f07
#define REG_A4XX_TPL1_PERFCTR_TP_SEL_4 0x00000f08
#define REG_A4XX_TPL1_PERFCTR_TP_SEL_5 0x00000f09
#define REG_A4XX_TPL1_PERFCTR_TP_SEL_6 0x00000f0a
#define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b
#define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380
......@@ -2021,9 +3101,23 @@ static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)
#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88
#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c89
#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c8a
#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b
#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c8c
#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c8d
#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c8e
#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c8f
#define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000
#define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000
#define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000
#define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003
#define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001
......@@ -2114,6 +3208,7 @@ static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val)
#define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073
#define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004
#define A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS 0x00000008
#define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074
#define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
......@@ -2285,6 +3380,20 @@ static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val)
#define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c
#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e8e
#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e8f
#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e90
#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e91
#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e92
#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e93
#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e94
#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95
#define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00
......@@ -2295,6 +3404,22 @@ static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val)
#define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e
#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e06
#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e07
#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e08
#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e09
#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e0a
#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e0b
#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e0c
#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e0d
#define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0
#define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
#define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
......@@ -2549,6 +3674,18 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
#define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10
#define REG_A4XX_PC_PERFCTR_PC_SEL_1 0x00000d11
#define REG_A4XX_PC_PERFCTR_PC_SEL_2 0x00000d12
#define REG_A4XX_PC_PERFCTR_PC_SEL_3 0x00000d13
#define REG_A4XX_PC_PERFCTR_PC_SEL_4 0x00000d14
#define REG_A4XX_PC_PERFCTR_PC_SEL_5 0x00000d15
#define REG_A4XX_PC_PERFCTR_PC_SEL_6 0x00000d16
#define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17
#define REG_A4XX_PC_BIN_BASE 0x000021c0
......@@ -2564,7 +3701,20 @@ static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
#define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
#define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
#define REG_A4XX_UNKNOWN_21C5 0x000021c5
#define REG_A4XX_PC_PRIM_VTX_CNTL2 0x000021c5
#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK 0x00000007
#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT 0
static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
{
return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK;
}
#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK 0x00000038
#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT 3
static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
{
return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK;
}
#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE 0x00000040
#define REG_A4XX_PC_RESTART_INDEX 0x000021c6
......@@ -2646,20 +3796,6 @@ static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
#define REG_A4XX_UNKNOWN_20EF 0x000020ef
#define REG_A4XX_UNKNOWN_20F0 0x000020f0
#define REG_A4XX_UNKNOWN_20F1 0x000020f1
#define REG_A4XX_UNKNOWN_20F2 0x000020f2
#define REG_A4XX_UNKNOWN_20F7 0x000020f7
#define A4XX_UNKNOWN_20F7__MASK 0xffffffff
#define A4XX_UNKNOWN_20F7__SHIFT 0
static inline uint32_t A4XX_UNKNOWN_20F7(float val)
{
return ((fui(val)) << A4XX_UNKNOWN_20F7__SHIFT) & A4XX_UNKNOWN_20F7__MASK;
}
#define REG_A4XX_UNKNOWN_2152 0x00002152
#define REG_A4XX_UNKNOWN_2153 0x00002153
......@@ -2720,6 +3856,12 @@ static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)
{
return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK;
}
#define A4XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
#define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val)
{
return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK;
}
#define REG_A4XX_TEX_SAMP_1 0x00000001
#define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
......@@ -2728,6 +3870,7 @@ static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val
{
return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
}
#define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
#define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
#define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
#define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
......@@ -2796,7 +3939,7 @@ static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val)
{
return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK;
}
#define A4XX_TEX_CONST_1_WIDTH__MASK 0x1fff8000
#define A4XX_TEX_CONST_1_WIDTH__MASK 0x3fff8000
#define A4XX_TEX_CONST_1_WIDTH__SHIFT 15
static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
{
......
drivers/gpu/drm/msm/adreno/a4xx_gpu.c
View file @ 912b330c
......@@ -102,11 +102,17 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu)
gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000222);
gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_HLSQ , 0x00000000);
gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000);
gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00020000);
gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA);
gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000);
/* Early A430's have a timing issue with SP/TP power collapse;
disabling HW clock gating prevents it. */
if (adreno_is_a430(adreno_gpu) && adreno_gpu->rev.patchid < 2)
gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0);
else
gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA);
gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2, 0);
}
static void a4xx_me_init(struct msm_gpu *gpu)
{
struct msm_ringbuffer *ring = gpu->rb;
......@@ -141,7 +147,7 @@ static int a4xx_hw_init(struct msm_gpu *gpu)
uint32_t *ptr, len;
int i, ret;
if (adreno_is_a4xx(adreno_gpu)) {
if (adreno_is_a420(adreno_gpu)) {
gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT, 0x0001001F);
gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT_CONF, 0x000000A4);
gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001);
......@@ -150,6 +156,13 @@ static int a4xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0, 0x18181818);
gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1, 0x00000018);
gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003);
} else if (adreno_is_a430(adreno_gpu)) {
gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001);
gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF0, 0x18181818);
gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF1, 0x00000018);
gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0, 0x18181818);
gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1, 0x00000018);
gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003);
} else {
BUG();
}
......@@ -161,6 +174,10 @@ static int a4xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A4XX_RBBM_SP_HYST_CNT, 0x10);
gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10);
if (adreno_is_a430(adreno_gpu)) {
gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2, 0x30);
}
/* Enable the RBBM error reporting bits */
gpu_write(gpu, REG_A4XX_RBBM_AHB_CTL0, 0x00000001);
......@@ -183,6 +200,14 @@ static int a4xx_hw_init(struct msm_gpu *gpu)
/* Turn on performance counters: */
gpu_write(gpu, REG_A4XX_RBBM_PERFCTR_CTL, 0x01);
/* use the first CP counter for timestamp queries.. userspace may set
* this as well but it selects the same counter/countable:
*/
gpu_write(gpu, REG_A4XX_CP_PERFCTR_CP_SEL_0, CP_ALWAYS_COUNT);
if (adreno_is_a430(adreno_gpu))
gpu_write(gpu, REG_A4XX_UCHE_CACHE_WAYS_VFD, 0x07);
/* Disable L2 bypass to avoid UCHE out of bounds errors */
gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_LO, 0xffff0000);
gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_HI, 0xffff0000);
......@@ -190,6 +215,15 @@ static int a4xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A4XX_CP_DEBUG, (1 << 25) |
(adreno_is_a420(adreno_gpu) ? (1 << 29) : 0));
/* On A430 enable SP regfile sleep for power savings */
/* TODO downstream does this for !420, so maybe applies for 405 too? */
if (!adreno_is_a420(adreno_gpu)) {
gpu_write(gpu, REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0,
0x00000441);
gpu_write(gpu, REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1,
0x00000441);
}
a4xx_enable_hwcg(gpu);
/*
......@@ -204,10 +238,6 @@ static int a4xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, val);
}
ret = adreno_hw_init(gpu);
if (ret)
return ret;
/* setup access protection: */
gpu_write(gpu, REG_A4XX_CP_PROTECT_CTRL, 0x00000007);
......@@ -263,6 +293,7 @@ static int a4xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A4XX_CP_ME_CNTL, 0);
a4xx_me_init(gpu);
return 0;
}
......@@ -317,6 +348,13 @@ static irqreturn_t a4xx_irq(struct msm_gpu *gpu)
status = gpu_read(gpu, REG_A4XX_RBBM_INT_0_STATUS);
DBG("%s: Int status %08x", gpu->name, status);
if (status & A4XX_INT0_CP_REG_PROTECT_FAULT) {
uint32_t reg = gpu_read(gpu, REG_A4XX_CP_PROTECT_STATUS);
printk("CP | Protected mode error| %s | addr=%x\n",
reg & (1 << 24) ? "WRITE" : "READ",
(reg & 0xFFFFF) >> 2);
}
gpu_write(gpu, REG_A4XX_RBBM_INT_CLEAR_CMD, status);
msm_gpu_retire(gpu);
......@@ -512,12 +550,63 @@ static void a4xx_dump(struct msm_gpu *gpu)
adreno_dump(gpu);
}
static int a4xx_pm_resume(struct msm_gpu *gpu) {
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
int ret;
ret = msm_gpu_pm_resume(gpu);
if (ret)
return ret;
if (adreno_is_a430(adreno_gpu)) {
unsigned int reg;
/* Set the default register values; set SW_COLLAPSE to 0 */
gpu_write(gpu, REG_A4XX_RBBM_POWER_CNTL_IP, 0x778000);
do {
udelay(5);
reg = gpu_read(gpu, REG_A4XX_RBBM_POWER_STATUS);
} while (!(reg & A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON));
}
return 0;
}
static int a4xx_pm_suspend(struct msm_gpu *gpu) {
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
int ret;
ret = msm_gpu_pm_suspend(gpu);
if (ret)
return ret;
if (adreno_is_a430(adreno_gpu)) {
/* Set the default register values; set SW_COLLAPSE to 1 */
gpu_write(gpu, REG_A4XX_RBBM_POWER_CNTL_IP, 0x778001);
}
return 0;
}
static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
{
uint32_t hi, lo, tmp;
tmp = gpu_read(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_HI);
do {
hi = tmp;
lo = gpu_read(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_LO);
tmp = gpu_read(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_HI);
} while (tmp != hi);
*value = (((uint64_t)hi) << 32) | lo;
return 0;
}
static const struct adreno_gpu_funcs funcs = {
.base = {
.get_param = adreno_get_param,
.hw_init = a4xx_hw_init,
.pm_suspend = msm_gpu_pm_suspend,
.pm_resume = msm_gpu_pm_resume,
.pm_suspend = a4xx_pm_suspend,
.pm_resume = a4xx_pm_resume,
.recover = a4xx_recover,
.last_fence = adreno_last_fence,
.submit = adreno_submit,
......@@ -529,6 +618,7 @@ static const struct adreno_gpu_funcs funcs = {
.show = a4xx_show,
#endif
},
.get_timestamp = a4xx_get_timestamp,
};
struct msm_gpu *a4xx_gpu_init(struct drm_device *dev)
......
drivers/gpu/drm/msm/adreno/adreno_common.xml.h
View file @ 912b330c
......@@ -9,16 +9,17 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
Copyright (C) 2013-2015 by the following authors:
Copyright (C) 2013-2016 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
......@@ -119,6 +120,23 @@ enum adreno_rb_copy_control_mode {
RB_COPY_DEPTH_STENCIL = 5,
};
enum a3xx_rop_code {
ROP_CLEAR = 0,
ROP_NOR = 1,
ROP_AND_INVERTED = 2,
ROP_COPY_INVERTED = 3,
ROP_AND_REVERSE = 4,
ROP_INVERT = 5,
ROP_NAND = 7,
ROP_AND = 8,
ROP_EQUIV = 9,
ROP_NOOP = 10,
ROP_OR_INVERTED = 11,
ROP_OR_REVERSE = 13,
ROP_OR = 14,
ROP_SET = 15,
};
enum a3xx_render_mode {
RB_RENDERING_PASS = 0,
RB_TILING_PASS = 1,
......
drivers/gpu/drm/msm/adreno/adreno_device.c
View file @ 912b330c
......@@ -69,6 +69,14 @@ static const struct adreno_info gpulist[] = {
.pfpfw = "a420_pfp.fw",
.gmem = (SZ_1M + SZ_512K),
.init = a4xx_gpu_init,
}, {
.rev = ADRENO_REV(4, 3, 0, ANY_ID),
.revn = 430,
.name = "A430",
.pm4fw = "a420_pm4.fw",
.pfpfw = "a420_pfp.fw",
.gmem = (SZ_1M + SZ_512K),
.init = a4xx_gpu_init,
},
};
......
drivers/gpu/drm/msm/adreno/adreno_gpu.c
View file @ 912b330c
......@@ -44,6 +44,10 @@ int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
case MSM_PARAM_MAX_FREQ:
*value = adreno_gpu->base.fast_rate;
return 0;
case MSM_PARAM_TIMESTAMP:
if (adreno_gpu->funcs->get_timestamp)
return adreno_gpu->funcs->get_timestamp(gpu, value);
return -EINVAL;
default:
DBG("%s: invalid param: %u", gpu->name, param);
return -EINVAL;
......@@ -71,18 +75,15 @@ int adreno_hw_init(struct msm_gpu *gpu)
adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
/* size is log2(quad-words): */
AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) |
AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)));
AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)) |
(adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
/* Setup ringbuffer address: */
adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_BASE, gpu->rb_iova);
adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
rbmemptr(adreno_gpu, rptr));
/* Setup scratch/timestamp: */
adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_ADDR,
rbmemptr(adreno_gpu, fence));
adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_UMSK, 0x1);
if (!adreno_is_a430(adreno_gpu))
adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
rbmemptr(adreno_gpu, rptr));
return 0;
}
......@@ -92,6 +93,16 @@ static uint32_t get_wptr(struct msm_ringbuffer *ring)
return ring->cur - ring->start;
}
/* Use this helper to read rptr, since a430 doesn't update rptr in memory */
static uint32_t get_rptr(struct adreno_gpu *adreno_gpu)
{
if (adreno_is_a430(adreno_gpu))
return adreno_gpu->memptrs->rptr = adreno_gpu_read(
adreno_gpu, REG_ADRENO_CP_RB_RPTR);
else
return adreno_gpu->memptrs->rptr;
}
uint32_t adreno_last_fence(struct msm_gpu *gpu)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
......@@ -140,7 +151,8 @@ int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
if (priv->lastctx == ctx)
break;
case MSM_SUBMIT_CMD_BUF:
OUT_PKT3(ring, CP_INDIRECT_BUFFER_PFD, 2);
OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ?
CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
OUT_RING(ring, submit->cmd[i].iova);
OUT_RING(ring, submit->cmd[i].size);
ibs++;
......@@ -219,9 +231,12 @@ void adreno_idle(struct msm_gpu *gpu)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
uint32_t wptr = get_wptr(gpu->rb);
int ret;
/* wait for CP to drain ringbuffer: */
if (spin_until(adreno_gpu->memptrs->rptr == wptr))
ret = spin_until(get_rptr(adreno_gpu) == wptr);
if (ret)
DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name);
/* TODO maybe we need to reset GPU here to recover from hang? */
......@@ -240,7 +255,7 @@ void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
seq_printf(m, "fence: %d/%d\n", adreno_gpu->memptrs->fence,
gpu->submitted_fence);
seq_printf(m, "rptr: %d\n", adreno_gpu->memptrs->rptr);
seq_printf(m, "rptr: %d\n", get_rptr(adreno_gpu));
seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr);
seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb));
......@@ -281,7 +296,7 @@ void adreno_dump_info(struct msm_gpu *gpu)
printk("fence: %d/%d\n", adreno_gpu->memptrs->fence,
gpu->submitted_fence);
printk("rptr: %d\n", adreno_gpu->memptrs->rptr);
printk("rptr: %d\n", get_rptr(adreno_gpu));
printk("wptr: %d\n", adreno_gpu->memptrs->wptr);
printk("rb wptr: %d\n", get_wptr(gpu->rb));
......@@ -316,7 +331,7 @@ static uint32_t ring_freewords(struct msm_gpu *gpu)
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
uint32_t size = gpu->rb->size / 4;
uint32_t wptr = get_wptr(gpu->rb);
uint32_t rptr = adreno_gpu->memptrs->rptr;
uint32_t rptr = get_rptr(adreno_gpu);
return (rptr + (size - 1) - wptr) % size;
}
......
drivers/gpu/drm/msm/adreno/adreno_gpu.h
View file @ 912b330c
......@@ -114,6 +114,7 @@ struct adreno_rev {
struct adreno_gpu_funcs {
struct msm_gpu_funcs base;
int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
};
struct adreno_info {
......@@ -228,6 +229,11 @@ static inline int adreno_is_a420(struct adreno_gpu *gpu)
return gpu->revn == 420;
}
static inline int adreno_is_a430(struct adreno_gpu *gpu)
{
return gpu->revn == 430;
}
int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
int adreno_hw_init(struct msm_gpu *gpu);
uint32_t adreno_last_fence(struct msm_gpu *gpu);
......
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
View file @ 912b330c
......@@ -9,16 +9,17 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
Copyright (C) 2013-2015 by the following authors:
Copyright (C) 2013-2016 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
......@@ -172,6 +173,11 @@ enum adreno_pm4_type3_packets {
CP_UNKNOWN_1A = 26,
CP_UNKNOWN_4E = 78,
CP_WIDE_REG_WRITE = 116,
CP_SCRATCH_TO_REG = 77,
CP_REG_TO_SCRATCH = 74,
CP_WAIT_MEM_WRITES = 18,
CP_COND_REG_EXEC = 71,
CP_MEM_TO_REG = 66,
IN_IB_PREFETCH_END = 23,
IN_SUBBLK_PREFETCH = 31,
IN_INSTR_PREFETCH = 32,
......@@ -199,7 +205,11 @@ enum adreno_state_type {
enum adreno_state_src {
SS_DIRECT = 0,
SS_INVALID_ALL_IC = 2,
SS_INVALID_PART_IC = 3,
SS_INDIRECT = 4,
SS_INDIRECT_TCM = 5,
SS_INDIRECT_STM = 6,
};
enum a4xx_index_size {
......@@ -227,7 +237,7 @@ static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
{
return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
}
#define CP_LOAD_STATE_0_NUM_UNIT__MASK 0x7fc00000
#define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000
#define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22
static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
{
......@@ -499,5 +509,29 @@ static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
}
#define REG_CP_REG_TO_MEM_0 0x00000000
#define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff
#define CP_REG_TO_MEM_0_REG__SHIFT 0
static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
{
return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
}
#define CP_REG_TO_MEM_0_CNT__MASK 0x3ff80000
#define CP_REG_TO_MEM_0_CNT__SHIFT 19
static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
{
return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
}
#define CP_REG_TO_MEM_0_64B 0x40000000
#define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000
#define REG_CP_REG_TO_MEM_1 0x00000001
#define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff
#define CP_REG_TO_MEM_1_DEST__SHIFT 0
static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
{
return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
}
#endif /* ADRENO_PM4_XML */
drivers/gpu/drm/msm/dsi/dsi.xml.h
View file @ 912b330c
......@@ -9,7 +9,7 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
......@@ -17,11 +17,12 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
......
drivers/gpu/drm/msm/dsi/dsi_cfg.c
View file @ 912b330c
......@@ -57,10 +57,9 @@ static const char * const dsi_8916_bus_clk_names[] = {
static const struct msm_dsi_config msm8916_dsi_cfg = {
.io_offset = DSI_6G_REG_SHIFT,
.reg_cfg = {
.num = 4,
.num = 3,
.regs = {
{"gdsc", -1, -1, -1, -1},
{"vdd", 2850000, 2850000, 100000, 100},
{"vdda", 1200000, 1200000, 100000, 100},
{"vddio", 1800000, 1800000, 100000, 100},
},
......
drivers/gpu/drm/msm/dsi/dsi_host.c
View file @ 912b330c
......@@ -163,6 +163,10 @@ struct msm_dsi_host {
enum mipi_dsi_pixel_format format;
unsigned long mode_flags;
/* lane data parsed via DT */
int dlane_swap;
int num_data_lanes;
u32 dma_cmd_ctrl_restore;
bool registered;
......@@ -845,19 +849,10 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
data = DSI_CTRL_CLK_EN;
DBG("lane number=%d", msm_host->lanes);
if (msm_host->lanes == 2) {
data |= DSI_CTRL_LANE1 | DSI_CTRL_LANE2;
/* swap lanes for 2-lane panel for better performance */
dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_1230));
} else {
/* Take 4 lanes as default */
data |= DSI_CTRL_LANE0 | DSI_CTRL_LANE1 | DSI_CTRL_LANE2 |
DSI_CTRL_LANE3;
/* Do not swap lanes for 4-lane panel */
dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_0123));
}
data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0);
dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
dsi_write(msm_host, REG_DSI_LANE_CTRL,
......@@ -1479,13 +1474,14 @@ static int dsi_host_attach(struct mipi_dsi_host *host,
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
int ret;
if (dsi->lanes > msm_host->num_data_lanes)
return -EINVAL;
msm_host->channel = dsi->channel;
msm_host->lanes = dsi->lanes;
msm_host->format = dsi->format;
msm_host->mode_flags = dsi->mode_flags;
WARN_ON(dsi->dev.of_node != msm_host->device_node);
/* Some gpios defined in panel DT need to be controlled by host */
ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
if (ret)
......@@ -1534,6 +1530,75 @@ static struct mipi_dsi_host_ops dsi_host_ops = {
.transfer = dsi_host_transfer,
};
/*
* List of supported physical to logical lane mappings.
* For example, the 2nd entry represents the following mapping:
*
* "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
*/
static const int supported_data_lane_swaps[][4] = {
{ 0, 1, 2, 3 },
{ 3, 0, 1, 2 },
{ 2, 3, 0, 1 },
{ 1, 2, 3, 0 },
{ 0, 3, 2, 1 },
{ 1, 0, 3, 2 },
{ 2, 1, 0, 3 },
{ 3, 2, 1, 0 },
};
static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
struct device_node *ep)
{
struct device *dev = &msm_host->pdev->dev;
struct property *prop;
u32 lane_map[4];
int ret, i, len, num_lanes;
prop = of_find_property(ep, "qcom,data-lane-map", &len);
if (!prop) {
dev_dbg(dev, "failed to find data lane mapping\n");
return -EINVAL;
}
num_lanes = len / sizeof(u32);
if (num_lanes < 1 || num_lanes > 4) {
dev_err(dev, "bad number of data lanes\n");
return -EINVAL;
}
msm_host->num_data_lanes = num_lanes;
ret = of_property_read_u32_array(ep, "qcom,data-lane-map", lane_map,
num_lanes);
if (ret) {
dev_err(dev, "failed to read lane data\n");
return ret;
}
/*
* compare DT specified physical-logical lane mappings with the ones
* supported by hardware
*/
for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) {
const int *swap = supported_data_lane_swaps[i];
int j;
for (j = 0; j < num_lanes; j++) {
if (swap[j] != lane_map[j])
break;
}
if (j == num_lanes) {
msm_host->dlane_swap = i;
return 0;
}
}
return -EINVAL;
}
static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
{
struct device *dev = &msm_host->pdev->dev;
......@@ -1560,17 +1625,21 @@ static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
return 0;
}
ret = dsi_host_parse_lane_data(msm_host, endpoint);
if (ret) {
dev_err(dev, "%s: invalid lane configuration %d\n",
__func__, ret);
goto err;
}
/* Get panel node from the output port's endpoint data */
device_node = of_graph_get_remote_port_parent(endpoint);
if (!device_node) {
dev_err(dev, "%s: no valid device\n", __func__);
of_node_put(endpoint);
return -ENODEV;
ret = -ENODEV;
goto err;
}
of_node_put(endpoint);
of_node_put(device_node);
msm_host->device_node = device_node;
if (of_property_read_bool(np, "syscon-sfpb")) {
......@@ -1579,11 +1648,16 @@ static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
if (IS_ERR(msm_host->sfpb)) {
dev_err(dev, "%s: failed to get sfpb regmap\n",
__func__);
return PTR_ERR(msm_host->sfpb);
ret = PTR_ERR(msm_host->sfpb);
}
}
return 0;
of_node_put(device_node);
err:
of_node_put(endpoint);
return ret;
}
int msm_dsi_host_init(struct msm_dsi *msm_dsi)
......
drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
View file @ 912b330c
......@@ -9,7 +9,7 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
......@@ -17,11 +17,12 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
......
drivers/gpu/drm/msm/dsi/pll/dsi_pll.h
View file @ 912b330c
......@@ -97,8 +97,8 @@ static inline struct msm_dsi_pll *msm_dsi_pll_28nm_init(
struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev,
int id);
#else
struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev,
int id)
static inline struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(
struct platform_device *pdev, int id)
{
return ERR_PTR(-ENODEV);
}
......
drivers/gpu/drm/msm/dsi/sfpb.xml.h
View file @ 912b330c
......@@ -9,7 +9,7 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
......@@ -17,11 +17,12 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
......
drivers/gpu/drm/msm/edp/edp.xml.h
View file @ 912b330c
......@@ -9,7 +9,7 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
......@@ -17,11 +17,12 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
......
drivers/gpu/drm/msm/hdmi/hdmi.c
View file @ 912b330c
......@@ -21,7 +21,7 @@
#include "hdmi.h"
void hdmi_set_mode(struct hdmi *hdmi, bool power_on)
void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on)
{
uint32_t ctrl = 0;
unsigned long flags;
......@@ -46,29 +46,27 @@ void hdmi_set_mode(struct hdmi *hdmi, bool power_on)
power_on ? "Enable" : "Disable", ctrl);
}
static irqreturn_t hdmi_irq(int irq, void *dev_id)
static irqreturn_t msm_hdmi_irq(int irq, void *dev_id)
{
struct hdmi *hdmi = dev_id;
/* Process HPD: */
hdmi_connector_irq(hdmi->connector);
msm_hdmi_connector_irq(hdmi->connector);
/* Process DDC: */
hdmi_i2c_irq(hdmi->i2c);
msm_hdmi_i2c_irq(hdmi->i2c);
/* Process HDCP: */
if (hdmi->hdcp_ctrl)
hdmi_hdcp_irq(hdmi->hdcp_ctrl);
msm_hdmi_hdcp_irq(hdmi->hdcp_ctrl);
/* TODO audio.. */
return IRQ_HANDLED;
}
static void hdmi_destroy(struct hdmi *hdmi)
static void msm_hdmi_destroy(struct hdmi *hdmi)
{
struct hdmi_phy *phy = hdmi->phy;
/*
* at this point, hpd has been disabled,
* after flush workq, it's safe to deinit hdcp
......@@ -77,21 +75,53 @@ static void hdmi_destroy(struct hdmi *hdmi)
flush_workqueue(hdmi->workq);
destroy_workqueue(hdmi->workq);
}
hdmi_hdcp_destroy(hdmi);
if (phy)
phy->funcs->destroy(phy);
msm_hdmi_hdcp_destroy(hdmi);
if (hdmi->phy_dev) {
put_device(hdmi->phy_dev);
hdmi->phy = NULL;
hdmi->phy_dev = NULL;
}
if (hdmi->i2c)
hdmi_i2c_destroy(hdmi->i2c);
msm_hdmi_i2c_destroy(hdmi->i2c);
platform_set_drvdata(hdmi->pdev, NULL);
}
static int msm_hdmi_get_phy(struct hdmi *hdmi)
{
struct platform_device *pdev = hdmi->pdev;
struct platform_device *phy_pdev;
struct device_node *phy_node;
phy_node = of_parse_phandle(pdev->dev.of_node, "phys", 0);
if (!phy_node) {
dev_err(&pdev->dev, "cannot find phy device\n");
return -ENXIO;
}
phy_pdev = of_find_device_by_node(phy_node);
if (phy_pdev)
hdmi->phy = platform_get_drvdata(phy_pdev);
of_node_put(phy_node);
if (!phy_pdev || !hdmi->phy) {
dev_err(&pdev->dev, "phy driver is not ready\n");
return -EPROBE_DEFER;
}
hdmi->phy_dev = get_device(&phy_pdev->dev);
return 0;
}
/* construct hdmi at bind/probe time, grab all the resources. If
* we are to EPROBE_DEFER we want to do it here, rather than later
* at modeset_init() time
*/
static struct hdmi *hdmi_init(struct platform_device *pdev)
static struct hdmi *msm_hdmi_init(struct platform_device *pdev)
{
struct hdmi_platform_config *config = pdev->dev.platform_data;
struct hdmi *hdmi = NULL;
......@@ -108,18 +138,6 @@ static struct hdmi *hdmi_init(struct platform_device *pdev)
hdmi->config = config;
spin_lock_init(&hdmi->reg_lock);
/* not sure about which phy maps to which msm.. probably I miss some */
if (config->phy_init) {
hdmi->phy = config->phy_init(hdmi);
if (IS_ERR(hdmi->phy)) {
ret = PTR_ERR(hdmi->phy);
dev_err(&pdev->dev, "failed to load phy: %d\n", ret);
hdmi->phy = NULL;
goto fail;
}
}
hdmi->mmio = msm_ioremap(pdev, config->mmio_name, "HDMI");
if (IS_ERR(hdmi->mmio)) {
ret = PTR_ERR(hdmi->mmio);
......@@ -222,7 +240,7 @@ static struct hdmi *hdmi_init(struct platform_device *pdev)
hdmi->workq = alloc_ordered_workqueue("msm_hdmi", 0);
hdmi->i2c = hdmi_i2c_init(hdmi);
hdmi->i2c = msm_hdmi_i2c_init(hdmi);
if (IS_ERR(hdmi->i2c)) {
ret = PTR_ERR(hdmi->i2c);
dev_err(&pdev->dev, "failed to get i2c: %d\n", ret);
......@@ -230,7 +248,13 @@ static struct hdmi *hdmi_init(struct platform_device *pdev)
goto fail;
}
hdmi->hdcp_ctrl = hdmi_hdcp_init(hdmi);
ret = msm_hdmi_get_phy(hdmi);
if (ret) {
dev_err(&pdev->dev, "failed to get phy\n");
goto fail;
}
hdmi->hdcp_ctrl = msm_hdmi_hdcp_init(hdmi);
if (IS_ERR(hdmi->hdcp_ctrl)) {
dev_warn(&pdev->dev, "failed to init hdcp: disabled\n");
hdmi->hdcp_ctrl = NULL;
......@@ -240,7 +264,7 @@ static struct hdmi *hdmi_init(struct platform_device *pdev)
fail:
if (hdmi)
hdmi_destroy(hdmi);
msm_hdmi_destroy(hdmi);
return ERR_PTR(ret);
}
......@@ -250,10 +274,10 @@ static struct hdmi *hdmi_init(struct platform_device *pdev)
* driver (not hdmi sub-device's probe/bind!)
*
* Any resource (regulator/clk/etc) which could be missing at boot
* should be handled in hdmi_init() so that failure happens from
* should be handled in msm_hdmi_init() so that failure happens from
* hdmi sub-device's probe.
*/
int hdmi_modeset_init(struct hdmi *hdmi,
int msm_hdmi_modeset_init(struct hdmi *hdmi,
struct drm_device *dev, struct drm_encoder *encoder)
{
struct msm_drm_private *priv = dev->dev_private;
......@@ -265,7 +289,7 @@ int hdmi_modeset_init(struct hdmi *hdmi,
hdmi_audio_infoframe_init(&hdmi->audio.infoframe);
hdmi->bridge = hdmi_bridge_init(hdmi);
hdmi->bridge = msm_hdmi_bridge_init(hdmi);
if (IS_ERR(hdmi->bridge)) {
ret = PTR_ERR(hdmi->bridge);
dev_err(dev->dev, "failed to create HDMI bridge: %d\n", ret);
......@@ -273,7 +297,7 @@ int hdmi_modeset_init(struct hdmi *hdmi,
goto fail;
}
hdmi->connector = hdmi_connector_init(hdmi);
hdmi->connector = msm_hdmi_connector_init(hdmi);
if (IS_ERR(hdmi->connector)) {
ret = PTR_ERR(hdmi->connector);
dev_err(dev->dev, "failed to create HDMI connector: %d\n", ret);
......@@ -289,7 +313,7 @@ int hdmi_modeset_init(struct hdmi *hdmi,
}
ret = devm_request_irq(&pdev->dev, hdmi->irq,
hdmi_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
msm_hdmi_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
"hdmi_isr", hdmi);
if (ret < 0) {
dev_err(dev->dev, "failed to request IRQ%u: %d\n",
......@@ -309,7 +333,7 @@ int hdmi_modeset_init(struct hdmi *hdmi,
fail:
/* bridge is normally destroyed by drm: */
if (hdmi->bridge) {
hdmi_bridge_destroy(hdmi->bridge);
msm_hdmi_bridge_destroy(hdmi->bridge);
hdmi->bridge = NULL;
}
if (hdmi->connector) {
......@@ -331,15 +355,12 @@ int hdmi_modeset_init(struct hdmi *hdmi,
static const char *pwr_reg_names_none[] = {};
static const char *hpd_reg_names_none[] = {};
static struct hdmi_platform_config hdmi_tx_8660_config = {
.phy_init = hdmi_phy_8x60_init,
};
static struct hdmi_platform_config hdmi_tx_8660_config;
static const char *hpd_reg_names_8960[] = {"core-vdda", "hdmi-mux"};
static const char *hpd_clk_names_8960[] = {"core_clk", "master_iface_clk", "slave_iface_clk"};
static struct hdmi_platform_config hdmi_tx_8960_config = {
.phy_init = hdmi_phy_8960_init,
HDMI_CFG(hpd_reg, 8960),
HDMI_CFG(hpd_clk, 8960),
};
......@@ -351,7 +372,6 @@ static const char *hpd_clk_names_8x74[] = {"iface_clk", "core_clk", "mdp_core_cl
static unsigned long hpd_clk_freq_8x74[] = {0, 19200000, 0};
static struct hdmi_platform_config hdmi_tx_8974_config = {
.phy_init = hdmi_phy_8x74_init,
HDMI_CFG(pwr_reg, 8x74),
HDMI_CFG(hpd_reg, 8x74),
HDMI_CFG(pwr_clk, 8x74),
......@@ -362,7 +382,6 @@ static struct hdmi_platform_config hdmi_tx_8974_config = {
static const char *hpd_reg_names_8084[] = {"hpd-gdsc", "hpd-5v", "hpd-5v-en"};
static struct hdmi_platform_config hdmi_tx_8084_config = {
.phy_init = hdmi_phy_8x74_init,
HDMI_CFG(pwr_reg, 8x74),
HDMI_CFG(hpd_reg, 8084),
HDMI_CFG(pwr_clk, 8x74),
......@@ -371,7 +390,6 @@ static struct hdmi_platform_config hdmi_tx_8084_config = {
};
static struct hdmi_platform_config hdmi_tx_8994_config = {
.phy_init = NULL, /* nothing to do for this HDMI PHY 20nm */
HDMI_CFG(pwr_reg, 8x74),
HDMI_CFG(hpd_reg, none),
HDMI_CFG(pwr_clk, 8x74),
......@@ -380,7 +398,6 @@ static struct hdmi_platform_config hdmi_tx_8994_config = {
};
static struct hdmi_platform_config hdmi_tx_8996_config = {
.phy_init = NULL,
HDMI_CFG(pwr_reg, none),
HDMI_CFG(hpd_reg, none),
HDMI_CFG(pwr_clk, 8x74),
......@@ -388,7 +405,21 @@ static struct hdmi_platform_config hdmi_tx_8996_config = {
.hpd_freq = hpd_clk_freq_8x74,
};
static int get_gpio(struct device *dev, struct device_node *of_node, const char *name)
static const struct {
const char *name;
const bool output;
const int value;
const char *label;
} msm_hdmi_gpio_pdata[] = {
{ "qcom,hdmi-tx-ddc-clk", true, 1, "HDMI_DDC_CLK" },
{ "qcom,hdmi-tx-ddc-data", true, 1, "HDMI_DDC_DATA" },
{ "qcom,hdmi-tx-hpd", false, 1, "HDMI_HPD" },
{ "qcom,hdmi-tx-mux-en", true, 1, "HDMI_MUX_EN" },
{ "qcom,hdmi-tx-mux-sel", true, 0, "HDMI_MUX_SEL" },
{ "qcom,hdmi-tx-mux-lpm", true, 1, "HDMI_MUX_LPM" },
};
static int msm_hdmi_get_gpio(struct device_node *of_node, const char *name)
{
int gpio = of_get_named_gpio(of_node, name, 0);
if (gpio < 0) {
......@@ -403,13 +434,14 @@ static int get_gpio(struct device *dev, struct device_node *of_node, const char
return gpio;
}
static int hdmi_bind(struct device *dev, struct device *master, void *data)
static int msm_hdmi_bind(struct device *dev, struct device *master, void *data)
{
struct drm_device *drm = dev_get_drvdata(master);
struct msm_drm_private *priv = drm->dev_private;
static struct hdmi_platform_config *hdmi_cfg;
struct hdmi *hdmi;
struct device_node *of_node = dev->of_node;
int i;
hdmi_cfg = (struct hdmi_platform_config *)
of_device_get_match_data(dev);
......@@ -420,16 +452,18 @@ static int hdmi_bind(struct device *dev, struct device *master, void *data)
hdmi_cfg->mmio_name = "core_physical";
hdmi_cfg->qfprom_mmio_name = "qfprom_physical";
hdmi_cfg->ddc_clk_gpio = get_gpio(dev, of_node, "qcom,hdmi-tx-ddc-clk");
hdmi_cfg->ddc_data_gpio = get_gpio(dev, of_node, "qcom,hdmi-tx-ddc-data");
hdmi_cfg->hpd_gpio = get_gpio(dev, of_node, "qcom,hdmi-tx-hpd");
hdmi_cfg->mux_en_gpio = get_gpio(dev, of_node, "qcom,hdmi-tx-mux-en");
hdmi_cfg->mux_sel_gpio = get_gpio(dev, of_node, "qcom,hdmi-tx-mux-sel");
hdmi_cfg->mux_lpm_gpio = get_gpio(dev, of_node, "qcom,hdmi-tx-mux-lpm");
for (i = 0; i < HDMI_MAX_NUM_GPIO; i++) {
hdmi_cfg->gpios[i].num = msm_hdmi_get_gpio(of_node,
msm_hdmi_gpio_pdata[i].name);
hdmi_cfg->gpios[i].output = msm_hdmi_gpio_pdata[i].output;
hdmi_cfg->gpios[i].value = msm_hdmi_gpio_pdata[i].value;
hdmi_cfg->gpios[i].label = msm_hdmi_gpio_pdata[i].label;
}
dev->platform_data = hdmi_cfg;
hdmi = hdmi_init(to_platform_device(dev));
hdmi = msm_hdmi_init(to_platform_device(dev));
if (IS_ERR(hdmi))
return PTR_ERR(hdmi);
priv->hdmi = hdmi;
......@@ -437,34 +471,34 @@ static int hdmi_bind(struct device *dev, struct device *master, void *data)
return 0;
}
static void hdmi_unbind(struct device *dev, struct device *master,
static void msm_hdmi_unbind(struct device *dev, struct device *master,
void *data)
{
struct drm_device *drm = dev_get_drvdata(master);
struct msm_drm_private *priv = drm->dev_private;
if (priv->hdmi) {
hdmi_destroy(priv->hdmi);
msm_hdmi_destroy(priv->hdmi);
priv->hdmi = NULL;
}
}
static const struct component_ops hdmi_ops = {
.bind = hdmi_bind,
.unbind = hdmi_unbind,
static const struct component_ops msm_hdmi_ops = {
.bind = msm_hdmi_bind,
.unbind = msm_hdmi_unbind,
};
static int hdmi_dev_probe(struct platform_device *pdev)
static int msm_hdmi_dev_probe(struct platform_device *pdev)
{
return component_add(&pdev->dev, &hdmi_ops);
return component_add(&pdev->dev, &msm_hdmi_ops);
}
static int hdmi_dev_remove(struct platform_device *pdev)
static int msm_hdmi_dev_remove(struct platform_device *pdev)
{
component_del(&pdev->dev, &hdmi_ops);
component_del(&pdev->dev, &msm_hdmi_ops);
return 0;
}
static const struct of_device_id dt_match[] = {
static const struct of_device_id msm_hdmi_dt_match[] = {
{ .compatible = "qcom,hdmi-tx-8996", .data = &hdmi_tx_8996_config },
{ .compatible = "qcom,hdmi-tx-8994", .data = &hdmi_tx_8994_config },
{ .compatible = "qcom,hdmi-tx-8084", .data = &hdmi_tx_8084_config },
......@@ -474,21 +508,23 @@ static const struct of_device_id dt_match[] = {
{}
};
static struct platform_driver hdmi_driver = {
.probe = hdmi_dev_probe,
.remove = hdmi_dev_remove,
static struct platform_driver msm_hdmi_driver = {
.probe = msm_hdmi_dev_probe,
.remove = msm_hdmi_dev_remove,
.driver = {
.name = "hdmi_msm",
.of_match_table = dt_match,
.of_match_table = msm_hdmi_dt_match,
},
};
void __init hdmi_register(void)
void __init msm_hdmi_register(void)
{
platform_driver_register(&hdmi_driver);
msm_hdmi_phy_driver_register();
platform_driver_register(&msm_hdmi_driver);
}
void __exit hdmi_unregister(void)
void __exit msm_hdmi_unregister(void)
{
platform_driver_unregister(&hdmi_driver);
platform_driver_unregister(&msm_hdmi_driver);
msm_hdmi_phy_driver_unregister();
}
drivers/gpu/drm/msm/hdmi/hdmi.h
View file @ 912b330c
......@@ -27,10 +27,18 @@
#include "msm_drv.h"
#include "hdmi.xml.h"
#define HDMI_MAX_NUM_GPIO 6
struct hdmi_phy;
struct hdmi_platform_config;
struct hdmi_gpio_data {
int num;
bool output;
int value;
const char *label;
};
struct hdmi_audio {
bool enabled;
struct hdmi_audio_infoframe infoframe;
......@@ -62,6 +70,8 @@ struct hdmi {
struct clk **pwr_clks;
struct hdmi_phy *phy;
struct device *phy_dev;
struct i2c_adapter *i2c;
struct drm_connector *connector;
struct drm_bridge *bridge;
......@@ -88,7 +98,6 @@ struct hdmi {
/* platform config data (ie. from DT, or pdata) */
struct hdmi_platform_config {
struct hdmi_phy *(*phy_init)(struct hdmi *hdmi);
const char *mmio_name;
const char *qfprom_mmio_name;
......@@ -110,11 +119,10 @@ struct hdmi_platform_config {
int pwr_clk_cnt;
/* gpio's: */
int ddc_clk_gpio, ddc_data_gpio, hpd_gpio, mux_en_gpio, mux_sel_gpio;
int mux_lpm_gpio;
struct hdmi_gpio_data gpios[HDMI_MAX_NUM_GPIO];
};
void hdmi_set_mode(struct hdmi *hdmi, bool power_on);
void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on);
static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data)
{
......@@ -132,65 +140,113 @@ static inline u32 hdmi_qfprom_read(struct hdmi *hdmi, u32 reg)
}
/*
* The phy appears to be different, for example between 8960 and 8x60,
* so split the phy related functions out and load the correct one at
* runtime:
* hdmi phy:
*/
struct hdmi_phy_funcs {
void (*destroy)(struct hdmi_phy *phy);
enum hdmi_phy_type {
MSM_HDMI_PHY_8x60,
MSM_HDMI_PHY_8960,
MSM_HDMI_PHY_8x74,
MSM_HDMI_PHY_8996,
MSM_HDMI_PHY_MAX,
};
struct hdmi_phy_cfg {
enum hdmi_phy_type type;
void (*powerup)(struct hdmi_phy *phy, unsigned long int pixclock);
void (*powerdown)(struct hdmi_phy *phy);
const char * const *reg_names;
int num_regs;
const char * const *clk_names;
int num_clks;
};
extern const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg;
extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg;
extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg;
extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg;
struct hdmi_phy {
struct platform_device *pdev;
void __iomem *mmio;
struct hdmi_phy_cfg *cfg;
const struct hdmi_phy_funcs *funcs;
struct regulator **regs;
struct clk **clks;
};
struct hdmi_phy *hdmi_phy_8960_init(struct hdmi *hdmi);
struct hdmi_phy *hdmi_phy_8x60_init(struct hdmi *hdmi);
struct hdmi_phy *hdmi_phy_8x74_init(struct hdmi *hdmi);
static inline void hdmi_phy_write(struct hdmi_phy *phy, u32 reg, u32 data)
{
msm_writel(data, phy->mmio + reg);
}
static inline u32 hdmi_phy_read(struct hdmi_phy *phy, u32 reg)
{
return msm_readl(phy->mmio + reg);
}
int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy);
void msm_hdmi_phy_resource_disable(struct hdmi_phy *phy);
void msm_hdmi_phy_powerup(struct hdmi_phy *phy, unsigned long int pixclock);
void msm_hdmi_phy_powerdown(struct hdmi_phy *phy);
void __init msm_hdmi_phy_driver_register(void);
void __exit msm_hdmi_phy_driver_unregister(void);
#ifdef CONFIG_COMMON_CLK
int msm_hdmi_pll_8960_init(struct platform_device *pdev);
int msm_hdmi_pll_8996_init(struct platform_device *pdev);
#else
static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev);
{
return -ENODEV;
}
static inline int msm_hdmi_pll_8996_init(struct platform_device *pdev)
{
return -ENODEV;
}
#endif
/*
* audio:
*/
int hdmi_audio_update(struct hdmi *hdmi);
int hdmi_audio_info_setup(struct hdmi *hdmi, bool enabled,
int msm_hdmi_audio_update(struct hdmi *hdmi);
int msm_hdmi_audio_info_setup(struct hdmi *hdmi, bool enabled,
uint32_t num_of_channels, uint32_t channel_allocation,
uint32_t level_shift, bool down_mix);
void hdmi_audio_set_sample_rate(struct hdmi *hdmi, int rate);
void msm_hdmi_audio_set_sample_rate(struct hdmi *hdmi, int rate);
/*
* hdmi bridge:
*/
struct drm_bridge *hdmi_bridge_init(struct hdmi *hdmi);
void hdmi_bridge_destroy(struct drm_bridge *bridge);
struct drm_bridge *msm_hdmi_bridge_init(struct hdmi *hdmi);
void msm_hdmi_bridge_destroy(struct drm_bridge *bridge);
/*
* hdmi connector:
*/
void hdmi_connector_irq(struct drm_connector *connector);
struct drm_connector *hdmi_connector_init(struct hdmi *hdmi);
void msm_hdmi_connector_irq(struct drm_connector *connector);
struct drm_connector *msm_hdmi_connector_init(struct hdmi *hdmi);
/*
* i2c adapter for ddc:
*/
void hdmi_i2c_irq(struct i2c_adapter *i2c);
void hdmi_i2c_destroy(struct i2c_adapter *i2c);
struct i2c_adapter *hdmi_i2c_init(struct hdmi *hdmi);
void msm_hdmi_i2c_irq(struct i2c_adapter *i2c);
void msm_hdmi_i2c_destroy(struct i2c_adapter *i2c);
struct i2c_adapter *msm_hdmi_i2c_init(struct hdmi *hdmi);
/*
* hdcp
*/
struct hdmi_hdcp_ctrl *hdmi_hdcp_init(struct hdmi *hdmi);
void hdmi_hdcp_destroy(struct hdmi *hdmi);
void hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl);
void hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl);
void hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl);
struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi);
void msm_hdmi_hdcp_destroy(struct hdmi *hdmi);
void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl);
void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl);
void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl);
#endif /* __HDMI_CONNECTOR_H__ */
drivers/gpu/drm/msm/hdmi/hdmi.xml.h
View file @ 912b330c
......@@ -9,7 +9,7 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
......@@ -17,11 +17,12 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
Copyright (C) 2013-2015 by the following authors:
Copyright (C) 2013-2016 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
......@@ -559,7 +560,7 @@ static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)
#define REG_HDMI_CEC_WR_CHECK_CONFIG 0x00000370
#define REG_HDMI_8x60_PHY_REG0 0x00000300
#define REG_HDMI_8x60_PHY_REG0 0x00000000
#define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK 0x0000001c
#define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT 2
static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val)
......@@ -567,7 +568,7 @@ static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val)
return ((val) << HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT) & HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK;
}
#define REG_HDMI_8x60_PHY_REG1 0x00000304
#define REG_HDMI_8x60_PHY_REG1 0x00000004
#define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK 0x000000f0
#define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT 4
static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val)
......@@ -581,7 +582,7 @@ static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
return ((val) << HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT) & HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK;
}
#define REG_HDMI_8x60_PHY_REG2 0x00000308
#define REG_HDMI_8x60_PHY_REG2 0x00000008
#define HDMI_8x60_PHY_REG2_PD_DESER 0x00000001
#define HDMI_8x60_PHY_REG2_PD_DRIVE_1 0x00000002
#define HDMI_8x60_PHY_REG2_PD_DRIVE_2 0x00000004
......@@ -591,152 +592,152 @@ static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
#define HDMI_8x60_PHY_REG2_PD_PWRGEN 0x00000040
#define HDMI_8x60_PHY_REG2_RCV_SENSE_EN 0x00000080
#define REG_HDMI_8x60_PHY_REG3 0x0000030c
#define REG_HDMI_8x60_PHY_REG3 0x0000000c
#define HDMI_8x60_PHY_REG3_PLL_ENABLE 0x00000001
#define REG_HDMI_8x60_PHY_REG4 0x00000310
#define REG_HDMI_8x60_PHY_REG4 0x00000010
#define REG_HDMI_8x60_PHY_REG5 0x00000314
#define REG_HDMI_8x60_PHY_REG5 0x00000014
#define REG_HDMI_8x60_PHY_REG6 0x00000318
#define REG_HDMI_8x60_PHY_REG6 0x00000018
#define REG_HDMI_8x60_PHY_REG7 0x0000031c
#define REG_HDMI_8x60_PHY_REG7 0x0000001c
#define REG_HDMI_8x60_PHY_REG8 0x00000320
#define REG_HDMI_8x60_PHY_REG8 0x00000020
#define REG_HDMI_8x60_PHY_REG9 0x00000324
#define REG_HDMI_8x60_PHY_REG9 0x00000024
#define REG_HDMI_8x60_PHY_REG10 0x00000328
#define REG_HDMI_8x60_PHY_REG10 0x00000028
#define REG_HDMI_8x60_PHY_REG11 0x0000032c
#define REG_HDMI_8x60_PHY_REG11 0x0000002c
#define REG_HDMI_8x60_PHY_REG12 0x00000330
#define REG_HDMI_8x60_PHY_REG12 0x00000030
#define HDMI_8x60_PHY_REG12_RETIMING_EN 0x00000001
#define HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN 0x00000002
#define HDMI_8x60_PHY_REG12_FORCE_LOCK 0x00000010
#define REG_HDMI_8960_PHY_REG0 0x00000400
#define REG_HDMI_8960_PHY_REG0 0x00000000
#define REG_HDMI_8960_PHY_REG1 0x00000404
#define REG_HDMI_8960_PHY_REG1 0x00000004
#define REG_HDMI_8960_PHY_REG2 0x00000408
#define REG_HDMI_8960_PHY_REG2 0x00000008
#define REG_HDMI_8960_PHY_REG3 0x0000040c
#define REG_HDMI_8960_PHY_REG3 0x0000000c
#define REG_HDMI_8960_PHY_REG4 0x00000410
#define REG_HDMI_8960_PHY_REG4 0x00000010
#define REG_HDMI_8960_PHY_REG5 0x00000414
#define REG_HDMI_8960_PHY_REG5 0x00000014
#define REG_HDMI_8960_PHY_REG6 0x00000418
#define REG_HDMI_8960_PHY_REG6 0x00000018
#define REG_HDMI_8960_PHY_REG7 0x0000041c
#define REG_HDMI_8960_PHY_REG7 0x0000001c
#define REG_HDMI_8960_PHY_REG8 0x00000420
#define REG_HDMI_8960_PHY_REG8 0x00000020
#define REG_HDMI_8960_PHY_REG9 0x00000424
#define REG_HDMI_8960_PHY_REG9 0x00000024
#define REG_HDMI_8960_PHY_REG10 0x00000428
#define REG_HDMI_8960_PHY_REG10 0x00000028
#define REG_HDMI_8960_PHY_REG11 0x0000042c
#define REG_HDMI_8960_PHY_REG11 0x0000002c
#define REG_HDMI_8960_PHY_REG12 0x00000430
#define REG_HDMI_8960_PHY_REG12 0x00000030
#define HDMI_8960_PHY_REG12_SW_RESET 0x00000020
#define HDMI_8960_PHY_REG12_PWRDN_B 0x00000080
#define REG_HDMI_8960_PHY_REG_BIST_CFG 0x00000434
#define REG_HDMI_8960_PHY_REG_BIST_CFG 0x00000034
#define REG_HDMI_8960_PHY_DEBUG_BUS_SEL 0x00000438
#define REG_HDMI_8960_PHY_DEBUG_BUS_SEL 0x00000038
#define REG_HDMI_8960_PHY_REG_MISC0 0x0000043c
#define REG_HDMI_8960_PHY_REG_MISC0 0x0000003c
#define REG_HDMI_8960_PHY_REG13 0x00000440
#define REG_HDMI_8960_PHY_REG13 0x00000040
#define REG_HDMI_8960_PHY_REG14 0x00000444
#define REG_HDMI_8960_PHY_REG14 0x00000044
#define REG_HDMI_8960_PHY_REG15 0x00000448
#define REG_HDMI_8960_PHY_REG15 0x00000048
#define REG_HDMI_8960_PHY_PLL_REFCLK_CFG 0x00000500
#define REG_HDMI_8960_PHY_PLL_REFCLK_CFG 0x00000000
#define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG 0x00000504
#define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG 0x00000004
#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 0x00000508
#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 0x00000008
#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 0x0000050c
#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 0x0000000c
#define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG 0x00000510
#define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG 0x00000010
#define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG 0x00000514
#define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG 0x00000014
#define REG_HDMI_8960_PHY_PLL_PWRDN_B 0x00000518
#define REG_HDMI_8960_PHY_PLL_PWRDN_B 0x00000018
#define HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL 0x00000002
#define HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B 0x00000008
#define REG_HDMI_8960_PHY_PLL_SDM_CFG0 0x0000051c
#define REG_HDMI_8960_PHY_PLL_SDM_CFG0 0x0000001c
#define REG_HDMI_8960_PHY_PLL_SDM_CFG1 0x00000520
#define REG_HDMI_8960_PHY_PLL_SDM_CFG1 0x00000020
#define REG_HDMI_8960_PHY_PLL_SDM_CFG2 0x00000524
#define REG_HDMI_8960_PHY_PLL_SDM_CFG2 0x00000024
#define REG_HDMI_8960_PHY_PLL_SDM_CFG3 0x00000528
#define REG_HDMI_8960_PHY_PLL_SDM_CFG3 0x00000028
#define REG_HDMI_8960_PHY_PLL_SDM_CFG4 0x0000052c
#define REG_HDMI_8960_PHY_PLL_SDM_CFG4 0x0000002c
#define REG_HDMI_8960_PHY_PLL_SSC_CFG0 0x00000530
#define REG_HDMI_8960_PHY_PLL_SSC_CFG0 0x00000030
#define REG_HDMI_8960_PHY_PLL_SSC_CFG1 0x00000534
#define REG_HDMI_8960_PHY_PLL_SSC_CFG1 0x00000034
#define REG_HDMI_8960_PHY_PLL_SSC_CFG2 0x00000538
#define REG_HDMI_8960_PHY_PLL_SSC_CFG2 0x00000038
#define REG_HDMI_8960_PHY_PLL_SSC_CFG3 0x0000053c
#define REG_HDMI_8960_PHY_PLL_SSC_CFG3 0x0000003c
#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 0x00000540
#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 0x00000040
#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 0x00000544
#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 0x00000044
#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 0x00000548
#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 0x00000048
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 0x0000054c
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 0x0000004c
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 0x00000550
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 0x00000050
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 0x00000554
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 0x00000054
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 0x00000558
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 0x00000058
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 0x0000055c
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 0x0000005c
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 0x00000560
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 0x00000060
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 0x00000564
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 0x00000064
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 0x00000568
#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 0x00000068
#define REG_HDMI_8960_PHY_PLL_DEBUG_SEL 0x0000056c
#define REG_HDMI_8960_PHY_PLL_DEBUG_SEL 0x0000006c
#define REG_HDMI_8960_PHY_PLL_MISC0 0x00000570
#define REG_HDMI_8960_PHY_PLL_MISC0 0x00000070
#define REG_HDMI_8960_PHY_PLL_MISC1 0x00000574
#define REG_HDMI_8960_PHY_PLL_MISC1 0x00000074
#define REG_HDMI_8960_PHY_PLL_MISC2 0x00000578
#define REG_HDMI_8960_PHY_PLL_MISC2 0x00000078
#define REG_HDMI_8960_PHY_PLL_MISC3 0x0000057c
#define REG_HDMI_8960_PHY_PLL_MISC3 0x0000007c
#define REG_HDMI_8960_PHY_PLL_MISC4 0x00000580
#define REG_HDMI_8960_PHY_PLL_MISC4 0x00000080
#define REG_HDMI_8960_PHY_PLL_MISC5 0x00000584
#define REG_HDMI_8960_PHY_PLL_MISC5 0x00000084
#define REG_HDMI_8960_PHY_PLL_MISC6 0x00000588
#define REG_HDMI_8960_PHY_PLL_MISC6 0x00000088
#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0 0x0000058c
#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0 0x0000008c
#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1 0x00000590
#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1 0x00000090
#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2 0x00000594
#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2 0x00000094
#define REG_HDMI_8960_PHY_PLL_STATUS0 0x00000598
#define REG_HDMI_8960_PHY_PLL_STATUS0 0x00000098
#define HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK 0x00000001
#define REG_HDMI_8960_PHY_PLL_STATUS1 0x0000059c
#define REG_HDMI_8960_PHY_PLL_STATUS1 0x0000009c
#define REG_HDMI_8x74_ANA_CFG0 0x00000000
......@@ -843,5 +844,501 @@ static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
#define REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
#define REG_HDMI_8996_PHY_CFG 0x00000000
#define REG_HDMI_8996_PHY_PD_CTL 0x00000004
#define REG_HDMI_8996_PHY_MODE 0x00000008
#define REG_HDMI_8996_PHY_MISR_CLEAR 0x0000000c
#define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG0 0x00000010
#define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG1 0x00000014
#define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE0 0x00000018
#define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE1 0x0000001c
#define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN0 0x00000020
#define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN1 0x00000024
#define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG0 0x00000028
#define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG1 0x0000002c
#define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE0 0x00000030
#define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE1 0x00000034
#define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN0 0x00000038
#define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN1 0x0000003c
#define REG_HDMI_8996_PHY_DEBUG_BUS_SEL 0x00000040
#define REG_HDMI_8996_PHY_TXCAL_CFG0 0x00000044
#define REG_HDMI_8996_PHY_TXCAL_CFG1 0x00000048
#define REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL 0x0000004c
#define REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL 0x00000050
#define REG_HDMI_8996_PHY_LANE_BIST_CONFIG 0x00000054
#define REG_HDMI_8996_PHY_CLOCK 0x00000058
#define REG_HDMI_8996_PHY_MISC1 0x0000005c
#define REG_HDMI_8996_PHY_MISC2 0x00000060
#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS0 0x00000064
#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS1 0x00000068
#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS2 0x0000006c
#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS0 0x00000070
#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS1 0x00000074
#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS2 0x00000078
#define REG_HDMI_8996_PHY_PRE_MISR_STATUS0 0x0000007c
#define REG_HDMI_8996_PHY_PRE_MISR_STATUS1 0x00000080
#define REG_HDMI_8996_PHY_PRE_MISR_STATUS2 0x00000084
#define REG_HDMI_8996_PHY_PRE_MISR_STATUS3 0x00000088
#define REG_HDMI_8996_PHY_POST_MISR_STATUS0 0x0000008c
#define REG_HDMI_8996_PHY_POST_MISR_STATUS1 0x00000090
#define REG_HDMI_8996_PHY_POST_MISR_STATUS2 0x00000094
#define REG_HDMI_8996_PHY_POST_MISR_STATUS3 0x00000098
#define REG_HDMI_8996_PHY_STATUS 0x0000009c
#define REG_HDMI_8996_PHY_MISC3_STATUS 0x000000a0
#define REG_HDMI_8996_PHY_MISC4_STATUS 0x000000a4
#define REG_HDMI_8996_PHY_DEBUG_BUS0 0x000000a8
#define REG_HDMI_8996_PHY_DEBUG_BUS1 0x000000ac
#define REG_HDMI_8996_PHY_DEBUG_BUS2 0x000000b0
#define REG_HDMI_8996_PHY_DEBUG_BUS3 0x000000b4
#define REG_HDMI_8996_PHY_PHY_REVISION_ID0 0x000000b8
#define REG_HDMI_8996_PHY_PHY_REVISION_ID1 0x000000bc
#define REG_HDMI_8996_PHY_PHY_REVISION_ID2 0x000000c0
#define REG_HDMI_8996_PHY_PHY_REVISION_ID3 0x000000c4
#define REG_HDMI_PHY_QSERDES_COM_ATB_SEL1 0x00000000
#define REG_HDMI_PHY_QSERDES_COM_ATB_SEL2 0x00000004
#define REG_HDMI_PHY_QSERDES_COM_FREQ_UPDATE 0x00000008
#define REG_HDMI_PHY_QSERDES_COM_BG_TIMER 0x0000000c
#define REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER 0x00000010
#define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER1 0x00000014
#define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER2 0x00000018
#define REG_HDMI_PHY_QSERDES_COM_SSC_PER1 0x0000001c
#define REG_HDMI_PHY_QSERDES_COM_SSC_PER2 0x00000020
#define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1 0x00000024
#define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2 0x00000028
#define REG_HDMI_PHY_QSERDES_COM_POST_DIV 0x0000002c
#define REG_HDMI_PHY_QSERDES_COM_POST_DIV_MUX 0x00000030
#define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x00000034
#define REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1 0x00000038
#define REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL 0x0000003c
#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE 0x00000040
#define REG_HDMI_PHY_QSERDES_COM_PLL_EN 0x00000044
#define REG_HDMI_PHY_QSERDES_COM_PLL_IVCO 0x00000048
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0 0x0000004c
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0 0x00000050
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0 0x00000054
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE1 0x00000058
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE1 0x0000005c
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE1 0x00000060
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE2 0x00000064
#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD0 0x00000064
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE2 0x00000068
#define REG_HDMI_PHY_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x00000068
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE2 0x0000006c
#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x0000006c
#define REG_HDMI_PHY_QSERDES_COM_BG_TRIM 0x00000070
#define REG_HDMI_PHY_QSERDES_COM_CLK_EP_DIV 0x00000074
#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0 0x00000078
#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE1 0x0000007c
#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE2 0x00000080
#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD1 0x00000080
#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0 0x00000084
#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE1 0x00000088
#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE2 0x0000008c
#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD2 0x0000008c
#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0 0x00000090
#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE1 0x00000094
#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE2 0x00000098
#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD3 0x00000098
#define REG_HDMI_PHY_QSERDES_COM_PLL_CNTRL 0x0000009c
#define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_CTRL 0x000000a0
#define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_DC 0x000000a4
#define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_IN_SYNC_SEL 0x000000a8
#define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x000000a8
#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL 0x000000ac
#define REG_HDMI_PHY_QSERDES_COM_CML_SYSCLK_SEL 0x000000b0
#define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL 0x000000b4
#define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL2 0x000000b8
#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL 0x000000bc
#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL2 0x000000c0
#define REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM 0x000000c4
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN 0x000000c8
#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_CFG 0x000000cc
#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0 0x000000d0
#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE1 0x000000d4
#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE2 0x000000d8
#define REG_HDMI_PHY_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x000000d8
#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 0x000000dc
#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 0x000000e0
#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x000000e4
#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE1 0x000000e8
#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE1 0x000000ec
#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE1 0x000000f0
#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE2 0x000000f4
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL1 0x000000f4
#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE2 0x000000f8
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL2 0x000000f8
#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE2 0x000000fc
#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD4 0x000000fc
#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_INITVAL 0x00000100
#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_EN 0x00000104
#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x00000108
#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x0000010c
#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x00000110
#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x00000114
#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE2 0x00000118
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL1 0x00000118
#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE2 0x0000011c
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL2 0x0000011c
#define REG_HDMI_PHY_QSERDES_COM_RES_TRIM_CONTROL2 0x00000120
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL 0x00000124
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP 0x00000128
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE0 0x0000012c
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE0 0x00000130
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE1 0x00000134
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE1 0x00000138
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE2 0x0000013c
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL1 0x0000013c
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE2 0x00000140
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL2 0x00000140
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER1 0x00000144
#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER2 0x00000148
#define REG_HDMI_PHY_QSERDES_COM_SAR 0x0000014c
#define REG_HDMI_PHY_QSERDES_COM_SAR_CLK 0x00000150
#define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_OUT_STATUS 0x00000154
#define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_READY_STATUS 0x00000158
#define REG_HDMI_PHY_QSERDES_COM_CMN_STATUS 0x0000015c
#define REG_HDMI_PHY_QSERDES_COM_RESET_SM_STATUS 0x00000160
#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CODE_STATUS 0x00000164
#define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE1_STATUS 0x00000168
#define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE2_STATUS 0x0000016c
#define REG_HDMI_PHY_QSERDES_COM_BG_CTRL 0x00000170
#define REG_HDMI_PHY_QSERDES_COM_CLK_SELECT 0x00000174
#define REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL 0x00000178
#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x0000017c
#define REG_HDMI_PHY_QSERDES_COM_PLL_ANALOG 0x00000180
#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV 0x00000184
#define REG_HDMI_PHY_QSERDES_COM_SW_RESET 0x00000188
#define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN 0x0000018c
#define REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS 0x00000190
#define REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG 0x00000194
#define REG_HDMI_PHY_QSERDES_COM_CMN_RATE_OVERRIDE 0x00000198
#define REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL 0x0000019c
#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS0 0x000001a0
#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS1 0x000001a4
#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS2 0x000001a8
#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS3 0x000001ac
#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS_SEL 0x000001b0
#define REG_HDMI_PHY_QSERDES_COM_CMN_MISC1 0x000001b4
#define REG_HDMI_PHY_QSERDES_COM_CMN_MISC2 0x000001b8
#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE1 0x000001bc
#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE2 0x000001c0
#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD5 0x000001c4
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_MODE_LANENO 0x00000000
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_INVERT 0x00000004
#define REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE 0x00000008
#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_ONE 0x0000000c
#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_TWO 0x00000010
#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_THREE 0x00000014
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL 0x00000018
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_POST2_EMPH 0x0000001c
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_BOOST_LVL_UP_DN 0x00000020
#define REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES 0x00000024
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_IDLE_LVL_LARGE_AMP 0x00000028
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL 0x0000002c
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET 0x00000030
#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN 0x00000034
#define REG_HDMI_PHY_QSERDES_TX_LX_PRE_STALL_LDO_BOOST_EN 0x00000038
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND 0x0000003c
#define REG_HDMI_PHY_QSERDES_TX_LX_SLEW_CNTL 0x00000040
#define REG_HDMI_PHY_QSERDES_TX_LX_INTERFACE_SELECT 0x00000044
#define REG_HDMI_PHY_QSERDES_TX_LX_LPB_EN 0x00000048
#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_TX 0x0000004c
#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_RX 0x00000050
#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET 0x00000054
#define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH1 0x00000058
#define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH2 0x0000005c
#define REG_HDMI_PHY_QSERDES_TX_LX_SERDES_BYP_EN_OUT 0x00000060
#define REG_HDMI_PHY_QSERDES_TX_LX_DEBUG_BUS_SEL 0x00000064
#define REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x00000068
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_POL_INV 0x0000006c
#define REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN 0x00000070
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN1 0x00000074
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN2 0x00000078
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN3 0x0000007c
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN4 0x00000080
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN5 0x00000084
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN6 0x00000088
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN7 0x0000008c
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN8 0x00000090
#define REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE 0x00000094
#define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE 0x00000098
#define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE_CONFIGURATION 0x0000009c
#define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL1 0x000000a0
#define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL2 0x000000a4
#define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL 0x000000a8
#define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL_2 0x000000ac
#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED1 0x000000b0
#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED2 0x000000b4
#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED3 0x000000b8
#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED4 0x000000bc
#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN 0x000000c0
#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN_MUXES 0x000000c4
#define REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN 0x000000c8
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_INTERFACE_MODE 0x000000cc
#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_CTRL 0x000000d0
#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_ENCODED_OR_DATA 0x000000d4
#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND2 0x000000d8
#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND2 0x000000dc
#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND2 0x000000e0
#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND2 0x000000e4
#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND0_1 0x000000e8
#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND0_1 0x000000ec
#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND0_1 0x000000f0
#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND0_1 0x000000f4
#define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1 0x000000f8
#define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2 0x000000fc
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV_CNTL 0x00000100
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_STATUS 0x00000104
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT1 0x00000108
#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT2 0x0000010c
#define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV 0x00000110
#endif /* HDMI_XML */
drivers/gpu/drm/msm/hdmi/hdmi_audio.c
View file @ 912b330c
......@@ -89,7 +89,7 @@ static const struct hdmi_msm_audio_arcs *get_arcs(unsigned long int pixclock)
return NULL;
}
int hdmi_audio_update(struct hdmi *hdmi)
int msm_hdmi_audio_update(struct hdmi *hdmi)
{
struct hdmi_audio *audio = &hdmi->audio;
struct hdmi_audio_infoframe *info = &audio->infoframe;
......@@ -232,7 +232,7 @@ int hdmi_audio_update(struct hdmi *hdmi)
return 0;
}
int hdmi_audio_info_setup(struct hdmi *hdmi, bool enabled,
int msm_hdmi_audio_info_setup(struct hdmi *hdmi, bool enabled,
uint32_t num_of_channels, uint32_t channel_allocation,
uint32_t level_shift, bool down_mix)
{
......@@ -252,10 +252,10 @@ int hdmi_audio_info_setup(struct hdmi *hdmi, bool enabled,
audio->infoframe.level_shift_value = level_shift;
audio->infoframe.downmix_inhibit = down_mix;
return hdmi_audio_update(hdmi);
return msm_hdmi_audio_update(hdmi);
}
void hdmi_audio_set_sample_rate(struct hdmi *hdmi, int rate)
void msm_hdmi_audio_set_sample_rate(struct hdmi *hdmi, int rate)
{
struct hdmi_audio *audio;
......@@ -268,5 +268,5 @@ void hdmi_audio_set_sample_rate(struct hdmi *hdmi, int rate)
return;
audio->rate = rate;
hdmi_audio_update(hdmi);
msm_hdmi_audio_update(hdmi);
}
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
View file @ 912b330c
......@@ -23,11 +23,11 @@ struct hdmi_bridge {
};
#define to_hdmi_bridge(x) container_of(x, struct hdmi_bridge, base)
void hdmi_bridge_destroy(struct drm_bridge *bridge)
void msm_hdmi_bridge_destroy(struct drm_bridge *bridge)
{
}
static void power_on(struct drm_bridge *bridge)
static void msm_hdmi_power_on(struct drm_bridge *bridge)
{
struct drm_device *dev = bridge->dev;
struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
......@@ -86,7 +86,7 @@ static void power_off(struct drm_bridge *bridge)
}
}
static void hdmi_bridge_pre_enable(struct drm_bridge *bridge)
static void msm_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
{
struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
struct hdmi *hdmi = hdmi_bridge->hdmi;
......@@ -95,51 +95,51 @@ static void hdmi_bridge_pre_enable(struct drm_bridge *bridge)
DBG("power up");
if (!hdmi->power_on) {
power_on(bridge);
msm_hdmi_phy_resource_enable(phy);
msm_hdmi_power_on(bridge);
hdmi->power_on = true;
hdmi_audio_update(hdmi);
msm_hdmi_audio_update(hdmi);
}
if (phy)
phy->funcs->powerup(phy, hdmi->pixclock);
msm_hdmi_phy_powerup(phy, hdmi->pixclock);
hdmi_set_mode(hdmi, true);
msm_hdmi_set_mode(hdmi, true);
if (hdmi->hdcp_ctrl)
hdmi_hdcp_on(hdmi->hdcp_ctrl);
msm_hdmi_hdcp_on(hdmi->hdcp_ctrl);
}
static void hdmi_bridge_enable(struct drm_bridge *bridge)
static void msm_hdmi_bridge_enable(struct drm_bridge *bridge)
{
}
static void hdmi_bridge_disable(struct drm_bridge *bridge)
static void msm_hdmi_bridge_disable(struct drm_bridge *bridge)
{
}
static void hdmi_bridge_post_disable(struct drm_bridge *bridge)
static void msm_hdmi_bridge_post_disable(struct drm_bridge *bridge)
{
struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
struct hdmi *hdmi = hdmi_bridge->hdmi;
struct hdmi_phy *phy = hdmi->phy;
if (hdmi->hdcp_ctrl)
hdmi_hdcp_off(hdmi->hdcp_ctrl);
msm_hdmi_hdcp_off(hdmi->hdcp_ctrl);
DBG("power down");
hdmi_set_mode(hdmi, false);
msm_hdmi_set_mode(hdmi, false);
if (phy)
phy->funcs->powerdown(phy);
msm_hdmi_phy_powerdown(phy);
if (hdmi->power_on) {
power_off(bridge);
hdmi->power_on = false;
hdmi_audio_update(hdmi);
msm_hdmi_audio_update(hdmi);
msm_hdmi_phy_resource_disable(phy);
}
}
static void hdmi_bridge_mode_set(struct drm_bridge *bridge,
static void msm_hdmi_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
......@@ -196,20 +196,20 @@ static void hdmi_bridge_mode_set(struct drm_bridge *bridge,
DBG("frame_ctrl=%08x", frame_ctrl);
hdmi_write(hdmi, REG_HDMI_FRAME_CTRL, frame_ctrl);
hdmi_audio_update(hdmi);
msm_hdmi_audio_update(hdmi);
}
static const struct drm_bridge_funcs hdmi_bridge_funcs = {
.pre_enable = hdmi_bridge_pre_enable,
.enable = hdmi_bridge_enable,
.disable = hdmi_bridge_disable,
.post_disable = hdmi_bridge_post_disable,
.mode_set = hdmi_bridge_mode_set,
static const struct drm_bridge_funcs msm_hdmi_bridge_funcs = {
.pre_enable = msm_hdmi_bridge_pre_enable,
.enable = msm_hdmi_bridge_enable,
.disable = msm_hdmi_bridge_disable,
.post_disable = msm_hdmi_bridge_post_disable,
.mode_set = msm_hdmi_bridge_mode_set,
};
/* initialize bridge */
struct drm_bridge *hdmi_bridge_init(struct hdmi *hdmi)
struct drm_bridge *msm_hdmi_bridge_init(struct hdmi *hdmi)
{
struct drm_bridge *bridge = NULL;
struct hdmi_bridge *hdmi_bridge;
......@@ -225,7 +225,7 @@ struct drm_bridge *hdmi_bridge_init(struct hdmi *hdmi)
hdmi_bridge->hdmi = hdmi;
bridge = &hdmi_bridge->base;
bridge->funcs = &hdmi_bridge_funcs;
bridge->funcs = &msm_hdmi_bridge_funcs;
ret = drm_bridge_attach(hdmi->dev, bridge);
if (ret)
......@@ -235,7 +235,7 @@ struct drm_bridge *hdmi_bridge_init(struct hdmi *hdmi)
fail:
if (bridge)
hdmi_bridge_destroy(bridge);
msm_hdmi_bridge_destroy(bridge);
return ERR_PTR(ret);
}
drivers/gpu/drm/msm/hdmi/hdmi_connector.c
View file @ 912b330c
......@@ -28,7 +28,7 @@ struct hdmi_connector {
};
#define to_hdmi_connector(x) container_of(x, struct hdmi_connector, base)
static void hdmi_phy_reset(struct hdmi *hdmi)
static void msm_hdmi_phy_reset(struct hdmi *hdmi)
{
unsigned int val;
......@@ -81,114 +81,54 @@ static int gpio_config(struct hdmi *hdmi, bool on)
{
struct device *dev = &hdmi->pdev->dev;
const struct hdmi_platform_config *config = hdmi->config;
int ret;
int ret, i;
if (on) {
if (config->ddc_clk_gpio != -1) {
ret = gpio_request(config->ddc_clk_gpio, "HDMI_DDC_CLK");
if (ret) {
dev_err(dev, "'%s'(%d) gpio_request failed: %d\n",
"HDMI_DDC_CLK", config->ddc_clk_gpio, ret);
goto error1;
}
gpio_set_value_cansleep(config->ddc_clk_gpio, 1);
}
if (config->ddc_data_gpio != -1) {
ret = gpio_request(config->ddc_data_gpio, "HDMI_DDC_DATA");
if (ret) {
dev_err(dev, "'%s'(%d) gpio_request failed: %d\n",
"HDMI_DDC_DATA", config->ddc_data_gpio, ret);
goto error2;
}
gpio_set_value_cansleep(config->ddc_data_gpio, 1);
}
ret = gpio_request(config->hpd_gpio, "HDMI_HPD");
if (ret) {
dev_err(dev, "'%s'(%d) gpio_request failed: %d\n",
"HDMI_HPD", config->hpd_gpio, ret);
goto error3;
}
gpio_direction_input(config->hpd_gpio);
gpio_set_value_cansleep(config->hpd_gpio, 1);
if (config->mux_en_gpio != -1) {
ret = gpio_request(config->mux_en_gpio, "HDMI_MUX_EN");
if (ret) {
dev_err(dev, "'%s'(%d) gpio_request failed: %d\n",
"HDMI_MUX_EN", config->mux_en_gpio, ret);
goto error4;
}
gpio_set_value_cansleep(config->mux_en_gpio, 1);
}
if (config->mux_sel_gpio != -1) {
ret = gpio_request(config->mux_sel_gpio, "HDMI_MUX_SEL");
if (ret) {
dev_err(dev, "'%s'(%d) gpio_request failed: %d\n",
"HDMI_MUX_SEL", config->mux_sel_gpio, ret);
goto error5;
for (i = 0; i < HDMI_MAX_NUM_GPIO; i++) {
struct hdmi_gpio_data gpio = config->gpios[i];
if (gpio.num != -1) {
ret = gpio_request(gpio.num, gpio.label);
if (ret) {
dev_err(dev,
"'%s'(%d) gpio_request failed: %d\n",
gpio.label, gpio.num, ret);
goto err;
}
if (gpio.output) {
gpio_direction_output(gpio.num,
gpio.value);
} else {
gpio_direction_input(gpio.num);
gpio_set_value_cansleep(gpio.num,
gpio.value);
}
}
gpio_set_value_cansleep(config->mux_sel_gpio, 0);
}
if (config->mux_lpm_gpio != -1) {
ret = gpio_request(config->mux_lpm_gpio,
"HDMI_MUX_LPM");
if (ret) {
dev_err(dev,
"'%s'(%d) gpio_request failed: %d\n",
"HDMI_MUX_LPM",
config->mux_lpm_gpio, ret);
goto error6;
}
gpio_set_value_cansleep(config->mux_lpm_gpio, 1);
}
DBG("gpio on");
} else {
if (config->ddc_clk_gpio != -1)
gpio_free(config->ddc_clk_gpio);
if (config->ddc_data_gpio != -1)
gpio_free(config->ddc_data_gpio);
for (i = 0; i < HDMI_MAX_NUM_GPIO; i++) {
struct hdmi_gpio_data gpio = config->gpios[i];
gpio_free(config->hpd_gpio);
if (gpio.output) {
int value = gpio.value ? 0 : 1;
if (config->mux_en_gpio != -1) {
gpio_set_value_cansleep(config->mux_en_gpio, 0);
gpio_free(config->mux_en_gpio);
}
gpio_set_value_cansleep(gpio.num, value);
}
if (config->mux_sel_gpio != -1) {
gpio_set_value_cansleep(config->mux_sel_gpio, 1);
gpio_free(config->mux_sel_gpio);
}
gpio_free(gpio.num);
};
if (config->mux_lpm_gpio != -1) {
gpio_set_value_cansleep(config->mux_lpm_gpio, 0);
gpio_free(config->mux_lpm_gpio);
}
DBG("gpio off");
}
return 0;
err:
while (i--)
gpio_free(config->gpios[i].num);
error6:
if (config->mux_sel_gpio != -1)
gpio_free(config->mux_sel_gpio);
error5:
if (config->mux_en_gpio != -1)
gpio_free(config->mux_en_gpio);
error4:
gpio_free(config->hpd_gpio);
error3:
if (config->ddc_data_gpio != -1)
gpio_free(config->ddc_data_gpio);
error2:
if (config->ddc_clk_gpio != -1)
gpio_free(config->ddc_clk_gpio);
error1:
return ret;
}
......@@ -239,9 +179,9 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector)
}
}
hdmi_set_mode(hdmi, false);
hdmi_phy_reset(hdmi);
hdmi_set_mode(hdmi, true);
msm_hdmi_set_mode(hdmi, false);
msm_hdmi_phy_reset(hdmi);
msm_hdmi_set_mode(hdmi, true);
hdmi_write(hdmi, REG_HDMI_USEC_REFTIMER, 0x0001001b);
......@@ -278,7 +218,7 @@ static void hdp_disable(struct hdmi_connector *hdmi_connector)
/* Disable HPD interrupt */
hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, 0);
hdmi_set_mode(hdmi, false);
msm_hdmi_set_mode(hdmi, false);
for (i = 0; i < config->hpd_clk_cnt; i++)
clk_disable_unprepare(hdmi->hpd_clks[i]);
......@@ -300,7 +240,7 @@ static void hdp_disable(struct hdmi_connector *hdmi_connector)
}
static void
hotplug_work(struct work_struct *work)
msm_hdmi_hotplug_work(struct work_struct *work)
{
struct hdmi_connector *hdmi_connector =
container_of(work, struct hdmi_connector, hpd_work);
......@@ -308,7 +248,7 @@ hotplug_work(struct work_struct *work)
drm_helper_hpd_irq_event(connector->dev);
}
void hdmi_connector_irq(struct drm_connector *connector)
void msm_hdmi_connector_irq(struct drm_connector *connector)
{
struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector);
struct hdmi *hdmi = hdmi_connector->hdmi;
......@@ -345,10 +285,13 @@ static enum drm_connector_status detect_reg(struct hdmi *hdmi)
connector_status_connected : connector_status_disconnected;
}
#define HPD_GPIO_INDEX 2
static enum drm_connector_status detect_gpio(struct hdmi *hdmi)
{
const struct hdmi_platform_config *config = hdmi->config;
return gpio_get_value(config->hpd_gpio) ?
struct hdmi_gpio_data hpd_gpio = config->gpios[HPD_GPIO_INDEX];
return gpio_get_value(hpd_gpio.num) ?
connector_status_connected :
connector_status_disconnected;
}
......@@ -358,9 +301,18 @@ static enum drm_connector_status hdmi_connector_detect(
{
struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector);
struct hdmi *hdmi = hdmi_connector->hdmi;
const struct hdmi_platform_config *config = hdmi->config;
struct hdmi_gpio_data hpd_gpio = config->gpios[HPD_GPIO_INDEX];
enum drm_connector_status stat_gpio, stat_reg;
int retry = 20;
/*
* some platforms may not have hpd gpio. Rely only on the status
* provided by REG_HDMI_HPD_INT_STATUS in this case.
*/
if (hpd_gpio.num == -1)
return detect_reg(hdmi);
do {
stat_gpio = detect_gpio(hdmi);
stat_reg = detect_reg(hdmi);
......@@ -395,7 +347,7 @@ static void hdmi_connector_destroy(struct drm_connector *connector)
kfree(hdmi_connector);
}
static int hdmi_connector_get_modes(struct drm_connector *connector)
static int msm_hdmi_connector_get_modes(struct drm_connector *connector)
{
struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector);
struct hdmi *hdmi = hdmi_connector->hdmi;
......@@ -421,7 +373,7 @@ static int hdmi_connector_get_modes(struct drm_connector *connector)
return ret;
}
static int hdmi_connector_mode_valid(struct drm_connector *connector,
static int msm_hdmi_connector_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector);
......@@ -451,7 +403,7 @@ static int hdmi_connector_mode_valid(struct drm_connector *connector,
}
static struct drm_encoder *
hdmi_connector_best_encoder(struct drm_connector *connector)
msm_hdmi_connector_best_encoder(struct drm_connector *connector)
{
struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector);
return hdmi_connector->hdmi->encoder;
......@@ -467,14 +419,14 @@ static const struct drm_connector_funcs hdmi_connector_funcs = {
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};
static const struct drm_connector_helper_funcs hdmi_connector_helper_funcs = {
.get_modes = hdmi_connector_get_modes,
.mode_valid = hdmi_connector_mode_valid,
.best_encoder = hdmi_connector_best_encoder,
static const struct drm_connector_helper_funcs msm_hdmi_connector_helper_funcs = {
.get_modes = msm_hdmi_connector_get_modes,
.mode_valid = msm_hdmi_connector_mode_valid,
.best_encoder = msm_hdmi_connector_best_encoder,
};
/* initialize connector */
struct drm_connector *hdmi_connector_init(struct hdmi *hdmi)
struct drm_connector *msm_hdmi_connector_init(struct hdmi *hdmi)
{
struct drm_connector *connector = NULL;
struct hdmi_connector *hdmi_connector;
......@@ -487,13 +439,13 @@ struct drm_connector *hdmi_connector_init(struct hdmi *hdmi)
}
hdmi_connector->hdmi = hdmi;
INIT_WORK(&hdmi_connector->hpd_work, hotplug_work);
INIT_WORK(&hdmi_connector->hpd_work, msm_hdmi_hotplug_work);
connector = &hdmi_connector->base;
drm_connector_init(hdmi->dev, connector, &hdmi_connector_funcs,
DRM_MODE_CONNECTOR_HDMIA);
drm_connector_helper_add(connector, &hdmi_connector_helper_funcs);
drm_connector_helper_add(connector, &msm_hdmi_connector_helper_funcs);
connector->polled = DRM_CONNECTOR_POLL_CONNECT |
DRM_CONNECTOR_POLL_DISCONNECT;
......
drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c
View file @ 912b330c
......@@ -84,7 +84,7 @@ struct hdmi_hdcp_ctrl {
bool max_dev_exceeded;
};
static int hdmi_ddc_read(struct hdmi *hdmi, u16 addr, u8 offset,
static int msm_hdmi_ddc_read(struct hdmi *hdmi, u16 addr, u8 offset,
u8 *data, u16 data_len)
{
int rc;
......@@ -122,7 +122,7 @@ static int hdmi_ddc_read(struct hdmi *hdmi, u16 addr, u8 offset,
#define HDCP_DDC_WRITE_MAX_BYTE_NUM 32
static int hdmi_ddc_write(struct hdmi *hdmi, u16 addr, u8 offset,
static int msm_hdmi_ddc_write(struct hdmi *hdmi, u16 addr, u8 offset,
u8 *data, u16 data_len)
{
int rc;
......@@ -162,7 +162,7 @@ static int hdmi_ddc_write(struct hdmi *hdmi, u16 addr, u8 offset,
return rc;
}
static int hdmi_hdcp_scm_wr(struct hdmi_hdcp_ctrl *hdcp_ctrl, u32 *preg,
static int msm_hdmi_hdcp_scm_wr(struct hdmi_hdcp_ctrl *hdcp_ctrl, u32 *preg,
u32 *pdata, u32 count)
{
struct hdmi *hdmi = hdcp_ctrl->hdmi;
......@@ -202,7 +202,7 @@ static int hdmi_hdcp_scm_wr(struct hdmi_hdcp_ctrl *hdcp_ctrl, u32 *preg,
return ret;
}
void hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl)
void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
struct hdmi *hdmi = hdcp_ctrl->hdmi;
u32 reg_val, hdcp_int_status;
......@@ -247,7 +247,7 @@ void hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl)
}
}
static int hdmi_hdcp_msleep(struct hdmi_hdcp_ctrl *hdcp_ctrl, u32 ms, u32 ev)
static int msm_hdmi_hdcp_msleep(struct hdmi_hdcp_ctrl *hdcp_ctrl, u32 ms, u32 ev)
{
int rc;
......@@ -264,7 +264,7 @@ static int hdmi_hdcp_msleep(struct hdmi_hdcp_ctrl *hdcp_ctrl, u32 ms, u32 ev)
return 0;
}
static int hdmi_hdcp_read_validate_aksv(struct hdmi_hdcp_ctrl *hdcp_ctrl)
static int msm_hdmi_hdcp_read_validate_aksv(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
struct hdmi *hdmi = hdcp_ctrl->hdmi;
......@@ -287,7 +287,7 @@ static int hdmi_hdcp_read_validate_aksv(struct hdmi_hdcp_ctrl *hdcp_ctrl)
return 0;
}
static int reset_hdcp_ddc_failures(struct hdmi_hdcp_ctrl *hdcp_ctrl)
static int msm_reset_hdcp_ddc_failures(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
struct hdmi *hdmi = hdcp_ctrl->hdmi;
u32 reg_val, failure, nack0;
......@@ -337,7 +337,7 @@ static int reset_hdcp_ddc_failures(struct hdmi_hdcp_ctrl *hdcp_ctrl)
reg_val |= HDMI_DDC_CTRL_SW_STATUS_RESET;
hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val);
rc = hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL);
reg_val &= ~HDMI_DDC_CTRL_SW_STATUS_RESET;
......@@ -350,7 +350,7 @@ static int reset_hdcp_ddc_failures(struct hdmi_hdcp_ctrl *hdcp_ctrl)
/* If previous msleep is aborted, skip this msleep */
if (!rc)
rc = hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL);
reg_val &= ~HDMI_DDC_CTRL_SOFT_RESET;
......@@ -362,7 +362,7 @@ static int reset_hdcp_ddc_failures(struct hdmi_hdcp_ctrl *hdcp_ctrl)
return rc;
}
static int hdmi_hdcp_hw_ddc_clean(struct hdmi_hdcp_ctrl *hdcp_ctrl)
static int msm_hdmi_hdcp_hw_ddc_clean(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
int rc;
u32 hdcp_ddc_status, ddc_hw_status;
......@@ -394,7 +394,7 @@ static int hdmi_hdcp_hw_ddc_clean(struct hdmi_hdcp_ctrl *hdcp_ctrl)
return -ETIMEDOUT;
}
rc = hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
if (rc)
return rc;
} while (1);
......@@ -402,7 +402,7 @@ static int hdmi_hdcp_hw_ddc_clean(struct hdmi_hdcp_ctrl *hdcp_ctrl)
return 0;
}
static void hdmi_hdcp_reauth_work(struct work_struct *work)
static void msm_hdmi_hdcp_reauth_work(struct work_struct *work)
{
struct hdmi_hdcp_ctrl *hdcp_ctrl = container_of(work,
struct hdmi_hdcp_ctrl, hdcp_reauth_work);
......@@ -430,7 +430,7 @@ static void hdmi_hdcp_reauth_work(struct work_struct *work)
HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE);
/* Wait to be clean on DDC HW engine */
if (hdmi_hdcp_hw_ddc_clean(hdcp_ctrl)) {
if (msm_hdmi_hdcp_hw_ddc_clean(hdcp_ctrl)) {
pr_info("%s: reauth work aborted\n", __func__);
return;
}
......@@ -461,7 +461,7 @@ static void hdmi_hdcp_reauth_work(struct work_struct *work)
queue_work(hdmi->workq, &hdcp_ctrl->hdcp_auth_work);
}
static int hdmi_hdcp_auth_prepare(struct hdmi_hdcp_ctrl *hdcp_ctrl)
static int msm_hdmi_hdcp_auth_prepare(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
struct hdmi *hdmi = hdcp_ctrl->hdmi;
u32 link0_status;
......@@ -470,7 +470,7 @@ static int hdmi_hdcp_auth_prepare(struct hdmi_hdcp_ctrl *hdcp_ctrl)
int rc;
if (!hdcp_ctrl->aksv_valid) {
rc = hdmi_hdcp_read_validate_aksv(hdcp_ctrl);
rc = msm_hdmi_hdcp_read_validate_aksv(hdcp_ctrl);
if (rc) {
pr_err("%s: ASKV validation failed\n", __func__);
hdcp_ctrl->hdcp_state = HDCP_STATE_NO_AKSV;
......@@ -538,12 +538,12 @@ static int hdmi_hdcp_auth_prepare(struct hdmi_hdcp_ctrl *hdcp_ctrl)
DBG("An not ready after enabling HDCP");
/* Clear any DDC failures from previous tries before enable HDCP*/
rc = reset_hdcp_ddc_failures(hdcp_ctrl);
rc = msm_reset_hdcp_ddc_failures(hdcp_ctrl);
return rc;
}
static void hdmi_hdcp_auth_fail(struct hdmi_hdcp_ctrl *hdcp_ctrl)
static void msm_hdmi_hdcp_auth_fail(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
struct hdmi *hdmi = hdcp_ctrl->hdmi;
u32 reg_val;
......@@ -561,7 +561,7 @@ static void hdmi_hdcp_auth_fail(struct hdmi_hdcp_ctrl *hdcp_ctrl)
queue_work(hdmi->workq, &hdcp_ctrl->hdcp_reauth_work);
}
static void hdmi_hdcp_auth_done(struct hdmi_hdcp_ctrl *hdcp_ctrl)
static void msm_hdmi_hdcp_auth_done(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
struct hdmi *hdmi = hdcp_ctrl->hdmi;
u32 reg_val;
......@@ -596,7 +596,7 @@ static void hdmi_hdcp_auth_done(struct hdmi_hdcp_ctrl *hdcp_ctrl)
* Write An and AKSV to sink
* Read BKSV from sink and write into HDCP engine
*/
static int hdmi_hdcp_wait_key_an_ready(struct hdmi_hdcp_ctrl *hdcp_ctrl)
static int msm_hdmi_hdcp_wait_key_an_ready(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
int rc;
struct hdmi *hdmi = hdcp_ctrl->hdmi;
......@@ -621,7 +621,7 @@ static int hdmi_hdcp_wait_key_an_ready(struct hdmi_hdcp_ctrl *hdcp_ctrl)
return -ETIMEDOUT;
}
rc = hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
if (rc)
return rc;
} while (1);
......@@ -643,7 +643,7 @@ static int hdmi_hdcp_wait_key_an_ready(struct hdmi_hdcp_ctrl *hdcp_ctrl)
return -ETIMEDOUT;
}
rc = hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
if (rc)
return rc;
} while (1);
......@@ -651,7 +651,7 @@ static int hdmi_hdcp_wait_key_an_ready(struct hdmi_hdcp_ctrl *hdcp_ctrl)
return 0;
}
static int hdmi_hdcp_send_aksv_an(struct hdmi_hdcp_ctrl *hdcp_ctrl)
static int msm_hdmi_hdcp_send_aksv_an(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
int rc = 0;
struct hdmi *hdmi = hdcp_ctrl->hdmi;
......@@ -676,7 +676,7 @@ static int hdmi_hdcp_send_aksv_an(struct hdmi_hdcp_ctrl *hdcp_ctrl)
aksv[4] = link0_aksv_1 & 0xFF;
/* Write An to offset 0x18 */
rc = hdmi_ddc_write(hdmi, HDCP_PORT_ADDR, 0x18, (u8 *)link0_an,
rc = msm_hdmi_ddc_write(hdmi, HDCP_PORT_ADDR, 0x18, (u8 *)link0_an,
(u16)sizeof(link0_an));
if (rc) {
pr_err("%s:An write failed\n", __func__);
......@@ -685,7 +685,7 @@ static int hdmi_hdcp_send_aksv_an(struct hdmi_hdcp_ctrl *hdcp_ctrl)
DBG("Link0-An=%08x%08x", link0_an[0], link0_an[1]);
/* Write AKSV to offset 0x10 */
rc = hdmi_ddc_write(hdmi, HDCP_PORT_ADDR, 0x10, aksv, 5);
rc = msm_hdmi_ddc_write(hdmi, HDCP_PORT_ADDR, 0x10, aksv, 5);
if (rc) {
pr_err("%s:AKSV write failed\n", __func__);
return rc;
......@@ -695,7 +695,7 @@ static int hdmi_hdcp_send_aksv_an(struct hdmi_hdcp_ctrl *hdcp_ctrl)
return 0;
}
static int hdmi_hdcp_recv_bksv(struct hdmi_hdcp_ctrl *hdcp_ctrl)
static int msm_hdmi_hdcp_recv_bksv(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
int rc = 0;
struct hdmi *hdmi = hdcp_ctrl->hdmi;
......@@ -703,7 +703,7 @@ static int hdmi_hdcp_recv_bksv(struct hdmi_hdcp_ctrl *hdcp_ctrl)
u32 reg[2], data[2];
/* Read BKSV at offset 0x00 */
rc = hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x00, bksv, 5);
rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x00, bksv, 5);
if (rc) {
pr_err("%s:BKSV read failed\n", __func__);
return rc;
......@@ -728,19 +728,19 @@ static int hdmi_hdcp_recv_bksv(struct hdmi_hdcp_ctrl *hdcp_ctrl)
data[0] = hdcp_ctrl->bksv_lsb;
reg[1] = REG_HDMI_HDCP_RCVPORT_DATA1;
data[1] = hdcp_ctrl->bksv_msb;
rc = hdmi_hdcp_scm_wr(hdcp_ctrl, reg, data, 2);
rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, reg, data, 2);
return rc;
}
static int hdmi_hdcp_recv_bcaps(struct hdmi_hdcp_ctrl *hdcp_ctrl)
static int msm_hdmi_hdcp_recv_bcaps(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
int rc = 0;
struct hdmi *hdmi = hdcp_ctrl->hdmi;
u32 reg, data;
u8 bcaps;
rc = hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x40, &bcaps, 1);
rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x40, &bcaps, 1);
if (rc) {
pr_err("%s:BCAPS read failed\n", __func__);
return rc;
......@@ -753,26 +753,26 @@ static int hdmi_hdcp_recv_bcaps(struct hdmi_hdcp_ctrl *hdcp_ctrl)
/* Write BCAPS to the hardware */
reg = REG_HDMI_HDCP_RCVPORT_DATA12;
data = (u32)bcaps;
rc = hdmi_hdcp_scm_wr(hdcp_ctrl, &reg, &data, 1);
rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, &reg, &data, 1);
return rc;
}
static int hdmi_hdcp_auth_part1_key_exchange(struct hdmi_hdcp_ctrl *hdcp_ctrl)
static int msm_hdmi_hdcp_auth_part1_key_exchange(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
struct hdmi *hdmi = hdcp_ctrl->hdmi;
unsigned long flags;
int rc;
/* Wait for AKSV key and An ready */
rc = hdmi_hdcp_wait_key_an_ready(hdcp_ctrl);
rc = msm_hdmi_hdcp_wait_key_an_ready(hdcp_ctrl);
if (rc) {
pr_err("%s: wait key and an ready failed\n", __func__);
return rc;
};
/* Read BCAPS and send to HDCP engine */
rc = hdmi_hdcp_recv_bcaps(hdcp_ctrl);
rc = msm_hdmi_hdcp_recv_bcaps(hdcp_ctrl);
if (rc) {
pr_err("%s: read bcaps error, abort\n", __func__);
return rc;
......@@ -785,14 +785,14 @@ static int hdmi_hdcp_auth_part1_key_exchange(struct hdmi_hdcp_ctrl *hdcp_ctrl)
hdmi_write(hdmi, REG_HDMI_HDCP_RCVPORT_DATA4, 0);
/* Send AKSV and An to sink */
rc = hdmi_hdcp_send_aksv_an(hdcp_ctrl);
rc = msm_hdmi_hdcp_send_aksv_an(hdcp_ctrl);
if (rc) {
pr_err("%s:An/Aksv write failed\n", __func__);
return rc;
}
/* Read BKSV and send to HDCP engine*/
rc = hdmi_hdcp_recv_bksv(hdcp_ctrl);
rc = msm_hdmi_hdcp_recv_bksv(hdcp_ctrl);
if (rc) {
pr_err("%s:BKSV Process failed\n", __func__);
return rc;
......@@ -812,7 +812,7 @@ static int hdmi_hdcp_auth_part1_key_exchange(struct hdmi_hdcp_ctrl *hdcp_ctrl)
}
/* read R0' from sink and pass it to HDCP engine */
static int hdmi_hdcp_auth_part1_recv_r0(struct hdmi_hdcp_ctrl *hdcp_ctrl)
static int msm_hdmi_hdcp_auth_part1_recv_r0(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
struct hdmi *hdmi = hdcp_ctrl->hdmi;
int rc = 0;
......@@ -822,12 +822,12 @@ static int hdmi_hdcp_auth_part1_recv_r0(struct hdmi_hdcp_ctrl *hdcp_ctrl)
* HDCP Compliance Test case 1A-01:
* Wait here at least 100ms before reading R0'
*/
rc = hdmi_hdcp_msleep(hdcp_ctrl, 125, AUTH_ABORT_EV);
rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 125, AUTH_ABORT_EV);
if (rc)
return rc;
/* Read R0' at offset 0x08 */
rc = hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x08, buf, 2);
rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x08, buf, 2);
if (rc) {
pr_err("%s:R0' read failed\n", __func__);
return rc;
......@@ -842,14 +842,14 @@ static int hdmi_hdcp_auth_part1_recv_r0(struct hdmi_hdcp_ctrl *hdcp_ctrl)
}
/* Wait for authenticating result: R0/R0' are matched or not */
static int hdmi_hdcp_auth_part1_verify_r0(struct hdmi_hdcp_ctrl *hdcp_ctrl)
static int msm_hdmi_hdcp_auth_part1_verify_r0(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
struct hdmi *hdmi = hdcp_ctrl->hdmi;
u32 link0_status;
int rc;
/* wait for hdcp irq, 10 sec should be long enough */
rc = hdmi_hdcp_msleep(hdcp_ctrl, 10000, AUTH_RESULT_RDY_EV);
rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 10000, AUTH_RESULT_RDY_EV);
if (!rc) {
pr_err("%s: Wait Auth IRQ timeout\n", __func__);
return -ETIMEDOUT;
......@@ -869,7 +869,7 @@ static int hdmi_hdcp_auth_part1_verify_r0(struct hdmi_hdcp_ctrl *hdcp_ctrl)
return 0;
}
static int hdmi_hdcp_recv_check_bstatus(struct hdmi_hdcp_ctrl *hdcp_ctrl,
static int msm_hdmi_hdcp_recv_check_bstatus(struct hdmi_hdcp_ctrl *hdcp_ctrl,
u16 *pbstatus)
{
int rc;
......@@ -880,7 +880,7 @@ static int hdmi_hdcp_recv_check_bstatus(struct hdmi_hdcp_ctrl *hdcp_ctrl,
u8 buf[2];
/* Read BSTATUS at offset 0x41 */
rc = hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x41, buf, 2);
rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x41, buf, 2);
if (rc) {
pr_err("%s: BSTATUS read failed\n", __func__);
goto error;
......@@ -936,7 +936,7 @@ static int hdmi_hdcp_recv_check_bstatus(struct hdmi_hdcp_ctrl *hdcp_ctrl,
return rc;
}
static int hdmi_hdcp_auth_part2_wait_ksv_fifo_ready(
static int msm_hdmi_hdcp_auth_part2_wait_ksv_fifo_ready(
struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
int rc;
......@@ -953,7 +953,7 @@ static int hdmi_hdcp_auth_part2_wait_ksv_fifo_ready(
timeout_count = 100;
do {
/* Read BCAPS at offset 0x40 */
rc = hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x40, &bcaps, 1);
rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x40, &bcaps, 1);
if (rc) {
pr_err("%s: BCAPS read failed\n", __func__);
return rc;
......@@ -968,12 +968,12 @@ static int hdmi_hdcp_auth_part2_wait_ksv_fifo_ready(
return -ETIMEDOUT;
}
rc = hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
if (rc)
return rc;
} while (1);
rc = hdmi_hdcp_recv_check_bstatus(hdcp_ctrl, &bstatus);
rc = msm_hdmi_hdcp_recv_check_bstatus(hdcp_ctrl, &bstatus);
if (rc) {
pr_err("%s: bstatus error\n", __func__);
return rc;
......@@ -982,7 +982,7 @@ static int hdmi_hdcp_auth_part2_wait_ksv_fifo_ready(
/* Write BSTATUS and BCAPS to HDCP registers */
reg = REG_HDMI_HDCP_RCVPORT_DATA12;
data = bcaps | (bstatus << 8);
rc = hdmi_hdcp_scm_wr(hdcp_ctrl, &reg, &data, 1);
rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, &reg, &data, 1);
if (rc) {
pr_err("%s: BSTATUS write failed\n", __func__);
return rc;
......@@ -997,7 +997,7 @@ static int hdmi_hdcp_auth_part2_wait_ksv_fifo_ready(
* transfer V' from sink to HDCP engine
* reset SHA engine
*/
static int hdmi_hdcp_transfer_v_h(struct hdmi_hdcp_ctrl *hdcp_ctrl)
static int msm_hdmi_hdcp_transfer_v_h(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
struct hdmi *hdmi = hdcp_ctrl->hdmi;
int rc = 0;
......@@ -1016,7 +1016,7 @@ static int hdmi_hdcp_transfer_v_h(struct hdmi_hdcp_ctrl *hdcp_ctrl)
for (i = 0; i < size; i++) {
rd = &reg_data[i];
rc = hdmi_ddc_read(hdmi, HDCP_PORT_ADDR,
rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR,
rd->off, (u8 *)&data[i], (u16)sizeof(data[i]));
if (rc) {
pr_err("%s: Read %s failed\n", __func__, rd->name);
......@@ -1027,13 +1027,13 @@ static int hdmi_hdcp_transfer_v_h(struct hdmi_hdcp_ctrl *hdcp_ctrl)
reg[i] = reg_data[i].reg_id;
}
rc = hdmi_hdcp_scm_wr(hdcp_ctrl, reg, data, size);
rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, reg, data, size);
error:
return rc;
}
static int hdmi_hdcp_recv_ksv_fifo(struct hdmi_hdcp_ctrl *hdcp_ctrl)
static int msm_hdmi_hdcp_recv_ksv_fifo(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
int rc;
struct hdmi *hdmi = hdcp_ctrl->hdmi;
......@@ -1041,7 +1041,7 @@ static int hdmi_hdcp_recv_ksv_fifo(struct hdmi_hdcp_ctrl *hdcp_ctrl)
ksv_bytes = 5 * hdcp_ctrl->dev_count;
rc = hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x43,
rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x43,
hdcp_ctrl->ksv_list, ksv_bytes);
if (rc)
pr_err("%s: KSV FIFO read failed\n", __func__);
......@@ -1049,7 +1049,7 @@ static int hdmi_hdcp_recv_ksv_fifo(struct hdmi_hdcp_ctrl *hdcp_ctrl)
return rc;
}
static int hdmi_hdcp_reset_sha_engine(struct hdmi_hdcp_ctrl *hdcp_ctrl)
static int msm_hdmi_hdcp_reset_sha_engine(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
u32 reg[2], data[2];
u32 rc = 0;
......@@ -1059,12 +1059,12 @@ static int hdmi_hdcp_reset_sha_engine(struct hdmi_hdcp_ctrl *hdcp_ctrl)
reg[1] = REG_HDMI_HDCP_SHA_CTRL;
data[1] = HDCP_REG_DISABLE;
rc = hdmi_hdcp_scm_wr(hdcp_ctrl, reg, data, 2);
rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, reg, data, 2);
return rc;
}
static int hdmi_hdcp_auth_part2_recv_ksv_fifo(
static int msm_hdmi_hdcp_auth_part2_recv_ksv_fifo(
struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
int rc;
......@@ -1081,7 +1081,7 @@ static int hdmi_hdcp_auth_part2_recv_ksv_fifo(
*/
timeout_count = 100;
do {
rc = hdmi_hdcp_recv_ksv_fifo(hdcp_ctrl);
rc = msm_hdmi_hdcp_recv_ksv_fifo(hdcp_ctrl);
if (!rc)
break;
......@@ -1091,19 +1091,19 @@ static int hdmi_hdcp_auth_part2_recv_ksv_fifo(
return -ETIMEDOUT;
}
rc = hdmi_hdcp_msleep(hdcp_ctrl, 25, AUTH_ABORT_EV);
rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 25, AUTH_ABORT_EV);
if (rc)
return rc;
} while (1);
rc = hdmi_hdcp_transfer_v_h(hdcp_ctrl);
rc = msm_hdmi_hdcp_transfer_v_h(hdcp_ctrl);
if (rc) {
pr_err("%s: transfer V failed\n", __func__);
return rc;
}
/* reset SHA engine before write ksv fifo */
rc = hdmi_hdcp_reset_sha_engine(hdcp_ctrl);
rc = msm_hdmi_hdcp_reset_sha_engine(hdcp_ctrl);
if (rc) {
pr_err("%s: fail to reset sha engine\n", __func__);
return rc;
......@@ -1120,7 +1120,7 @@ static int hdmi_hdcp_auth_part2_recv_ksv_fifo(
* If the last byte is written, we need to poll for
* HDCP_SHA_COMP_DONE to wait until HW finish
*/
static int hdmi_hdcp_write_ksv_fifo(struct hdmi_hdcp_ctrl *hdcp_ctrl)
static int msm_hdmi_hdcp_write_ksv_fifo(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
int i;
struct hdmi *hdmi = hdcp_ctrl->hdmi;
......@@ -1169,7 +1169,7 @@ static int hdmi_hdcp_write_ksv_fifo(struct hdmi_hdcp_ctrl *hdcp_ctrl)
reg = REG_HDMI_HDCP_SHA_DATA;
data = reg_val;
rc = hdmi_hdcp_scm_wr(hdcp_ctrl, &reg, &data, 1);
rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, &reg, &data, 1);
if (rc)
return rc;
......@@ -1184,7 +1184,7 @@ static int hdmi_hdcp_write_ksv_fifo(struct hdmi_hdcp_ctrl *hdcp_ctrl)
}
/* write ksv fifo into HDCP engine */
static int hdmi_hdcp_auth_part2_write_ksv_fifo(
static int msm_hdmi_hdcp_auth_part2_write_ksv_fifo(
struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
int rc;
......@@ -1193,7 +1193,7 @@ static int hdmi_hdcp_auth_part2_write_ksv_fifo(
hdcp_ctrl->ksv_fifo_w_index = 0;
timeout_count = 100;
do {
rc = hdmi_hdcp_write_ksv_fifo(hdcp_ctrl);
rc = msm_hdmi_hdcp_write_ksv_fifo(hdcp_ctrl);
if (!rc)
break;
......@@ -1206,7 +1206,7 @@ static int hdmi_hdcp_auth_part2_write_ksv_fifo(
return -ETIMEDOUT;
}
rc = hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
if (rc)
return rc;
} while (1);
......@@ -1214,7 +1214,7 @@ static int hdmi_hdcp_auth_part2_write_ksv_fifo(
return 0;
}
static int hdmi_hdcp_auth_part2_check_v_match(struct hdmi_hdcp_ctrl *hdcp_ctrl)
static int msm_hdmi_hdcp_auth_part2_check_v_match(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
int rc = 0;
struct hdmi *hdmi = hdcp_ctrl->hdmi;
......@@ -1232,7 +1232,7 @@ static int hdmi_hdcp_auth_part2_check_v_match(struct hdmi_hdcp_ctrl *hdcp_ctrl)
return -ETIMEDOUT;
}
rc = hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV);
if (rc)
return rc;
} while (1);
......@@ -1240,32 +1240,32 @@ static int hdmi_hdcp_auth_part2_check_v_match(struct hdmi_hdcp_ctrl *hdcp_ctrl)
return 0;
}
static void hdmi_hdcp_auth_work(struct work_struct *work)
static void msm_hdmi_hdcp_auth_work(struct work_struct *work)
{
struct hdmi_hdcp_ctrl *hdcp_ctrl = container_of(work,
struct hdmi_hdcp_ctrl, hdcp_auth_work);
int rc;
rc = hdmi_hdcp_auth_prepare(hdcp_ctrl);
rc = msm_hdmi_hdcp_auth_prepare(hdcp_ctrl);
if (rc) {
pr_err("%s: auth prepare failed %d\n", __func__, rc);
goto end;
}
/* HDCP PartI */
rc = hdmi_hdcp_auth_part1_key_exchange(hdcp_ctrl);
rc = msm_hdmi_hdcp_auth_part1_key_exchange(hdcp_ctrl);
if (rc) {
pr_err("%s: key exchange failed %d\n", __func__, rc);
goto end;
}
rc = hdmi_hdcp_auth_part1_recv_r0(hdcp_ctrl);
rc = msm_hdmi_hdcp_auth_part1_recv_r0(hdcp_ctrl);
if (rc) {
pr_err("%s: receive r0 failed %d\n", __func__, rc);
goto end;
}
rc = hdmi_hdcp_auth_part1_verify_r0(hdcp_ctrl);
rc = msm_hdmi_hdcp_auth_part1_verify_r0(hdcp_ctrl);
if (rc) {
pr_err("%s: verify r0 failed %d\n", __func__, rc);
goto end;
......@@ -1275,25 +1275,25 @@ static void hdmi_hdcp_auth_work(struct work_struct *work)
goto end;
/* HDCP PartII */
rc = hdmi_hdcp_auth_part2_wait_ksv_fifo_ready(hdcp_ctrl);
rc = msm_hdmi_hdcp_auth_part2_wait_ksv_fifo_ready(hdcp_ctrl);
if (rc) {
pr_err("%s: wait ksv fifo ready failed %d\n", __func__, rc);
goto end;
}
rc = hdmi_hdcp_auth_part2_recv_ksv_fifo(hdcp_ctrl);
rc = msm_hdmi_hdcp_auth_part2_recv_ksv_fifo(hdcp_ctrl);
if (rc) {
pr_err("%s: recv ksv fifo failed %d\n", __func__, rc);
goto end;
}
rc = hdmi_hdcp_auth_part2_write_ksv_fifo(hdcp_ctrl);
rc = msm_hdmi_hdcp_auth_part2_write_ksv_fifo(hdcp_ctrl);
if (rc) {
pr_err("%s: write ksv fifo failed %d\n", __func__, rc);
goto end;
}
rc = hdmi_hdcp_auth_part2_check_v_match(hdcp_ctrl);
rc = msm_hdmi_hdcp_auth_part2_check_v_match(hdcp_ctrl);
if (rc)
pr_err("%s: check v match failed %d\n", __func__, rc);
......@@ -1304,13 +1304,13 @@ static void hdmi_hdcp_auth_work(struct work_struct *work)
pr_info("%s: hdcp is not supported\n", __func__);
} else if (rc) {
pr_err("%s: hdcp authentication failed\n", __func__);
hdmi_hdcp_auth_fail(hdcp_ctrl);
msm_hdmi_hdcp_auth_fail(hdcp_ctrl);
} else {
hdmi_hdcp_auth_done(hdcp_ctrl);
msm_hdmi_hdcp_auth_done(hdcp_ctrl);
}
}
void hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl)
void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
struct hdmi *hdmi = hdcp_ctrl->hdmi;
u32 reg_val;
......@@ -1335,7 +1335,7 @@ void hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl)
queue_work(hdmi->workq, &hdcp_ctrl->hdcp_auth_work);
}
void hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl)
void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl)
{
struct hdmi *hdmi = hdcp_ctrl->hdmi;
unsigned long flags;
......@@ -1399,7 +1399,7 @@ void hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl)
DBG("HDCP: Off");
}
struct hdmi_hdcp_ctrl *hdmi_hdcp_init(struct hdmi *hdmi)
struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi)
{
struct hdmi_hdcp_ctrl *hdcp_ctrl = NULL;
......@@ -1413,8 +1413,8 @@ struct hdmi_hdcp_ctrl *hdmi_hdcp_init(struct hdmi *hdmi)
if (!hdcp_ctrl)
return ERR_PTR(-ENOMEM);
INIT_WORK(&hdcp_ctrl->hdcp_auth_work, hdmi_hdcp_auth_work);
INIT_WORK(&hdcp_ctrl->hdcp_reauth_work, hdmi_hdcp_reauth_work);
INIT_WORK(&hdcp_ctrl->hdcp_auth_work, msm_hdmi_hdcp_auth_work);
INIT_WORK(&hdcp_ctrl->hdcp_reauth_work, msm_hdmi_hdcp_reauth_work);
init_waitqueue_head(&hdcp_ctrl->auth_event_queue);
hdcp_ctrl->hdmi = hdmi;
hdcp_ctrl->hdcp_state = HDCP_STATE_INACTIVE;
......@@ -1428,7 +1428,7 @@ struct hdmi_hdcp_ctrl *hdmi_hdcp_init(struct hdmi *hdmi)
return hdcp_ctrl;
}
void hdmi_hdcp_destroy(struct hdmi *hdmi)
void msm_hdmi_hdcp_destroy(struct hdmi *hdmi)
{
if (hdmi && hdmi->hdcp_ctrl) {
kfree(hdmi->hdcp_ctrl);
......
drivers/gpu/drm/msm/hdmi/hdmi_i2c.c
View file @ 912b330c
......@@ -97,7 +97,7 @@ static bool sw_done(struct hdmi_i2c_adapter *hdmi_i2c)
return hdmi_i2c->sw_done;
}
static int hdmi_i2c_xfer(struct i2c_adapter *i2c,
static int msm_hdmi_i2c_xfer(struct i2c_adapter *i2c,
struct i2c_msg *msgs, int num)
{
struct hdmi_i2c_adapter *hdmi_i2c = to_hdmi_i2c_adapter(i2c);
......@@ -216,17 +216,17 @@ static int hdmi_i2c_xfer(struct i2c_adapter *i2c,
return i;
}
static u32 hdmi_i2c_func(struct i2c_adapter *adapter)
static u32 msm_hdmi_i2c_func(struct i2c_adapter *adapter)
{
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}
static const struct i2c_algorithm hdmi_i2c_algorithm = {
.master_xfer = hdmi_i2c_xfer,
.functionality = hdmi_i2c_func,
static const struct i2c_algorithm msm_hdmi_i2c_algorithm = {
.master_xfer = msm_hdmi_i2c_xfer,
.functionality = msm_hdmi_i2c_func,
};
void hdmi_i2c_irq(struct i2c_adapter *i2c)
void msm_hdmi_i2c_irq(struct i2c_adapter *i2c)
{
struct hdmi_i2c_adapter *hdmi_i2c = to_hdmi_i2c_adapter(i2c);
......@@ -234,14 +234,14 @@ void hdmi_i2c_irq(struct i2c_adapter *i2c)
wake_up_all(&hdmi_i2c->ddc_event);
}
void hdmi_i2c_destroy(struct i2c_adapter *i2c)
void msm_hdmi_i2c_destroy(struct i2c_adapter *i2c)
{
struct hdmi_i2c_adapter *hdmi_i2c = to_hdmi_i2c_adapter(i2c);
i2c_del_adapter(i2c);
kfree(hdmi_i2c);
}
struct i2c_adapter *hdmi_i2c_init(struct hdmi *hdmi)
struct i2c_adapter *msm_hdmi_i2c_init(struct hdmi *hdmi)
{
struct drm_device *dev = hdmi->dev;
struct hdmi_i2c_adapter *hdmi_i2c;
......@@ -264,7 +264,7 @@ struct i2c_adapter *hdmi_i2c_init(struct hdmi *hdmi)
i2c->class = I2C_CLASS_DDC;
snprintf(i2c->name, sizeof(i2c->name), "msm hdmi i2c");
i2c->dev.parent = &hdmi->pdev->dev;
i2c->algo = &hdmi_i2c_algorithm;
i2c->algo = &msm_hdmi_i2c_algorithm;
ret = i2c_add_adapter(i2c);
if (ret) {
......@@ -276,6 +276,6 @@ struct i2c_adapter *hdmi_i2c_init(struct hdmi *hdmi)
fail:
if (i2c)
hdmi_i2c_destroy(i2c);
msm_hdmi_i2c_destroy(i2c);
return ERR_PTR(ret);
}
drivers/gpu/drm/msm/hdmi/hdmi_phy.c 0 → 100644
View file @ 912b330c
/*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/of_device.h>
#include "hdmi.h"
static int msm_hdmi_phy_resource_init(struct hdmi_phy *phy)
{
struct hdmi_phy_cfg *cfg = phy->cfg;
struct device *dev = &phy->pdev->dev;
int i, ret;
phy->regs = devm_kzalloc(dev, sizeof(phy->regs[0]) * cfg->num_regs,
GFP_KERNEL);
if (!phy->regs)
return -ENOMEM;
phy->clks = devm_kzalloc(dev, sizeof(phy->clks[0]) * cfg->num_clks,
GFP_KERNEL);
if (!phy->clks)
return -ENOMEM;
for (i = 0; i < cfg->num_regs; i++) {
struct regulator *reg;
reg = devm_regulator_get(dev, cfg->reg_names[i]);
if (IS_ERR(reg)) {
ret = PTR_ERR(reg);
dev_err(dev, "failed to get phy regulator: %s (%d)\n",
cfg->reg_names[i], ret);
return ret;
}
phy->regs[i] = reg;
}
for (i = 0; i < cfg->num_clks; i++) {
struct clk *clk;
clk = devm_clk_get(dev, cfg->clk_names[i]);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
dev_err(dev, "failed to get phy clock: %s (%d)\n",
cfg->clk_names[i], ret);
return ret;
}
phy->clks[i] = clk;
}
return 0;
}
int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy)
{
struct hdmi_phy_cfg *cfg = phy->cfg;
struct device *dev = &phy->pdev->dev;
int i, ret = 0;
pm_runtime_get_sync(dev);
for (i = 0; i < cfg->num_regs; i++) {
ret = regulator_enable(phy->regs[i]);
if (ret)
dev_err(dev, "failed to enable regulator: %s (%d)\n",
cfg->reg_names[i], ret);
}
for (i = 0; i < cfg->num_clks; i++) {
ret = clk_prepare_enable(phy->clks[i]);
if (ret)
dev_err(dev, "failed to enable clock: %s (%d)\n",
cfg->clk_names[i], ret);
}
return ret;
}
void msm_hdmi_phy_resource_disable(struct hdmi_phy *phy)
{
struct hdmi_phy_cfg *cfg = phy->cfg;
struct device *dev = &phy->pdev->dev;
int i;
for (i = cfg->num_clks - 1; i >= 0; i--)
clk_disable_unprepare(phy->clks[i]);
for (i = cfg->num_regs - 1; i >= 0; i--)
regulator_disable(phy->regs[i]);
pm_runtime_put_sync(dev);
}
void msm_hdmi_phy_powerup(struct hdmi_phy *phy, unsigned long int pixclock)
{
if (!phy || !phy->cfg->powerup)
return;
phy->cfg->powerup(phy, pixclock);
}
void msm_hdmi_phy_powerdown(struct hdmi_phy *phy)
{
if (!phy || !phy->cfg->powerdown)
return;
phy->cfg->powerdown(phy);
}
static int msm_hdmi_phy_pll_init(struct platform_device *pdev,
enum hdmi_phy_type type)
{
int ret;
switch (type) {
case MSM_HDMI_PHY_8960:
ret = msm_hdmi_pll_8960_init(pdev);
break;
case MSM_HDMI_PHY_8996:
ret = msm_hdmi_pll_8996_init(pdev);
break;
/*
* we don't have PLL support for these, don't report an error for now
*/
case MSM_HDMI_PHY_8x60:
case MSM_HDMI_PHY_8x74:
default:
ret = 0;
break;
}
return ret;
}
static int msm_hdmi_phy_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct hdmi_phy *phy;
int ret;
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
if (!phy)
return -ENODEV;
phy->cfg = (struct hdmi_phy_cfg *)of_device_get_match_data(dev);
if (!phy->cfg)
return -ENODEV;
phy->mmio = msm_ioremap(pdev, "hdmi_phy", "HDMI_PHY");
if (IS_ERR(phy->mmio)) {
dev_err(dev, "%s: failed to map phy base\n", __func__);
return -ENOMEM;
}
phy->pdev = pdev;
ret = msm_hdmi_phy_resource_init(phy);
if (ret)
return ret;
pm_runtime_enable(&pdev->dev);
ret = msm_hdmi_phy_resource_enable(phy);
if (ret)
return ret;
ret = msm_hdmi_phy_pll_init(pdev, phy->cfg->type);
if (ret) {
dev_err(dev, "couldn't init PLL\n");
msm_hdmi_phy_resource_disable(phy);
return ret;
}
msm_hdmi_phy_resource_disable(phy);
platform_set_drvdata(pdev, phy);
return 0;
}
static int msm_hdmi_phy_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
return 0;
}
static const struct of_device_id msm_hdmi_phy_dt_match[] = {
{ .compatible = "qcom,hdmi-phy-8660",
.data = &msm_hdmi_phy_8x60_cfg },
{ .compatible = "qcom,hdmi-phy-8960",
.data = &msm_hdmi_phy_8960_cfg },
{ .compatible = "qcom,hdmi-phy-8974",
.data = &msm_hdmi_phy_8x74_cfg },
{ .compatible = "qcom,hdmi-phy-8084",
.data = &msm_hdmi_phy_8x74_cfg },
{ .compatible = "qcom,hdmi-phy-8996",
.data = &msm_hdmi_phy_8996_cfg },
{}
};
static struct platform_driver msm_hdmi_phy_platform_driver = {
.probe = msm_hdmi_phy_probe,
.remove = msm_hdmi_phy_remove,
.driver = {
.name = "msm_hdmi_phy",
.of_match_table = msm_hdmi_phy_dt_match,
},
};
void __init msm_hdmi_phy_driver_register(void)
{
platform_driver_register(&msm_hdmi_phy_platform_driver);
}
void __exit msm_hdmi_phy_driver_unregister(void)
{
platform_driver_unregister(&msm_hdmi_phy_platform_driver);
}
drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c
View file @ 912b330c
......@@ -15,495 +15,48 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifdef CONFIG_COMMON_CLK
#include <linux/clk.h>
#include <linux/clk-provider.h>
#endif
#include "hdmi.h"
struct hdmi_phy_8960 {
struct hdmi_phy base;
struct hdmi *hdmi;
#ifdef CONFIG_COMMON_CLK
struct clk_hw pll_hw;
struct clk *pll;
unsigned long pixclk;
#endif
};
#define to_hdmi_phy_8960(x) container_of(x, struct hdmi_phy_8960, base)
#ifdef CONFIG_COMMON_CLK
#define clk_to_phy(x) container_of(x, struct hdmi_phy_8960, pll_hw)
/*
* HDMI PLL:
*
* To get the parent clock setup properly, we need to plug in hdmi pll
* configuration into common-clock-framework.
*/
struct pll_rate {
unsigned long rate;
struct {
uint32_t val;
uint32_t reg;
} conf[32];
};
/* NOTE: keep sorted highest freq to lowest: */
static const struct pll_rate freqtbl[] = {
{ 154000000, {
{ 0x08, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
{ 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
{ 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
{ 0x03, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
{ 0x0d, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
{ 0x4d, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
{ 0x5e, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
{ 0x42, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
{ 0, 0 } }
},
/* 1080p60/1080p50 case */
{ 148500000, {
{ 0x02, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
{ 0x02, REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG },
{ 0x01, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
{ 0x33, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
{ 0x2c, REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG },
{ 0x06, REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG },
{ 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
{ 0x76, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
{ 0x01, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
{ 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
{ 0xc0, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
{ 0x9a, REG_HDMI_8960_PHY_PLL_SSC_CFG0 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG1 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG2 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG3 },
{ 0x10, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 },
{ 0x1a, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 },
{ 0x0d, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 },
{ 0xe6, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
{ 0x33, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 },
{ 0, 0 } }
},
{ 108000000, {
{ 0x08, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
{ 0x21, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
{ 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
{ 0x1c, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
{ 0x49, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
{ 0x49, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
{ 0, 0 } }
},
/* 720p60/720p50/1080i60/1080i50/1080p24/1080p30/1080p25 */
{ 74250000, {
{ 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
{ 0x12, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
{ 0x01, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
{ 0x33, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
{ 0x76, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
{ 0xe6, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
{ 0, 0 } }
},
{ 74176000, {
{ 0x18, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
{ 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
{ 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
{ 0xe5, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
{ 0x0c, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
{ 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
{ 0x7d, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
{ 0xbc, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
{ 0, 0 } }
},
{ 65000000, {
{ 0x18, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
{ 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
{ 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
{ 0x8a, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
{ 0x0b, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
{ 0x4b, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
{ 0x7b, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
{ 0x09, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
{ 0, 0 } }
},
/* 480p60/480i60 */
{ 27030000, {
{ 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
{ 0x38, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
{ 0x02, REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG },
{ 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
{ 0xff, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
{ 0x4e, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
{ 0xd7, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
{ 0x03, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
{ 0x2a, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
{ 0x03, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
{ 0x33, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 },
{ 0, 0 } }
},
/* 576p50/576i50 */
{ 27000000, {
{ 0x32, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
{ 0x02, REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG },
{ 0x01, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
{ 0x33, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
{ 0x2c, REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG },
{ 0x06, REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG },
{ 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
{ 0x7b, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
{ 0x01, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
{ 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
{ 0xc0, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
{ 0x9a, REG_HDMI_8960_PHY_PLL_SSC_CFG0 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG1 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG2 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG3 },
{ 0x10, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 },
{ 0x1a, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 },
{ 0x0d, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 },
{ 0x2a, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
{ 0x03, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
{ 0x33, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 },
{ 0, 0 } }
},
/* 640x480p60 */
{ 25200000, {
{ 0x32, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
{ 0x02, REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG },
{ 0x01, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
{ 0x33, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
{ 0x2c, REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG },
{ 0x06, REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG },
{ 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
{ 0x77, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
{ 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
{ 0xc0, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
{ 0x9a, REG_HDMI_8960_PHY_PLL_SSC_CFG0 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG1 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG2 },
{ 0x20, REG_HDMI_8960_PHY_PLL_SSC_CFG3 },
{ 0x10, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 },
{ 0x1a, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 },
{ 0x0d, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 },
{ 0xf4, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
{ 0x33, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 },
{ 0, 0 } }
},
};
static int hdmi_pll_enable(struct clk_hw *hw)
{
struct hdmi_phy_8960 *phy_8960 = clk_to_phy(hw);
struct hdmi *hdmi = phy_8960->hdmi;
int timeout_count, pll_lock_retry = 10;
unsigned int val;
DBG("");
/* Assert PLL S/W reset */
hdmi_write(hdmi, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x8d);
hdmi_write(hdmi, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0, 0x10);
hdmi_write(hdmi, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1, 0x1a);
/* Wait for a short time before de-asserting
* to allow the hardware to complete its job.
* This much of delay should be fine for hardware
* to assert and de-assert.
*/
udelay(10);
/* De-assert PLL S/W reset */
hdmi_write(hdmi, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x0d);
val = hdmi_read(hdmi, REG_HDMI_8960_PHY_REG12);
val |= HDMI_8960_PHY_REG12_SW_RESET;
/* Assert PHY S/W reset */
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG12, val);
val &= ~HDMI_8960_PHY_REG12_SW_RESET;
/* Wait for a short time before de-asserting
to allow the hardware to complete its job.
This much of delay should be fine for hardware
to assert and de-assert. */
udelay(10);
/* De-assert PHY S/W reset */
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG12, val);
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG2, 0x3f);
val = hdmi_read(hdmi, REG_HDMI_8960_PHY_REG12);
val |= HDMI_8960_PHY_REG12_PWRDN_B;
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG12, val);
/* Wait 10 us for enabling global power for PHY */
mb();
udelay(10);
val = hdmi_read(hdmi, REG_HDMI_8960_PHY_PLL_PWRDN_B);
val |= HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B;
val &= ~HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL;
hdmi_write(hdmi, REG_HDMI_8960_PHY_PLL_PWRDN_B, val);
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG2, 0x80);
timeout_count = 1000;
while (--pll_lock_retry > 0) {
/* are we there yet? */
val = hdmi_read(hdmi, REG_HDMI_8960_PHY_PLL_STATUS0);
if (val & HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK)
break;
udelay(1);
if (--timeout_count > 0)
continue;
/*
* PLL has still not locked.
* Do a software reset and try again
* Assert PLL S/W reset first
*/
hdmi_write(hdmi, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x8d);
udelay(10);
hdmi_write(hdmi, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x0d);
/*
* Wait for a short duration for the PLL calibration
* before checking if the PLL gets locked
*/
udelay(350);
timeout_count = 1000;
}
return 0;
}
static void hdmi_pll_disable(struct clk_hw *hw)
{
struct hdmi_phy_8960 *phy_8960 = clk_to_phy(hw);
struct hdmi *hdmi = phy_8960->hdmi;
unsigned int val;
DBG("");
val = hdmi_read(hdmi, REG_HDMI_8960_PHY_REG12);
val &= ~HDMI_8960_PHY_REG12_PWRDN_B;
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG12, val);
val = hdmi_read(hdmi, REG_HDMI_8960_PHY_PLL_PWRDN_B);
val |= HDMI_8960_PHY_REG12_SW_RESET;
val &= ~HDMI_8960_PHY_REG12_PWRDN_B;
hdmi_write(hdmi, REG_HDMI_8960_PHY_PLL_PWRDN_B, val);
/* Make sure HDMI PHY/PLL are powered down */
mb();
}
static const struct pll_rate *find_rate(unsigned long rate)
{
int i;
for (i = 1; i < ARRAY_SIZE(freqtbl); i++)
if (rate > freqtbl[i].rate)
return &freqtbl[i-1];
return &freqtbl[i-1];
}
static unsigned long hdmi_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct hdmi_phy_8960 *phy_8960 = clk_to_phy(hw);
return phy_8960->pixclk;
}
static long hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
const struct pll_rate *pll_rate = find_rate(rate);
return pll_rate->rate;
}
static int hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct hdmi_phy_8960 *phy_8960 = clk_to_phy(hw);
struct hdmi *hdmi = phy_8960->hdmi;
const struct pll_rate *pll_rate = find_rate(rate);
int i;
DBG("rate=%lu", rate);
for (i = 0; pll_rate->conf[i].reg; i++)
hdmi_write(hdmi, pll_rate->conf[i].reg, pll_rate->conf[i].val);
phy_8960->pixclk = rate;
return 0;
}
static const struct clk_ops hdmi_pll_ops = {
.enable = hdmi_pll_enable,
.disable = hdmi_pll_disable,
.recalc_rate = hdmi_pll_recalc_rate,
.round_rate = hdmi_pll_round_rate,
.set_rate = hdmi_pll_set_rate,
};
static const char *hdmi_pll_parents[] = {
"pxo",
};
static struct clk_init_data pll_init = {
.name = "hdmi_pll",
.ops = &hdmi_pll_ops,
.parent_names = hdmi_pll_parents,
.num_parents = ARRAY_SIZE(hdmi_pll_parents),
};
#endif
/*
* HDMI Phy:
*/
static void hdmi_phy_8960_destroy(struct hdmi_phy *phy)
{
struct hdmi_phy_8960 *phy_8960 = to_hdmi_phy_8960(phy);
kfree(phy_8960);
}
static void hdmi_phy_8960_powerup(struct hdmi_phy *phy,
unsigned long int pixclock)
unsigned long int pixclock)
{
struct hdmi_phy_8960 *phy_8960 = to_hdmi_phy_8960(phy);
struct hdmi *hdmi = phy_8960->hdmi;
DBG("pixclock: %lu", pixclock);
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG2, 0x00);
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG0, 0x1b);
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG1, 0xf2);
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG4, 0x00);
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG5, 0x00);
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG6, 0x00);
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG7, 0x00);
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG8, 0x00);
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG9, 0x00);
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG10, 0x00);
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG11, 0x00);
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG3, 0x20);
hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG2, 0x00);
hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG0, 0x1b);
hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG1, 0xf2);
hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG4, 0x00);
hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG5, 0x00);
hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG6, 0x00);
hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG7, 0x00);
hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG8, 0x00);
hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG9, 0x00);
hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG10, 0x00);
hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG11, 0x00);
hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG3, 0x20);
}
static void hdmi_phy_8960_powerdown(struct hdmi_phy *phy)
{
struct hdmi_phy_8960 *phy_8960 = to_hdmi_phy_8960(phy);
struct hdmi *hdmi = phy_8960->hdmi;
DBG("");
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG2, 0x7f);
hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG2, 0x7f);
}
static const struct hdmi_phy_funcs hdmi_phy_8960_funcs = {
.destroy = hdmi_phy_8960_destroy,
.powerup = hdmi_phy_8960_powerup,
.powerdown = hdmi_phy_8960_powerdown,
static const char * const hdmi_phy_8960_reg_names[] = {
"core-vdda",
};
struct hdmi_phy *hdmi_phy_8960_init(struct hdmi *hdmi)
{
struct hdmi_phy_8960 *phy_8960;
struct hdmi_phy *phy = NULL;
int ret;
#ifdef CONFIG_COMMON_CLK
int i;
/* sanity check: */
for (i = 0; i < (ARRAY_SIZE(freqtbl) - 1); i++)
if (WARN_ON(freqtbl[i].rate < freqtbl[i+1].rate))
return ERR_PTR(-EINVAL);
#endif
phy_8960 = kzalloc(sizeof(*phy_8960), GFP_KERNEL);
if (!phy_8960) {
ret = -ENOMEM;
goto fail;
}
phy = &phy_8960->base;
phy->funcs = &hdmi_phy_8960_funcs;
phy_8960->hdmi = hdmi;
#ifdef CONFIG_COMMON_CLK
phy_8960->pll_hw.init = &pll_init;
phy_8960->pll = devm_clk_register(&hdmi->pdev->dev, &phy_8960->pll_hw);
if (IS_ERR(phy_8960->pll)) {
ret = PTR_ERR(phy_8960->pll);
phy_8960->pll = NULL;
goto fail;
}
#endif
return phy;
static const char * const hdmi_phy_8960_clk_names[] = {
"slave_iface_clk",
};
fail:
if (phy)
hdmi_phy_8960_destroy(phy);
return ERR_PTR(ret);
}
const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg = {
.type = MSM_HDMI_PHY_8960,
.powerup = hdmi_phy_8960_powerup,
.powerdown = hdmi_phy_8960_powerdown,
.reg_names = hdmi_phy_8960_reg_names,
.num_regs = ARRAY_SIZE(hdmi_phy_8960_reg_names),
.clk_names = hdmi_phy_8960_clk_names,
.num_clks = ARRAY_SIZE(hdmi_phy_8960_clk_names),
};
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 0 → 100644
View file @ 912b330c
/*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/clk-provider.h>
#include "hdmi.h"
#define HDMI_VCO_MAX_FREQ 12000000000UL
#define HDMI_VCO_MIN_FREQ 8000000000UL
#define HDMI_PCLK_MAX_FREQ 600000000
#define HDMI_PCLK_MIN_FREQ 25000000
#define HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD 3400000000UL
#define HDMI_DIG_FREQ_BIT_CLK_THRESHOLD 1500000000UL
#define HDMI_MID_FREQ_BIT_CLK_THRESHOLD 750000000UL
#define HDMI_CORECLK_DIV 5
#define HDMI_DEFAULT_REF_CLOCK 19200000
#define HDMI_PLL_CMP_CNT 1024
#define HDMI_PLL_POLL_MAX_READS 100
#define HDMI_PLL_POLL_TIMEOUT_US 150
#define HDMI_NUM_TX_CHANNEL 4
struct hdmi_pll_8996 {
struct platform_device *pdev;
struct clk_hw clk_hw;
/* pll mmio base */
void __iomem *mmio_qserdes_com;
/* tx channel base */
void __iomem *mmio_qserdes_tx[HDMI_NUM_TX_CHANNEL];
};
#define hw_clk_to_pll(x) container_of(x, struct hdmi_pll_8996, clk_hw)
struct hdmi_8996_phy_pll_reg_cfg {
u32 tx_lx_lane_mode[HDMI_NUM_TX_CHANNEL];
u32 tx_lx_tx_band[HDMI_NUM_TX_CHANNEL];
u32 com_svs_mode_clk_sel;
u32 com_hsclk_sel;
u32 com_pll_cctrl_mode0;
u32 com_pll_rctrl_mode0;
u32 com_cp_ctrl_mode0;
u32 com_dec_start_mode0;
u32 com_div_frac_start1_mode0;
u32 com_div_frac_start2_mode0;
u32 com_div_frac_start3_mode0;
u32 com_integloop_gain0_mode0;
u32 com_integloop_gain1_mode0;
u32 com_lock_cmp_en;
u32 com_lock_cmp1_mode0;
u32 com_lock_cmp2_mode0;
u32 com_lock_cmp3_mode0;
u32 com_core_clk_en;
u32 com_coreclk_div;
u32 com_vco_tune_ctrl;
u32 tx_lx_tx_drv_lvl[HDMI_NUM_TX_CHANNEL];
u32 tx_lx_tx_emp_post1_lvl[HDMI_NUM_TX_CHANNEL];
u32 tx_lx_vmode_ctrl1[HDMI_NUM_TX_CHANNEL];
u32 tx_lx_vmode_ctrl2[HDMI_NUM_TX_CHANNEL];
u32 tx_lx_res_code_lane_tx[HDMI_NUM_TX_CHANNEL];
u32 tx_lx_hp_pd_enables[HDMI_NUM_TX_CHANNEL];
u32 phy_mode;
};
struct hdmi_8996_post_divider {
u64 vco_freq;
int hsclk_divsel;
int vco_ratio;
int tx_band_sel;
int half_rate_mode;
};
static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8996 *pll)
{
return platform_get_drvdata(pll->pdev);
}
static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset,
u32 data)
{
msm_writel(data, pll->mmio_qserdes_com + offset);
}
static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset)
{
return msm_readl(pll->mmio_qserdes_com + offset);
}
static inline void hdmi_tx_chan_write(struct hdmi_pll_8996 *pll, int channel,
int offset, int data)
{
msm_writel(data, pll->mmio_qserdes_tx[channel] + offset);
}
static inline u32 pll_get_cpctrl(u64 frac_start, unsigned long ref_clk,
bool gen_ssc)
{
if ((frac_start != 0) || gen_ssc)
return (11000000 / (ref_clk / 20));
return 0x23;
}
static inline u32 pll_get_rctrl(u64 frac_start, bool gen_ssc)
{
if ((frac_start != 0) || gen_ssc)
return 0x16;
return 0x10;
}
static inline u32 pll_get_cctrl(u64 frac_start, bool gen_ssc)
{
if ((frac_start != 0) || gen_ssc)
return 0x28;
return 0x1;
}
static inline u32 pll_get_integloop_gain(u64 frac_start, u64 bclk, u32 ref_clk,
bool gen_ssc)
{
int digclk_divsel = bclk >= HDMI_DIG_FREQ_BIT_CLK_THRESHOLD ? 1 : 2;
u64 base;
if ((frac_start != 0) || gen_ssc)
base = (64 * ref_clk) / HDMI_DEFAULT_REF_CLOCK;
else
base = (1022 * ref_clk) / 100;
base <<= digclk_divsel;
return (base <= 2046 ? base : 2046);
}
static inline u32 pll_get_pll_cmp(u64 fdata, unsigned long ref_clk)
{
u64 dividend = HDMI_PLL_CMP_CNT * fdata;
u32 divisor = ref_clk * 10;
u32 rem;
rem = do_div(dividend, divisor);
if (rem > (divisor >> 1))
dividend++;
return dividend - 1;
}
static inline u64 pll_cmp_to_fdata(u32 pll_cmp, unsigned long ref_clk)
{
u64 fdata = ((u64)pll_cmp) * ref_clk * 10;
do_div(fdata, HDMI_PLL_CMP_CNT);
return fdata;
}
static int pll_get_post_div(struct hdmi_8996_post_divider *pd, u64 bclk)
{
int ratio[] = { 2, 3, 4, 5, 6, 9, 10, 12, 14, 15, 20, 21, 25, 28, 35 };
int hs_divsel[] = { 0, 4, 8, 12, 1, 5, 2, 9, 3, 13, 10, 7, 14, 11, 15 };
int tx_band_sel[] = { 0, 1, 2, 3 };
u64 vco_freq[60];
u64 vco, vco_optimal;
int half_rate_mode = 0;
int vco_optimal_index, vco_freq_index;
int i, j;
retry:
vco_optimal = HDMI_VCO_MAX_FREQ;
vco_optimal_index = -1;
vco_freq_index = 0;
for (i = 0; i < 15; i++) {
for (j = 0; j < 4; j++) {
u32 ratio_mult = ratio[i] << tx_band_sel[j];
vco = bclk >> half_rate_mode;
vco *= ratio_mult;
vco_freq[vco_freq_index++] = vco;
}
}
for (i = 0; i < 60; i++) {
u64 vco_tmp = vco_freq[i];
if ((vco_tmp >= HDMI_VCO_MIN_FREQ) &&
(vco_tmp <= vco_optimal)) {
vco_optimal = vco_tmp;
vco_optimal_index = i;
}
}
if (vco_optimal_index == -1) {
if (!half_rate_mode) {
half_rate_mode = 1;
goto retry;
}
} else {
pd->vco_freq = vco_optimal;
pd->tx_band_sel = tx_band_sel[vco_optimal_index % 4];
pd->vco_ratio = ratio[vco_optimal_index / 4];
pd->hsclk_divsel = hs_divsel[vco_optimal_index / 4];
return 0;
}
return -EINVAL;
}
static int pll_calculate(unsigned long pix_clk, unsigned long ref_clk,
struct hdmi_8996_phy_pll_reg_cfg *cfg)
{
struct hdmi_8996_post_divider pd;
u64 bclk;
u64 tmds_clk;
u64 dec_start;
u64 frac_start;
u64 fdata;
u32 pll_divisor;
u32 rem;
u32 cpctrl;
u32 rctrl;
u32 cctrl;
u32 integloop_gain;
u32 pll_cmp;
int i, ret;
/* bit clk = 10 * pix_clk */
bclk = ((u64)pix_clk) * 10;
if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD)
tmds_clk = pix_clk >> 2;
else
tmds_clk = pix_clk;
ret = pll_get_post_div(&pd, bclk);
if (ret)
return ret;
dec_start = pd.vco_freq;
pll_divisor = 4 * ref_clk;
do_div(dec_start, pll_divisor);
frac_start = pd.vco_freq * (1 << 20);
rem = do_div(frac_start, pll_divisor);
frac_start -= dec_start * (1 << 20);
if (rem > (pll_divisor >> 1))
frac_start++;
cpctrl = pll_get_cpctrl(frac_start, ref_clk, false);
rctrl = pll_get_rctrl(frac_start, false);
cctrl = pll_get_cctrl(frac_start, false);
integloop_gain = pll_get_integloop_gain(frac_start, bclk,
ref_clk, false);
fdata = pd.vco_freq;
do_div(fdata, pd.vco_ratio);
pll_cmp = pll_get_pll_cmp(fdata, ref_clk);
DBG("VCO freq: %llu", pd.vco_freq);
DBG("fdata: %llu", fdata);
DBG("pix_clk: %lu", pix_clk);
DBG("tmds clk: %llu", tmds_clk);
DBG("HSCLK_SEL: %d", pd.hsclk_divsel);
DBG("DEC_START: %llu", dec_start);
DBG("DIV_FRAC_START: %llu", frac_start);
DBG("PLL_CPCTRL: %u", cpctrl);
DBG("PLL_RCTRL: %u", rctrl);
DBG("PLL_CCTRL: %u", cctrl);
DBG("INTEGLOOP_GAIN: %u", integloop_gain);
DBG("TX_BAND: %d", pd.tx_band_sel);
DBG("PLL_CMP: %u", pll_cmp);
/* Convert these values to register specific values */
if (bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD)
cfg->com_svs_mode_clk_sel = 1;
else
cfg->com_svs_mode_clk_sel = 2;
cfg->com_hsclk_sel = (0x20 | pd.hsclk_divsel);
cfg->com_pll_cctrl_mode0 = cctrl;
cfg->com_pll_rctrl_mode0 = rctrl;
cfg->com_cp_ctrl_mode0 = cpctrl;
cfg->com_dec_start_mode0 = dec_start;
cfg->com_div_frac_start1_mode0 = (frac_start & 0xff);
cfg->com_div_frac_start2_mode0 = ((frac_start & 0xff00) >> 8);
cfg->com_div_frac_start3_mode0 = ((frac_start & 0xf0000) >> 16);
cfg->com_integloop_gain0_mode0 = (integloop_gain & 0xff);
cfg->com_integloop_gain1_mode0 = ((integloop_gain & 0xf00) >> 8);
cfg->com_lock_cmp1_mode0 = (pll_cmp & 0xff);
cfg->com_lock_cmp2_mode0 = ((pll_cmp & 0xff00) >> 8);
cfg->com_lock_cmp3_mode0 = ((pll_cmp & 0x30000) >> 16);
cfg->com_lock_cmp_en = 0x0;
cfg->com_core_clk_en = 0x2c;
cfg->com_coreclk_div = HDMI_CORECLK_DIV;
cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x10 : 0x0;
cfg->com_vco_tune_ctrl = 0x0;
cfg->tx_lx_lane_mode[0] =
cfg->tx_lx_lane_mode[2] = 0x43;
cfg->tx_lx_hp_pd_enables[0] =
cfg->tx_lx_hp_pd_enables[1] =
cfg->tx_lx_hp_pd_enables[2] = 0x0c;
cfg->tx_lx_hp_pd_enables[3] = 0x3;
for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++)
cfg->tx_lx_tx_band[i] = pd.tx_band_sel + 4;
if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) {
cfg->tx_lx_tx_drv_lvl[0] =
cfg->tx_lx_tx_drv_lvl[1] =
cfg->tx_lx_tx_drv_lvl[2] = 0x25;
cfg->tx_lx_tx_drv_lvl[3] = 0x22;
cfg->tx_lx_tx_emp_post1_lvl[0] =
cfg->tx_lx_tx_emp_post1_lvl[1] =
cfg->tx_lx_tx_emp_post1_lvl[2] = 0x23;
cfg->tx_lx_tx_emp_post1_lvl[3] = 0x27;
cfg->tx_lx_vmode_ctrl1[0] =
cfg->tx_lx_vmode_ctrl1[1] =
cfg->tx_lx_vmode_ctrl1[2] =
cfg->tx_lx_vmode_ctrl1[3] = 0x00;
cfg->tx_lx_vmode_ctrl2[0] =
cfg->tx_lx_vmode_ctrl2[1] =
cfg->tx_lx_vmode_ctrl2[2] = 0x0D;
cfg->tx_lx_vmode_ctrl2[3] = 0x00;
} else if (bclk > HDMI_MID_FREQ_BIT_CLK_THRESHOLD) {
for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) {
cfg->tx_lx_tx_drv_lvl[i] = 0x25;
cfg->tx_lx_tx_emp_post1_lvl[i] = 0x23;
cfg->tx_lx_vmode_ctrl1[i] = 0x00;
}
cfg->tx_lx_vmode_ctrl2[0] =
cfg->tx_lx_vmode_ctrl2[1] =
cfg->tx_lx_vmode_ctrl2[2] = 0x0D;
cfg->tx_lx_vmode_ctrl2[3] = 0x00;
} else {
for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) {
cfg->tx_lx_tx_drv_lvl[i] = 0x20;
cfg->tx_lx_tx_emp_post1_lvl[i] = 0x20;
cfg->tx_lx_vmode_ctrl1[i] = 0x00;
cfg->tx_lx_vmode_ctrl2[i] = 0x0E;
}
}
DBG("com_svs_mode_clk_sel = 0x%x", cfg->com_svs_mode_clk_sel);
DBG("com_hsclk_sel = 0x%x", cfg->com_hsclk_sel);
DBG("com_lock_cmp_en = 0x%x", cfg->com_lock_cmp_en);
DBG("com_pll_cctrl_mode0 = 0x%x", cfg->com_pll_cctrl_mode0);
DBG("com_pll_rctrl_mode0 = 0x%x", cfg->com_pll_rctrl_mode0);
DBG("com_cp_ctrl_mode0 = 0x%x", cfg->com_cp_ctrl_mode0);
DBG("com_dec_start_mode0 = 0x%x", cfg->com_dec_start_mode0);
DBG("com_div_frac_start1_mode0 = 0x%x", cfg->com_div_frac_start1_mode0);
DBG("com_div_frac_start2_mode0 = 0x%x", cfg->com_div_frac_start2_mode0);
DBG("com_div_frac_start3_mode0 = 0x%x", cfg->com_div_frac_start3_mode0);
DBG("com_integloop_gain0_mode0 = 0x%x", cfg->com_integloop_gain0_mode0);
DBG("com_integloop_gain1_mode0 = 0x%x", cfg->com_integloop_gain1_mode0);
DBG("com_lock_cmp1_mode0 = 0x%x", cfg->com_lock_cmp1_mode0);
DBG("com_lock_cmp2_mode0 = 0x%x", cfg->com_lock_cmp2_mode0);
DBG("com_lock_cmp3_mode0 = 0x%x", cfg->com_lock_cmp3_mode0);
DBG("com_core_clk_en = 0x%x", cfg->com_core_clk_en);
DBG("com_coreclk_div = 0x%x", cfg->com_coreclk_div);
DBG("phy_mode = 0x%x", cfg->phy_mode);
DBG("tx_l0_lane_mode = 0x%x", cfg->tx_lx_lane_mode[0]);
DBG("tx_l2_lane_mode = 0x%x", cfg->tx_lx_lane_mode[2]);
for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) {
DBG("tx_l%d_tx_band = 0x%x", i, cfg->tx_lx_tx_band[i]);
DBG("tx_l%d_tx_drv_lvl = 0x%x", i, cfg->tx_lx_tx_drv_lvl[i]);
DBG("tx_l%d_tx_emp_post1_lvl = 0x%x", i,
cfg->tx_lx_tx_emp_post1_lvl[i]);
DBG("tx_l%d_vmode_ctrl1 = 0x%x", i, cfg->tx_lx_vmode_ctrl1[i]);
DBG("tx_l%d_vmode_ctrl2 = 0x%x", i, cfg->tx_lx_vmode_ctrl2[i]);
}
return 0;
}
static int hdmi_8996_pll_set_clk_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw);
struct hdmi_phy *phy = pll_get_phy(pll);
struct hdmi_8996_phy_pll_reg_cfg cfg;
int i, ret;
memset(&cfg, 0x00, sizeof(cfg));
ret = pll_calculate(rate, parent_rate, &cfg);
if (ret) {
DRM_ERROR("PLL calculation failed\n");
return ret;
}
/* Initially shut down PHY */
DBG("Disabling PHY");
hdmi_phy_write(phy, REG_HDMI_8996_PHY_PD_CTL, 0x0);
udelay(500);
/* Power up sequence */
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_BG_CTRL, 0x04);
hdmi_phy_write(phy, REG_HDMI_8996_PHY_PD_CTL, 0x1);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL, 0x20);
hdmi_phy_write(phy, REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL, 0x0F);
hdmi_phy_write(phy, REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL, 0x0F);
for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) {
hdmi_tx_chan_write(pll, i,
REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE,
0x03);
hdmi_tx_chan_write(pll, i,
REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND,
cfg.tx_lx_tx_band[i]);
hdmi_tx_chan_write(pll, i,
REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN,
0x03);
}
hdmi_tx_chan_write(pll, 0, REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE,
cfg.tx_lx_lane_mode[0]);
hdmi_tx_chan_write(pll, 2, REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE,
cfg.tx_lx_lane_mode[2]);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1E);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x07);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL, 0x37);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL, 0x02);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1, 0x0E);
/* Bypass VCO calibration */
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL,
cfg.com_svs_mode_clk_sel);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_BG_TRIM, 0x0F);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_PLL_IVCO, 0x0F);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL,
cfg.com_vco_tune_ctrl);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_BG_CTRL, 0x06);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CLK_SELECT, 0x30);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL,
cfg.com_hsclk_sel);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN,
cfg.com_lock_cmp_en);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0,
cfg.com_pll_cctrl_mode0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0,
cfg.com_pll_rctrl_mode0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0,
cfg.com_cp_ctrl_mode0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0,
cfg.com_dec_start_mode0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0,
cfg.com_div_frac_start1_mode0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0,
cfg.com_div_frac_start2_mode0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0,
cfg.com_div_frac_start3_mode0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0,
cfg.com_integloop_gain0_mode0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0,
cfg.com_integloop_gain1_mode0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0,
cfg.com_lock_cmp1_mode0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0,
cfg.com_lock_cmp2_mode0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0,
cfg.com_lock_cmp3_mode0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP, 0x00);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN,
cfg.com_core_clk_en);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV,
cfg.com_coreclk_div);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG, 0x02);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM, 0x15);
/* TX lanes setup (TX 0/1/2/3) */
for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) {
hdmi_tx_chan_write(pll, i,
REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL,
cfg.tx_lx_tx_drv_lvl[i]);
hdmi_tx_chan_write(pll, i,
REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL,
cfg.tx_lx_tx_emp_post1_lvl[i]);
hdmi_tx_chan_write(pll, i,
REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1,
cfg.tx_lx_vmode_ctrl1[i]);
hdmi_tx_chan_write(pll, i,
REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2,
cfg.tx_lx_vmode_ctrl2[i]);
hdmi_tx_chan_write(pll, i,
REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET,
0x00);
hdmi_tx_chan_write(pll, i,
REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET,
0x00);
hdmi_tx_chan_write(pll, i,
REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN,
0x03);
hdmi_tx_chan_write(pll, i,
REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN,
0x40);
hdmi_tx_chan_write(pll, i,
REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES,
cfg.tx_lx_hp_pd_enables[i]);
}
hdmi_phy_write(phy, REG_HDMI_8996_PHY_MODE, cfg.phy_mode);
hdmi_phy_write(phy, REG_HDMI_8996_PHY_PD_CTL, 0x1F);
/*
* Ensure that vco configuration gets flushed to hardware before
* enabling the PLL
*/
wmb();
return 0;
}
static int hdmi_8996_phy_ready_status(struct hdmi_phy *phy)
{
u32 nb_tries = HDMI_PLL_POLL_MAX_READS;
unsigned long timeout = HDMI_PLL_POLL_TIMEOUT_US;
u32 status;
int phy_ready = 0;
DBG("Waiting for PHY ready");
while (nb_tries--) {
status = hdmi_phy_read(phy, REG_HDMI_8996_PHY_STATUS);
phy_ready = status & BIT(0);
if (phy_ready)
break;
udelay(timeout);
}
DBG("PHY is %sready", phy_ready ? "" : "*not* ");
return phy_ready;
}
static int hdmi_8996_pll_lock_status(struct hdmi_pll_8996 *pll)
{
u32 status;
int nb_tries = HDMI_PLL_POLL_MAX_READS;
unsigned long timeout = HDMI_PLL_POLL_TIMEOUT_US;
int pll_locked = 0;
DBG("Waiting for PLL lock");
while (nb_tries--) {
status = hdmi_pll_read(pll,
REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS);
pll_locked = status & BIT(0);
if (pll_locked)
break;
udelay(timeout);
}
DBG("HDMI PLL is %slocked", pll_locked ? "" : "*not* ");
return pll_locked;
}
static int hdmi_8996_pll_prepare(struct clk_hw *hw)
{
struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw);
struct hdmi_phy *phy = pll_get_phy(pll);
int i, ret = 0;
hdmi_phy_write(phy, REG_HDMI_8996_PHY_CFG, 0x1);
udelay(100);
hdmi_phy_write(phy, REG_HDMI_8996_PHY_CFG, 0x19);
udelay(100);
ret = hdmi_8996_pll_lock_status(pll);
if (!ret)
return ret;
for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++)
hdmi_tx_chan_write(pll, i,
REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN,
0x6F);
/* Disable SSC */
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_PER1, 0x0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_PER2, 0x0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1, 0x0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2, 0x0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER, 0x2);
ret = hdmi_8996_phy_ready_status(phy);
if (!ret)
return ret;
/* Restart the retiming buffer */
hdmi_phy_write(phy, REG_HDMI_8996_PHY_CFG, 0x18);
udelay(1);
hdmi_phy_write(phy, REG_HDMI_8996_PHY_CFG, 0x19);
return 0;
}
static long hdmi_8996_pll_round_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long *parent_rate)
{
if (rate < HDMI_PCLK_MIN_FREQ)
return HDMI_PCLK_MIN_FREQ;
else if (rate > HDMI_PCLK_MAX_FREQ)
return HDMI_PCLK_MAX_FREQ;
else
return rate;
}
static unsigned long hdmi_8996_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw);
u64 fdata;
u32 cmp1, cmp2, cmp3, pll_cmp;
cmp1 = hdmi_pll_read(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0);
cmp2 = hdmi_pll_read(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0);
cmp3 = hdmi_pll_read(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0);
pll_cmp = cmp1 | (cmp2 << 8) | (cmp3 << 16);
fdata = pll_cmp_to_fdata(pll_cmp + 1, parent_rate);
do_div(fdata, 10);
return fdata;
}
static void hdmi_8996_pll_unprepare(struct clk_hw *hw)
{
}
static int hdmi_8996_pll_is_enabled(struct clk_hw *hw)
{
struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw);
u32 status;
int pll_locked;
status = hdmi_pll_read(pll, REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS);
pll_locked = status & BIT(0);
return pll_locked;
}
static struct clk_ops hdmi_8996_pll_ops = {
.set_rate = hdmi_8996_pll_set_clk_rate,
.round_rate = hdmi_8996_pll_round_rate,
.recalc_rate = hdmi_8996_pll_recalc_rate,
.prepare = hdmi_8996_pll_prepare,
.unprepare = hdmi_8996_pll_unprepare,
.is_enabled = hdmi_8996_pll_is_enabled,
};
static const char * const hdmi_pll_parents[] = {
"xo",
};
static struct clk_init_data pll_init = {
.name = "hdmipll",
.ops = &hdmi_8996_pll_ops,
.parent_names = hdmi_pll_parents,
.num_parents = ARRAY_SIZE(hdmi_pll_parents),
};
int msm_hdmi_pll_8996_init(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct hdmi_pll_8996 *pll;
struct clk *clk;
int i;
pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
if (!pll)
return -ENOMEM;
pll->pdev = pdev;
pll->mmio_qserdes_com = msm_ioremap(pdev, "hdmi_pll", "HDMI_PLL");
if (IS_ERR(pll->mmio_qserdes_com)) {
dev_err(dev, "failed to map pll base\n");
return -ENOMEM;
}
for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) {
char name[32], label[32];
snprintf(name, sizeof(name), "hdmi_tx_l%d", i);
snprintf(label, sizeof(label), "HDMI_TX_L%d", i);
pll->mmio_qserdes_tx[i] = msm_ioremap(pdev, name, label);
if (IS_ERR(pll->mmio_qserdes_tx[i])) {
dev_err(dev, "failed to map pll base\n");
return -ENOMEM;
}
}
pll->clk_hw.init = &pll_init;
clk = devm_clk_register(dev, &pll->clk_hw);
if (IS_ERR(clk)) {
dev_err(dev, "failed to register pll clock\n");
return -EINVAL;
}
return 0;
}
static const char * const hdmi_phy_8996_reg_names[] = {
"vddio",
"vcca",
};
static const char * const hdmi_phy_8996_clk_names[] = {
"mmagic_iface_clk",
"iface_clk",
"ref_clk",
};
const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg = {
.type = MSM_HDMI_PHY_8996,
.reg_names = hdmi_phy_8996_reg_names,
.num_regs = ARRAY_SIZE(hdmi_phy_8996_reg_names),
.clk_names = hdmi_phy_8996_clk_names,
.num_clks = ARRAY_SIZE(hdmi_phy_8996_clk_names),
};
drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c
View file @ 912b330c
......@@ -17,166 +17,122 @@
#include "hdmi.h"
struct hdmi_phy_8x60 {
struct hdmi_phy base;
struct hdmi *hdmi;
};
#define to_hdmi_phy_8x60(x) container_of(x, struct hdmi_phy_8x60, base)
static void hdmi_phy_8x60_destroy(struct hdmi_phy *phy)
{
struct hdmi_phy_8x60 *phy_8x60 = to_hdmi_phy_8x60(phy);
kfree(phy_8x60);
}
static void hdmi_phy_8x60_powerup(struct hdmi_phy *phy,
unsigned long int pixclock)
{
struct hdmi_phy_8x60 *phy_8x60 = to_hdmi_phy_8x60(phy);
struct hdmi *hdmi = phy_8x60->hdmi;
/* De-serializer delay D/C for non-lbk mode: */
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG0,
HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(3));
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG0,
HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(3));
if (pixclock == 27000000) {
/* video_format == HDMI_VFRMT_720x480p60_16_9 */
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG1,
HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(5) |
HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(3));
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG1,
HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(5) |
HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(3));
} else {
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG1,
HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(5) |
HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(4));
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG1,
HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(5) |
HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(4));
}
/* No matter what, start from the power down mode: */
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
HDMI_8x60_PHY_REG2_PD_PWRGEN |
HDMI_8x60_PHY_REG2_PD_PLL |
HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
HDMI_8x60_PHY_REG2_PD_DESER);
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
HDMI_8x60_PHY_REG2_PD_PWRGEN |
HDMI_8x60_PHY_REG2_PD_PLL |
HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
HDMI_8x60_PHY_REG2_PD_DESER);
/* Turn PowerGen on: */
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
HDMI_8x60_PHY_REG2_PD_PLL |
HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
HDMI_8x60_PHY_REG2_PD_DESER);
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
HDMI_8x60_PHY_REG2_PD_PLL |
HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
HDMI_8x60_PHY_REG2_PD_DESER);
/* Turn PLL power on: */
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
HDMI_8x60_PHY_REG2_PD_DESER);
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
HDMI_8x60_PHY_REG2_PD_DESER);
/* Write to HIGH after PLL power down de-assert: */
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG3,
HDMI_8x60_PHY_REG3_PLL_ENABLE);
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG3,
HDMI_8x60_PHY_REG3_PLL_ENABLE);
/* ASIC power on; PHY REG9 = 0 */
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG9, 0);
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG9, 0);
/* Enable PLL lock detect, PLL lock det will go high after lock
* Enable the re-time logic
*/
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG12,
HDMI_8x60_PHY_REG12_RETIMING_EN |
HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN);
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG12,
HDMI_8x60_PHY_REG12_RETIMING_EN |
HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN);
/* Drivers are on: */
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
HDMI_8x60_PHY_REG2_PD_DESER);
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
HDMI_8x60_PHY_REG2_PD_DESER);
/* If the RX detector is needed: */
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
HDMI_8x60_PHY_REG2_RCV_SENSE_EN |
HDMI_8x60_PHY_REG2_PD_DESER);
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG4, 0);
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG5, 0);
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG6, 0);
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG7, 0);
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG8, 0);
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG9, 0);
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG10, 0);
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG11, 0);
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
HDMI_8x60_PHY_REG2_RCV_SENSE_EN |
HDMI_8x60_PHY_REG2_PD_DESER);
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG4, 0);
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG5, 0);
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG6, 0);
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG7, 0);
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG8, 0);
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG9, 0);
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG10, 0);
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG11, 0);
/* If we want to use lock enable based on counting: */
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG12,
HDMI_8x60_PHY_REG12_RETIMING_EN |
HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN |
HDMI_8x60_PHY_REG12_FORCE_LOCK);
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG12,
HDMI_8x60_PHY_REG12_RETIMING_EN |
HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN |
HDMI_8x60_PHY_REG12_FORCE_LOCK);
}
static void hdmi_phy_8x60_powerdown(struct hdmi_phy *phy)
{
struct hdmi_phy_8x60 *phy_8x60 = to_hdmi_phy_8x60(phy);
struct hdmi *hdmi = phy_8x60->hdmi;
/* Assert RESET PHY from controller */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
HDMI_PHY_CTRL_SW_RESET);
hdmi_phy_write(phy, REG_HDMI_PHY_CTRL,
HDMI_PHY_CTRL_SW_RESET);
udelay(10);
/* De-assert RESET PHY from controller */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL, 0);
hdmi_phy_write(phy, REG_HDMI_PHY_CTRL, 0);
/* Turn off Driver */
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
HDMI_8x60_PHY_REG2_PD_DESER);
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
HDMI_8x60_PHY_REG2_PD_DESER);
udelay(10);
/* Disable PLL */
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG3, 0);
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG3, 0);
/* Power down PHY, but keep RX-sense: */
hdmi_write(hdmi, REG_HDMI_8x60_PHY_REG2,
HDMI_8x60_PHY_REG2_RCV_SENSE_EN |
HDMI_8x60_PHY_REG2_PD_PWRGEN |
HDMI_8x60_PHY_REG2_PD_PLL |
HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
HDMI_8x60_PHY_REG2_PD_DESER);
hdmi_phy_write(phy, REG_HDMI_8x60_PHY_REG2,
HDMI_8x60_PHY_REG2_RCV_SENSE_EN |
HDMI_8x60_PHY_REG2_PD_PWRGEN |
HDMI_8x60_PHY_REG2_PD_PLL |
HDMI_8x60_PHY_REG2_PD_DRIVE_4 |
HDMI_8x60_PHY_REG2_PD_DRIVE_3 |
HDMI_8x60_PHY_REG2_PD_DRIVE_2 |
HDMI_8x60_PHY_REG2_PD_DRIVE_1 |
HDMI_8x60_PHY_REG2_PD_DESER);
}
static const struct hdmi_phy_funcs hdmi_phy_8x60_funcs = {
.destroy = hdmi_phy_8x60_destroy,
.powerup = hdmi_phy_8x60_powerup,
.powerdown = hdmi_phy_8x60_powerdown,
const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg = {
.type = MSM_HDMI_PHY_8x60,
.powerup = hdmi_phy_8x60_powerup,
.powerdown = hdmi_phy_8x60_powerdown,
};
struct hdmi_phy *hdmi_phy_8x60_init(struct hdmi *hdmi)
{
struct hdmi_phy_8x60 *phy_8x60;
struct hdmi_phy *phy = NULL;
int ret;
phy_8x60 = kzalloc(sizeof(*phy_8x60), GFP_KERNEL);
if (!phy_8x60) {
ret = -ENOMEM;
goto fail;
}
phy = &phy_8x60->base;
phy->funcs = &hdmi_phy_8x60_funcs;
phy_8x60->hdmi = hdmi;
return phy;
fail:
if (phy)
hdmi_phy_8x60_destroy(phy);
return ERR_PTR(ret);
}
drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c
View file @ 912b330c
......@@ -17,84 +17,40 @@
#include "hdmi.h"
struct hdmi_phy_8x74 {
struct hdmi_phy base;
void __iomem *mmio;
};
#define to_hdmi_phy_8x74(x) container_of(x, struct hdmi_phy_8x74, base)
static void phy_write(struct hdmi_phy_8x74 *phy, u32 reg, u32 data)
{
msm_writel(data, phy->mmio + reg);
}
//static u32 phy_read(struct hdmi_phy_8x74 *phy, u32 reg)
//{
// return msm_readl(phy->mmio + reg);
//}
static void hdmi_phy_8x74_destroy(struct hdmi_phy *phy)
{
struct hdmi_phy_8x74 *phy_8x74 = to_hdmi_phy_8x74(phy);
kfree(phy_8x74);
}
static void hdmi_phy_8x74_powerup(struct hdmi_phy *phy,
unsigned long int pixclock)
{
struct hdmi_phy_8x74 *phy_8x74 = to_hdmi_phy_8x74(phy);
phy_write(phy_8x74, REG_HDMI_8x74_ANA_CFG0, 0x1b);
phy_write(phy_8x74, REG_HDMI_8x74_ANA_CFG1, 0xf2);
phy_write(phy_8x74, REG_HDMI_8x74_BIST_CFG0, 0x0);
phy_write(phy_8x74, REG_HDMI_8x74_BIST_PATN0, 0x0);
phy_write(phy_8x74, REG_HDMI_8x74_BIST_PATN1, 0x0);
phy_write(phy_8x74, REG_HDMI_8x74_BIST_PATN2, 0x0);
phy_write(phy_8x74, REG_HDMI_8x74_BIST_PATN3, 0x0);
phy_write(phy_8x74, REG_HDMI_8x74_PD_CTRL1, 0x20);
hdmi_phy_write(phy, REG_HDMI_8x74_ANA_CFG0, 0x1b);
hdmi_phy_write(phy, REG_HDMI_8x74_ANA_CFG1, 0xf2);
hdmi_phy_write(phy, REG_HDMI_8x74_BIST_CFG0, 0x0);
hdmi_phy_write(phy, REG_HDMI_8x74_BIST_PATN0, 0x0);
hdmi_phy_write(phy, REG_HDMI_8x74_BIST_PATN1, 0x0);
hdmi_phy_write(phy, REG_HDMI_8x74_BIST_PATN2, 0x0);
hdmi_phy_write(phy, REG_HDMI_8x74_BIST_PATN3, 0x0);
hdmi_phy_write(phy, REG_HDMI_8x74_PD_CTRL1, 0x20);
}
static void hdmi_phy_8x74_powerdown(struct hdmi_phy *phy)
{
struct hdmi_phy_8x74 *phy_8x74 = to_hdmi_phy_8x74(phy);
phy_write(phy_8x74, REG_HDMI_8x74_PD_CTRL0, 0x7f);
hdmi_phy_write(phy, REG_HDMI_8x74_PD_CTRL0, 0x7f);
}
static const struct hdmi_phy_funcs hdmi_phy_8x74_funcs = {
.destroy = hdmi_phy_8x74_destroy,
.powerup = hdmi_phy_8x74_powerup,
.powerdown = hdmi_phy_8x74_powerdown,
static const char * const hdmi_phy_8x74_reg_names[] = {
"core-vdda",
"vddio",
};
struct hdmi_phy *hdmi_phy_8x74_init(struct hdmi *hdmi)
{
struct hdmi_phy_8x74 *phy_8x74;
struct hdmi_phy *phy = NULL;
int ret;
phy_8x74 = kzalloc(sizeof(*phy_8x74), GFP_KERNEL);
if (!phy_8x74) {
ret = -ENOMEM;
goto fail;
}
phy = &phy_8x74->base;
phy->funcs = &hdmi_phy_8x74_funcs;
/* for 8x74, the phy mmio is mapped separately: */
phy_8x74->mmio = msm_ioremap(hdmi->pdev,
"phy_physical", "HDMI_8x74");
if (IS_ERR(phy_8x74->mmio)) {
ret = PTR_ERR(phy_8x74->mmio);
goto fail;
}
return phy;
static const char * const hdmi_phy_8x74_clk_names[] = {
"iface_clk",
"alt_iface_clk"
};
fail:
if (phy)
hdmi_phy_8x74_destroy(phy);
return ERR_PTR(ret);
}
const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg = {
.type = MSM_HDMI_PHY_8x74,
.powerup = hdmi_phy_8x74_powerup,
.powerdown = hdmi_phy_8x74_powerdown,
.reg_names = hdmi_phy_8x74_reg_names,
.num_regs = ARRAY_SIZE(hdmi_phy_8x74_reg_names),
.clk_names = hdmi_phy_8x74_clk_names,
.num_clks = ARRAY_SIZE(hdmi_phy_8x74_clk_names),
};
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c 0 → 100644
View file @ 912b330c
/*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
* Copyright (C) 2013 Red Hat
* Author: Rob Clark <robdclark@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/clk-provider.h>
#include "hdmi.h"
struct hdmi_pll_8960 {
struct platform_device *pdev;
struct clk_hw clk_hw;
void __iomem *mmio;
unsigned long pixclk;
};
#define hw_clk_to_pll(x) container_of(x, struct hdmi_pll_8960, clk_hw)
/*
* HDMI PLL:
*
* To get the parent clock setup properly, we need to plug in hdmi pll
* configuration into common-clock-framework.
*/
struct pll_rate {
unsigned long rate;
int num_reg;
struct {
u32 val;
u32 reg;
} conf[32];
};
/* NOTE: keep sorted highest freq to lowest: */
static const struct pll_rate freqtbl[] = {
{ 154000000, 14, {
{ 0x08, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
{ 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
{ 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
{ 0x03, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
{ 0x0d, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
{ 0x4d, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
{ 0x5e, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
{ 0x42, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
}
},
/* 1080p60/1080p50 case */
{ 148500000, 27, {
{ 0x02, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
{ 0x02, REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG },
{ 0x01, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
{ 0x33, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
{ 0x2c, REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG },
{ 0x06, REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG },
{ 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
{ 0x76, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
{ 0x01, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
{ 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
{ 0xc0, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
{ 0x9a, REG_HDMI_8960_PHY_PLL_SSC_CFG0 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG1 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG2 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG3 },
{ 0x10, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 },
{ 0x1a, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 },
{ 0x0d, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 },
{ 0xe6, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
{ 0x33, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 },
}
},
{ 108000000, 13, {
{ 0x08, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
{ 0x21, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
{ 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
{ 0x1c, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
{ 0x49, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
{ 0x49, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
}
},
/* 720p60/720p50/1080i60/1080i50/1080p24/1080p30/1080p25 */
{ 74250000, 8, {
{ 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
{ 0x12, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
{ 0x01, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
{ 0x33, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
{ 0x76, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
{ 0xe6, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
}
},
{ 74176000, 14, {
{ 0x18, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
{ 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
{ 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
{ 0xe5, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
{ 0x0c, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
{ 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
{ 0x7d, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
{ 0xbc, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
}
},
{ 65000000, 14, {
{ 0x18, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
{ 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
{ 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
{ 0x8a, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
{ 0x0b, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
{ 0x4b, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
{ 0x7b, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
{ 0x09, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
}
},
/* 480p60/480i60 */
{ 27030000, 18, {
{ 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
{ 0x38, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
{ 0x02, REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG },
{ 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
{ 0xff, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
{ 0x4e, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
{ 0xd7, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
{ 0x03, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
{ 0x2a, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
{ 0x03, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
{ 0x33, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 },
}
},
/* 576p50/576i50 */
{ 27000000, 27, {
{ 0x32, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
{ 0x02, REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG },
{ 0x01, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
{ 0x33, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
{ 0x2c, REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG },
{ 0x06, REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG },
{ 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
{ 0x7b, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
{ 0x01, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
{ 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
{ 0xc0, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
{ 0x9a, REG_HDMI_8960_PHY_PLL_SSC_CFG0 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG1 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG2 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG3 },
{ 0x10, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 },
{ 0x1a, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 },
{ 0x0d, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 },
{ 0x2a, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
{ 0x03, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
{ 0x33, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 },
}
},
/* 640x480p60 */
{ 25200000, 27, {
{ 0x32, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
{ 0x02, REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG },
{ 0x01, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
{ 0x33, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
{ 0x2c, REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG },
{ 0x06, REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG },
{ 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
{ 0x77, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
{ 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
{ 0xc0, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
{ 0x9a, REG_HDMI_8960_PHY_PLL_SSC_CFG0 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG1 },
{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG2 },
{ 0x20, REG_HDMI_8960_PHY_PLL_SSC_CFG3 },
{ 0x10, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 },
{ 0x1a, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 },
{ 0x0d, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 },
{ 0xf4, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
{ 0x33, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 },
{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 },
}
},
};
static inline void pll_write(struct hdmi_pll_8960 *pll, u32 reg, u32 data)
{
msm_writel(data, pll->mmio + reg);
}
static inline u32 pll_read(struct hdmi_pll_8960 *pll, u32 reg)
{
return msm_readl(pll->mmio + reg);
}
static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8960 *pll)
{
return platform_get_drvdata(pll->pdev);
}
static int hdmi_pll_enable(struct clk_hw *hw)
{
struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw);
struct hdmi_phy *phy = pll_get_phy(pll);
int timeout_count, pll_lock_retry = 10;
unsigned int val;
DBG("");
/* Assert PLL S/W reset */
pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x8d);
pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0, 0x10);
pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1, 0x1a);
/* Wait for a short time before de-asserting
* to allow the hardware to complete its job.
* This much of delay should be fine for hardware
* to assert and de-assert.
*/
udelay(10);
/* De-assert PLL S/W reset */
pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x0d);
val = hdmi_phy_read(phy, REG_HDMI_8960_PHY_REG12);
val |= HDMI_8960_PHY_REG12_SW_RESET;
/* Assert PHY S/W reset */
hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG12, val);
val &= ~HDMI_8960_PHY_REG12_SW_RESET;
/*
* Wait for a short time before de-asserting to allow the hardware to
* complete its job. This much of delay should be fine for hardware to
* assert and de-assert.
*/
udelay(10);
/* De-assert PHY S/W reset */
hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG12, val);
hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG2, 0x3f);
val = hdmi_phy_read(phy, REG_HDMI_8960_PHY_REG12);
val |= HDMI_8960_PHY_REG12_PWRDN_B;
hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG12, val);
/* Wait 10 us for enabling global power for PHY */
mb();
udelay(10);
val = pll_read(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B);
val |= HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B;
val &= ~HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL;
pll_write(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B, val);
hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG2, 0x80);
timeout_count = 1000;
while (--pll_lock_retry > 0) {
/* are we there yet? */
val = pll_read(pll, REG_HDMI_8960_PHY_PLL_STATUS0);
if (val & HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK)
break;
udelay(1);
if (--timeout_count > 0)
continue;
/*
* PLL has still not locked.
* Do a software reset and try again
* Assert PLL S/W reset first
*/
pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x8d);
udelay(10);
pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x0d);
/*
* Wait for a short duration for the PLL calibration
* before checking if the PLL gets locked
*/
udelay(350);
timeout_count = 1000;
}
return 0;
}
static void hdmi_pll_disable(struct clk_hw *hw)
{
struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw);
struct hdmi_phy *phy = pll_get_phy(pll);
unsigned int val;
DBG("");
val = hdmi_phy_read(phy, REG_HDMI_8960_PHY_REG12);
val &= ~HDMI_8960_PHY_REG12_PWRDN_B;
hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG12, val);
val = pll_read(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B);
val |= HDMI_8960_PHY_REG12_SW_RESET;
val &= ~HDMI_8960_PHY_REG12_PWRDN_B;
pll_write(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B, val);
/* Make sure HDMI PHY/PLL are powered down */
mb();
}
static const struct pll_rate *find_rate(unsigned long rate)
{
int i;
for (i = 1; i < ARRAY_SIZE(freqtbl); i++)
if (rate > freqtbl[i].rate)
return &freqtbl[i - 1];
return &freqtbl[i - 1];
}
static unsigned long hdmi_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw);
return pll->pixclk;
}
static long hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
const struct pll_rate *pll_rate = find_rate(rate);
return pll_rate->rate;
}
static int hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw);
const struct pll_rate *pll_rate = find_rate(rate);
int i;
DBG("rate=%lu", rate);
for (i = 0; i < pll_rate->num_reg; i++)
pll_write(pll, pll_rate->conf[i].reg, pll_rate->conf[i].val);
pll->pixclk = rate;
return 0;
}
static const struct clk_ops hdmi_pll_ops = {
.enable = hdmi_pll_enable,
.disable = hdmi_pll_disable,
.recalc_rate = hdmi_pll_recalc_rate,
.round_rate = hdmi_pll_round_rate,
.set_rate = hdmi_pll_set_rate,
};
static const char * const hdmi_pll_parents[] = {
"pxo",
};
static struct clk_init_data pll_init = {
.name = "hdmi_pll",
.ops = &hdmi_pll_ops,
.parent_names = hdmi_pll_parents,
.num_parents = ARRAY_SIZE(hdmi_pll_parents),
};
int msm_hdmi_pll_8960_init(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct hdmi_pll_8960 *pll;
struct clk *clk;
int i;
/* sanity check: */
for (i = 0; i < (ARRAY_SIZE(freqtbl) - 1); i++)
if (WARN_ON(freqtbl[i].rate < freqtbl[i + 1].rate))
return -EINVAL;
pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
if (!pll)
return -ENOMEM;
pll->mmio = msm_ioremap(pdev, "hdmi_pll", "HDMI_PLL");
if (IS_ERR(pll->mmio)) {
dev_err(dev, "failed to map pll base\n");
return -ENOMEM;
}
pll->pdev = pdev;
pll->clk_hw.init = &pll_init;
clk = devm_clk_register(dev, &pll->clk_hw);
if (IS_ERR(clk)) {
dev_err(dev, "failed to register pll clock\n");
return -EINVAL;
}
return 0;
}
drivers/gpu/drm/msm/hdmi/qfprom.xml.h
View file @ 912b330c
......@@ -9,7 +9,7 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
......@@ -17,11 +17,12 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
......
drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
View file @ 912b330c
......@@ -9,7 +9,7 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
......@@ -17,11 +17,12 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
......
drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
View file @ 912b330c
......@@ -361,13 +361,6 @@ static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc,
request_pending(crtc, PENDING_FLIP);
}
static int mdp4_crtc_set_property(struct drm_crtc *crtc,
struct drm_property *property, uint64_t val)
{
// XXX
return -EINVAL;
}
#define CURSOR_WIDTH 64
#define CURSOR_HEIGHT 64
......@@ -499,7 +492,7 @@ static const struct drm_crtc_funcs mdp4_crtc_funcs = {
.set_config = drm_atomic_helper_set_config,
.destroy = mdp4_crtc_destroy,
.page_flip = drm_atomic_helper_page_flip,
.set_property = mdp4_crtc_set_property,
.set_property = drm_atomic_helper_crtc_set_property,
.cursor_set = mdp4_crtc_cursor_set,
.cursor_move = mdp4_crtc_cursor_move,
.reset = drm_atomic_helper_crtc_reset,
......
drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
View file @ 912b330c
......@@ -179,9 +179,20 @@ static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
}
}
static const char * const iommu_ports[] = {
"mdp_port0_cb0", "mdp_port1_cb0",
};
static void mdp4_destroy(struct msm_kms *kms)
{
struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
struct msm_mmu *mmu = mdp4_kms->mmu;
if (mmu) {
mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports));
mmu->funcs->destroy(mmu);
}
if (mdp4_kms->blank_cursor_iova)
msm_gem_put_iova(mdp4_kms->blank_cursor_bo, mdp4_kms->id);
if (mdp4_kms->blank_cursor_bo)
......@@ -315,7 +326,7 @@ static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms,
if (priv->hdmi) {
/* Construct bridge/connector for HDMI: */
ret = hdmi_modeset_init(priv->hdmi, dev, encoder);
ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
if (ret) {
dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret);
return ret;
......@@ -446,10 +457,6 @@ static int modeset_init(struct mdp4_kms *mdp4_kms)
return ret;
}
static const char *iommu_ports[] = {
"mdp_port0_cb0", "mdp_port1_cb0",
};
struct msm_kms *mdp4_kms_init(struct drm_device *dev)
{
struct platform_device *pdev = dev->platformdev;
......@@ -554,6 +561,8 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev)
ARRAY_SIZE(iommu_ports));
if (ret)
goto fail;
mdp4_kms->mmu = mmu;
} else {
dev_info(dev->dev, "no iommu, fallback to phys "
"contig buffers for scanout\n");
......
drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h
View file @ 912b330c
......@@ -45,6 +45,7 @@ struct mdp4_kms {
struct clk *pclk;
struct clk *lut_clk;
struct clk *axi_clk;
struct msm_mmu *mmu;
struct mdp_irq error_handler;
......
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
View file @ 912b330c
......@@ -9,7 +9,7 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
......@@ -17,11 +17,12 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
......
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
View file @ 912b330c
......@@ -468,13 +468,6 @@ static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc,
request_pending(crtc, PENDING_FLIP);
}
static int mdp5_crtc_set_property(struct drm_crtc *crtc,
struct drm_property *property, uint64_t val)
{
// XXX
return -EINVAL;
}
static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h)
{
struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
......@@ -625,7 +618,7 @@ static const struct drm_crtc_funcs mdp5_crtc_funcs = {
.set_config = drm_atomic_helper_set_config,
.destroy = mdp5_crtc_destroy,
.page_flip = drm_atomic_helper_page_flip,
.set_property = mdp5_crtc_set_property,
.set_property = drm_atomic_helper_crtc_set_property,
.reset = drm_atomic_helper_crtc_reset,
.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
......
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
View file @ 912b330c
......@@ -284,7 +284,7 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_kms, int intf_num)
break;
}
ret = hdmi_modeset_init(priv->hdmi, dev, encoder);
ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
break;
case INTF_DSI:
{
......
drivers/gpu/drm/msm/mdp/mdp_common.xml.h
View file @ 912b330c
......@@ -9,7 +9,7 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28)
......@@ -17,11 +17,12 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
......
drivers/gpu/drm/msm/msm_drv.c
View file @ 912b330c
......@@ -61,7 +61,7 @@ module_param(fbdev, bool, 0600);
#endif
static char *vram = "16m";
MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU");
MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
module_param(vram, charp, 0);
/*
......@@ -196,6 +196,11 @@ static int msm_unload(struct drm_device *dev)
}
drm_kms_helper_poll_fini(dev);
#ifdef CONFIG_DRM_FBDEV_EMULATION
if (fbdev && priv->fbdev)
msm_fbdev_free(dev);
#endif
drm_mode_config_cleanup(dev);
drm_vblank_cleanup(dev);
......@@ -1116,7 +1121,7 @@ static int __init msm_drm_register(void)
DBG("init");
msm_dsi_register();
msm_edp_register();
hdmi_register();
msm_hdmi_register();
adreno_register();
return platform_driver_register(&msm_platform_driver);
}
......@@ -1125,7 +1130,7 @@ static void __exit msm_drm_unregister(void)
{
DBG("fini");
platform_driver_unregister(&msm_platform_driver);
hdmi_unregister();
msm_hdmi_unregister();
adreno_unregister();
msm_edp_unregister();
msm_dsi_unregister();
......
drivers/gpu/drm/msm/msm_drv.h
View file @ 912b330c
......@@ -240,12 +240,13 @@ struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
void msm_fbdev_free(struct drm_device *dev);
struct hdmi;
int hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
struct drm_encoder *encoder);
void __init hdmi_register(void);
void __exit hdmi_unregister(void);
void __init msm_hdmi_register(void);
void __exit msm_hdmi_unregister(void);
struct msm_edp;
void __init msm_edp_register(void);
......
drivers/gpu/drm/msm/msm_gem_submit.c
View file @ 912b330c
......@@ -323,28 +323,27 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
struct drm_msm_gem_submit *args = data;
struct msm_file_private *ctx = file->driver_priv;
struct msm_gem_submit *submit;
struct msm_gpu *gpu;
struct msm_gpu *gpu = priv->gpu;
unsigned i;
int ret;
if (!gpu)
return -ENXIO;
/* for now, we just have 3d pipe.. eventually this would need to
* be more clever to dispatch to appropriate gpu module:
*/
if (args->pipe != MSM_PIPE_3D0)
return -EINVAL;
gpu = priv->gpu;
if (args->nr_cmds > MAX_CMDS)
return -EINVAL;
mutex_lock(&dev->struct_mutex);
submit = submit_create(dev, gpu, args->nr_bos);
if (!submit) {
ret = -ENOMEM;
goto out;
}
if (!submit)
return -ENOMEM;
mutex_lock(&dev->struct_mutex);
ret = submit_lookup_objects(submit, args, file);
if (ret)
......@@ -419,8 +418,7 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
args->fence = submit->fence;
out:
if (submit)
submit_cleanup(submit, !!ret);
submit_cleanup(submit, !!ret);
mutex_unlock(&dev->struct_mutex);
return ret;
}
drivers/gpu/drm/msm/msm_iommu.c
View file @ 912b330c
......@@ -31,13 +31,15 @@ static int msm_fault_handler(struct iommu_domain *iommu, struct device *dev,
return 0;
}
static int msm_iommu_attach(struct msm_mmu *mmu, const char **names, int cnt)
static int msm_iommu_attach(struct msm_mmu *mmu, const char * const *names,
int cnt)
{
struct msm_iommu *iommu = to_msm_iommu(mmu);
return iommu_attach_device(iommu->domain, mmu->dev);
}
static void msm_iommu_detach(struct msm_mmu *mmu, const char **names, int cnt)
static void msm_iommu_detach(struct msm_mmu *mmu, const char * const *names,
int cnt)
{
struct msm_iommu *iommu = to_msm_iommu(mmu);
iommu_detach_device(iommu->domain, mmu->dev);
......
drivers/gpu/drm/msm/msm_mmu.h
View file @ 912b330c
......@@ -21,8 +21,8 @@
#include <linux/iommu.h>
struct msm_mmu_funcs {
int (*attach)(struct msm_mmu *mmu, const char **names, int cnt);
void (*detach)(struct msm_mmu *mmu, const char **names, int cnt);
int (*attach)(struct msm_mmu *mmu, const char * const *names, int cnt);
void (*detach)(struct msm_mmu *mmu, const char * const *names, int cnt);
int (*map)(struct msm_mmu *mmu, uint32_t iova, struct sg_table *sgt,
unsigned len, int prot);
int (*unmap)(struct msm_mmu *mmu, uint32_t iova, struct sg_table *sgt,
......
include/uapi/drm/msm_drm.h
View file @ 912b330c
......@@ -51,6 +51,7 @@ struct drm_msm_timespec {
#define MSM_PARAM_GMEM_SIZE 0x02
#define MSM_PARAM_CHIP_ID 0x03
#define MSM_PARAM_MAX_FREQ 0x04
#define MSM_PARAM_TIMESTAMP 0x05
struct drm_msm_param {
__u32 pipe; /* in, MSM_PIPE_x */
......
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