Commit 91b3a24a authored by Will Deacon's avatar Will Deacon

Merge branch 'iommu/allwinner/sun50i' into iommu/next

* iommu/allwinner/sun50i:
  iommu: sun50i: Add H616 compatible string
  dt-bindings: iommu: add new compatible strings
  iommu: sun50i: allocate page tables from below 4 GiB
  iommu: sun50i: clear bypass register
parents 83a7eefe 8db07ce5
...@@ -17,7 +17,12 @@ properties: ...@@ -17,7 +17,12 @@ properties:
The content of the cell is the master ID. The content of the cell is the master ID.
compatible: compatible:
const: allwinner,sun50i-h6-iommu oneOf:
- const: allwinner,sun50i-h6-iommu
- const: allwinner,sun50i-h616-iommu
- items:
- const: allwinner,sun55i-a523-iommu
- const: allwinner,sun50i-h616-iommu
reg: reg:
maxItems: 1 maxItems: 1
......
...@@ -452,6 +452,7 @@ static int sun50i_iommu_enable(struct sun50i_iommu *iommu) ...@@ -452,6 +452,7 @@ static int sun50i_iommu_enable(struct sun50i_iommu *iommu)
IOMMU_TLB_PREFETCH_MASTER_ENABLE(3) | IOMMU_TLB_PREFETCH_MASTER_ENABLE(3) |
IOMMU_TLB_PREFETCH_MASTER_ENABLE(4) | IOMMU_TLB_PREFETCH_MASTER_ENABLE(4) |
IOMMU_TLB_PREFETCH_MASTER_ENABLE(5)); IOMMU_TLB_PREFETCH_MASTER_ENABLE(5));
iommu_write(iommu, IOMMU_BYPASS_REG, 0);
iommu_write(iommu, IOMMU_INT_ENABLE_REG, IOMMU_INT_MASK); iommu_write(iommu, IOMMU_INT_ENABLE_REG, IOMMU_INT_MASK);
iommu_write(iommu, IOMMU_DM_AUT_CTRL_REG(SUN50I_IOMMU_ACI_NONE), iommu_write(iommu, IOMMU_DM_AUT_CTRL_REG(SUN50I_IOMMU_ACI_NONE),
IOMMU_DM_AUT_CTRL_RD_UNAVAIL(SUN50I_IOMMU_ACI_NONE, 0) | IOMMU_DM_AUT_CTRL_RD_UNAVAIL(SUN50I_IOMMU_ACI_NONE, 0) |
...@@ -601,6 +602,14 @@ static int sun50i_iommu_map(struct iommu_domain *domain, unsigned long iova, ...@@ -601,6 +602,14 @@ static int sun50i_iommu_map(struct iommu_domain *domain, unsigned long iova,
u32 *page_table, *pte_addr; u32 *page_table, *pte_addr;
int ret = 0; int ret = 0;
/* the IOMMU can only handle 32-bit addresses, both input and output */
if ((uint64_t)paddr >> 32) {
ret = -EINVAL;
dev_warn_once(iommu->dev,
"attempt to map address beyond 4GB\n");
goto out;
}
page_table = sun50i_dte_get_page_table(sun50i_domain, iova, gfp); page_table = sun50i_dte_get_page_table(sun50i_domain, iova, gfp);
if (IS_ERR(page_table)) { if (IS_ERR(page_table)) {
ret = PTR_ERR(page_table); ret = PTR_ERR(page_table);
...@@ -681,7 +690,8 @@ sun50i_iommu_domain_alloc_paging(struct device *dev) ...@@ -681,7 +690,8 @@ sun50i_iommu_domain_alloc_paging(struct device *dev)
if (!sun50i_domain) if (!sun50i_domain)
return NULL; return NULL;
sun50i_domain->dt = iommu_alloc_pages(GFP_KERNEL, get_order(DT_SIZE)); sun50i_domain->dt = iommu_alloc_pages(GFP_KERNEL | GFP_DMA32,
get_order(DT_SIZE));
if (!sun50i_domain->dt) if (!sun50i_domain->dt)
goto err_free_domain; goto err_free_domain;
...@@ -996,7 +1006,7 @@ static int sun50i_iommu_probe(struct platform_device *pdev) ...@@ -996,7 +1006,7 @@ static int sun50i_iommu_probe(struct platform_device *pdev)
iommu->pt_pool = kmem_cache_create(dev_name(&pdev->dev), iommu->pt_pool = kmem_cache_create(dev_name(&pdev->dev),
PT_SIZE, PT_SIZE, PT_SIZE, PT_SIZE,
SLAB_HWCACHE_ALIGN, SLAB_HWCACHE_ALIGN | SLAB_CACHE_DMA32,
NULL); NULL);
if (!iommu->pt_pool) if (!iommu->pt_pool)
return -ENOMEM; return -ENOMEM;
...@@ -1057,6 +1067,7 @@ static int sun50i_iommu_probe(struct platform_device *pdev) ...@@ -1057,6 +1067,7 @@ static int sun50i_iommu_probe(struct platform_device *pdev)
static const struct of_device_id sun50i_iommu_dt[] = { static const struct of_device_id sun50i_iommu_dt[] = {
{ .compatible = "allwinner,sun50i-h6-iommu", }, { .compatible = "allwinner,sun50i-h6-iommu", },
{ .compatible = "allwinner,sun50i-h616-iommu", },
{ /* sentinel */ }, { /* sentinel */ },
}; };
MODULE_DEVICE_TABLE(of, sun50i_iommu_dt); MODULE_DEVICE_TABLE(of, sun50i_iommu_dt);
......
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