Commit 91ec4b0d authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'mips_6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Thomas Bogendoerfer:

 - added support for Huawei B593u-12

 - added support for virt board aligned to QEMU MIPS virt board

 - added support for doing DMA coherence on a per device base

 - reworked handling of RALINK SoCs

 - cleanup for Loongon64 barriers

 - removed deprecated support for MIPS_CMP SMP handling method

 - removed support Sibyte CARMEL and CHRINE boards

 - cleanups and fixes

* tag 'mips_6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (59 commits)
  MIPS: uprobes: Restore thread.trap_nr
  MIPS: Don't clear _PAGE_SPECIAL in _PAGE_CHG_MASK
  MIPS: Sink body of check_bugs_early() into its only call site
  MIPS: Mark check_bugs() as __init
  Revert "MIPS: generic: Enable all CPUs supported by virt board in Kconfig"
  MIPS: octeon_switch: Remove duplicated labels
  MIPS: loongson2ef: Add missing break in cs5536_isa
  MIPS: Remove set_swbp() in uprobes.c
  MIPS: Use def_bool y for ARCH_SUPPORTS_UPROBES
  MIPS: fw: Allow firmware to pass a empty env
  MIPS: Remove deprecated CONFIG_MIPS_CMP
  MIPS: lantiq: remove unused function declaration
  MIPS: Drop unused positional parameter in local_irq_{dis,en}able
  MIPS: mm: Remove local_cache_flush_page
  MIPS: Remove no longer used ide.h
  MIPS: mm: Remove unused *cache_page_indexed flush functions
  MIPS: generic: Enable all CPUs supported by virt board in Kconfig
  MIPS: Add board config for virt board
  MIPS: Octeon: Disable CVMSEG by default on other platforms
  MIPS: Loongson: Don't select platform features with CPU
  ...
parents 513f17f8 46e614cc
...@@ -37,6 +37,18 @@ properties: ...@@ -37,6 +37,18 @@ properties:
items: items:
- const: loongson,loongson64v-4core-virtio - const: loongson,loongson64v-4core-virtio
- description: LS1B based boards
items:
- enum:
- loongson,lsgz-1b-dev
- const: loongson,ls1b
- description: LS1C based boards
items:
- enum:
- loongmasses,smartloong-1c
- const: loongson,ls1c
additionalProperties: true additionalProperties: true
... ...
...@@ -777,6 +777,8 @@ patternProperties: ...@@ -777,6 +777,8 @@ patternProperties:
description: Lontium Semiconductor Corporation description: Lontium Semiconductor Corporation
"^loongson,.*": "^loongson,.*":
description: Loongson Technology Corporation Limited description: Loongson Technology Corporation Limited
"^loongmasses,.*":
description: Nanjing Loongmasses Ltd.
"^lsi,.*": "^lsi,.*":
description: LSI Corp. (LSI Logic) description: LSI Corp. (LSI Logic)
"^lwn,.*": "^lwn,.*":
......
...@@ -29,7 +29,6 @@ platform-$(CONFIG_SGI_IP30) += sgi-ip30/ ...@@ -29,7 +29,6 @@ platform-$(CONFIG_SGI_IP30) += sgi-ip30/
platform-$(CONFIG_SGI_IP32) += sgi-ip32/ platform-$(CONFIG_SGI_IP32) += sgi-ip32/
platform-$(CONFIG_SIBYTE_BCM112X) += sibyte/ platform-$(CONFIG_SIBYTE_BCM112X) += sibyte/
platform-$(CONFIG_SIBYTE_SB1250) += sibyte/ platform-$(CONFIG_SIBYTE_SB1250) += sibyte/
platform-$(CONFIG_SIBYTE_BCM1x55) += sibyte/
platform-$(CONFIG_SIBYTE_BCM1x80) += sibyte/ platform-$(CONFIG_SIBYTE_BCM1x80) += sibyte/
platform-$(CONFIG_SNI_RM) += sni/ platform-$(CONFIG_SNI_RM) += sni/
platform-$(CONFIG_MACH_TX49XX) += txx9/ platform-$(CONFIG_MACH_TX49XX) += txx9/
......
...@@ -16,7 +16,6 @@ config MIPS ...@@ -16,7 +16,6 @@ config MIPS
select ARCH_HAS_UBSAN_SANITIZE_ALL select ARCH_HAS_UBSAN_SANITIZE_ALL
select ARCH_HAS_GCOV_PROFILE_ALL select ARCH_HAS_GCOV_PROFILE_ALL
select ARCH_KEEP_MEMBLOCK select ARCH_KEEP_MEMBLOCK
select ARCH_SUPPORTS_UPROBES
select ARCH_USE_BUILTIN_BSWAP select ARCH_USE_BUILTIN_BSWAP
select ARCH_USE_CMPXCHG_LOCKREF if 64BIT select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
select ARCH_USE_MEMTEST select ARCH_USE_MEMTEST
...@@ -113,7 +112,6 @@ config MACH_INGENIC ...@@ -113,7 +112,6 @@ config MACH_INGENIC
select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_ZBOOT select SYS_SUPPORTS_ZBOOT
select DMA_NONCOHERENT select DMA_NONCOHERENT
select ARCH_HAS_SYNC_DMA_FOR_CPU
select IRQ_MIPS_CPU select IRQ_MIPS_CPU
select PINCTRL select PINCTRL
select GPIOLIB select GPIOLIB
...@@ -132,7 +130,6 @@ choice ...@@ -132,7 +130,6 @@ choice
config MIPS_GENERIC_KERNEL config MIPS_GENERIC_KERNEL
bool "Generic board-agnostic MIPS kernel" bool "Generic board-agnostic MIPS kernel"
select ARCH_HAS_SETUP_DMA_OPS
select MIPS_GENERIC select MIPS_GENERIC
select BOOT_RAW select BOOT_RAW
select BUILTIN_DTB select BUILTIN_DTB
...@@ -488,7 +485,6 @@ config MACH_LOONGSON64 ...@@ -488,7 +485,6 @@ config MACH_LOONGSON64
select BOARD_SCACHE select BOARD_SCACHE
select CSRC_R4K select CSRC_R4K
select CEVT_R4K select CEVT_R4K
select CPU_HAS_WB
select FORCE_PCI select FORCE_PCI
select ISA select ISA
select I8259 select I8259
...@@ -565,7 +561,6 @@ config MIPS_MALTA ...@@ -565,7 +561,6 @@ config MIPS_MALTA
select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_MICROMIPS select SYS_SUPPORTS_MICROMIPS
select SYS_SUPPORTS_MIPS16 select SYS_SUPPORTS_MIPS16
select SYS_SUPPORTS_MIPS_CMP
select SYS_SUPPORTS_MIPS_CPS select SYS_SUPPORTS_MIPS_CPS
select SYS_SUPPORTS_MULTITHREADING select SYS_SUPPORTS_MULTITHREADING
select SYS_SUPPORTS_RELOCATABLE select SYS_SUPPORTS_RELOCATABLE
...@@ -793,24 +788,6 @@ config SGI_IP32 ...@@ -793,24 +788,6 @@ config SGI_IP32
help help
If you want this kernel to run on SGI O2 workstation, say Y here. If you want this kernel to run on SGI O2 workstation, say Y here.
config SIBYTE_CRHINE
bool "Sibyte BCM91120C-CRhine"
select BOOT_ELF32
select SIBYTE_BCM1120
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
config SIBYTE_CARMEL
bool "Sibyte BCM91120x-Carmel"
select BOOT_ELF32
select SIBYTE_BCM1120
select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_LITTLE_ENDIAN
config SIBYTE_CRHONE config SIBYTE_CRHONE
bool "Sibyte BCM91125C-CRhone" bool "Sibyte BCM91125C-CRhone"
select BOOT_ELF32 select BOOT_ELF32
...@@ -824,7 +801,7 @@ config SIBYTE_CRHONE ...@@ -824,7 +801,7 @@ config SIBYTE_CRHONE
config SIBYTE_RHONE config SIBYTE_RHONE
bool "Sibyte BCM91125E-Rhone" bool "Sibyte BCM91125E-Rhone"
select BOOT_ELF32 select BOOT_ELF32
select SIBYTE_BCM1125H select SIBYTE_SB1250
select SWAP_IO_SPACE select SWAP_IO_SPACE
select SYS_HAS_CPU_SB1 select SYS_HAS_CPU_SB1
select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_BIG_ENDIAN
...@@ -1075,7 +1052,7 @@ config FW_CFE ...@@ -1075,7 +1052,7 @@ config FW_CFE
bool bool
config ARCH_SUPPORTS_UPROBES config ARCH_SUPPORTS_UPROBES
bool def_bool y
config DMA_NONCOHERENT config DMA_NONCOHERENT
bool bool
...@@ -1086,8 +1063,10 @@ config DMA_NONCOHERENT ...@@ -1086,8 +1063,10 @@ config DMA_NONCOHERENT
# by pgprot_writcombine can be mixed, and the latter sometimes provides # by pgprot_writcombine can be mixed, and the latter sometimes provides
# significant advantages. # significant advantages.
# #
select ARCH_HAS_SETUP_DMA_OPS
select ARCH_HAS_DMA_WRITE_COMBINE select ARCH_HAS_DMA_WRITE_COMBINE
select ARCH_HAS_DMA_PREP_COHERENT select ARCH_HAS_DMA_PREP_COHERENT
select ARCH_HAS_SYNC_DMA_FOR_CPU
select ARCH_HAS_SYNC_DMA_FOR_DEVICE select ARCH_HAS_SYNC_DMA_FOR_DEVICE
select ARCH_HAS_DMA_SET_UNCACHED select ARCH_HAS_DMA_SET_UNCACHED
select DMA_NONCOHERENT_MMAP select DMA_NONCOHERENT_MMAP
...@@ -1181,12 +1160,6 @@ config SYS_SUPPORTS_LITTLE_ENDIAN ...@@ -1181,12 +1160,6 @@ config SYS_SUPPORTS_LITTLE_ENDIAN
config MIPS_HUGE_TLB_SUPPORT config MIPS_HUGE_TLB_SUPPORT
def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
config IRQ_MSP_SLP
bool
config IRQ_MSP_CIC
bool
config IRQ_TXX9 config IRQ_TXX9
bool bool
...@@ -1364,7 +1337,6 @@ config CPU_LOONGSON2F ...@@ -1364,7 +1337,6 @@ config CPU_LOONGSON2F
bool "Loongson 2F" bool "Loongson 2F"
depends on SYS_HAS_CPU_LOONGSON2F depends on SYS_HAS_CPU_LOONGSON2F
select CPU_LOONGSON2EF select CPU_LOONGSON2EF
select GPIOLIB
help help
The Loongson 2F processor implements the MIPS III instruction set The Loongson 2F processor implements the MIPS III instruction set
with many extensions. with many extensions.
...@@ -1786,7 +1758,6 @@ config CPU_LOONGSON2EF ...@@ -1786,7 +1758,6 @@ config CPU_LOONGSON2EF
select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_HUGEPAGES select CPU_SUPPORTS_HUGEPAGES
select ARCH_HAS_PHYS_TO_DMA
config CPU_LOONGSON32 config CPU_LOONGSON32
bool bool
...@@ -1851,11 +1822,9 @@ config SYS_HAS_CPU_MIPS32_R3_5 ...@@ -1851,11 +1822,9 @@ config SYS_HAS_CPU_MIPS32_R3_5
config SYS_HAS_CPU_MIPS32_R5 config SYS_HAS_CPU_MIPS32_R5
bool bool
select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
config SYS_HAS_CPU_MIPS32_R6 config SYS_HAS_CPU_MIPS32_R6
bool bool
select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
config SYS_HAS_CPU_MIPS64_R1 config SYS_HAS_CPU_MIPS64_R1
bool bool
...@@ -1865,15 +1834,12 @@ config SYS_HAS_CPU_MIPS64_R2 ...@@ -1865,15 +1834,12 @@ config SYS_HAS_CPU_MIPS64_R2
config SYS_HAS_CPU_MIPS64_R5 config SYS_HAS_CPU_MIPS64_R5
bool bool
select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
config SYS_HAS_CPU_MIPS64_R6 config SYS_HAS_CPU_MIPS64_R6
bool bool
select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
config SYS_HAS_CPU_P5600 config SYS_HAS_CPU_P5600
bool bool
select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
config SYS_HAS_CPU_R3000 config SYS_HAS_CPU_R3000
bool bool
...@@ -1898,7 +1864,6 @@ config SYS_HAS_CPU_NEVADA ...@@ -1898,7 +1864,6 @@ config SYS_HAS_CPU_NEVADA
config SYS_HAS_CPU_R10000 config SYS_HAS_CPU_R10000
bool bool
select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
config SYS_HAS_CPU_RM7000 config SYS_HAS_CPU_RM7000
bool bool
...@@ -1927,7 +1892,6 @@ config SYS_HAS_CPU_BMIPS4380 ...@@ -1927,7 +1892,6 @@ config SYS_HAS_CPU_BMIPS4380
config SYS_HAS_CPU_BMIPS5000 config SYS_HAS_CPU_BMIPS5000
bool bool
select SYS_HAS_CPU_BMIPS select SYS_HAS_CPU_BMIPS
select ARCH_HAS_SYNC_DMA_FOR_CPU
# #
# CPU may reorder R->R, R->W, W->R, W->W # CPU may reorder R->R, R->W, W->R, W->W
...@@ -2298,15 +2262,10 @@ config MIPS_VPE_LOADER ...@@ -2298,15 +2262,10 @@ config MIPS_VPE_LOADER
Includes a loader for loading an elf relocatable object Includes a loader for loading an elf relocatable object
onto another VPE and running it. onto another VPE and running it.
config MIPS_VPE_LOADER_CMP
bool
default "y"
depends on MIPS_VPE_LOADER && MIPS_CMP
config MIPS_VPE_LOADER_MT config MIPS_VPE_LOADER_MT
bool bool
default "y" default "y"
depends on MIPS_VPE_LOADER && !MIPS_CMP depends on MIPS_VPE_LOADER
config MIPS_VPE_LOADER_TOM config MIPS_VPE_LOADER_TOM
bool "Load VPE program into memory hidden from linux" bool "Load VPE program into memory hidden from linux"
...@@ -2322,31 +2281,10 @@ config MIPS_VPE_APSP_API ...@@ -2322,31 +2281,10 @@ config MIPS_VPE_APSP_API
bool "Enable support for AP/SP API (RTLX)" bool "Enable support for AP/SP API (RTLX)"
depends on MIPS_VPE_LOADER depends on MIPS_VPE_LOADER
config MIPS_VPE_APSP_API_CMP
bool
default "y"
depends on MIPS_VPE_APSP_API && MIPS_CMP
config MIPS_VPE_APSP_API_MT config MIPS_VPE_APSP_API_MT
bool bool
default "y" default "y"
depends on MIPS_VPE_APSP_API && !MIPS_CMP depends on MIPS_VPE_APSP_API
config MIPS_CMP
bool "MIPS CMP framework support (DEPRECATED)"
depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
select SMP
select SYNC_R4K
select SYS_SUPPORTS_SMP
select WEAK_ORDERING
default n
help
Select this if you are using a bootloader which implements the "CMP
framework" protocol (ie. YAMON) and want your kernel to make use of
its ability to start secondary CPUs.
Unless you have a specific need, you should use CONFIG_MIPS_CPS
instead of this.
config MIPS_CPS config MIPS_CPS
bool "MIPS Coherent Processing System support" bool "MIPS Coherent Processing System support"
...@@ -2802,9 +2740,6 @@ config HOTPLUG_CPU ...@@ -2802,9 +2740,6 @@ config HOTPLUG_CPU
config SMP_UP config SMP_UP
bool bool
config SYS_SUPPORTS_MIPS_CMP
bool
config SYS_SUPPORTS_MIPS_CPS config SYS_SUPPORTS_MIPS_CPS
bool bool
......
...@@ -181,9 +181,47 @@ endif ...@@ -181,9 +181,47 @@ endif
cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1 cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
cflags-$(CONFIG_CPU_BMIPS) += -march=mips32 -Wa,-mips32 -Wa,--trap cflags-$(CONFIG_CPU_BMIPS) += -march=mips32 -Wa,-mips32 -Wa,--trap
cflags-$(CONFIG_CPU_LOONGSON2E) += -march=loongson2e -Wa,--trap
cflags-$(CONFIG_CPU_LOONGSON2F) += -march=loongson2f -Wa,--trap
# Some -march= flags enable MMI instructions, and GCC complains about that
# support being enabled alongside -msoft-float. Thus explicitly disable MMI.
cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call cc-option,-mno-loongson-mmi)
ifdef CONFIG_CPU_LOONGSON64
cflags-$(CONFIG_CPU_LOONGSON64) += -Wa,--trap
cflags-$(CONFIG_CC_IS_GCC) += -march=loongson3a
cflags-$(CONFIG_CC_IS_CLANG) += -march=mips64r2
endif
cflags-$(CONFIG_CPU_LOONGSON64) += $(call cc-option,-mno-loongson-mmi)
cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)
cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,) cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,)
ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa,-mfix-loongson2f-nop
cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa,-mfix-loongson2f-jump
endif
#
# Some versions of binutils, not currently mainline as of 2019/02/04, support
# an -mfix-loongson3-llsc flag which emits a sync prior to each ll instruction
# to work around a CPU bug (see __SYNC_loongson3_war in asm/sync.h for a
# description).
#
# We disable this in order to prevent the assembler meddling with the
# instruction that labels refer to, ie. if we label an ll instruction:
#
# 1: ll v0, 0(a0)
#
# ...then with the assembler fix applied the label may actually point at a sync
# instruction inserted by the assembler, and if we were using the label in an
# exception table the table would no longer contain the address of the ll
# instruction.
#
# Avoid this by explicitly disabling that assembler behaviour. If upstream
# binutils does not merge support for the flag then we can revisit & remove
# this later - for now it ensures vendor toolchains don't cause problems.
#
cflags-$(CONFIG_CPU_LOONGSON64) += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
# For smartmips configurations, there are hundreds of warnings due to ISA overrides # For smartmips configurations, there are hundreds of warnings due to ISA overrides
# in assembly and header files. smartmips is only supported for MIPS32r1 onwards # in assembly and header files. smartmips is only supported for MIPS32r1 onwards
......
...@@ -29,20 +29,4 @@ config SOC_QCA955X ...@@ -29,20 +29,4 @@ config SOC_QCA955X
config PCI_AR724X config PCI_AR724X
def_bool n def_bool n
config ATH79_DEV_GPIO_BUTTONS
def_bool n
config ATH79_DEV_LEDS_GPIO
def_bool n
config ATH79_DEV_SPI
def_bool n
config ATH79_DEV_USB
def_bool n
config ATH79_DEV_WMAC
depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
def_bool n
endif endif
...@@ -193,6 +193,7 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = { ...@@ -193,6 +193,7 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = {
/* boardtype, boardnum, boardrev */ /* boardtype, boardnum, boardrev */
static const static const
struct bcm47xx_board_type_list3 bcm47xx_board_list_board[] __initconst = { struct bcm47xx_board_type_list3 bcm47xx_board_list_board[] __initconst = {
{{BCM47XX_BOARD_HUAWEI_B593U_12, "Huawei B593u-12"}, "0x053d", "1234", "0x1301"},
{{BCM47XX_BOARD_HUAWEI_E970, "Huawei E970"}, "0x048e", "0x5347", "0x11"}, {{BCM47XX_BOARD_HUAWEI_E970, "Huawei E970"}, "0x048e", "0x5347", "0x11"},
{{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"}, {{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"},
{{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"}, {{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"},
......
...@@ -222,6 +222,11 @@ bcm47xx_leds_dlink_dir330[] __initconst = { ...@@ -222,6 +222,11 @@ bcm47xx_leds_dlink_dir330[] __initconst = {
/* Huawei */ /* Huawei */
static const struct gpio_led
bcm47xx_leds_huawei_b593u_12[] __initconst = {
BCM47XX_GPIO_LED(5, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
};
static const struct gpio_led static const struct gpio_led
bcm47xx_leds_huawei_e970[] __initconst = { bcm47xx_leds_huawei_e970[] __initconst = {
BCM47XX_GPIO_LED(0, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), BCM47XX_GPIO_LED(0, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
...@@ -672,6 +677,9 @@ void __init bcm47xx_leds_register(void) ...@@ -672,6 +677,9 @@ void __init bcm47xx_leds_register(void)
bcm47xx_set_pdata(bcm47xx_leds_dlink_dir330); bcm47xx_set_pdata(bcm47xx_leds_dlink_dir330);
break; break;
case BCM47XX_BOARD_HUAWEI_B593U_12:
bcm47xx_set_pdata(bcm47xx_leds_huawei_b593u_12);
break;
case BCM47XX_BOARD_HUAWEI_E970: case BCM47XX_BOARD_HUAWEI_E970:
bcm47xx_set_pdata(bcm47xx_leds_huawei_e970); bcm47xx_set_pdata(bcm47xx_leds_huawei_e970);
break; break;
......
...@@ -14,7 +14,8 @@ config CAVIUM_CN63XXP1 ...@@ -14,7 +14,8 @@ config CAVIUM_CN63XXP1
config CAVIUM_OCTEON_CVMSEG_SIZE config CAVIUM_OCTEON_CVMSEG_SIZE
int "Number of L1 cache lines reserved for CVMSEG memory" int "Number of L1 cache lines reserved for CVMSEG memory"
range 0 54 range 0 54
default 1 default 0 if !CAVIUM_OCTEON_SOC
default 1 if CAVIUM_OCTEON_SOC
help help
CVMSEG LM is a segment that accesses portions of the dcache as a CVMSEG LM is a segment that accesses portions of the dcache as a
local memory; the larger CVMSEG is, the smaller the cache is. local memory; the larger CVMSEG is, the smaller the cache is.
......
...@@ -2290,7 +2290,7 @@ static irqreturn_t octeon_irq_cib_handler(int my_irq, void *data) ...@@ -2290,7 +2290,7 @@ static irqreturn_t octeon_irq_cib_handler(int my_irq, void *data)
static int __init octeon_irq_init_cib(struct device_node *ciu_node, static int __init octeon_irq_init_cib(struct device_node *ciu_node,
struct device_node *parent) struct device_node *parent)
{ {
const __be32 *addr; struct resource res;
u32 val; u32 val;
struct octeon_irq_cib_host_data *host_data; struct octeon_irq_cib_host_data *host_data;
int parent_irq; int parent_irq;
...@@ -2309,21 +2309,19 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node, ...@@ -2309,21 +2309,19 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
return -ENOMEM; return -ENOMEM;
raw_spin_lock_init(&host_data->lock); raw_spin_lock_init(&host_data->lock);
addr = of_get_address(ciu_node, 0, NULL, NULL); r = of_address_to_resource(ciu_node, 0, &res);
if (!addr) { if (r) {
pr_err("ERROR: Couldn't acquire reg(0) %pOFn\n", ciu_node); pr_err("ERROR: Couldn't acquire reg(0) %pOFn\n", ciu_node);
return -EINVAL; return r;
} }
host_data->raw_reg = (u64)phys_to_virt( host_data->raw_reg = (u64)phys_to_virt(res.start);
of_translate_address(ciu_node, addr));
addr = of_get_address(ciu_node, 1, NULL, NULL); r = of_address_to_resource(ciu_node, 1, &res);
if (!addr) { if (r) {
pr_err("ERROR: Couldn't acquire reg(1) %pOFn\n", ciu_node); pr_err("ERROR: Couldn't acquire reg(1) %pOFn\n", ciu_node);
return -EINVAL; return r;
} }
host_data->en_reg = (u64)phys_to_virt( host_data->en_reg = (u64)phys_to_virt(res.start);
of_translate_address(ciu_node, addr));
r = of_property_read_u32(ciu_node, "cavium,max-bits", &val); r = of_property_read_u32(ciu_node, "cavium,max-bits", &val);
if (r) { if (r) {
...@@ -2874,11 +2872,11 @@ static struct irq_chip octeon_irq_chip_ciu3_mbox = { ...@@ -2874,11 +2872,11 @@ static struct irq_chip octeon_irq_chip_ciu3_mbox = {
static int __init octeon_irq_init_ciu3(struct device_node *ciu_node, static int __init octeon_irq_init_ciu3(struct device_node *ciu_node,
struct device_node *parent) struct device_node *parent)
{ {
int i; int i, ret;
int node; int node;
struct irq_domain *domain; struct irq_domain *domain;
struct octeon_ciu3_info *ciu3_info; struct octeon_ciu3_info *ciu3_info;
const __be32 *zero_addr; struct resource res;
u64 base_addr; u64 base_addr;
union cvmx_ciu3_const consts; union cvmx_ciu3_const consts;
...@@ -2888,14 +2886,11 @@ static int __init octeon_irq_init_ciu3(struct device_node *ciu_node, ...@@ -2888,14 +2886,11 @@ static int __init octeon_irq_init_ciu3(struct device_node *ciu_node,
if (!ciu3_info) if (!ciu3_info)
return -ENOMEM; return -ENOMEM;
zero_addr = of_get_address(ciu_node, 0, NULL, NULL); ret = of_address_to_resource(ciu_node, 0, &res);
if (WARN_ON(!zero_addr)) if (WARN_ON(ret))
return -EINVAL; return ret;
base_addr = of_translate_address(ciu_node, zero_addr);
base_addr = (u64)phys_to_virt(base_addr);
ciu3_info->ciu3_addr = base_addr; ciu3_info->ciu3_addr = base_addr = (u64)phys_to_virt(res.start);
ciu3_info->node = node; ciu3_info->node = node;
consts.u64 = cvmx_read_csr(base_addr + CIU3_CONST); consts.u64 = cvmx_read_csr(base_addr + CIU3_CONST);
......
CONFIG_COMMON_CLK=y
CONFIG_GOLDFISH=y
CONFIG_GOLDFISH_PIC=y
CONFIG_PCI=y
CONFIG_PCI_MSI=y
CONFIG_PCI_HOST_GENERIC=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_SYSCON_REBOOT_MODE=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_GOLDFISH=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_MTD=y
CONFIG_MTD_CFI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_XHCI_HCD=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_MMIO=y
CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_BLK=y
CONFIG_VIRTIO_NET=y
CONFIG_NET_9P=y
CONFIG_NET_9P_VIRTIO=y
...@@ -53,7 +53,7 @@ char *fw_getenv(char *envname) ...@@ -53,7 +53,7 @@ char *fw_getenv(char *envname)
{ {
char *result = NULL; char *result = NULL;
if (_fw_envp != NULL) { if (_fw_envp != NULL && fw_envp(0) != NULL) {
/* /*
* Return a pointer to the given environment variable. * Return a pointer to the given environment variable.
* YAMON uses "name", "value" pairs, while U-Boot uses * YAMON uses "name", "value" pairs, while U-Boot uses
......
...@@ -45,12 +45,12 @@ ...@@ -45,12 +45,12 @@
#endif #endif
#ifdef CONFIG_CPU_HAS_DIEI #ifdef CONFIG_CPU_HAS_DIEI
.macro local_irq_enable reg=t0 .macro local_irq_enable
ei ei
irq_enable_hazard irq_enable_hazard
.endm .endm
.macro local_irq_disable reg=t0 .macro local_irq_disable
di di
irq_disable_hazard irq_disable_hazard
.endm .endm
......
...@@ -24,13 +24,7 @@ extern void check_bugs64_early(void); ...@@ -24,13 +24,7 @@ extern void check_bugs64_early(void);
extern void check_bugs32(void); extern void check_bugs32(void);
extern void check_bugs64(void); extern void check_bugs64(void);
static inline void check_bugs_early(void) static inline void __init check_bugs(void)
{
if (IS_ENABLED(CONFIG_CPU_R4X00_BUGS64))
check_bugs64_early();
}
static inline void check_bugs(void)
{ {
unsigned int cpu = smp_processor_id(); unsigned int cpu = smp_processor_id();
......
...@@ -16,4 +16,6 @@ ...@@ -16,4 +16,6 @@
#define __read_mostly __section(".data..read_mostly") #define __read_mostly __section(".data..read_mostly")
extern void cache_noop(void);
#endif /* _ASM_CACHE_H */ #endif /* _ASM_CACHE_H */
...@@ -110,7 +110,6 @@ extern void copy_from_user_page(struct vm_area_struct *vma, ...@@ -110,7 +110,6 @@ extern void copy_from_user_page(struct vm_area_struct *vma,
unsigned long len); unsigned long len);
extern void (*flush_icache_all)(void); extern void (*flush_icache_all)(void);
extern void (*local_flush_data_cache_page)(void * addr);
extern void (*flush_data_cache_page)(unsigned long addr); extern void (*flush_data_cache_page)(unsigned long addr);
/* Run kernel code uncached, useful for cache probing functions. */ /* Run kernel code uncached, useful for cache probing functions. */
......
...@@ -118,10 +118,27 @@ ...@@ -118,10 +118,27 @@
#define cpu_has_3k_cache __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE) #define cpu_has_3k_cache __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE)
#endif #endif
#ifndef cpu_has_4k_cache #ifndef cpu_has_4k_cache
#define cpu_has_4k_cache __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE) #define cpu_has_4k_cache __opt(MIPS_CPU_4K_CACHE)
#endif #endif
#ifndef cpu_has_octeon_cache #ifndef cpu_has_octeon_cache
#define cpu_has_octeon_cache 0 #define cpu_has_octeon_cache \
({ \
int __res; \
\
switch (current_cpu_type()) { \
case CPU_CAVIUM_OCTEON: \
case CPU_CAVIUM_OCTEON_PLUS: \
case CPU_CAVIUM_OCTEON2: \
case CPU_CAVIUM_OCTEON3: \
__res = 1; \
break; \
\
default: \
__res = 0; \
} \
\
__res; \
})
#endif #endif
/* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */ /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */
#ifndef cpu_has_fpu #ifndef cpu_has_fpu
......
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* This file contains the MIPS architecture specific IDE code.
*/
#ifndef __ASM_IDE_H
#define __ASM_IDE_H
#include <ide.h>
#endif /* __ASM_IDE_H */
...@@ -210,7 +210,7 @@ void iounmap(const volatile void __iomem *addr); ...@@ -210,7 +210,7 @@ void iounmap(const volatile void __iomem *addr);
#define ioremap_wc(offset, size) \ #define ioremap_wc(offset, size) \
ioremap_prot((offset), (size), boot_cpu_data.writecombine) ioremap_prot((offset), (size), boot_cpu_data.writecombine)
#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64) #if defined(CONFIG_CPU_CAVIUM_OCTEON)
#define war_io_reorder_wmb() wmb() #define war_io_reorder_wmb() wmb()
#else #else
#define war_io_reorder_wmb() barrier() #define war_io_reorder_wmb() barrier()
......
...@@ -53,6 +53,7 @@ enum bcm47xx_board { ...@@ -53,6 +53,7 @@ enum bcm47xx_board {
BCM47XX_BOARD_DLINK_DIR130, BCM47XX_BOARD_DLINK_DIR130,
BCM47XX_BOARD_DLINK_DIR330, BCM47XX_BOARD_DLINK_DIR330,
BCM47XX_BOARD_HUAWEI_B593U_12,
BCM47XX_BOARD_HUAWEI_E970, BCM47XX_BOARD_HUAWEI_E970,
BCM47XX_BOARD_LINKSYS_E900V1, BCM47XX_BOARD_LINKSYS_E900V1,
......
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994-1996 Linus Torvalds & authors
*
* Copied from i386; many of the especially older MIPS or ISA-based platforms
* are basically identical. Using this file probably implies i8259 PIC
* support in a system but the very least interrupt numbers 0 - 15 need to
* be put aside for legacy devices.
*/
#ifndef __ASM_MACH_GENERIC_IDE_H
#define __ASM_MACH_GENERIC_IDE_H
#ifdef __KERNEL__
#include <linux/pci.h>
#include <linux/stddef.h>
#include <asm/processor.h>
/* MIPS port and memory-mapped I/O string operations. */
static inline void __ide_flush_prologue(void)
{
#ifdef CONFIG_SMP
if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
preempt_disable();
#endif
}
static inline void __ide_flush_epilogue(void)
{
#ifdef CONFIG_SMP
if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
preempt_enable();
#endif
}
static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
{
if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) {
unsigned long end = addr + size;
while (addr < end) {
local_flush_data_cache_page((void *)addr);
addr += PAGE_SIZE;
}
}
}
/*
* insw() and gang might be called with interrupts disabled, so we can't
* send IPIs for flushing due to the potencial of deadlocks, see the comment
* above smp_call_function() in arch/mips/kernel/smp.c. We work around the
* problem by disabling preemption so we know we actually perform the flush
* on the processor that actually has the lines to be flushed which hopefully
* is even better for performance anyway.
*/
static inline void __ide_insw(unsigned long port, void *addr,
unsigned int count)
{
__ide_flush_prologue();
insw(port, addr, count);
__ide_flush_dcache_range((unsigned long)addr, count * 2);
__ide_flush_epilogue();
}
static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
{
__ide_flush_prologue();
insl(port, addr, count);
__ide_flush_dcache_range((unsigned long)addr, count * 4);
__ide_flush_epilogue();
}
static inline void __ide_outsw(unsigned long port, const void *addr,
unsigned long count)
{
__ide_flush_prologue();
outsw(port, addr, count);
__ide_flush_dcache_range((unsigned long)addr, count * 2);
__ide_flush_epilogue();
}
static inline void __ide_outsl(unsigned long port, const void *addr,
unsigned long count)
{
__ide_flush_prologue();
outsl(port, addr, count);
__ide_flush_dcache_range((unsigned long)addr, count * 4);
__ide_flush_epilogue();
}
static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count)
{
__ide_flush_prologue();
readsw(port, addr, count);
__ide_flush_dcache_range((unsigned long)addr, count * 2);
__ide_flush_epilogue();
}
static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count)
{
__ide_flush_prologue();
readsl(port, addr, count);
__ide_flush_dcache_range((unsigned long)addr, count * 4);
__ide_flush_epilogue();
}
static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count)
{
__ide_flush_prologue();
writesw(port, addr, count);
__ide_flush_dcache_range((unsigned long)addr, count * 2);
__ide_flush_epilogue();
}
static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count)
{
__ide_flush_prologue();
writesl(port, addr, count);
__ide_flush_dcache_range((unsigned long)addr, count * 4);
__ide_flush_epilogue();
}
/* ide_insw calls insw, not __ide_insw. Why? */
#undef insw
#undef insl
#undef outsw
#undef outsl
#define insw(port, addr, count) __ide_insw(port, addr, count)
#define insl(port, addr, count) __ide_insl(port, addr, count)
#define outsw(port, addr, count) __ide_outsw(port, addr, count)
#define outsl(port, addr, count) __ide_outsl(port, addr, count)
#endif /* __KERNEL__ */
#endif /* __ASM_MACH_GENERIC_IDE_H */
...@@ -94,9 +94,6 @@ extern __iomem void *ltq_cgu_membase; ...@@ -94,9 +94,6 @@ extern __iomem void *ltq_cgu_membase;
#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000) #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
#define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344)) #define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
/* allow booting xrx200 phys */
int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr);
/* request a non-gpio and set the PIO config */ /* request a non-gpio and set the PIO config */
#define PMU_PPE BIT(13) #define PMU_PPE BIT(13)
extern void ltq_pmu_enable(unsigned int module); extern void ltq_pmu_enable(unsigned int module);
......
...@@ -11,7 +11,8 @@ ...@@ -11,7 +11,8 @@
#ifndef _MT7620_REGS_H_ #ifndef _MT7620_REGS_H_
#define _MT7620_REGS_H_ #define _MT7620_REGS_H_
#define MT7620_SYSC_BASE 0x10000000 #define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x)))
#define MT7620_SYSC_BASE IOMEM(0x10000000)
#define SYSC_REG_CHIP_NAME0 0x00 #define SYSC_REG_CHIP_NAME0 0x00
#define SYSC_REG_CHIP_NAME1 0x04 #define SYSC_REG_CHIP_NAME1 0x04
......
...@@ -11,7 +11,8 @@ ...@@ -11,7 +11,8 @@
#ifndef _RT288X_REGS_H_ #ifndef _RT288X_REGS_H_
#define _RT288X_REGS_H_ #define _RT288X_REGS_H_
#define RT2880_SYSC_BASE 0x00300000 #define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x)))
#define RT2880_SYSC_BASE IOMEM(0x00300000)
#define SYSC_REG_CHIP_NAME0 0x00 #define SYSC_REG_CHIP_NAME0 0x00
#define SYSC_REG_CHIP_NAME1 0x04 #define SYSC_REG_CHIP_NAME1 0x04
......
...@@ -43,7 +43,8 @@ static inline int soc_is_rt5350(void) ...@@ -43,7 +43,8 @@ static inline int soc_is_rt5350(void)
return ralink_soc == RT305X_SOC_RT5350; return ralink_soc == RT305X_SOC_RT5350;
} }
#define RT305X_SYSC_BASE 0x10000000 #define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x)))
#define RT305X_SYSC_BASE IOMEM(0x10000000)
#define SYSC_REG_CHIP_NAME0 0x00 #define SYSC_REG_CHIP_NAME0 0x00
#define SYSC_REG_CHIP_NAME1 0x04 #define SYSC_REG_CHIP_NAME1 0x04
......
...@@ -10,8 +10,10 @@ ...@@ -10,8 +10,10 @@
#include <linux/bitops.h> #include <linux/bitops.h>
#define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x)))
#define RT3883_SDRAM_BASE 0x00000000 #define RT3883_SDRAM_BASE 0x00000000
#define RT3883_SYSC_BASE 0x10000000 #define RT3883_SYSC_BASE IOMEM(0x10000000)
#define RT3883_TIMER_BASE 0x10000100 #define RT3883_TIMER_BASE 0x10000100
#define RT3883_INTC_BASE 0x10000200 #define RT3883_INTC_BASE 0x10000200
#define RT3883_MEMC_BASE 0x10000300 #define RT3883_MEMC_BASE 0x10000300
......
...@@ -280,6 +280,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) ...@@ -280,6 +280,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
#define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED) #define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)
#define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \ #define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \
_PAGE_SOFT_DIRTY | _PFN_MASK | _CACHE_MASK) _PAGE_SOFT_DIRTY | _PFN_MASK | \
_CACHE_MASK | _PAGE_SPECIAL)
#endif /* _ASM_PGTABLE_BITS_H */ #endif /* _ASM_PGTABLE_BITS_H */
...@@ -202,11 +202,13 @@ struct octeon_cop2_state { ...@@ -202,11 +202,13 @@ struct octeon_cop2_state {
#define COP2_INIT \ #define COP2_INIT \
.cp2 = {0,}, .cp2 = {0,},
#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
struct octeon_cvmseg_state { struct octeon_cvmseg_state {
unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE] unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
[cpu_dcache_line_size() / sizeof(unsigned long)]; [cpu_dcache_line_size() / sizeof(unsigned long)];
}; };
#endif
#else #else
#define COP2_INIT #define COP2_INIT
#endif #endif
...@@ -263,7 +265,10 @@ struct thread_struct { ...@@ -263,7 +265,10 @@ struct thread_struct {
unsigned long trap_nr; unsigned long trap_nr;
#ifdef CONFIG_CPU_CAVIUM_OCTEON #ifdef CONFIG_CPU_CAVIUM_OCTEON
struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
#endif
#endif #endif
struct mips_abi *abi; struct mips_abi *abi;
}; };
......
...@@ -81,7 +81,6 @@ struct rtlx_channel { ...@@ -81,7 +81,6 @@ struct rtlx_channel {
extern struct rtlx_info { extern struct rtlx_info {
unsigned long id; unsigned long id;
enum rtlx_state state; enum rtlx_state state;
int ap_int_pending; /* Status of 0 or 1 for CONFIG_MIPS_CMP only */
struct rtlx_channel channel[RTLX_CHANNELS]; struct rtlx_channel channel[RTLX_CHANNELS];
} *rtlx; } *rtlx;
......
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
#define _SIBYTE_BOARD_H #define _SIBYTE_BOARD_H
#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_CRHONE) || \ #if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_CRHONE) || \
defined(CONFIG_SIBYTE_CRHINE) || defined(CONFIG_SIBYTE_LITTLESUR) defined(CONFIG_SIBYTE_LITTLESUR)
#include <asm/sibyte/swarm.h> #include <asm/sibyte/swarm.h>
#endif #endif
...@@ -15,10 +15,6 @@ ...@@ -15,10 +15,6 @@
#include <asm/sibyte/sentosa.h> #include <asm/sibyte/sentosa.h>
#endif #endif
#ifdef CONFIG_SIBYTE_CARMEL
#include <asm/sibyte/carmel.h>
#endif
#ifdef CONFIG_SIBYTE_BIGSUR #ifdef CONFIG_SIBYTE_BIGSUR
#include <asm/sibyte/bigsur.h> #include <asm/sibyte/bigsur.h>
#endif #endif
......
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2002 Broadcom Corporation
*/
#ifndef __ASM_SIBYTE_CARMEL_H
#define __ASM_SIBYTE_CARMEL_H
#include <asm/sibyte/sb1250.h>
#include <asm/sibyte/sb1250_int.h>
#define SIBYTE_BOARD_NAME "Carmel"
#define GPIO_PHY_INTERRUPT 2
#define GPIO_NONMASKABLE_INT 3
#define GPIO_CF_INSERTED 6
#define GPIO_MONTEREY_RESET 7
#define GPIO_QUADUART_INT 8
#define GPIO_CF_INT 9
#define GPIO_FPGA_CCLK 10
#define GPIO_FPGA_DOUT 11
#define GPIO_FPGA_DIN 12
#define GPIO_FPGA_PGM 13
#define GPIO_FPGA_DONE 14
#define GPIO_FPGA_INIT 15
#define LEDS_CS 2
#define LEDS_PHYS 0x100C0000
#define MLEDS_CS 3
#define MLEDS_PHYS 0x100A0000
#define UART_CS 4
#define UART_PHYS 0x100D0000
#define ARAVALI_CS 5
#define ARAVALI_PHYS 0x11000000
#define IDE_CS 6
#define IDE_PHYS 0x100B0000
#define ARAVALI2_CS 7
#define ARAVALI2_PHYS 0x100E0000
#if defined(CONFIG_SIBYTE_CARMEL)
#define K_GPIO_GB_IDE 9
#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE)
#endif
#endif /* __ASM_SIBYTE_CARMEL_H */
...@@ -24,11 +24,6 @@ ...@@ -24,11 +24,6 @@
#define SIBYTE_HAVE_PCMCIA 0 #define SIBYTE_HAVE_PCMCIA 0
#define SIBYTE_HAVE_IDE 0 #define SIBYTE_HAVE_IDE 0
#endif #endif
#ifdef CONFIG_SIBYTE_CRHINE
#define SIBYTE_BOARD_NAME "BCM91120C (CRhine)"
#define SIBYTE_HAVE_PCMCIA 0
#define SIBYTE_HAVE_IDE 0
#endif
/* Generic bus chip selects */ /* Generic bus chip selects */
#define LEDS_CS 3 #define LEDS_CS 3
......
...@@ -80,22 +80,6 @@ static inline int register_up_smp_ops(void) ...@@ -80,22 +80,6 @@ static inline int register_up_smp_ops(void)
#endif #endif
} }
static inline int register_cmp_smp_ops(void)
{
#ifdef CONFIG_MIPS_CMP
extern const struct plat_smp_ops cmp_smp_ops;
if (!mips_cm_present())
return -ENODEV;
register_smp_ops(&cmp_smp_ops);
return 0;
#else
return -ENODEV;
#endif
}
static inline int register_vsmp_smp_ops(void) static inline int register_vsmp_smp_ops(void)
{ {
#ifdef CONFIG_MIPS_MT_SMP #ifdef CONFIG_MIPS_MT_SMP
......
...@@ -29,12 +29,8 @@ ...@@ -29,12 +29,8 @@
static inline int aprp_cpu_index(void) static inline int aprp_cpu_index(void)
{ {
#ifdef CONFIG_MIPS_CMP
return setup_max_cpus;
#else
extern int tclimit; extern int tclimit;
return tclimit; return tclimit;
#endif
} }
enum vpe_state { enum vpe_state {
......
...@@ -58,16 +58,13 @@ obj-$(CONFIG_CPU_BMIPS) += smp-bmips.o bmips_vec.o bmips_5xxx_init.o ...@@ -58,16 +58,13 @@ obj-$(CONFIG_CPU_BMIPS) += smp-bmips.o bmips_vec.o bmips_5xxx_init.o
obj-$(CONFIG_MIPS_MT) += mips-mt.o obj-$(CONFIG_MIPS_MT) += mips-mt.o
obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o
obj-$(CONFIG_MIPS_MT_SMP) += smp-mt.o obj-$(CONFIG_MIPS_MT_SMP) += smp-mt.o
obj-$(CONFIG_MIPS_CMP) += smp-cmp.o
obj-$(CONFIG_MIPS_CPS) += smp-cps.o cps-vec.o obj-$(CONFIG_MIPS_CPS) += smp-cps.o cps-vec.o
obj-$(CONFIG_MIPS_CPS_NS16550) += cps-vec-ns16550.o obj-$(CONFIG_MIPS_CPS_NS16550) += cps-vec-ns16550.o
obj-$(CONFIG_MIPS_SPRAM) += spram.o obj-$(CONFIG_MIPS_SPRAM) += spram.o
obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o
obj-$(CONFIG_MIPS_VPE_LOADER_CMP) += vpe-cmp.o
obj-$(CONFIG_MIPS_VPE_LOADER_MT) += vpe-mt.o obj-$(CONFIG_MIPS_VPE_LOADER_MT) += vpe-mt.o
obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o
obj-$(CONFIG_MIPS_VPE_APSP_API_CMP) += rtlx-cmp.o
obj-$(CONFIG_MIPS_VPE_APSP_API_MT) += rtlx-mt.o obj-$(CONFIG_MIPS_VPE_APSP_API_MT) += rtlx-mt.o
obj-$(CONFIG_MIPS_MSC) += irq-msc01.o obj-$(CONFIG_MIPS_MSC) += irq-msc01.o
......
...@@ -306,7 +306,10 @@ void output_octeon_cop2_state_defines(void) ...@@ -306,7 +306,10 @@ void output_octeon_cop2_state_defines(void)
OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw); OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw);
OFFSET(OCTEON_CP2_SHA3, octeon_cop2_state, cop2_sha3); OFFSET(OCTEON_CP2_SHA3, octeon_cop2_state, cop2_sha3);
OFFSET(THREAD_CP2, task_struct, thread.cp2); OFFSET(THREAD_CP2, task_struct, thread.cp2);
#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg); OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg);
#endif
BLANK(); BLANK();
} }
#endif #endif
......
...@@ -116,6 +116,8 @@ not_nmi: ...@@ -116,6 +116,8 @@ not_nmi:
li t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS li t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS
mtc0 t0, CP0_STATUS mtc0 t0, CP0_STATUS
/* We don't know how to do coherence setup on earlier ISA */
#if MIPS_ISA_REV > 0
/* Skip cache & coherence setup if we're already coherent */ /* Skip cache & coherence setup if we're already coherent */
lw s7, GCR_CL_COHERENCE_OFS(s1) lw s7, GCR_CL_COHERENCE_OFS(s1)
bnez s7, 1f bnez s7, 1f
...@@ -129,6 +131,7 @@ not_nmi: ...@@ -129,6 +131,7 @@ not_nmi:
li t0, 0xff li t0, 0xff
sw t0, GCR_CL_COHERENCE_OFS(s1) sw t0, GCR_CL_COHERENCE_OFS(s1)
ehb ehb
#endif /* MIPS_ISA_REV > 0 */
/* Set Kseg0 CCA to that in s0 */ /* Set Kseg0 CCA to that in s0 */
1: mfc0 t0, CP0_CONFIG 1: mfc0 t0, CP0_CONFIG
...@@ -515,6 +518,7 @@ LEAF(mips_cps_boot_vpes) ...@@ -515,6 +518,7 @@ LEAF(mips_cps_boot_vpes)
nop nop
END(mips_cps_boot_vpes) END(mips_cps_boot_vpes)
#if MIPS_ISA_REV > 0
LEAF(mips_cps_cache_init) LEAF(mips_cps_cache_init)
/* /*
* Clear the bits used to index the caches. Note that the architecture * Clear the bits used to index the caches. Note that the architecture
...@@ -588,6 +592,7 @@ dcache_done: ...@@ -588,6 +592,7 @@ dcache_done:
jr ra jr ra
nop nop
END(mips_cps_cache_init) END(mips_cps_cache_init)
#endif /* MIPS_ISA_REV > 0 */
#if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM) #if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM)
......
...@@ -1602,6 +1602,8 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -1602,6 +1602,8 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
{ {
decode_configs(c); decode_configs(c);
/* Octeon has different cache interface */
c->options &= ~MIPS_CPU_4K_CACHE;
switch (c->processor_id & PRID_IMP_MASK) { switch (c->processor_id & PRID_IMP_MASK) {
case PRID_IMP_CAVIUM_CN38XX: case PRID_IMP_CAVIUM_CN38XX:
case PRID_IMP_CAVIUM_CN31XX: case PRID_IMP_CAVIUM_CN31XX:
......
...@@ -181,11 +181,16 @@ static DEFINE_PER_CPU_ALIGNED(unsigned long, cm_core_lock_flags); ...@@ -181,11 +181,16 @@ static DEFINE_PER_CPU_ALIGNED(unsigned long, cm_core_lock_flags);
phys_addr_t __mips_cm_phys_base(void) phys_addr_t __mips_cm_phys_base(void)
{ {
u32 config3 = read_c0_config3();
unsigned long cmgcr; unsigned long cmgcr;
/* Check the CMGCRBase register is implemented */ /* Check the CMGCRBase register is implemented */
if (!(config3 & MIPS_CONF3_CMGCR)) if (!(read_c0_config() & MIPS_CONF_M))
return 0;
if (!(read_c0_config2() & MIPS_CONF_M))
return 0;
if (!(read_c0_config3() & MIPS_CONF3_CMGCR))
return 0; return 0;
/* Read the address from CMGCRBase */ /* Read the address from CMGCRBase */
......
...@@ -428,7 +428,6 @@ done_restore: ...@@ -428,7 +428,6 @@ done_restore:
jr ra jr ra
nop nop
.space 30 * 4, 0 .space 30 * 4, 0
octeon_mult_save_end:
EXPORT(octeon_mult_save_end) EXPORT(octeon_mult_save_end)
END(octeon_mult_save) END(octeon_mult_save)
...@@ -448,7 +447,6 @@ octeon_mult_save_end: ...@@ -448,7 +447,6 @@ octeon_mult_save_end:
sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */ sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */
jr ra jr ra
sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */ sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */
octeon_mult_save2_end:
EXPORT(octeon_mult_save2_end) EXPORT(octeon_mult_save2_end)
END(octeon_mult_save2) END(octeon_mult_save2)
...@@ -480,7 +478,6 @@ octeon_mult_save2_end: ...@@ -480,7 +478,6 @@ octeon_mult_save2_end:
sd $10, PT_MPL+(4*8)(sp) /* store MPL4 */ sd $10, PT_MPL+(4*8)(sp) /* store MPL4 */
jr ra jr ra
sd $11, PT_MPL+(5*8)(sp) /* store MPL5 */ sd $11, PT_MPL+(5*8)(sp) /* store MPL5 */
octeon_mult_save3_end:
EXPORT(octeon_mult_save3_end) EXPORT(octeon_mult_save3_end)
END(octeon_mult_save3) END(octeon_mult_save3)
.set pop .set pop
...@@ -498,7 +495,6 @@ octeon_mult_save3_end: ...@@ -498,7 +495,6 @@ octeon_mult_save3_end:
jr ra jr ra
nop nop
.space 30 * 4, 0 .space 30 * 4, 0
octeon_mult_restore_end:
EXPORT(octeon_mult_restore_end) EXPORT(octeon_mult_restore_end)
END(octeon_mult_restore) END(octeon_mult_restore)
...@@ -517,7 +513,6 @@ octeon_mult_restore_end: ...@@ -517,7 +513,6 @@ octeon_mult_restore_end:
mtp1 v0 /* P1 */ mtp1 v0 /* P1 */
jr ra jr ra
mtp0 v1 /* P0 */ mtp0 v1 /* P0 */
octeon_mult_restore2_end:
EXPORT(octeon_mult_restore2_end) EXPORT(octeon_mult_restore2_end)
END(octeon_mult_restore2) END(octeon_mult_restore2)
...@@ -548,7 +543,6 @@ octeon_mult_restore2_end: ...@@ -548,7 +543,6 @@ octeon_mult_restore2_end:
.word 0x714b000b .word 0x714b000b
/* mtp2 $10, $11 restore P2 and P5 */ /* mtp2 $10, $11 restore P2 and P5 */
octeon_mult_restore3_end:
EXPORT(octeon_mult_restore3_end) EXPORT(octeon_mult_restore3_end)
END(octeon_mult_restore3) END(octeon_mult_restore3)
.set pop .set pop
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
* Copyright (C) 2013 Imagination Technologies Ltd.
*/
#include <linux/device.h>
#include <linux/fs.h>
#include <linux/err.h>
#include <linux/wait.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <asm/mips_mt.h>
#include <asm/vpe.h>
#include <asm/rtlx.h>
static int major;
static void rtlx_interrupt(void)
{
int i;
struct rtlx_info *info;
struct rtlx_info **p = vpe_get_shared(aprp_cpu_index());
if (p == NULL || *p == NULL)
return;
info = *p;
if (info->ap_int_pending == 1 && smp_processor_id() == 0) {
for (i = 0; i < RTLX_CHANNELS; i++) {
wake_up(&channel_wqs[i].lx_queue);
wake_up(&channel_wqs[i].rt_queue);
}
info->ap_int_pending = 0;
}
}
void _interrupt_sp(void)
{
smp_send_reschedule(aprp_cpu_index());
}
int __init rtlx_module_init(void)
{
struct device *dev;
int i, err;
if (!cpu_has_mipsmt) {
pr_warn("VPE loader: not a MIPS MT capable processor\n");
return -ENODEV;
}
if (num_possible_cpus() - aprp_cpu_index() < 1) {
pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n"
"Pass maxcpus=<n> argument as kernel argument\n");
return -ENODEV;
}
major = register_chrdev(0, RTLX_MODULE_NAME, &rtlx_fops);
if (major < 0) {
pr_err("rtlx_module_init: unable to register device\n");
return major;
}
/* initialise the wait queues */
for (i = 0; i < RTLX_CHANNELS; i++) {
init_waitqueue_head(&channel_wqs[i].rt_queue);
init_waitqueue_head(&channel_wqs[i].lx_queue);
atomic_set(&channel_wqs[i].in_open, 0);
mutex_init(&channel_wqs[i].mutex);
dev = device_create(mt_class, NULL, MKDEV(major, i), NULL,
"%s%d", RTLX_MODULE_NAME, i);
if (IS_ERR(dev)) {
while (i--)
device_destroy(mt_class, MKDEV(major, i));
err = PTR_ERR(dev);
goto out_chrdev;
}
}
/* set up notifiers */
rtlx_notify.start = rtlx_starting;
rtlx_notify.stop = rtlx_stopping;
vpe_notify(aprp_cpu_index(), &rtlx_notify);
if (cpu_has_vint) {
aprp_hook = rtlx_interrupt;
} else {
pr_err("APRP RTLX init on non-vectored-interrupt processor\n");
err = -ENODEV;
goto out_class;
}
return 0;
out_class:
for (i = 0; i < RTLX_CHANNELS; i++)
device_destroy(mt_class, MKDEV(major, i));
out_chrdev:
unregister_chrdev(major, RTLX_MODULE_NAME);
return err;
}
void __exit rtlx_module_exit(void)
{
int i;
for (i = 0; i < RTLX_CHANNELS; i++)
device_destroy(mt_class, MKDEV(major, i));
unregister_chrdev(major, RTLX_MODULE_NAME);
aprp_hook = NULL;
}
...@@ -786,7 +786,8 @@ void __init setup_arch(char **cmdline_p) ...@@ -786,7 +786,8 @@ void __init setup_arch(char **cmdline_p)
setup_early_printk(); setup_early_printk();
#endif #endif
cpu_report(); cpu_report();
check_bugs_early(); if (IS_ENABLED(CONFIG_CPU_R4X00_BUGS64))
check_bugs64_early();
#if defined(CONFIG_VT) #if defined(CONFIG_VT)
#if defined(CONFIG_VGA_CONSOLE) #if defined(CONFIG_VGA_CONSOLE)
......
// SPDX-License-Identifier: GPL-2.0-only
/*
*
* Copyright (C) 2007 MIPS Technologies, Inc.
* Chris Dearman (chris@mips.com)
*/
#undef DEBUG
#include <linux/kernel.h>
#include <linux/sched/task_stack.h>
#include <linux/smp.h>
#include <linux/cpumask.h>
#include <linux/interrupt.h>
#include <linux/compiler.h>
#include <linux/atomic.h>
#include <asm/cacheflush.h>
#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/smp.h>
#include <asm/time.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/mips_mt.h>
#include <asm/amon.h>
static void cmp_init_secondary(void)
{
struct cpuinfo_mips *c __maybe_unused = &current_cpu_data;
/* Assume GIC is present */
change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
/* Enable per-cpu interrupts: platform specific */
#ifdef CONFIG_MIPS_MT_SMP
if (cpu_has_mipsmt)
cpu_set_vpe_id(c, (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
TCBIND_CURVPE);
#endif
}
static void cmp_smp_finish(void)
{
pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
/* CDFIXME: remove this? */
write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
#ifdef CONFIG_MIPS_MT_FPAFF
/* If we have an FPU, enroll ourselves in the FPU-full mask */
if (cpu_has_fpu)
cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
#endif /* CONFIG_MIPS_MT_FPAFF */
local_irq_enable();
}
/*
* Setup the PC, SP, and GP of a secondary processor and start it running
* smp_bootstrap is the place to resume from
* __KSTK_TOS(idle) is apparently the stack pointer
* (unsigned long)idle->thread_info the gp
*/
static int cmp_boot_secondary(int cpu, struct task_struct *idle)
{
struct thread_info *gp = task_thread_info(idle);
unsigned long sp = __KSTK_TOS(idle);
unsigned long pc = (unsigned long)&smp_bootstrap;
unsigned long a0 = 0;
pr_debug("SMPCMP: CPU%d: %s cpu %d\n", smp_processor_id(),
__func__, cpu);
#if 0
/* Needed? */
flush_icache_range((unsigned long)gp,
(unsigned long)(gp + sizeof(struct thread_info)));
#endif
amon_cpu_start(cpu, pc, sp, (unsigned long)gp, a0);
return 0;
}
/*
* Common setup before any secondaries are started
*/
void __init cmp_smp_setup(void)
{
int i;
int ncpu = 0;
pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
#ifdef CONFIG_MIPS_MT_FPAFF
/* If we have an FPU, enroll ourselves in the FPU-full mask */
if (cpu_has_fpu)
cpumask_set_cpu(0, &mt_fpu_cpumask);
#endif /* CONFIG_MIPS_MT_FPAFF */
for (i = 1; i < NR_CPUS; i++) {
if (amon_cpu_avail(i)) {
set_cpu_possible(i, true);
__cpu_number_map[i] = ++ncpu;
__cpu_logical_map[ncpu] = i;
}
}
if (cpu_has_mipsmt) {
unsigned int nvpe = 1;
#ifdef CONFIG_MIPS_MT_SMP
unsigned int mvpconf0 = read_c0_mvpconf0();
nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
#endif
smp_num_siblings = nvpe;
}
pr_info("Detected %i available secondary CPU(s)\n", ncpu);
}
void __init cmp_prepare_cpus(unsigned int max_cpus)
{
pr_debug("SMPCMP: CPU%d: %s max_cpus=%d\n",
smp_processor_id(), __func__, max_cpus);
#ifdef CONFIG_MIPS_MT
/*
* FIXME: some of these options are per-system, some per-core and
* some per-cpu
*/
mips_mt_set_cpuoptions();
#endif
}
const struct plat_smp_ops cmp_smp_ops = {
.send_ipi_single = mips_smp_send_ipi_single,
.send_ipi_mask = mips_smp_send_ipi_mask,
.init_secondary = cmp_init_secondary,
.smp_finish = cmp_smp_finish,
.boot_secondary = cmp_boot_secondary,
.smp_setup = cmp_smp_setup,
.prepare_cpus = cmp_prepare_cpus,
};
...@@ -361,6 +361,8 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle) ...@@ -361,6 +361,8 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle)
static void cps_init_secondary(void) static void cps_init_secondary(void)
{ {
int core = cpu_core(&current_cpu_data);
/* Disable MT - we only want to run 1 TC per VPE */ /* Disable MT - we only want to run 1 TC per VPE */
if (cpu_has_mipsmt) if (cpu_has_mipsmt)
dmt(); dmt();
...@@ -376,6 +378,9 @@ static void cps_init_secondary(void) ...@@ -376,6 +378,9 @@ static void cps_init_secondary(void)
BUG_ON(ident != mips_cm_vp_id(smp_processor_id())); BUG_ON(ident != mips_cm_vp_id(smp_processor_id()));
} }
if (core > 0 && !read_gcr_cl_coherence())
pr_warn("Core %u is not in coherent domain\n", core);
if (cpu_has_veic) if (cpu_has_veic)
clear_c0_status(ST0_IM); clear_c0_status(ST0_IM);
else else
......
...@@ -191,6 +191,7 @@ void arch_uprobe_abort_xol(struct arch_uprobe *aup, ...@@ -191,6 +191,7 @@ void arch_uprobe_abort_xol(struct arch_uprobe *aup,
{ {
struct uprobe_task *utask = current->utask; struct uprobe_task *utask = current->utask;
current->thread.trap_nr = utask->autask.saved_trap_nr;
instruction_pointer_set(regs, utask->vaddr); instruction_pointer_set(regs, utask->vaddr);
} }
...@@ -207,24 +208,6 @@ unsigned long arch_uretprobe_hijack_return_addr( ...@@ -207,24 +208,6 @@ unsigned long arch_uretprobe_hijack_return_addr(
return ra; return ra;
} }
/**
* set_swbp - store breakpoint at a given address.
* @auprobe: arch specific probepoint information.
* @mm: the probed process address space.
* @vaddr: the virtual address to insert the opcode.
*
* For mm @mm, store the breakpoint instruction at @vaddr.
* Return 0 (success) or a negative errno.
*
* This version overrides the weak version in kernel/events/uprobes.c.
* It is required to handle MIPS16 and microMIPS.
*/
int __weak set_swbp(struct arch_uprobe *auprobe, struct mm_struct *mm,
unsigned long vaddr)
{
return uprobe_write_opcode(auprobe, mm, vaddr, UPROBE_SWBP_INSN);
}
void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr, void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr,
void *src, unsigned long len) void *src, unsigned long len)
{ {
......
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
* Copyright (C) 2013 Imagination Technologies Ltd.
*/
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/fs.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <asm/vpe.h>
static int major;
void cleanup_tc(struct tc *tc)
{
}
static ssize_t store_kill(struct device *dev, struct device_attribute *attr,
const char *buf, size_t len)
{
struct vpe *vpe = get_vpe(aprp_cpu_index());
struct vpe_notifications *notifier;
list_for_each_entry(notifier, &vpe->notify, list)
notifier->stop(aprp_cpu_index());
release_progmem(vpe->load_addr);
vpe->state = VPE_STATE_UNUSED;
return len;
}
static DEVICE_ATTR(kill, S_IWUSR, NULL, store_kill);
static ssize_t ntcs_show(struct device *cd, struct device_attribute *attr,
char *buf)
{
struct vpe *vpe = get_vpe(aprp_cpu_index());
return sprintf(buf, "%d\n", vpe->ntcs);
}
static ssize_t ntcs_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t len)
{
struct vpe *vpe = get_vpe(aprp_cpu_index());
unsigned long new;
int ret;
ret = kstrtoul(buf, 0, &new);
if (ret < 0)
return ret;
/* APRP can only reserve one TC in a VPE and no more. */
if (new != 1)
return -EINVAL;
vpe->ntcs = new;
return len;
}
static DEVICE_ATTR_RW(ntcs);
static struct attribute *vpe_attrs[] = {
&dev_attr_kill.attr,
&dev_attr_ntcs.attr,
NULL,
};
ATTRIBUTE_GROUPS(vpe);
static void vpe_device_release(struct device *cd)
{
}
static struct class vpe_class = {
.name = "vpe",
.dev_release = vpe_device_release,
.dev_groups = vpe_groups,
};
static struct device vpe_device;
int __init vpe_module_init(void)
{
struct vpe *v = NULL;
struct tc *t;
int err;
if (!cpu_has_mipsmt) {
pr_warn("VPE loader: not a MIPS MT capable processor\n");
return -ENODEV;
}
if (num_possible_cpus() - aprp_cpu_index() < 1) {
pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n"
"Pass maxcpus=<n> argument as kernel argument\n");
return -ENODEV;
}
major = register_chrdev(0, VPE_MODULE_NAME, &vpe_fops);
if (major < 0) {
pr_warn("VPE loader: unable to register character device\n");
return major;
}
err = class_register(&vpe_class);
if (err) {
pr_err("vpe_class registration failed\n");
goto out_chrdev;
}
device_initialize(&vpe_device);
vpe_device.class = &vpe_class;
vpe_device.parent = NULL;
dev_set_name(&vpe_device, "vpe_sp");
vpe_device.devt = MKDEV(major, VPE_MODULE_MINOR);
err = device_add(&vpe_device);
if (err) {
pr_err("Adding vpe_device failed\n");
goto out_class;
}
t = alloc_tc(aprp_cpu_index());
if (!t) {
pr_warn("VPE: unable to allocate TC\n");
err = -ENOMEM;
goto out_dev;
}
/* VPE */
v = alloc_vpe(aprp_cpu_index());
if (v == NULL) {
pr_warn("VPE: unable to allocate VPE\n");
kfree(t);
err = -ENOMEM;
goto out_dev;
}
v->ntcs = 1;
/* add the tc to the list of this vpe's tc's. */
list_add(&t->tc, &v->tc);
/* TC */
t->pvpe = v; /* set the parent vpe */
return 0;
out_dev:
device_del(&vpe_device);
out_class:
put_device(&vpe_device);
class_unregister(&vpe_class);
out_chrdev:
unregister_chrdev(major, VPE_MODULE_NAME);
return err;
}
void __exit vpe_module_exit(void)
{
struct vpe *v, *n;
device_unregister(&vpe_device);
class_unregister(&vpe_class);
unregister_chrdev(major, VPE_MODULE_NAME);
/* No locking needed here */
list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list)
if (v->state != VPE_STATE_UNUSED)
release_vpe(v);
}
...@@ -794,7 +794,7 @@ static int vpe_open(struct inode *inode, struct file *filp) ...@@ -794,7 +794,7 @@ static int vpe_open(struct inode *inode, struct file *filp)
static int vpe_release(struct inode *inode, struct file *filp) static int vpe_release(struct inode *inode, struct file *filp)
{ {
#if defined(CONFIG_MIPS_VPE_LOADER_MT) || defined(CONFIG_MIPS_VPE_LOADER_CMP) #ifdef CONFIG_MIPS_VPE_LOADER_MT
struct vpe *v; struct vpe *v;
Elf_Ehdr *hdr; Elf_Ehdr *hdr;
int ret = 0; int ret = 0;
......
...@@ -7,6 +7,7 @@ choice ...@@ -7,6 +7,7 @@ choice
config LEMOTE_FULOONG2E config LEMOTE_FULOONG2E
bool "Lemote Fuloong(2e) mini-PC" bool "Lemote Fuloong(2e) mini-PC"
select ARCH_SPARSEMEM_ENABLE select ARCH_SPARSEMEM_ENABLE
select ARCH_HAS_PHYS_TO_DMA
select ARCH_MIGHT_HAVE_PC_PARPORT select ARCH_MIGHT_HAVE_PC_PARPORT
select ARCH_MIGHT_HAVE_PC_SERIO select ARCH_MIGHT_HAVE_PC_SERIO
select CEVT_R4K select CEVT_R4K
...@@ -36,6 +37,7 @@ config LEMOTE_FULOONG2E ...@@ -36,6 +37,7 @@ config LEMOTE_FULOONG2E
config LEMOTE_MACH2F config LEMOTE_MACH2F
bool "Lemote Loongson 2F family machines" bool "Lemote Loongson 2F family machines"
select ARCH_SPARSEMEM_ENABLE select ARCH_SPARSEMEM_ENABLE
select ARCH_HAS_PHYS_TO_DMA
select ARCH_MIGHT_HAVE_PC_PARPORT select ARCH_MIGHT_HAVE_PC_PARPORT
select ARCH_MIGHT_HAVE_PC_SERIO select ARCH_MIGHT_HAVE_PC_SERIO
select BOARD_SCACHE select BOARD_SCACHE
...@@ -46,6 +48,7 @@ config LEMOTE_MACH2F ...@@ -46,6 +48,7 @@ config LEMOTE_MACH2F
select CSRC_R4K if ! MIPS_EXTERNAL_TIMER select CSRC_R4K if ! MIPS_EXTERNAL_TIMER
select DMA_NONCOHERENT select DMA_NONCOHERENT
select GENERIC_ISA_DMA_SUPPORT_BROKEN select GENERIC_ISA_DMA_SUPPORT_BROKEN
select GPIOLIB
select FORCE_PCI select FORCE_PCI
select I8259 select I8259
select IRQ_MIPS_CPU select IRQ_MIPS_CPU
......
...@@ -2,41 +2,6 @@ ...@@ -2,41 +2,6 @@
# Loongson Processors' Support # Loongson Processors' Support
# #
cflags-$(CONFIG_CPU_LOONGSON2EF) += -Wa,--trap
cflags-$(CONFIG_CPU_LOONGSON2E) += -march=loongson2e
cflags-$(CONFIG_CPU_LOONGSON2F) += -march=loongson2f
#
# Some versions of binutils, not currently mainline as of 2019/02/04, support
# an -mfix-loongson3-llsc flag which emits a sync prior to each ll instruction
# to work around a CPU bug (see __SYNC_loongson3_war in asm/sync.h for a
# description).
#
# We disable this in order to prevent the assembler meddling with the
# instruction that labels refer to, ie. if we label an ll instruction:
#
# 1: ll v0, 0(a0)
#
# ...then with the assembler fix applied the label may actually point at a sync
# instruction inserted by the assembler, and if we were using the label in an
# exception table the table would no longer contain the address of the ll
# instruction.
#
# Avoid this by explicitly disabling that assembler behaviour. If upstream
# binutils does not merge support for the flag then we can revisit & remove
# this later - for now it ensures vendor toolchains don't cause problems.
#
cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call cc-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
# Enable the workarounds for Loongson2f
ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa,-mfix-loongson2f-nop
cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa,-mfix-loongson2f-jump
endif
# Some -march= flags enable MMI instructions, and GCC complains about that
# support being enabled alongside -msoft-float. Thus explicitly disable MMI.
cflags-y += $(call cc-option,-mno-loongson-mmi)
# #
# Loongson Machines' Support # Loongson Machines' Support
# #
......
...@@ -213,7 +213,7 @@ void pci_isa_write_reg(int reg, u32 value) ...@@ -213,7 +213,7 @@ void pci_isa_write_reg(int reg, u32 value)
lo |= 0x00000063; lo |= 0x00000063;
_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
} }
break;
default: default:
/* ALL OTHER PCI CONFIG SPACE HEADER IS NOT IMPLEMENTED. */ /* ALL OTHER PCI CONFIG SPACE HEADER IS NOT IMPLEMENTED. */
break; break;
......
#
# Loongson Processors' Support
#
cflags-$(CONFIG_CPU_LOONGSON64) += -Wa,--trap
ifdef CONFIG_CPU_LOONGSON64
cflags-$(CONFIG_CC_IS_GCC) += -march=loongson3a
cflags-$(CONFIG_CC_IS_CLANG) += -march=mips64r2
endif
# Some -march= flags enable MMI instructions, and GCC complains about that
# support being enabled alongside -msoft-float. Thus explicitly disable MMI.
cflags-y += $(call cc-option,-mno-loongson-mmi)
# #
# Loongson Machines' Support # Loongson Machines' Support
# #
......
...@@ -6,7 +6,6 @@ ...@@ -6,7 +6,6 @@
#include <linux/export.h> #include <linux/export.h>
#include <linux/init.h> #include <linux/init.h>
#include <asm/wbflush.h>
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
#include <linux/libfdt.h> #include <linux/libfdt.h>
#include <linux/of_fdt.h> #include <linux/of_fdt.h>
...@@ -17,20 +16,6 @@ ...@@ -17,20 +16,6 @@
void *loongson_fdt_blob; void *loongson_fdt_blob;
static void wbflush_loongson(void)
{
asm(".set\tpush\n\t"
".set\tnoreorder\n\t"
".set mips3\n\t"
"sync\n\t"
"nop\n\t"
".set\tpop\n\t"
".set mips0\n\t");
}
void (*__wbflush)(void) = wbflush_loongson;
EXPORT_SYMBOL(__wbflush);
void __init plat_mem_setup(void) void __init plat_mem_setup(void)
{ {
if (loongson_fdt_blob) if (loongson_fdt_blob)
......
...@@ -27,30 +27,13 @@ DEFINE_PER_CPU(int, cpu_state); ...@@ -27,30 +27,13 @@ DEFINE_PER_CPU(int, cpu_state);
#define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6) #define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6)
static void *ipi_set0_regs[16]; static void __iomem *ipi_set0_regs[16];
static void *ipi_clear0_regs[16]; static void __iomem *ipi_clear0_regs[16];
static void *ipi_status0_regs[16]; static void __iomem *ipi_status0_regs[16];
static void *ipi_en0_regs[16]; static void __iomem *ipi_en0_regs[16];
static void *ipi_mailbox_buf[16]; static void __iomem *ipi_mailbox_buf[16];
static uint32_t core0_c0count[NR_CPUS]; static uint32_t core0_c0count[NR_CPUS];
/* read a 32bit value from ipi register */
#define loongson3_ipi_read32(addr) readl(addr)
/* read a 64bit value from ipi register */
#define loongson3_ipi_read64(addr) readq(addr)
/* write a 32bit value to ipi register */
#define loongson3_ipi_write32(action, addr) \
do { \
writel(action, addr); \
__wbflush(); \
} while (0)
/* write a 64bit value to ipi register */
#define loongson3_ipi_write64(action, addr) \
do { \
writeq(action, addr); \
__wbflush(); \
} while (0)
static u32 (*ipi_read_clear)(int cpu); static u32 (*ipi_read_clear)(int cpu);
static void (*ipi_write_action)(int cpu, u32 action); static void (*ipi_write_action)(int cpu, u32 action);
static void (*ipi_write_enable)(int cpu); static void (*ipi_write_enable)(int cpu);
...@@ -136,26 +119,28 @@ static u32 legacy_ipi_read_clear(int cpu) ...@@ -136,26 +119,28 @@ static u32 legacy_ipi_read_clear(int cpu)
u32 action; u32 action;
/* Load the ipi register to figure out what we're supposed to do */ /* Load the ipi register to figure out what we're supposed to do */
action = loongson3_ipi_read32(ipi_status0_regs[cpu_logical_map(cpu)]); action = readl_relaxed(ipi_status0_regs[cpu_logical_map(cpu)]);
/* Clear the ipi register to clear the interrupt */ /* Clear the ipi register to clear the interrupt */
loongson3_ipi_write32(action, ipi_clear0_regs[cpu_logical_map(cpu)]); writel_relaxed(action, ipi_clear0_regs[cpu_logical_map(cpu)]);
nudge_writes();
return action; return action;
} }
static void legacy_ipi_write_action(int cpu, u32 action) static void legacy_ipi_write_action(int cpu, u32 action)
{ {
loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu]); writel_relaxed((u32)action, ipi_set0_regs[cpu]);
nudge_writes();
} }
static void legacy_ipi_write_enable(int cpu) static void legacy_ipi_write_enable(int cpu)
{ {
loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]); writel_relaxed(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]);
} }
static void legacy_ipi_clear_buf(int cpu) static void legacy_ipi_clear_buf(int cpu)
{ {
loongson3_ipi_write64(0, ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); writeq_relaxed(0, ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0);
} }
static void legacy_ipi_write_buf(int cpu, struct task_struct *idle) static void legacy_ipi_write_buf(int cpu, struct task_struct *idle)
...@@ -171,14 +156,15 @@ static void legacy_ipi_write_buf(int cpu, struct task_struct *idle) ...@@ -171,14 +156,15 @@ static void legacy_ipi_write_buf(int cpu, struct task_struct *idle)
pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n", pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
cpu, startargs[0], startargs[1], startargs[2]); cpu, startargs[0], startargs[1], startargs[2]);
loongson3_ipi_write64(startargs[3], writeq_relaxed(startargs[3],
ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x18); ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x18);
loongson3_ipi_write64(startargs[2], writeq_relaxed(startargs[2],
ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x10); ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x10);
loongson3_ipi_write64(startargs[1], writeq_relaxed(startargs[1],
ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x8); ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x8);
loongson3_ipi_write64(startargs[0], writeq_relaxed(startargs[0],
ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0);
nudge_writes();
} }
static void csr_ipi_probe(void) static void csr_ipi_probe(void)
...@@ -418,7 +404,7 @@ static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id) ...@@ -418,7 +404,7 @@ static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id)
c0count = c0count ? c0count : 1; c0count = c0count ? c0count : 1;
for (i = 1; i < nr_cpu_ids; i++) for (i = 1; i < nr_cpu_ids; i++)
core0_c0count[i] = c0count; core0_c0count[i] = c0count;
__wbflush(); /* Let others see the result ASAP */ nudge_writes(); /* Let others see the result ASAP */
} }
return IRQ_HANDLED; return IRQ_HANDLED;
......
...@@ -83,8 +83,13 @@ static void octeon_flush_icache_all_cores(struct vm_area_struct *vma) ...@@ -83,8 +83,13 @@ static void octeon_flush_icache_all_cores(struct vm_area_struct *vma)
else else
mask = *cpu_online_mask; mask = *cpu_online_mask;
cpumask_clear_cpu(cpu, &mask); cpumask_clear_cpu(cpu, &mask);
#ifdef CONFIG_CAVIUM_OCTEON_SOC
for_each_cpu(cpu, &mask) for_each_cpu(cpu, &mask)
octeon_send_ipi_single(cpu, SMP_ICACHE_FLUSH); octeon_send_ipi_single(cpu, SMP_ICACHE_FLUSH);
#else
smp_call_function_many(&mask, (smp_call_func_t)octeon_local_flush_icache,
NULL, 1);
#endif
preempt_enable(); preempt_enable();
#endif #endif
......
...@@ -261,10 +261,6 @@ static void r3k_flush_cache_page(struct vm_area_struct *vma, ...@@ -261,10 +261,6 @@ static void r3k_flush_cache_page(struct vm_area_struct *vma,
r3k_flush_icache_range(kaddr, kaddr + PAGE_SIZE); r3k_flush_icache_range(kaddr, kaddr + PAGE_SIZE);
} }
static void local_r3k_flush_data_cache_page(void *addr)
{
}
static void r3k_flush_data_cache_page(unsigned long addr) static void r3k_flush_data_cache_page(unsigned long addr)
{ {
} }
...@@ -302,7 +298,6 @@ void r3k_cache_init(void) ...@@ -302,7 +298,6 @@ void r3k_cache_init(void)
__flush_kernel_vmap_range = r3k_flush_kernel_vmap_range; __flush_kernel_vmap_range = r3k_flush_kernel_vmap_range;
local_flush_data_cache_page = local_r3k_flush_data_cache_page;
flush_data_cache_page = r3k_flush_data_cache_page; flush_data_cache_page = r3k_flush_data_cache_page;
_dma_cache_wback_inv = r3k_dma_cache_wback_inv; _dma_cache_wback_inv = r3k_dma_cache_wback_inv;
......
...@@ -110,20 +110,6 @@ static unsigned long dcache_size __read_mostly; ...@@ -110,20 +110,6 @@ static unsigned long dcache_size __read_mostly;
static unsigned long vcache_size __read_mostly; static unsigned long vcache_size __read_mostly;
static unsigned long scache_size __read_mostly; static unsigned long scache_size __read_mostly;
/*
* Dummy cache handling routines for machines without boardcaches
*/
static void cache_noop(void) {}
static struct bcache_ops no_sc_ops = {
.bc_enable = (void *)cache_noop,
.bc_disable = (void *)cache_noop,
.bc_wback_inv = (void *)cache_noop,
.bc_inv = (void *)cache_noop
};
struct bcache_ops *bcops = &no_sc_ops;
#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
...@@ -201,24 +187,6 @@ static void r4k_blast_dcache_user_page_setup(void) ...@@ -201,24 +187,6 @@ static void r4k_blast_dcache_user_page_setup(void)
#endif #endif
static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
static void r4k_blast_dcache_page_indexed_setup(void)
{
unsigned long dc_lsize = cpu_dcache_line_size();
if (dc_lsize == 0)
r4k_blast_dcache_page_indexed = (void *)cache_noop;
else if (dc_lsize == 16)
r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
else if (dc_lsize == 32)
r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
else if (dc_lsize == 64)
r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
else if (dc_lsize == 128)
r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed;
}
void (* r4k_blast_dcache)(void); void (* r4k_blast_dcache)(void);
EXPORT_SYMBOL(r4k_blast_dcache); EXPORT_SYMBOL(r4k_blast_dcache);
...@@ -280,39 +248,6 @@ static inline void tx49_blast_icache32(void) ...@@ -280,39 +248,6 @@ static inline void tx49_blast_icache32(void)
addr | ws, 32); addr | ws, 32);
} }
static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
{
unsigned long flags;
local_irq_save(flags);
blast_icache32_page_indexed(page);
local_irq_restore(flags);
}
static inline void tx49_blast_icache32_page_indexed(unsigned long page)
{
unsigned long indexmask = current_cpu_data.icache.waysize - 1;
unsigned long start = INDEX_BASE + (page & indexmask);
unsigned long end = start + PAGE_SIZE;
unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
unsigned long ws_end = current_cpu_data.icache.ways <<
current_cpu_data.icache.waybit;
unsigned long ws, addr;
CACHE32_UNROLL32_ALIGN2;
/* I'm in even chunk. blast odd chunks */
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
cache_unroll(32, kernel_cache, Index_Invalidate_I,
addr | ws, 32);
CACHE32_UNROLL32_ALIGN;
/* I'm in odd chunk. blast even chunks */
for (ws = 0; ws < ws_end; ws += ws_inc)
for (addr = start; addr < end; addr += 0x400 * 2)
cache_unroll(32, kernel_cache, Index_Invalidate_I,
addr | ws, 32);
}
static void (* r4k_blast_icache_page)(unsigned long addr); static void (* r4k_blast_icache_page)(unsigned long addr);
static void r4k_blast_icache_page_setup(void) static void r4k_blast_icache_page_setup(void)
...@@ -355,34 +290,6 @@ static void r4k_blast_icache_user_page_setup(void) ...@@ -355,34 +290,6 @@ static void r4k_blast_icache_user_page_setup(void)
#endif #endif
static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
static void r4k_blast_icache_page_indexed_setup(void)
{
unsigned long ic_lsize = cpu_icache_line_size();
if (ic_lsize == 0)
r4k_blast_icache_page_indexed = (void *)cache_noop;
else if (ic_lsize == 16)
r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
else if (ic_lsize == 32) {
if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
cpu_is_r4600_v1_x())
r4k_blast_icache_page_indexed =
blast_icache32_r4600_v1_page_indexed;
else if (IS_ENABLED(CONFIG_WAR_TX49XX_ICACHE_INDEX_INV))
r4k_blast_icache_page_indexed =
tx49_blast_icache32_page_indexed;
else if (current_cpu_type() == CPU_LOONGSON2EF)
r4k_blast_icache_page_indexed =
loongson2_blast_icache32_page_indexed;
else
r4k_blast_icache_page_indexed =
blast_icache32_page_indexed;
} else if (ic_lsize == 64)
r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
}
void (* r4k_blast_icache)(void); void (* r4k_blast_icache)(void);
EXPORT_SYMBOL(r4k_blast_icache); EXPORT_SYMBOL(r4k_blast_icache);
...@@ -428,24 +335,6 @@ static void r4k_blast_scache_page_setup(void) ...@@ -428,24 +335,6 @@ static void r4k_blast_scache_page_setup(void)
r4k_blast_scache_page = blast_scache128_page; r4k_blast_scache_page = blast_scache128_page;
} }
static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
static void r4k_blast_scache_page_indexed_setup(void)
{
unsigned long sc_lsize = cpu_scache_line_size();
if (scache_size == 0)
r4k_blast_scache_page_indexed = (void *)cache_noop;
else if (sc_lsize == 16)
r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
else if (sc_lsize == 32)
r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
else if (sc_lsize == 64)
r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
else if (sc_lsize == 128)
r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
}
static void (* r4k_blast_scache)(void); static void (* r4k_blast_scache)(void);
static void r4k_blast_scache_setup(void) static void r4k_blast_scache_setup(void)
...@@ -1821,13 +1710,10 @@ void r4k_cache_init(void) ...@@ -1821,13 +1710,10 @@ void r4k_cache_init(void)
setup_scache(); setup_scache();
r4k_blast_dcache_page_setup(); r4k_blast_dcache_page_setup();
r4k_blast_dcache_page_indexed_setup();
r4k_blast_dcache_setup(); r4k_blast_dcache_setup();
r4k_blast_icache_page_setup(); r4k_blast_icache_page_setup();
r4k_blast_icache_page_indexed_setup();
r4k_blast_icache_setup(); r4k_blast_icache_setup();
r4k_blast_scache_page_setup(); r4k_blast_scache_page_setup();
r4k_blast_scache_page_indexed_setup();
r4k_blast_scache_setup(); r4k_blast_scache_setup();
r4k_blast_scache_node_setup(); r4k_blast_scache_node_setup();
#ifdef CONFIG_EVA #ifdef CONFIG_EVA
...@@ -1859,7 +1745,6 @@ void r4k_cache_init(void) ...@@ -1859,7 +1745,6 @@ void r4k_cache_init(void)
__flush_kernel_vmap_range = r4k_flush_kernel_vmap_range; __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
flush_icache_all = r4k_flush_icache_all; flush_icache_all = r4k_flush_icache_all;
local_flush_data_cache_page = local_r4k_flush_data_cache_page;
flush_data_cache_page = r4k_flush_data_cache_page; flush_data_cache_page = r4k_flush_data_cache_page;
flush_icache_range = r4k_flush_icache_range; flush_icache_range = r4k_flush_icache_range;
local_flush_icache_range = local_r4k_flush_icache_range; local_flush_icache_range = local_r4k_flush_icache_range;
...@@ -1867,15 +1752,9 @@ void r4k_cache_init(void) ...@@ -1867,15 +1752,9 @@ void r4k_cache_init(void)
__local_flush_icache_user_range = local_r4k_flush_icache_user_range; __local_flush_icache_user_range = local_r4k_flush_icache_user_range;
#ifdef CONFIG_DMA_NONCOHERENT #ifdef CONFIG_DMA_NONCOHERENT
if (dma_default_coherent) {
_dma_cache_wback_inv = (void *)cache_noop;
_dma_cache_wback = (void *)cache_noop;
_dma_cache_inv = (void *)cache_noop;
} else {
_dma_cache_wback_inv = r4k_dma_cache_wback_inv; _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
_dma_cache_wback = r4k_dma_cache_wback_inv; _dma_cache_wback = r4k_dma_cache_wback_inv;
_dma_cache_inv = r4k_dma_cache_inv; _dma_cache_inv = r4k_dma_cache_inv;
}
#endif /* CONFIG_DMA_NONCOHERENT */ #endif /* CONFIG_DMA_NONCOHERENT */
build_clear_page(); build_clear_page();
...@@ -1908,7 +1787,6 @@ void r4k_cache_init(void) ...@@ -1908,7 +1787,6 @@ void r4k_cache_init(void)
/* I$ fills from D$ just by emptying the write buffers */ /* I$ fills from D$ just by emptying the write buffers */
flush_cache_page = (void *)b5k_instruction_hazard; flush_cache_page = (void *)b5k_instruction_hazard;
flush_cache_range = (void *)b5k_instruction_hazard; flush_cache_range = (void *)b5k_instruction_hazard;
local_flush_data_cache_page = (void *)b5k_instruction_hazard;
flush_data_cache_page = (void *)b5k_instruction_hazard; flush_data_cache_page = (void *)b5k_instruction_hazard;
flush_icache_range = (void *)b5k_instruction_hazard; flush_icache_range = (void *)b5k_instruction_hazard;
local_flush_icache_range = (void *)b5k_instruction_hazard; local_flush_icache_range = (void *)b5k_instruction_hazard;
...@@ -1928,7 +1806,6 @@ void r4k_cache_init(void) ...@@ -1928,7 +1806,6 @@ void r4k_cache_init(void)
flush_cache_range = (void *)cache_noop; flush_cache_range = (void *)cache_noop;
flush_icache_all = (void *)cache_noop; flush_icache_all = (void *)cache_noop;
flush_data_cache_page = (void *)cache_noop; flush_data_cache_page = (void *)cache_noop;
local_flush_data_cache_page = (void *)cache_noop;
break; break;
} }
} }
......
...@@ -17,6 +17,7 @@ ...@@ -17,6 +17,7 @@
#include <linux/highmem.h> #include <linux/highmem.h>
#include <linux/pagemap.h> #include <linux/pagemap.h>
#include <asm/bcache.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/cpu.h> #include <asm/cpu.h>
...@@ -48,14 +49,30 @@ void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size); ...@@ -48,14 +49,30 @@ void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
EXPORT_SYMBOL_GPL(__flush_kernel_vmap_range); EXPORT_SYMBOL_GPL(__flush_kernel_vmap_range);
/* MIPS specific cache operations */ /* MIPS specific cache operations */
void (*local_flush_data_cache_page)(void * addr);
void (*flush_data_cache_page)(unsigned long addr); void (*flush_data_cache_page)(unsigned long addr);
void (*flush_icache_all)(void); void (*flush_icache_all)(void);
EXPORT_SYMBOL_GPL(local_flush_data_cache_page);
EXPORT_SYMBOL(flush_data_cache_page); EXPORT_SYMBOL(flush_data_cache_page);
EXPORT_SYMBOL(flush_icache_all); EXPORT_SYMBOL(flush_icache_all);
/*
* Dummy cache handling routine
*/
void cache_noop(void) {}
#ifdef CONFIG_BOARD_SCACHE
static struct bcache_ops no_sc_ops = {
.bc_enable = (void *)cache_noop,
.bc_disable = (void *)cache_noop,
.bc_wback_inv = (void *)cache_noop,
.bc_inv = (void *)cache_noop
};
struct bcache_ops *bcops = &no_sc_ops;
#endif
#ifdef CONFIG_DMA_NONCOHERENT #ifdef CONFIG_DMA_NONCOHERENT
/* DMA cache operations. */ /* DMA cache operations. */
......
...@@ -14,6 +14,4 @@ obj-y += malta-platform.o ...@@ -14,6 +14,4 @@ obj-y += malta-platform.o
obj-y += malta-setup.o obj-y += malta-setup.o
obj-y += malta-time.o obj-y += malta-time.o
obj-$(CONFIG_MIPS_CMP) += malta-amon.o
CFLAGS_malta-dtshim.o = -I$(src)/../../../scripts/dtc/libfdt CFLAGS_malta-dtshim.o = -I$(src)/../../../scripts/dtc/libfdt
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2007 MIPS Technologies, Inc. All rights reserved.
* Copyright (C) 2013 Imagination Technologies Ltd.
*
* Arbitrary Monitor Interface
*/
#include <linux/kernel.h>
#include <linux/smp.h>
#include <asm/addrspace.h>
#include <asm/mipsmtregs.h>
#include <asm/mips-boards/launch.h>
#include <asm/vpe.h>
int amon_cpu_avail(int cpu)
{
struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
if (cpu < 0 || cpu >= NCPULAUNCH) {
pr_debug("avail: cpu%d is out of range\n", cpu);
return 0;
}
launch += cpu;
if (!(launch->flags & LAUNCH_FREADY)) {
pr_debug("avail: cpu%d is not ready\n", cpu);
return 0;
}
if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) {
pr_debug("avail: too late.. cpu%d is already gone\n", cpu);
return 0;
}
return 1;
}
int amon_cpu_start(int cpu,
unsigned long pc, unsigned long sp,
unsigned long gp, unsigned long a0)
{
volatile struct cpulaunch *launch =
(struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
if (!amon_cpu_avail(cpu))
return -1;
if (cpu == smp_processor_id()) {
pr_debug("launch: I am cpu%d!\n", cpu);
return -1;
}
launch += cpu;
pr_debug("launch: starting cpu%d\n", cpu);
launch->pc = pc;
launch->gp = gp;
launch->sp = sp;
launch->a0 = a0;
smp_wmb(); /* Target must see parameters before go */
launch->flags |= LAUNCH_FGO;
smp_wmb(); /* Target must see go before we poll */
while ((launch->flags & LAUNCH_FGONE) == 0)
;
smp_rmb(); /* Target will be updating flags soon */
pr_debug("launch: cpu%d gone!\n", cpu);
return 0;
}
#ifdef CONFIG_MIPS_VPE_LOADER_CMP
int vpe_run(struct vpe *v)
{
struct vpe_notifications *n;
if (amon_cpu_start(aprp_cpu_index(), v->__start, 0, 0, 0) < 0)
return -1;
list_for_each_entry(n, &v->notify, list)
n->start(VPE_MODULE_MINOR);
return 0;
}
#endif
...@@ -289,8 +289,6 @@ void __init prom_init(void) ...@@ -289,8 +289,6 @@ void __init prom_init(void)
if (!register_cps_smp_ops()) if (!register_cps_smp_ops())
return; return;
if (!register_cmp_smp_ops())
return;
if (!register_vsmp_smp_ops()) if (!register_vsmp_smp_ops())
return; return;
register_up_smp_ops(); register_up_smp_ops();
......
...@@ -43,7 +43,6 @@ ...@@ -43,7 +43,6 @@
static struct plat_serial8250_port uart8250_data[] = { static struct plat_serial8250_port uart8250_data[] = {
SMC_PORT(0x3F8, 4), SMC_PORT(0x3F8, 4),
SMC_PORT(0x2F8, 3), SMC_PORT(0x2F8, 3),
#ifndef CONFIG_MIPS_CMP
{ {
.mapbase = 0x1f000900, /* The CBUS UART */ .mapbase = 0x1f000900, /* The CBUS UART */
.irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2, .irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2,
...@@ -53,7 +52,6 @@ static struct plat_serial8250_port uart8250_data[] = { ...@@ -53,7 +52,6 @@ static struct plat_serial8250_port uart8250_data[] = {
.flags = CBUS_UART_FLAGS, .flags = CBUS_UART_FLAGS,
.regshift = 3, .regshift = 3,
}, },
#endif
{ }, { },
}; };
......
...@@ -118,7 +118,7 @@ static int ltq_pci_startup(struct platform_device *pdev) ...@@ -118,7 +118,7 @@ static int ltq_pci_startup(struct platform_device *pdev)
/* and enable the clocks */ /* and enable the clocks */
clk_enable(clk_pci); clk_enable(clk_pci);
if (of_find_property(node, "lantiq,external-clock", NULL)) if (of_property_read_bool(node, "lantiq,external-clock"))
clk_enable(clk_external); clk_enable(clk_external);
else else
clk_disable(clk_external); clk_disable(clk_external);
......
...@@ -419,7 +419,7 @@ static int rt3883_pci_probe(struct platform_device *pdev) ...@@ -419,7 +419,7 @@ static int rt3883_pci_probe(struct platform_device *pdev)
/* find the interrupt controller child node */ /* find the interrupt controller child node */
for_each_child_of_node(np, child) { for_each_child_of_node(np, child) {
if (of_get_property(child, "interrupt-controller", NULL)) { if (of_property_read_bool(child, "interrupt-controller")) {
rpc->intc_of_node = child; rpc->intc_of_node = child;
break; break;
} }
......
...@@ -29,18 +29,22 @@ choice ...@@ -29,18 +29,22 @@ choice
select MIPS_AUTO_PFN_OFFSET select MIPS_AUTO_PFN_OFFSET
select MIPS_L1_CACHE_SHIFT_4 select MIPS_L1_CACHE_SHIFT_4
select HAVE_PCI select HAVE_PCI
select SOC_BUS
config SOC_RT305X config SOC_RT305X
bool "RT305x" bool "RT305x"
select SOC_BUS
config SOC_RT3883 config SOC_RT3883
bool "RT3883" bool "RT3883"
select HAVE_PCI select HAVE_PCI
select SOC_BUS
config SOC_MT7620 config SOC_MT7620
bool "MT7620/8" bool "MT7620/8"
select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_IRQ_VI
select HAVE_PCI select HAVE_PCI
select SOC_BUS
config SOC_MT7621 config SOC_MT7621
bool "MT7621" bool "MT7621"
......
...@@ -11,6 +11,8 @@ ...@@ -11,6 +11,8 @@
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/bug.h> #include <linux/bug.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
#include <asm/mipsregs.h> #include <asm/mipsregs.h>
#include <asm/mach-ralink/ralink_regs.h> #include <asm/mach-ralink/ralink_regs.h>
...@@ -49,6 +51,8 @@ ...@@ -49,6 +51,8 @@
/* does the board have sdram or ddram */ /* does the board have sdram or ddram */
static int dram_type; static int dram_type;
static struct ralink_soc_info *soc_info_ptr;
static __init u32 static __init u32
mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
{ {
...@@ -324,35 +328,76 @@ mt7628_dram_init(struct ralink_soc_info *soc_info) ...@@ -324,35 +328,76 @@ mt7628_dram_init(struct ralink_soc_info *soc_info)
} }
} }
void __init prom_soc_init(struct ralink_soc_info *soc_info) static unsigned int __init mt7620_get_soc_name0(void)
{ {
void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE); return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME0);
unsigned char *name = NULL; }
u32 n0;
u32 n1; static unsigned int __init mt7620_get_soc_name1(void)
u32 rev; {
u32 cfg0; return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME1);
u32 pmu0; }
u32 pmu1;
u32 bga; static bool __init mt7620_soc_valid(void)
{
if (mt7620_get_soc_name0() == MT7620_CHIP_NAME0 &&
mt7620_get_soc_name1() == MT7620_CHIP_NAME1)
return true;
else
return false;
}
static bool __init mt7628_soc_valid(void)
{
if (mt7620_get_soc_name0() == MT7620_CHIP_NAME0 &&
mt7620_get_soc_name1() == MT7628_CHIP_NAME1)
return true;
else
return false;
}
static unsigned int __init mt7620_get_rev(void)
{
return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_REV);
}
static unsigned int __init mt7620_get_bga(void)
{
return (mt7620_get_rev() >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
}
static unsigned int __init mt7620_get_efuse(void)
{
return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_EFUSE_CFG);
}
static unsigned int __init mt7620_get_soc_ver(void)
{
return (mt7620_get_rev() >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK;
}
n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); static unsigned int __init mt7620_get_soc_eco(void)
n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); {
rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); return (mt7620_get_rev() & CHIP_REV_ECO_MASK);
bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK; }
static const char __init *mt7620_get_soc_name(struct ralink_soc_info *soc_info)
{
if (mt7620_soc_valid()) {
u32 bga = mt7620_get_bga();
if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
if (bga) { if (bga) {
ralink_soc = MT762X_SOC_MT7620A; ralink_soc = MT762X_SOC_MT7620A;
name = "MT7620A";
soc_info->compatible = "ralink,mt7620a-soc"; soc_info->compatible = "ralink,mt7620a-soc";
return "MT7620A";
} else { } else {
ralink_soc = MT762X_SOC_MT7620N; ralink_soc = MT762X_SOC_MT7620N;
name = "MT7620N";
soc_info->compatible = "ralink,mt7620n-soc"; soc_info->compatible = "ralink,mt7620n-soc";
return "MT7620N";
} }
} else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) { } else if (mt7628_soc_valid()) {
u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG); u32 efuse = mt7620_get_efuse();
unsigned char *name = NULL;
if (efuse & EFUSE_MT7688) { if (efuse & EFUSE_MT7688) {
ralink_soc = MT762X_SOC_MT7688; ralink_soc = MT762X_SOC_MT7688;
...@@ -362,17 +407,63 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) ...@@ -362,17 +407,63 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info)
name = "MT7628AN"; name = "MT7628AN";
} }
soc_info->compatible = "ralink,mt7628an-soc"; soc_info->compatible = "ralink,mt7628an-soc";
return name;
} else { } else {
panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); panic("mt762x: unknown SoC, n0:%08x n1:%08x\n",
mt7620_get_soc_name0(), mt7620_get_soc_name1());
}
}
static const char __init *mt7620_get_soc_id_name(void)
{
if (ralink_soc == MT762X_SOC_MT7620A)
return "mt7620a";
else if (ralink_soc == MT762X_SOC_MT7620N)
return "mt7620n";
else if (ralink_soc == MT762X_SOC_MT7688)
return "mt7688";
else if (ralink_soc == MT762X_SOC_MT7628AN)
return "mt7628n";
else
return "invalid";
}
static int __init mt7620_soc_dev_init(void)
{
struct soc_device *soc_dev;
struct soc_device_attribute *soc_dev_attr;
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
return -ENOMEM;
soc_dev_attr->family = "Ralink";
soc_dev_attr->soc_id = mt7620_get_soc_id_name();
soc_dev_attr->data = soc_info_ptr;
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev)) {
kfree(soc_dev_attr);
return PTR_ERR(soc_dev);
} }
return 0;
}
device_initcall(mt7620_soc_dev_init);
void __init prom_soc_init(struct ralink_soc_info *soc_info)
{
const char *name = mt7620_get_soc_name(soc_info);
u32 cfg0;
u32 pmu0;
u32 pmu1;
snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
"MediaTek %s ver:%u eco:%u", "MediaTek %s ver:%u eco:%u",
name, name, mt7620_get_soc_ver(), mt7620_get_soc_eco());
(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
(rev & CHIP_REV_ECO_MASK));
cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0); cfg0 = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_SYSTEM_CONFIG0);
if (is_mt76x8()) { if (is_mt76x8()) {
dram_type = cfg0 & DRAM_TYPE_MT7628_MASK; dram_type = cfg0 & DRAM_TYPE_MT7628_MASK;
} else { } else {
...@@ -388,11 +479,13 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) ...@@ -388,11 +479,13 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info)
else else
mt7620_dram_init(soc_info); mt7620_dram_init(soc_info);
pmu0 = __raw_readl(sysc + PMU0_CFG); pmu0 = __raw_readl(MT7620_SYSC_BASE + PMU0_CFG);
pmu1 = __raw_readl(sysc + PMU1_CFG); pmu1 = __raw_readl(MT7620_SYSC_BASE + PMU1_CFG);
pr_info("Analog PMU set to %s control\n", pr_info("Analog PMU set to %s control\n",
(pmu0 & PMU_SW_SET) ? ("sw") : ("hw")); (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
pr_info("Digital PMU set to %s control\n", pr_info("Digital PMU set to %s control\n",
(pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
soc_info_ptr = soc_info;
} }
...@@ -217,8 +217,6 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) ...@@ -217,8 +217,6 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info)
if (!register_cps_smp_ops()) if (!register_cps_smp_ops())
return; return;
if (!register_cmp_smp_ops())
return;
if (!register_vsmp_smp_ops()) if (!register_vsmp_smp_ops())
return; return;
} }
...@@ -10,6 +10,8 @@ ...@@ -10,6 +10,8 @@
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
#include <asm/mipsregs.h> #include <asm/mipsregs.h>
#include <asm/mach-ralink/ralink_regs.h> #include <asm/mach-ralink/ralink_regs.h>
...@@ -17,6 +19,8 @@ ...@@ -17,6 +19,8 @@
#include "common.h" #include "common.h"
static struct ralink_soc_info *soc_info_ptr;
void __init ralink_clk_init(void) void __init ralink_clk_init(void)
{ {
unsigned long cpu_rate, wmac_rate = 40000000; unsigned long cpu_rate, wmac_rate = 40000000;
...@@ -57,34 +61,90 @@ void __init ralink_of_remap(void) ...@@ -57,34 +61,90 @@ void __init ralink_of_remap(void)
panic("Failed to remap core resources"); panic("Failed to remap core resources");
} }
void __init prom_soc_init(struct ralink_soc_info *soc_info) static unsigned int __init rt2880_get_soc_name0(void)
{ {
void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE); return __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME0);
const char *name; }
u32 n0;
u32 n1;
u32 id;
n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); static unsigned int __init rt2880_get_soc_name1(void)
n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); {
id = __raw_readl(sysc + SYSC_REG_CHIP_ID); return __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME1);
}
if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) { static bool __init rt2880_soc_valid(void)
soc_info->compatible = "ralink,r2880-soc"; {
name = "RT2880"; if (rt2880_get_soc_name0() == RT2880_CHIP_NAME0 &&
} else { rt2880_get_soc_name1() == RT2880_CHIP_NAME1)
panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1); return true;
else
return false;
}
static const char __init *rt2880_get_soc_name(void)
{
if (rt2880_soc_valid())
return "RT2880";
else
return "invalid";
}
static unsigned int __init rt2880_get_soc_id(void)
{
return __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_ID);
}
static unsigned int __init rt2880_get_soc_ver(void)
{
return (rt2880_get_soc_id() >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK;
}
static unsigned int __init rt2880_get_soc_rev(void)
{
return (rt2880_get_soc_id() & CHIP_ID_REV_MASK);
}
static int __init rt2880_soc_dev_init(void)
{
struct soc_device *soc_dev;
struct soc_device_attribute *soc_dev_attr;
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
return -ENOMEM;
soc_dev_attr->family = "Ralink";
soc_dev_attr->soc_id = rt2880_get_soc_name();
soc_dev_attr->data = soc_info_ptr;
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev)) {
kfree(soc_dev_attr);
return PTR_ERR(soc_dev);
} }
return 0;
}
device_initcall(rt2880_soc_dev_init);
void __init prom_soc_init(struct ralink_soc_info *soc_info)
{
if (rt2880_soc_valid())
soc_info->compatible = "ralink,r2880-soc";
else
panic("rt288x: unknown SoC, n0:%08x n1:%08x",
rt2880_get_soc_name0(), rt2880_get_soc_name1());
snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
"Ralink %s id:%u rev:%u", "Ralink %s id:%u rev:%u",
name, rt2880_get_soc_name(),
(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, rt2880_get_soc_ver(),
(id & CHIP_ID_REV_MASK)); rt2880_get_soc_rev());
soc_info->mem_base = RT2880_SDRAM_BASE; soc_info->mem_base = RT2880_SDRAM_BASE;
soc_info->mem_size_min = RT2880_MEM_SIZE_MIN; soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
soc_info->mem_size_max = RT2880_MEM_SIZE_MAX; soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
ralink_soc = RT2880_SOC; ralink_soc = RT2880_SOC;
soc_info_ptr = soc_info;
} }
...@@ -11,6 +11,8 @@ ...@@ -11,6 +11,8 @@
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/bug.h> #include <linux/bug.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/mipsregs.h> #include <asm/mipsregs.h>
...@@ -19,13 +21,14 @@ ...@@ -19,13 +21,14 @@
#include "common.h" #include "common.h"
static struct ralink_soc_info *soc_info_ptr;
static unsigned long rt5350_get_mem_size(void) static unsigned long rt5350_get_mem_size(void)
{ {
void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
unsigned long ret; unsigned long ret;
u32 t; u32 t;
t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG); t = __raw_readl(RT305X_SYSC_BASE + SYSC_REG_SYSTEM_CONFIG);
t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) & t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
RT5350_SYSCFG0_DRAM_SIZE_MASK; RT5350_SYSCFG0_DRAM_SIZE_MASK;
...@@ -140,53 +143,149 @@ void __init ralink_of_remap(void) ...@@ -140,53 +143,149 @@ void __init ralink_of_remap(void)
panic("Failed to remap core resources"); panic("Failed to remap core resources");
} }
void __init prom_soc_init(struct ralink_soc_info *soc_info) static unsigned int __init rt305x_get_soc_name0(void)
{
return __raw_readl(RT305X_SYSC_BASE + SYSC_REG_CHIP_NAME0);
}
static unsigned int __init rt305x_get_soc_name1(void)
{
return __raw_readl(RT305X_SYSC_BASE + SYSC_REG_CHIP_NAME1);
}
static bool __init rt3052_soc_valid(void)
{
if (rt305x_get_soc_name0() == RT3052_CHIP_NAME0 &&
rt305x_get_soc_name1() == RT3052_CHIP_NAME1)
return true;
else
return false;
}
static bool __init rt3350_soc_valid(void)
{ {
void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); if (rt305x_get_soc_name0() == RT3350_CHIP_NAME0 &&
unsigned char *name; rt305x_get_soc_name1() == RT3350_CHIP_NAME1)
u32 n0; return true;
u32 n1; else
u32 id; return false;
}
static bool __init rt3352_soc_valid(void)
{
if (rt305x_get_soc_name0() == RT3352_CHIP_NAME0 &&
rt305x_get_soc_name1() == RT3352_CHIP_NAME1)
return true;
else
return false;
}
n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); static bool __init rt5350_soc_valid(void)
n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); {
if (rt305x_get_soc_name0() == RT5350_CHIP_NAME0 &&
rt305x_get_soc_name1() == RT5350_CHIP_NAME1)
return true;
else
return false;
}
if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) { static const char __init *rt305x_get_soc_name(struct ralink_soc_info *soc_info)
{
if (rt3052_soc_valid()) {
unsigned long icache_sets; unsigned long icache_sets;
icache_sets = (read_c0_config1() >> 22) & 7; icache_sets = (read_c0_config1() >> 22) & 7;
if (icache_sets == 1) { if (icache_sets == 1) {
ralink_soc = RT305X_SOC_RT3050; ralink_soc = RT305X_SOC_RT3050;
name = "RT3050";
soc_info->compatible = "ralink,rt3050-soc"; soc_info->compatible = "ralink,rt3050-soc";
return "RT3050";
} else { } else {
ralink_soc = RT305X_SOC_RT3052; ralink_soc = RT305X_SOC_RT3052;
name = "RT3052";
soc_info->compatible = "ralink,rt3052-soc"; soc_info->compatible = "ralink,rt3052-soc";
return "RT3052";
} }
} else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) { } else if (rt3350_soc_valid()) {
ralink_soc = RT305X_SOC_RT3350; ralink_soc = RT305X_SOC_RT3350;
name = "RT3350";
soc_info->compatible = "ralink,rt3350-soc"; soc_info->compatible = "ralink,rt3350-soc";
} else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) { return "RT3350";
} else if (rt3352_soc_valid()) {
ralink_soc = RT305X_SOC_RT3352; ralink_soc = RT305X_SOC_RT3352;
name = "RT3352";
soc_info->compatible = "ralink,rt3352-soc"; soc_info->compatible = "ralink,rt3352-soc";
} else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) { return "RT3352";
} else if (rt5350_soc_valid()) {
ralink_soc = RT305X_SOC_RT5350; ralink_soc = RT305X_SOC_RT5350;
name = "RT5350";
soc_info->compatible = "ralink,rt5350-soc"; soc_info->compatible = "ralink,rt5350-soc";
return "RT5350";
} else { } else {
panic("rt305x: unknown SoC, n0:%08x n1:%08x", n0, n1); panic("rt305x: unknown SoC, n0:%08x n1:%08x",
rt305x_get_soc_name0(), rt305x_get_soc_name1());
} }
}
id = __raw_readl(sysc + SYSC_REG_CHIP_ID); static unsigned int __init rt305x_get_soc_id(void)
{
return __raw_readl(RT305X_SYSC_BASE + SYSC_REG_CHIP_ID);
}
static unsigned int __init rt305x_get_soc_ver(void)
{
return (rt305x_get_soc_id() >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK;
}
static unsigned int __init rt305x_get_soc_rev(void)
{
return (rt305x_get_soc_id() & CHIP_ID_REV_MASK);
}
static const char __init *rt305x_get_soc_id_name(void)
{
if (soc_is_rt3050())
return "rt3050";
else if (soc_is_rt3052())
return "rt3052";
else if (soc_is_rt3350())
return "rt3350";
else if (soc_is_rt3352())
return "rt3352";
else if (soc_is_rt5350())
return "rt5350";
else
return "invalid";
}
static int __init rt305x_soc_dev_init(void)
{
struct soc_device *soc_dev;
struct soc_device_attribute *soc_dev_attr;
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
return -ENOMEM;
soc_dev_attr->family = "Ralink";
soc_dev_attr->soc_id = rt305x_get_soc_id_name();
soc_dev_attr->data = soc_info_ptr;
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev)) {
kfree(soc_dev_attr);
return PTR_ERR(soc_dev);
}
return 0;
}
device_initcall(rt305x_soc_dev_init);
void __init prom_soc_init(struct ralink_soc_info *soc_info)
{
const char *name = rt305x_get_soc_name(soc_info);
snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
"Ralink %s id:%u rev:%u", "Ralink %s id:%u rev:%u",
name, name,
(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, rt305x_get_soc_ver(),
(id & CHIP_ID_REV_MASK)); rt305x_get_soc_rev());
soc_info->mem_base = RT305X_SDRAM_BASE; soc_info->mem_base = RT305X_SDRAM_BASE;
if (soc_is_rt5350()) { if (soc_is_rt5350()) {
...@@ -198,4 +297,6 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) ...@@ -198,4 +297,6 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info)
soc_info->mem_size_min = RT3352_MEM_SIZE_MIN; soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
soc_info->mem_size_max = RT3352_MEM_SIZE_MAX; soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
} }
soc_info_ptr = soc_info;
} }
...@@ -10,6 +10,8 @@ ...@@ -10,6 +10,8 @@
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
#include <asm/mipsregs.h> #include <asm/mipsregs.h>
#include <asm/mach-ralink/ralink_regs.h> #include <asm/mach-ralink/ralink_regs.h>
...@@ -17,6 +19,8 @@ ...@@ -17,6 +19,8 @@
#include "common.h" #include "common.h"
static struct ralink_soc_info *soc_info_ptr;
void __init ralink_clk_init(void) void __init ralink_clk_init(void)
{ {
unsigned long cpu_rate, sys_rate; unsigned long cpu_rate, sys_rate;
...@@ -70,34 +74,90 @@ void __init ralink_of_remap(void) ...@@ -70,34 +74,90 @@ void __init ralink_of_remap(void)
panic("Failed to remap core resources"); panic("Failed to remap core resources");
} }
void __init prom_soc_init(struct ralink_soc_info *soc_info) static unsigned int __init rt3883_get_soc_name0(void)
{ {
void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE); return __raw_readl(RT3883_SYSC_BASE + RT3883_SYSC_REG_CHIPID0_3);
const char *name; }
u32 n0;
u32 n1;
u32 id;
n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3); static unsigned int __init rt3883_get_soc_name1(void)
n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7); {
id = __raw_readl(sysc + RT3883_SYSC_REG_REVID); return __raw_readl(RT3883_SYSC_BASE + RT3883_SYSC_REG_CHIPID4_7);
}
if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) { static bool __init rt3883_soc_valid(void)
soc_info->compatible = "ralink,rt3883-soc"; {
name = "RT3883"; if (rt3883_get_soc_name0() == RT3883_CHIP_NAME0 &&
} else { rt3883_get_soc_name1() == RT3883_CHIP_NAME1)
panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1); return true;
else
return false;
}
static const char __init *rt3883_get_soc_name(void)
{
if (rt3883_soc_valid())
return "RT3883";
else
return "invalid";
}
static unsigned int __init rt3883_get_soc_id(void)
{
return __raw_readl(RT3883_SYSC_BASE + RT3883_SYSC_REG_REVID);
}
static unsigned int __init rt3883_get_soc_ver(void)
{
return (rt3883_get_soc_id() >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK;
}
static unsigned int __init rt3883_get_soc_rev(void)
{
return (rt3883_get_soc_id() & RT3883_REVID_ECO_ID_MASK);
}
static int __init rt3883_soc_dev_init(void)
{
struct soc_device *soc_dev;
struct soc_device_attribute *soc_dev_attr;
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
return -ENOMEM;
soc_dev_attr->family = "Ralink";
soc_dev_attr->soc_id = rt3883_get_soc_name();
soc_dev_attr->data = soc_info_ptr;
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev)) {
kfree(soc_dev_attr);
return PTR_ERR(soc_dev);
} }
return 0;
}
device_initcall(rt3883_soc_dev_init);
void __init prom_soc_init(struct ralink_soc_info *soc_info)
{
if (rt3883_soc_valid())
soc_info->compatible = "ralink,rt3883-soc";
else
panic("rt3883: unknown SoC, n0:%08x n1:%08x",
rt3883_get_soc_name0(), rt3883_get_soc_name1());
snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
"Ralink %s ver:%u eco:%u", "Ralink %s ver:%u eco:%u",
name, rt3883_get_soc_name(),
(id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK, rt3883_get_soc_ver(),
(id & RT3883_REVID_ECO_ID_MASK)); rt3883_get_soc_rev());
soc_info->mem_base = RT3883_SDRAM_BASE; soc_info->mem_base = RT3883_SDRAM_BASE;
soc_info->mem_size_min = RT3883_MEM_SIZE_MIN; soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
soc_info->mem_size_max = RT3883_MEM_SIZE_MAX; soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
ralink_soc = RT3883_SOC; ralink_soc = RT3883_SOC;
soc_info_ptr = soc_info;
} }
...@@ -10,15 +10,6 @@ config SIBYTE_SB1250 ...@@ -10,15 +10,6 @@ config SIBYTE_SB1250
select SIBYTE_SB1xxx_SOC select SIBYTE_SB1xxx_SOC
select SYS_SUPPORTS_SMP select SYS_SUPPORTS_SMP
config SIBYTE_BCM1120
bool
select CEVT_SB1250
select CSRC_SB1250
select IRQ_MIPS_CPU
select SIBYTE_BCM112X
select SIBYTE_HAS_ZBUS_PROFILING
select SIBYTE_SB1xxx_SOC
config SIBYTE_BCM1125 config SIBYTE_BCM1125
bool bool
select CEVT_SB1250 select CEVT_SB1250
...@@ -29,17 +20,6 @@ config SIBYTE_BCM1125 ...@@ -29,17 +20,6 @@ config SIBYTE_BCM1125
select SIBYTE_HAS_ZBUS_PROFILING select SIBYTE_HAS_ZBUS_PROFILING
select SIBYTE_SB1xxx_SOC select SIBYTE_SB1xxx_SOC
config SIBYTE_BCM1125H
bool
select CEVT_SB1250
select CSRC_SB1250
select HAVE_PCI
select IRQ_MIPS_CPU
select SIBYTE_BCM112X
select SIBYTE_ENABLE_LDT_IF_PCI
select SIBYTE_HAS_ZBUS_PROFILING
select SIBYTE_SB1xxx_SOC
config SIBYTE_BCM112X config SIBYTE_BCM112X
bool bool
select CEVT_SB1250 select CEVT_SB1250
...@@ -58,16 +38,6 @@ config SIBYTE_BCM1x80 ...@@ -58,16 +38,6 @@ config SIBYTE_BCM1x80
select SIBYTE_SB1xxx_SOC select SIBYTE_SB1xxx_SOC
select SYS_SUPPORTS_SMP select SYS_SUPPORTS_SMP
config SIBYTE_BCM1x55
bool
select CEVT_BCM1480
select CSRC_BCM1480
select HAVE_PCI
select IRQ_MIPS_CPU
select SIBYTE_SB1xxx_SOC
select SIBYTE_HAS_ZBUS_PROFILING
select SYS_SUPPORTS_SMP
config SIBYTE_SB1xxx_SOC config SIBYTE_SB1xxx_SOC
bool bool
select IRQ_MIPS_CPU select IRQ_MIPS_CPU
...@@ -143,8 +113,7 @@ config SIBYTE_CFE_CONSOLE ...@@ -143,8 +113,7 @@ config SIBYTE_CFE_CONSOLE
config SIBYTE_BUS_WATCHER config SIBYTE_BUS_WATCHER
bool "Support for Bus Watcher statistics" bool "Support for Bus Watcher statistics"
depends on SIBYTE_SB1xxx_SOC && \ depends on SIBYTE_SB1xxx_SOC && \
(SIBYTE_BCM112X || SIBYTE_SB1250 || \ (SIBYTE_BCM112X || SIBYTE_SB1250 || SIBYTE_BCM1x80)
SIBYTE_BCM1x55 || SIBYTE_BCM1x80)
help help
Handle and keep statistics on the bus error interrupts (COR_ECC, Handle and keep statistics on the bus error interrupts (COR_ECC,
BAD_ECC, IO_BUS). BAD_ECC, IO_BUS).
......
...@@ -6,21 +6,15 @@ obj-$(CONFIG_SIBYTE_BCM112X) += sb1250/ ...@@ -6,21 +6,15 @@ obj-$(CONFIG_SIBYTE_BCM112X) += sb1250/
obj-$(CONFIG_SIBYTE_BCM112X) += common/ obj-$(CONFIG_SIBYTE_BCM112X) += common/
obj-$(CONFIG_SIBYTE_SB1250) += sb1250/ obj-$(CONFIG_SIBYTE_SB1250) += sb1250/
obj-$(CONFIG_SIBYTE_SB1250) += common/ obj-$(CONFIG_SIBYTE_SB1250) += common/
obj-$(CONFIG_SIBYTE_BCM1x55) += bcm1480/
obj-$(CONFIG_SIBYTE_BCM1x55) += common/
obj-$(CONFIG_SIBYTE_BCM1x80) += bcm1480/ obj-$(CONFIG_SIBYTE_BCM1x80) += bcm1480/
obj-$(CONFIG_SIBYTE_BCM1x80) += common/ obj-$(CONFIG_SIBYTE_BCM1x80) += common/
# #
# Sibyte BCM91120x (Carmel) board
# Sibyte BCM91120C (CRhine) board
# Sibyte BCM91125C (CRhone) board # Sibyte BCM91125C (CRhone) board
# Sibyte BCM91125E (Rhone) board # Sibyte BCM91125E (Rhone) board
# Sibyte SWARM board # Sibyte SWARM board
# Sibyte BCM91x80 (BigSur) board # Sibyte BCM91x80 (BigSur) board
# #
obj-$(CONFIG_SIBYTE_CARMEL) += swarm/
obj-$(CONFIG_SIBYTE_CRHINE) += swarm/
obj-$(CONFIG_SIBYTE_CRHONE) += swarm/ obj-$(CONFIG_SIBYTE_CRHONE) += swarm/
obj-$(CONFIG_SIBYTE_RHONE) += swarm/ obj-$(CONFIG_SIBYTE_RHONE) += swarm/
obj-$(CONFIG_SIBYTE_SENTOSA) += swarm/ obj-$(CONFIG_SIBYTE_SENTOSA) += swarm/
......
...@@ -13,25 +13,17 @@ cflags-$(CONFIG_SIBYTE_SB1250) += \ ...@@ -13,25 +13,17 @@ cflags-$(CONFIG_SIBYTE_SB1250) += \
-I$(srctree)/arch/mips/include/asm/mach-sibyte \ -I$(srctree)/arch/mips/include/asm/mach-sibyte \
-DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
cflags-$(CONFIG_SIBYTE_BCM1x55) += \
-I$(srctree)/arch/mips/include/asm/mach-sibyte \
-DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
cflags-$(CONFIG_SIBYTE_BCM1x80) += \ cflags-$(CONFIG_SIBYTE_BCM1x80) += \
-I$(srctree)/arch/mips/include/asm/mach-sibyte \ -I$(srctree)/arch/mips/include/asm/mach-sibyte \
-DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
# #
# Sibyte BCM91120x (Carmel) board
# Sibyte BCM91120C (CRhine) board
# Sibyte BCM91125C (CRhone) board # Sibyte BCM91125C (CRhone) board
# Sibyte BCM91125E (Rhone) board # Sibyte BCM91125E (Rhone) board
# Sibyte BCM91250A (SWARM) board # Sibyte BCM91250A (SWARM) board
# Sibyte BCM91250C2 (LittleSur) board # Sibyte BCM91250C2 (LittleSur) board
# Sibyte BCM91x80 (BigSur) board # Sibyte BCM91x80 (BigSur) board
# #
load-$(CONFIG_SIBYTE_CARMEL) := 0xffffffff80100000
load-$(CONFIG_SIBYTE_CRHINE) := 0xffffffff80100000
load-$(CONFIG_SIBYTE_CRHONE) := 0xffffffff80100000 load-$(CONFIG_SIBYTE_CRHONE) := 0xffffffff80100000
load-$(CONFIG_SIBYTE_RHONE) := 0xffffffff80100000 load-$(CONFIG_SIBYTE_RHONE) := 0xffffffff80100000
load-$(CONFIG_SIBYTE_SENTOSA) := 0xffffffff80100000 load-$(CONFIG_SIBYTE_SENTOSA) := 0xffffffff80100000
......
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
#include <asm/sibyte/sb1250_regs.h> #include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_int.h> #include <asm/sibyte/sb1250_int.h>
#include <asm/sibyte/sb1250_scd.h> #include <asm/sibyte/sb1250_scd.h>
#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) #ifdef CONFIG_SIBYTE_BCM1x80
#include <asm/sibyte/bcm1480_regs.h> #include <asm/sibyte/bcm1480_regs.h>
#endif #endif
...@@ -71,7 +71,7 @@ void check_bus_watcher(void) ...@@ -71,7 +71,7 @@ void check_bus_watcher(void)
#if defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250) #if defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250)
/* Use non-destructive register */ /* Use non-destructive register */
status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG)); status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG));
#elif defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) #elif defined(CONFIG_SIBYTE_BCM1x80)
/* Use non-destructive register */ /* Use non-destructive register */
/* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */ /* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */
status = csr_in32(IOADDR(A_BCM1480_BUS_ERR_STATUS_DEBUG)); status = csr_in32(IOADDR(A_BCM1480_BUS_ERR_STATUS_DEBUG));
......
...@@ -35,11 +35,6 @@ ...@@ -35,11 +35,6 @@
#endif #endif
#endif #endif
#define SIBYTE_MAX_MEM_REGIONS 8
phys_addr_t board_mem_region_addrs[SIBYTE_MAX_MEM_REGIONS];
phys_addr_t board_mem_region_sizes[SIBYTE_MAX_MEM_REGIONS];
unsigned int board_mem_region_count;
int cfe_cons_handle; int cfe_cons_handle;
#ifdef CONFIG_BLK_DEV_INITRD #ifdef CONFIG_BLK_DEV_INITRD
...@@ -141,16 +136,6 @@ static __init void prom_meminit(void) ...@@ -141,16 +136,6 @@ static __init void prom_meminit(void)
size -= 512; size -= 512;
memblock_add(addr, size); memblock_add(addr, size);
} }
board_mem_region_addrs[board_mem_region_count] = addr;
board_mem_region_sizes[board_mem_region_count] = size;
board_mem_region_count++;
if (board_mem_region_count ==
SIBYTE_MAX_MEM_REGIONS) {
/*
* Too many regions. Need to configure more
*/
while(1);
}
} }
} }
#ifdef CONFIG_BLK_DEV_INITRD #ifdef CONFIG_BLK_DEV_INITRD
...@@ -310,7 +295,7 @@ void __init prom_init(void) ...@@ -310,7 +295,7 @@ void __init prom_init(void)
#if defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250) #if defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250)
register_smp_ops(&sb_smp_ops); register_smp_ops(&sb_smp_ops);
#endif #endif
#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) #ifdef CONFIG_SIBYTE_BCM1x80
register_smp_ops(&bcm1480_smp_ops); register_smp_ops(&bcm1480_smp_ops);
#endif #endif
} }
......
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
#include <asm/io.h> #include <asm/io.h>
#include <asm/sibyte/sb1250.h> #include <asm/sibyte/sb1250.h>
#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) #ifdef CONFIG_SIBYTE_BCM1x80
#include <asm/sibyte/bcm1480_regs.h> #include <asm/sibyte/bcm1480_regs.h>
#include <asm/sibyte/bcm1480_scd.h> #include <asm/sibyte/bcm1480_scd.h>
#include <asm/sibyte/bcm1480_int.h> #include <asm/sibyte/bcm1480_int.h>
...@@ -35,7 +35,7 @@ ...@@ -35,7 +35,7 @@
#error invalid SiByte UART configuration #error invalid SiByte UART configuration
#endif #endif
#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) #ifdef CONFIG_SIBYTE_BCM1x80
#undef K_INT_TRACE_FREEZE #undef K_INT_TRACE_FREEZE
#define K_INT_TRACE_FREEZE K_BCM1480_INT_TRACE_FREEZE #define K_INT_TRACE_FREEZE K_BCM1480_INT_TRACE_FREEZE
#undef K_INT_PERF_CNT #undef K_INT_PERF_CNT
...@@ -157,7 +157,7 @@ static void arm_tb(void) ...@@ -157,7 +157,7 @@ static void arm_tb(void)
* a previous interrupt request. This means that bus profiling * a previous interrupt request. This means that bus profiling
* requires ALL of the SCD perf counters. * requires ALL of the SCD perf counters.
*/ */
#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) #ifdef CONFIG_SIBYTE_BCM1x80
__raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
/* keep counters 0,2,3,4,5,6,7 as is */ /* keep counters 0,2,3,4,5,6,7 as is */
V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */ V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */
...@@ -290,7 +290,7 @@ static int sbprof_zbprof_start(struct file *filp) ...@@ -290,7 +290,7 @@ static int sbprof_zbprof_start(struct file *filp)
* pass them through. I am exploiting my knowledge that * pass them through. I am exploiting my knowledge that
* cp0_status masks out IP[5]. krw * cp0_status masks out IP[5]. krw
*/ */
#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) #ifdef CONFIG_SIBYTE_BCM1x80
__raw_writeq(K_BCM1480_INT_MAP_I3, __raw_writeq(K_BCM1480_INT_MAP_I3,
IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) +
((K_BCM1480_INT_PERF_CNT & 0x3f) << 3))); ((K_BCM1480_INT_PERF_CNT & 0x3f) << 3)));
...@@ -343,7 +343,7 @@ static int sbprof_zbprof_start(struct file *filp) ...@@ -343,7 +343,7 @@ static int sbprof_zbprof_start(struct file *filp)
__raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7)); __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
/* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */ /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) #ifdef CONFIG_SIBYTE_BCM1x80
__raw_writeq(1ULL << (K_BCM1480_INT_PERF_CNT & 0x3f), __raw_writeq(1ULL << (K_BCM1480_INT_PERF_CNT & 0x3f),
IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_TRACE_L))); IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_TRACE_L)));
#else #else
......
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
#include <asm/time.h> #include <asm/time.h>
#include <asm/traps.h> #include <asm/traps.h>
#include <asm/sibyte/sb1250.h> #include <asm/sibyte/sb1250.h>
#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) #ifdef CONFIG_SIBYTE_BCM1x80
#include <asm/sibyte/bcm1480_regs.h> #include <asm/sibyte/bcm1480_regs.h>
#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
#include <asm/sibyte/sb1250_regs.h> #include <asm/sibyte/sb1250_regs.h>
...@@ -34,7 +34,7 @@ ...@@ -34,7 +34,7 @@
#include <asm/sibyte/sb1250_genbus.h> #include <asm/sibyte/sb1250_genbus.h>
#include <asm/sibyte/board.h> #include <asm/sibyte/board.h>
#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) #ifdef CONFIG_SIBYTE_BCM1x80
extern void bcm1480_setup(void); extern void bcm1480_setup(void);
#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
extern void sb1250_setup(void); extern void sb1250_setup(void);
...@@ -114,7 +114,7 @@ int update_persistent_clock64(struct timespec64 now) ...@@ -114,7 +114,7 @@ int update_persistent_clock64(struct timespec64 now)
void __init plat_mem_setup(void) void __init plat_mem_setup(void)
{ {
#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) #ifdef CONFIG_SIBYTE_BCM1x80
bcm1480_setup(); bcm1480_setup();
#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
sb1250_setup(); sb1250_setup();
...@@ -146,12 +146,6 @@ void __init plat_mem_setup(void) ...@@ -146,12 +146,6 @@ void __init plat_mem_setup(void)
#ifdef LEDS_PHYS #ifdef LEDS_PHYS
#ifdef CONFIG_SIBYTE_CARMEL
/* XXXKW need to detect Monterey/LittleSur/etc */
#undef LEDS_PHYS
#define LEDS_PHYS MLEDS_PHYS
#endif
void setleds(char *str) void setleds(char *str)
{ {
void *reg; void *reg;
......
...@@ -54,7 +54,6 @@ static DEFINE_SPINLOCK(gic_lock); ...@@ -54,7 +54,6 @@ static DEFINE_SPINLOCK(gic_lock);
static struct irq_domain *gic_irq_domain; static struct irq_domain *gic_irq_domain;
static int gic_shared_intrs; static int gic_shared_intrs;
static unsigned int gic_cpu_pin; static unsigned int gic_cpu_pin;
static unsigned int timer_cpu_pin;
static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller; static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
#ifdef CONFIG_GENERIC_IRQ_IPI #ifdef CONFIG_GENERIC_IRQ_IPI
...@@ -499,9 +498,6 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, ...@@ -499,9 +498,6 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
*/ */
switch (intr) { switch (intr) {
case GIC_LOCAL_INT_TIMER: case GIC_LOCAL_INT_TIMER:
/* CONFIG_MIPS_CMP workaround (see __gic_init) */
map = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin;
fallthrough;
case GIC_LOCAL_INT_PERFCTR: case GIC_LOCAL_INT_PERFCTR:
case GIC_LOCAL_INT_FDC: case GIC_LOCAL_INT_FDC:
/* /*
...@@ -795,34 +791,12 @@ static int __init gic_of_init(struct device_node *node, ...@@ -795,34 +791,12 @@ static int __init gic_of_init(struct device_node *node,
if (cpu_has_veic) { if (cpu_has_veic) {
/* Always use vector 1 in EIC mode */ /* Always use vector 1 in EIC mode */
gic_cpu_pin = 0; gic_cpu_pin = 0;
timer_cpu_pin = gic_cpu_pin;
set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET, set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
__gic_irq_dispatch); __gic_irq_dispatch);
} else { } else {
gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET; gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec, irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
gic_irq_dispatch); gic_irq_dispatch);
/*
* With the CMP implementation of SMP (deprecated), other CPUs
* are started by the bootloader and put into a timer based
* waiting poll loop. We must not re-route those CPU's local
* timer interrupts as the wait instruction will never finish,
* so just handle whatever CPU interrupt it is routed to by
* default.
*
* This workaround should be removed when CMP support is
* dropped.
*/
if (IS_ENABLED(CONFIG_MIPS_CMP) &&
gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
timer_cpu_pin = read_gic_vl_timer_map() & GIC_MAP_PIN_MAP;
irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
GIC_CPU_PIN_OFFSET +
timer_cpu_pin,
gic_irq_dispatch);
} else {
timer_cpu_pin = gic_cpu_pin;
}
} }
gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS + gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +
......
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