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Commit 91f6c90c authored by Tony Lindgren's avatar Tony Lindgren
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Merge branch 'omap4_and_sdrc_2.6.27' of git://git.pwsan.com/linux-2.6 into omap-for-linus

parents 6e457bb0 a3fed9bc
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arch/arm/mach-omap2/clock44xx_data.c
View file @ 91f6c90c
......@@ -17,12 +17,15 @@
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* XXX Some of the ES1 clocks have been removed/changed; once support
* is added for discriminating clocks by ES level, these should be added back
* in.
*/
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <plat/control.h>
#include <plat/clkdev_omap.h>
......@@ -175,21 +178,27 @@ static struct clk sys_clkin_ck = {
.recalc = &omap2_clksel_recalc,
};
static struct clk tie_low_clock_ck = {
.name = "tie_low_clock_ck",
.rate = 0,
.ops = &clkops_null,
};
static struct clk utmi_phy_clkout_ck = {
.name = "utmi_phy_clkout_ck",
.rate = 12000000,
.rate = 60000000,
.ops = &clkops_null,
};
static struct clk xclk60mhsp1_ck = {
.name = "xclk60mhsp1_ck",
.rate = 12000000,
.rate = 60000000,
.ops = &clkops_null,
};
static struct clk xclk60mhsp2_ck = {
.name = "xclk60mhsp2_ck",
.rate = 12000000,
.rate = 60000000,
.ops = &clkops_null,
};
......@@ -201,39 +210,23 @@ static struct clk xclk60motg_ck = {
/* Module clocks and DPLL outputs */
static const struct clksel_rate div2_1to2_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
{ .div = 2, .val = 1, .flags = RATE_IN_4430 },
{ .div = 0 },
};
static const struct clksel dpll_sys_ref_clk_div[] = {
{ .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
{ .parent = NULL },
};
static struct clk dpll_sys_ref_clk = {
.name = "dpll_sys_ref_clk",
static struct clk abe_dpll_bypass_clk_mux_ck = {
.name = "abe_dpll_bypass_clk_mux_ck",
.parent = &sys_clkin_ck,
.clksel = dpll_sys_ref_clk_div,
.clksel_reg = OMAP4430_CM_DPLL_SYS_REF_CLKSEL,
.clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
};
static const struct clksel abe_dpll_refclk_mux_sel[] = {
{ .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
{ .parent = NULL },
.recalc = &followparent_recalc,
};
static struct clk abe_dpll_refclk_mux_ck = {
.name = "abe_dpll_refclk_mux_ck",
.parent = &dpll_sys_ref_clk,
.clksel = abe_dpll_refclk_mux_sel,
.parent = &sys_clkin_ck,
.clksel = abe_dpll_bypass_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
.clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
......@@ -244,7 +237,7 @@ static struct clk abe_dpll_refclk_mux_ck = {
/* DPLL_ABE */
static struct dpll_data dpll_abe_dd = {
.mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
.clk_bypass = &sys_clkin_ck,
.clk_bypass = &abe_dpll_bypass_clk_mux_ck,
.clk_ref = &abe_dpll_refclk_mux_ck,
.control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
......@@ -310,6 +303,12 @@ static struct clk abe_clk = {
.set_rate = &omap2_clksel_set_rate,
};
static const struct clksel_rate div2_1to2_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
{ .div = 2, .val = 1, .flags = RATE_IN_4430 },
{ .div = 0 },
};
static const struct clksel aess_fclk_div[] = {
{ .parent = &abe_clk, .rates = div2_1to2_rates },
{ .parent = NULL },
......@@ -380,14 +379,14 @@ static struct clk dpll_abe_m3_ck = {
};
static const struct clksel core_hsd_byp_clk_mux_sel[] = {
{ .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
{ .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates },
{ .parent = NULL },
};
static struct clk core_hsd_byp_clk_mux_ck = {
.name = "core_hsd_byp_clk_mux_ck",
.parent = &dpll_sys_ref_clk,
.parent = &sys_clkin_ck,
.clksel = core_hsd_byp_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
......@@ -400,7 +399,7 @@ static struct clk core_hsd_byp_clk_mux_ck = {
static struct dpll_data dpll_core_dd = {
.mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
.clk_bypass = &core_hsd_byp_clk_mux_ck,
.clk_ref = &dpll_sys_ref_clk,
.clk_ref = &sys_clkin_ck,
.control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
.autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
......@@ -418,7 +417,7 @@ static struct dpll_data dpll_core_dd = {
static struct clk dpll_core_ck = {
.name = "dpll_core_ck",
.parent = &dpll_sys_ref_clk,
.parent = &sys_clkin_ck,
.dpll_data = &dpll_core_dd,
.init = &omap2_init_dpll_parent,
.ops = &clkops_null,
......@@ -596,14 +595,14 @@ static struct clk dpll_core_m7_ck = {
};
static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
{ .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
{ .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
{ .parent = NULL },
};
static struct clk iva_hsd_byp_clk_mux_ck = {
.name = "iva_hsd_byp_clk_mux_ck",
.parent = &dpll_sys_ref_clk,
.parent = &sys_clkin_ck,
.ops = &clkops_null,
.recalc = &followparent_recalc,
};
......@@ -612,7 +611,7 @@ static struct clk iva_hsd_byp_clk_mux_ck = {
static struct dpll_data dpll_iva_dd = {
.mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
.clk_bypass = &iva_hsd_byp_clk_mux_ck,
.clk_ref = &dpll_sys_ref_clk,
.clk_ref = &sys_clkin_ck,
.control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
.autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
......@@ -630,7 +629,7 @@ static struct dpll_data dpll_iva_dd = {
static struct clk dpll_iva_ck = {
.name = "dpll_iva_ck",
.parent = &dpll_sys_ref_clk,
.parent = &sys_clkin_ck,
.dpll_data = &dpll_iva_dd,
.init = &omap2_init_dpll_parent,
.ops = &clkops_omap3_noncore_dpll_ops,
......@@ -672,7 +671,7 @@ static struct clk dpll_iva_m5_ck = {
static struct dpll_data dpll_mpu_dd = {
.mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
.clk_bypass = &div_mpu_hs_clk,
.clk_ref = &dpll_sys_ref_clk,
.clk_ref = &sys_clkin_ck,
.control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
.autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
......@@ -690,7 +689,7 @@ static struct dpll_data dpll_mpu_dd = {
static struct clk dpll_mpu_ck = {
.name = "dpll_mpu_ck",
.parent = &dpll_sys_ref_clk,
.parent = &sys_clkin_ck,
.dpll_data = &dpll_mpu_dd,
.init = &omap2_init_dpll_parent,
.ops = &clkops_omap3_noncore_dpll_ops,
......@@ -724,14 +723,14 @@ static struct clk per_hs_clk_div_ck = {
};
static const struct clksel per_hsd_byp_clk_mux_sel[] = {
{ .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
{ .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
{ .parent = NULL },
};
static struct clk per_hsd_byp_clk_mux_ck = {
.name = "per_hsd_byp_clk_mux_ck",
.parent = &dpll_sys_ref_clk,
.parent = &sys_clkin_ck,
.clksel = per_hsd_byp_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
......@@ -744,7 +743,7 @@ static struct clk per_hsd_byp_clk_mux_ck = {
static struct dpll_data dpll_per_dd = {
.mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
.clk_bypass = &per_hsd_byp_clk_mux_ck,
.clk_ref = &dpll_sys_ref_clk,
.clk_ref = &sys_clkin_ck,
.control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
.autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
......@@ -762,7 +761,7 @@ static struct dpll_data dpll_per_dd = {
static struct clk dpll_per_ck = {
.name = "dpll_per_ck",
.parent = &dpll_sys_ref_clk,
.parent = &sys_clkin_ck,
.dpll_data = &dpll_per_dd,
.init = &omap2_init_dpll_parent,
.ops = &clkops_omap3_noncore_dpll_ops,
......@@ -858,8 +857,8 @@ static struct clk dpll_per_m7_ck = {
/* DPLL_UNIPRO */
static struct dpll_data dpll_unipro_dd = {
.mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
.clk_bypass = &dpll_sys_ref_clk,
.clk_ref = &dpll_sys_ref_clk,
.clk_bypass = &sys_clkin_ck,
.clk_ref = &sys_clkin_ck,
.control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
.autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
......@@ -877,7 +876,7 @@ static struct dpll_data dpll_unipro_dd = {
static struct clk dpll_unipro_ck = {
.name = "dpll_unipro_ck",
.parent = &dpll_sys_ref_clk,
.parent = &sys_clkin_ck,
.dpll_data = &dpll_unipro_dd,
.init = &omap2_init_dpll_parent,
.ops = &clkops_omap3_noncore_dpll_ops,
......@@ -914,7 +913,8 @@ static struct clk usb_hs_clk_div_ck = {
static struct dpll_data dpll_usb_dd = {
.mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
.clk_bypass = &usb_hs_clk_div_ck,
.clk_ref = &dpll_sys_ref_clk,
.flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL,
.clk_ref = &sys_clkin_ck,
.control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
.autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
......@@ -927,13 +927,12 @@ static struct dpll_data dpll_usb_dd = {
.max_multiplier = OMAP4430_MAX_DPLL_MULT,
.max_divider = OMAP4430_MAX_DPLL_DIV,
.min_divider = 1,
.flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL
};
static struct clk dpll_usb_ck = {
.name = "dpll_usb_ck",
.parent = &dpll_sys_ref_clk,
.parent = &sys_clkin_ck,
.dpll_data = &dpll_usb_dd,
.init = &omap2_init_dpll_parent,
.ops = &clkops_omap3_noncore_dpll_ops,
......@@ -1222,7 +1221,7 @@ static struct clk per_abe_24m_fclk = {
static const struct clksel pmd_stm_clock_mux_sel[] = {
{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
{ .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
{ .parent = &dpll_per_m7_ck, .rates = div_1_2_rates },
{ .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
{ .parent = NULL },
};
......@@ -1240,10 +1239,15 @@ static struct clk pmd_trace_clk_mux_ck = {
.recalc = &followparent_recalc,
};
static const struct clksel syc_clk_div_div[] = {
{ .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
{ .parent = NULL },
};
static struct clk syc_clk_div_ck = {
.name = "syc_clk_div_ck",
.parent = &sys_clkin_ck,
.clksel = dpll_sys_ref_clk_div,
.clksel = syc_clk_div_div,
.clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
.clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
.ops = &clkops_null,
......@@ -1284,13 +1288,13 @@ static struct clk aess_fck = {
.recalc = &followparent_recalc,
};
static struct clk cust_efuse_fck = {
.name = "cust_efuse_fck",
static struct clk bandgap_fclk = {
.name = "bandgap_fclk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_cefuse_clkdm",
.parent = &sys_clkin_ck,
.enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
.clkdm_name = "l4_wkup_clkdm",
.parent = &sys_32k_ck,
.recalc = &followparent_recalc,
};
......@@ -1344,6 +1348,56 @@ static struct clk dmic_fck = {
.clkdm_name = "abe_clkdm",
};
static struct clk dsp_fck = {
.name = "dsp_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "tesla_clkdm",
.parent = &dpll_iva_m4_ck,
.recalc = &followparent_recalc,
};
static struct clk dss_sys_clk = {
.name = "dss_sys_clk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
.clkdm_name = "l3_dss_clkdm",
.parent = &syc_clk_div_ck,
.recalc = &followparent_recalc,
};
static struct clk dss_tv_clk = {
.name = "dss_tv_clk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
.clkdm_name = "l3_dss_clkdm",
.parent = &extalt_clkin_ck,
.recalc = &followparent_recalc,
};
static struct clk dss_dss_clk = {
.name = "dss_dss_clk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
.clkdm_name = "l3_dss_clkdm",
.parent = &dpll_per_m5_ck,
.recalc = &followparent_recalc,
};
static struct clk dss_48mhz_clk = {
.name = "dss_48mhz_clk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
.clkdm_name = "l3_dss_clkdm",
.parent = &func_48mc_fclk,
.recalc = &followparent_recalc,
};
static struct clk dss_fck = {
.name = "dss_fck",
.ops = &clkops_omap2_dflt,
......@@ -1354,18 +1408,18 @@ static struct clk dss_fck = {
.recalc = &followparent_recalc,
};
static struct clk ducati_ick = {
.name = "ducati_ick",
static struct clk efuse_ctrl_cust_fck = {
.name = "efuse_ctrl_cust_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "ducati_clkdm",
.parent = &ducati_clk_mux_ck,
.enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_cefuse_clkdm",
.parent = &sys_clkin_ck,
.recalc = &followparent_recalc,
};
static struct clk emif1_ick = {
.name = "emif1_ick",
static struct clk emif1_fck = {
.name = "emif1_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
......@@ -1375,8 +1429,8 @@ static struct clk emif1_ick = {
.recalc = &followparent_recalc,
};
static struct clk emif2_ick = {
.name = "emif2_ick",
static struct clk emif2_fck = {
.name = "emif2_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
......@@ -1407,42 +1461,24 @@ static struct clk fdif_fck = {
.clkdm_name = "iss_clkdm",
};
static const struct clksel per_sgx_fclk_div[] = {
{ .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
{ .parent = NULL },
};
static struct clk per_sgx_fclk = {
.name = "per_sgx_fclk",
.parent = &dpll_per_m2x2_ck,
.clksel = per_sgx_fclk_div,
.clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_PER_192M_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
};
static const struct clksel sgx_clk_mux_sel[] = {
{ .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
{ .parent = &per_sgx_fclk, .rates = div_1_1_rates },
{ .parent = NULL },
static struct clk fpka_fck = {
.name = "fpka_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_secure_clkdm",
.parent = &l4_div_ck,
.recalc = &followparent_recalc,
};
/* Merged sgx_clk_mux into gfx */
static struct clk gfx_fck = {
.name = "gfx_fck",
.parent = &dpll_core_m7_ck,
.clksel = sgx_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
static struct clk gpio1_dbclk = {
.name = "gpio1_dbclk",
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l3_gfx_clkdm",
.enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
.clkdm_name = "l4_wkup_clkdm",
.parent = &sys_32k_ck,
.recalc = &followparent_recalc,
};
static struct clk gpio1_ick = {
......@@ -1455,6 +1491,16 @@ static struct clk gpio1_ick = {
.recalc = &followparent_recalc,
};
static struct clk gpio2_dbclk = {
.name = "gpio2_dbclk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
.clkdm_name = "l4_per_clkdm",
.parent = &sys_32k_ck,
.recalc = &followparent_recalc,
};
static struct clk gpio2_ick = {
.name = "gpio2_ick",
.ops = &clkops_omap2_dflt,
......@@ -1465,6 +1511,16 @@ static struct clk gpio2_ick = {
.recalc = &followparent_recalc,
};
static struct clk gpio3_dbclk = {
.name = "gpio3_dbclk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
.clkdm_name = "l4_per_clkdm",
.parent = &sys_32k_ck,
.recalc = &followparent_recalc,
};
static struct clk gpio3_ick = {
.name = "gpio3_ick",
.ops = &clkops_omap2_dflt,
......@@ -1475,6 +1531,16 @@ static struct clk gpio3_ick = {
.recalc = &followparent_recalc,
};
static struct clk gpio4_dbclk = {
.name = "gpio4_dbclk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
.clkdm_name = "l4_per_clkdm",
.parent = &sys_32k_ck,
.recalc = &followparent_recalc,
};
static struct clk gpio4_ick = {
.name = "gpio4_ick",
.ops = &clkops_omap2_dflt,
......@@ -1485,6 +1551,16 @@ static struct clk gpio4_ick = {
.recalc = &followparent_recalc,
};
static struct clk gpio5_dbclk = {
.name = "gpio5_dbclk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
.clkdm_name = "l4_per_clkdm",
.parent = &sys_32k_ck,
.recalc = &followparent_recalc,
};
static struct clk gpio5_ick = {
.name = "gpio5_ick",
.ops = &clkops_omap2_dflt,
......@@ -1495,6 +1571,16 @@ static struct clk gpio5_ick = {
.recalc = &followparent_recalc,
};
static struct clk gpio6_dbclk = {
.name = "gpio6_dbclk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
.clkdm_name = "l4_per_clkdm",
.parent = &sys_32k_ck,
.recalc = &followparent_recalc,
};
static struct clk gpio6_ick = {
.name = "gpio6_ick",
.ops = &clkops_omap2_dflt,
......@@ -1515,278 +1601,114 @@ static struct clk gpmc_ick = {
.recalc = &followparent_recalc,
};
static const struct clksel dmt1_clk_mux_sel[] = {
{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
static const struct clksel sgx_clk_mux_sel[] = {
{ .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
{ .parent = &dpll_per_m7_ck, .rates = div_1_1_rates },
{ .parent = NULL },
};
/*
* Merged dmt1_clk_mux into gptimer1
* gptimer1 renamed temporarily into gpt1 to match OMAP3 convention
*/
static struct clk gpt1_fck = {
.name = "gpt1_fck",
.parent = &sys_clkin_ck,
.clksel = dmt1_clk_mux_sel,
/* Merged sgx_clk_mux into gpu */
static struct clk gpu_fck = {
.name = "gpu_fck",
.parent = &dpll_core_m7_ck,
.clksel = sgx_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
.clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
.enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_wkup_clkdm",
.clkdm_name = "l3_gfx_clkdm",
};
/*
* Merged cm2_dm10_mux into gptimer10
* gptimer10 renamed temporarily into gpt10 to match OMAP3 convention
*/
static struct clk gpt10_fck = {
.name = "gpt10_fck",
.parent = &sys_clkin_ck,
.clksel = dmt1_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
static struct clk hdq1w_fck = {
.name = "hdq1w_fck",
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
.enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
.parent = &func_12m_fclk,
.recalc = &followparent_recalc,
};
/*
* Merged cm2_dm11_mux into gptimer11
* gptimer11 renamed temporarily into gpt11 to match OMAP3 convention
*/
static struct clk gpt11_fck = {
.name = "gpt11_fck",
.parent = &sys_clkin_ck,
.clksel = dmt1_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
static const struct clksel hsi_fclk_div[] = {
{ .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
{ .parent = NULL },
};
/* Merged hsi_fclk into hsi */
static struct clk hsi_fck = {
.name = "hsi_fck",
.parent = &dpll_per_m2x2_ck,
.clksel = hsi_fclk_div,
.clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
.enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "l3_init_clkdm",
};
static struct clk i2c1_fck = {
.name = "i2c1_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
.parent = &func_96m_fclk,
.recalc = &followparent_recalc,
};
/*
* Merged cm2_dm2_mux into gptimer2
* gptimer2 renamed temporarily into gpt2 to match OMAP3 convention
*/
static struct clk gpt2_fck = {
.name = "gpt2_fck",
.parent = &sys_clkin_ck,
.clksel = dmt1_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
static struct clk i2c2_fck = {
.name = "i2c2_fck",
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
.enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
.parent = &func_96m_fclk,
.recalc = &followparent_recalc,
};
/*
* Merged cm2_dm3_mux into gptimer3
* gptimer3 renamed temporarily into gpt3 to match OMAP3 convention
*/
static struct clk gpt3_fck = {
.name = "gpt3_fck",
.parent = &sys_clkin_ck,
.clksel = dmt1_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
static struct clk i2c3_fck = {
.name = "i2c3_fck",
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
.enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
.parent = &func_96m_fclk,
.recalc = &followparent_recalc,
};
/*
* Merged cm2_dm4_mux into gptimer4
* gptimer4 renamed temporarily into gpt4 to match OMAP3 convention
*/
static struct clk gpt4_fck = {
.name = "gpt4_fck",
.parent = &sys_clkin_ck,
.clksel = dmt1_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
};
static const struct clksel timer5_sync_mux_sel[] = {
{ .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
{ .parent = NULL },
};
/*
* Merged timer5_sync_mux into gptimer5
* gptimer5 renamed temporarily into gpt5 to match OMAP3 convention
*/
static struct clk gpt5_fck = {
.name = "gpt5_fck",
.parent = &syc_clk_div_ck,
.clksel = timer5_sync_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
};
/*
* Merged timer6_sync_mux into gptimer6
* gptimer6 renamed temporarily into gpt6 to match OMAP3 convention
*/
static struct clk gpt6_fck = {
.name = "gpt6_fck",
.parent = &syc_clk_div_ck,
.clksel = timer5_sync_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
};
/*
* Merged timer7_sync_mux into gptimer7
* gptimer7 renamed temporarily into gpt7 to match OMAP3 convention
*/
static struct clk gpt7_fck = {
.name = "gpt7_fck",
.parent = &syc_clk_div_ck,
.clksel = timer5_sync_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
};
/*
* Merged timer8_sync_mux into gptimer8
* gptimer8 renamed temporarily into gpt8 to match OMAP3 convention
*/
static struct clk gpt8_fck = {
.name = "gpt8_fck",
.parent = &syc_clk_div_ck,
.clksel = timer5_sync_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
};
/*
* Merged cm2_dm9_mux into gptimer9
* gptimer9 renamed temporarily into gpt9 to match OMAP3 convention
*/
static struct clk gpt9_fck = {
.name = "gpt9_fck",
.parent = &sys_clkin_ck,
.clksel = dmt1_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
};
static struct clk hdq1w_fck = {
.name = "hdq1w_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
.parent = &func_12m_fclk,
.recalc = &followparent_recalc,
};
/* Merged hsi_fclk into hsi */
static struct clk hsi_ick = {
.name = "hsi_ick",
.parent = &dpll_per_m2x2_ck,
.clksel = per_sgx_fclk_div,
.clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
.enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "l3_init_clkdm",
};
static struct clk i2c1_fck = {
.name = "i2c1_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
.parent = &func_96m_fclk,
.recalc = &followparent_recalc,
};
static struct clk i2c2_fck = {
.name = "i2c2_fck",
static struct clk i2c4_fck = {
.name = "i2c4_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
.enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
.parent = &func_96m_fclk,
.recalc = &followparent_recalc,
};
static struct clk i2c3_fck = {
.name = "i2c3_fck",
static struct clk ipu_fck = {
.name = "ipu_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
.parent = &func_96m_fclk,
.enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "ducati_clkdm",
.parent = &ducati_clk_mux_ck,
.recalc = &followparent_recalc,
};
static struct clk i2c4_fck = {
.name = "i2c4_fck",
static struct clk iss_ctrlclk = {
.name = "iss_ctrlclk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
.enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
.clkdm_name = "iss_clkdm",
.parent = &func_96m_fclk,
.recalc = &followparent_recalc,
};
......@@ -1801,8 +1723,8 @@ static struct clk iss_fck = {
.recalc = &followparent_recalc,
};
static struct clk ivahd_ick = {
.name = "ivahd_ick",
static struct clk iva_fck = {
.name = "iva_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
......@@ -1811,8 +1733,8 @@ static struct clk ivahd_ick = {
.recalc = &followparent_recalc,
};
static struct clk keyboard_fck = {
.name = "keyboard_fck",
static struct clk kbd_fck = {
.name = "kbd_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
......@@ -1821,8 +1743,8 @@ static struct clk keyboard_fck = {
.recalc = &followparent_recalc,
};
static struct clk l3_instr_interconnect_ick = {
.name = "l3_instr_interconnect_ick",
static struct clk l3_instr_ick = {
.name = "l3_instr_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
......@@ -1831,8 +1753,8 @@ static struct clk l3_instr_interconnect_ick = {
.recalc = &followparent_recalc,
};
static struct clk l3_interconnect_3_ick = {
.name = "l3_interconnect_3_ick",
static struct clk l3_main_3_ick = {
.name = "l3_main_3_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
......@@ -2005,6 +1927,16 @@ static struct clk mcbsp4_fck = {
.clkdm_name = "l4_per_clkdm",
};
static struct clk mcpdm_fck = {
.name = "mcpdm_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
.parent = &pad_clks_ck,
.recalc = &followparent_recalc,
};
static struct clk mcspi1_fck = {
.name = "mcspi1_fck",
.ops = &clkops_omap2_dflt,
......@@ -2105,33 +2037,33 @@ static struct clk mmc5_fck = {
.recalc = &followparent_recalc,
};
static struct clk ocp_wp1_ick = {
.name = "ocp_wp1_ick",
static struct clk ocp2scp_usb_phy_phy_48m = {
.name = "ocp2scp_usb_phy_phy_48m",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "l3_instr_clkdm",
.parent = &l3_div_ck,
.enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
.clkdm_name = "l3_init_clkdm",
.parent = &func_48m_fclk,
.recalc = &followparent_recalc,
};
static struct clk pdm_fck = {
.name = "pdm_fck",
static struct clk ocp2scp_usb_phy_ick = {
.name = "ocp2scp_usb_phy_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
.parent = &pad_clks_ck,
.enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "l3_init_clkdm",
.parent = &l4_div_ck,
.recalc = &followparent_recalc,
};
static struct clk pkaeip29_fck = {
.name = "pkaeip29_fck",
static struct clk ocp_wp_noc_ick = {
.name = "ocp_wp_noc_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_secure_clkdm",
.parent = &l4_div_ck,
.enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "l3_instr_clkdm",
.parent = &l3_div_ck,
.recalc = &followparent_recalc,
};
......@@ -2145,8 +2077,8 @@ static struct clk rng_ick = {
.recalc = &followparent_recalc,
};
static struct clk sha2md51_fck = {
.name = "sha2md51_fck",
static struct clk sha2md5_fck = {
.name = "sha2md5_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
......@@ -2155,8 +2087,8 @@ static struct clk sha2md51_fck = {
.recalc = &followparent_recalc,
};
static struct clk sl2_ick = {
.name = "sl2_ick",
static struct clk sl2if_ick = {
.name = "sl2if_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
......@@ -2165,129 +2097,340 @@ static struct clk sl2_ick = {
.recalc = &followparent_recalc,
};
static struct clk slimbus1_fck = {
.name = "slimbus1_fck",
static struct clk slimbus1_fclk_1 = {
.name = "slimbus1_fclk_1",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
.clkdm_name = "abe_clkdm",
.parent = &ocp_abe_iclk,
.parent = &func_24m_clk,
.recalc = &followparent_recalc,
};
static struct clk slimbus2_fck = {
.name = "slimbus2_fck",
static struct clk slimbus1_fclk_0 = {
.name = "slimbus1_fclk_0",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
.parent = &l4_div_ck,
.enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
.clkdm_name = "abe_clkdm",
.parent = &abe_24m_fclk,
.recalc = &followparent_recalc,
};
static struct clk sr_core_fck = {
.name = "sr_core_fck",
static struct clk slimbus1_fclk_2 = {
.name = "slimbus1_fclk_2",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_ao_clkdm",
.parent = &l4_wkup_clk_mux_ck,
.enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
.clkdm_name = "abe_clkdm",
.parent = &pad_clks_ck,
.recalc = &followparent_recalc,
};
static struct clk sr_iva_fck = {
.name = "sr_iva_fck",
static struct clk slimbus1_slimbus_clk = {
.name = "slimbus1_slimbus_clk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_ao_clkdm",
.parent = &l4_wkup_clk_mux_ck,
.enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
.clkdm_name = "abe_clkdm",
.parent = &slimbus_clk,
.recalc = &followparent_recalc,
};
static struct clk sr_mpu_fck = {
.name = "sr_mpu_fck",
static struct clk slimbus1_fck = {
.name = "slimbus1_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
.enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_ao_clkdm",
.parent = &l4_wkup_clk_mux_ck,
.clkdm_name = "abe_clkdm",
.parent = &ocp_abe_iclk,
.recalc = &followparent_recalc,
};
static struct clk tesla_ick = {
.name = "tesla_ick",
static struct clk slimbus2_fclk_1 = {
.name = "slimbus2_fclk_1",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "tesla_clkdm",
.parent = &dpll_iva_m4_ck,
.enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
.clkdm_name = "l4_per_clkdm",
.parent = &per_abe_24m_fclk,
.recalc = &followparent_recalc,
};
static struct clk uart1_fck = {
.name = "uart1_fck",
static struct clk slimbus2_fclk_0 = {
.name = "slimbus2_fclk_0",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
.clkdm_name = "l4_per_clkdm",
.parent = &func_48m_fclk,
.parent = &func_24mc_fclk,
.recalc = &followparent_recalc,
};
static struct clk uart2_fck = {
.name = "uart2_fck",
static struct clk slimbus2_slimbus_clk = {
.name = "slimbus2_slimbus_clk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
.clkdm_name = "l4_per_clkdm",
.parent = &func_48m_fclk,
.parent = &pad_slimbus_core_clks_ck,
.recalc = &followparent_recalc,
};
static struct clk uart3_fck = {
.name = "uart3_fck",
static struct clk slimbus2_fck = {
.name = "slimbus2_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
.enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
.parent = &func_48m_fclk,
.parent = &l4_div_ck,
.recalc = &followparent_recalc,
};
static struct clk uart4_fck = {
.name = "uart4_fck",
static struct clk smartreflex_core_fck = {
.name = "smartreflex_core_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
.enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
.parent = &func_48m_fclk,
.clkdm_name = "l4_ao_clkdm",
.parent = &l4_wkup_clk_mux_ck,
.recalc = &followparent_recalc,
};
static struct clk unipro1_fck = {
.name = "unipro1_fck",
static struct clk smartreflex_iva_fck = {
.name = "smartreflex_iva_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL,
.enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l3_init_clkdm",
.parent = &func_96m_fclk,
.clkdm_name = "l4_ao_clkdm",
.parent = &l4_wkup_clk_mux_ck,
.recalc = &followparent_recalc,
};
static struct clk usb_host_fck = {
.name = "usb_host_fck",
static struct clk smartreflex_mpu_fck = {
.name = "smartreflex_mpu_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
.enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l3_init_clkdm",
.parent = &init_60m_fclk,
.clkdm_name = "l4_ao_clkdm",
.parent = &l4_wkup_clk_mux_ck,
.recalc = &followparent_recalc,
};
static struct clk usb_host_fs_fck = {
.name = "usb_host_fs_fck",
.ops = &clkops_omap2_dflt,
/* Merged dmt1_clk_mux into timer1 */
static struct clk timer1_fck = {
.name = "timer1_fck",
.parent = &sys_clkin_ck,
.clksel = abe_dpll_bypass_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_wkup_clkdm",
};
/* Merged cm2_dm10_mux into timer10 */
static struct clk timer10_fck = {
.name = "timer10_fck",
.parent = &sys_clkin_ck,
.clksel = abe_dpll_bypass_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
};
/* Merged cm2_dm11_mux into timer11 */
static struct clk timer11_fck = {
.name = "timer11_fck",
.parent = &sys_clkin_ck,
.clksel = abe_dpll_bypass_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
};
/* Merged cm2_dm2_mux into timer2 */
static struct clk timer2_fck = {
.name = "timer2_fck",
.parent = &sys_clkin_ck,
.clksel = abe_dpll_bypass_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
};
/* Merged cm2_dm3_mux into timer3 */
static struct clk timer3_fck = {
.name = "timer3_fck",
.parent = &sys_clkin_ck,
.clksel = abe_dpll_bypass_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
};
/* Merged cm2_dm4_mux into timer4 */
static struct clk timer4_fck = {
.name = "timer4_fck",
.parent = &sys_clkin_ck,
.clksel = abe_dpll_bypass_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
};
static const struct clksel timer5_sync_mux_sel[] = {
{ .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
{ .parent = NULL },
};
/* Merged timer5_sync_mux into timer5 */
static struct clk timer5_fck = {
.name = "timer5_fck",
.parent = &syc_clk_div_ck,
.clksel = timer5_sync_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
};
/* Merged timer6_sync_mux into timer6 */
static struct clk timer6_fck = {
.name = "timer6_fck",
.parent = &syc_clk_div_ck,
.clksel = timer5_sync_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
};
/* Merged timer7_sync_mux into timer7 */
static struct clk timer7_fck = {
.name = "timer7_fck",
.parent = &syc_clk_div_ck,
.clksel = timer5_sync_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
};
/* Merged timer8_sync_mux into timer8 */
static struct clk timer8_fck = {
.name = "timer8_fck",
.parent = &syc_clk_div_ck,
.clksel = timer5_sync_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
};
/* Merged cm2_dm9_mux into timer9 */
static struct clk timer9_fck = {
.name = "timer9_fck",
.parent = &sys_clkin_ck,
.clksel = abe_dpll_bypass_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
};
static struct clk uart1_fck = {
.name = "uart1_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
.parent = &func_48m_fclk,
.recalc = &followparent_recalc,
};
static struct clk uart2_fck = {
.name = "uart2_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
.parent = &func_48m_fclk,
.recalc = &followparent_recalc,
};
static struct clk uart3_fck = {
.name = "uart3_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
.parent = &func_48m_fclk,
.recalc = &followparent_recalc,
};
static struct clk uart4_fck = {
.name = "uart4_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_per_clkdm",
.parent = &func_48m_fclk,
.recalc = &followparent_recalc,
};
static struct clk usb_host_fs_fck = {
.name = "usb_host_fs_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l3_init_clkdm",
......@@ -2295,75 +2438,138 @@ static struct clk usb_host_fs_fck = {
.recalc = &followparent_recalc,
};
static struct clk usb_otg_ick = {
.name = "usb_otg_ick",
static struct clk usb_host_hs_utmi_p3_clk = {
.name = "usb_host_hs_utmi_p3_clk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
.clkdm_name = "l3_init_clkdm",
.parent = &l3_div_ck,
.parent = &init_60m_fclk,
.recalc = &followparent_recalc,
};
static struct clk usb_tll_ick = {
.name = "usb_tll_ick",
static struct clk usb_host_hs_hsic60m_p1_clk = {
.name = "usb_host_hs_hsic60m_p1_clk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
.clkdm_name = "l3_init_clkdm",
.parent = &l4_div_ck,
.parent = &init_60m_fclk,
.recalc = &followparent_recalc,
};
static struct clk usbphyocp2scp_ick = {
.name = "usbphyocp2scp_ick",
static struct clk usb_host_hs_hsic60m_p2_clk = {
.name = "usb_host_hs_hsic60m_p2_clk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
.clkdm_name = "l3_init_clkdm",
.parent = &l4_div_ck,
.parent = &init_60m_fclk,
.recalc = &followparent_recalc,
};
static struct clk usim_fck = {
.name = "usim_fck",
static const struct clksel utmi_p1_gfclk_sel[] = {
{ .parent = &init_60m_fclk, .rates = div_1_0_rates },
{ .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
{ .parent = NULL },
};
static struct clk utmi_p1_gfclk = {
.name = "utmi_p1_gfclk",
.parent = &init_60m_fclk,
.clksel = utmi_p1_gfclk_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
};
static struct clk usb_host_hs_utmi_p1_clk = {
.name = "usb_host_hs_utmi_p1_clk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_wkup_clkdm",
.parent = &sys_32k_ck,
.enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
.clkdm_name = "l3_init_clkdm",
.parent = &utmi_p1_gfclk,
.recalc = &followparent_recalc,
};
static struct clk wdt2_fck = {
.name = "wdt2_fck",
static const struct clksel utmi_p2_gfclk_sel[] = {
{ .parent = &init_60m_fclk, .rates = div_1_0_rates },
{ .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
{ .parent = NULL },
};
static struct clk utmi_p2_gfclk = {
.name = "utmi_p2_gfclk",
.parent = &init_60m_fclk,
.clksel = utmi_p2_gfclk_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
};
static struct clk usb_host_hs_utmi_p2_clk = {
.name = "usb_host_hs_utmi_p2_clk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_wkup_clkdm",
.parent = &sys_32k_ck,
.enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
.clkdm_name = "l3_init_clkdm",
.parent = &utmi_p2_gfclk,
.recalc = &followparent_recalc,
};
static struct clk wdt3_fck = {
.name = "wdt3_fck",
static struct clk usb_host_hs_hsic480m_p1_clk = {
.name = "usb_host_hs_hsic480m_p1_clk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
.enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
.clkdm_name = "l3_init_clkdm",
.parent = &dpll_usb_m2_ck,
.recalc = &followparent_recalc,
};
static struct clk usb_host_hs_hsic480m_p2_clk = {
.name = "usb_host_hs_hsic480m_p2_clk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
.clkdm_name = "l3_init_clkdm",
.parent = &dpll_usb_m2_ck,
.recalc = &followparent_recalc,
};
static struct clk usb_host_hs_func48mclk = {
.name = "usb_host_hs_func48mclk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
.clkdm_name = "l3_init_clkdm",
.parent = &func_48mc_fclk,
.recalc = &followparent_recalc,
};
static struct clk usb_host_hs_fck = {
.name = "usb_host_hs_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
.parent = &sys_32k_ck,
.clkdm_name = "l3_init_clkdm",
.parent = &init_60m_fclk,
.recalc = &followparent_recalc,
};
/* Remaining optional clocks */
static const struct clksel otg_60m_gfclk_sel[] = {
{ .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
{ .parent = &xclk60motg_ck, .rates = div_1_1_rates },
{ .parent = NULL },
};
static struct clk otg_60m_gfclk_ck = {
.name = "otg_60m_gfclk_ck",
static struct clk otg_60m_gfclk = {
.name = "otg_60m_gfclk",
.parent = &utmi_phy_clkout_ck,
.clksel = otg_60m_gfclk_sel,
.init = &omap2_init_clksel_parent,
......@@ -2373,38 +2579,74 @@ static struct clk otg_60m_gfclk_ck = {
.recalc = &omap2_clksel_recalc,
};
static const struct clksel stm_clk_div_div[] = {
{ .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
{ .parent = NULL },
static struct clk usb_otg_hs_xclk = {
.name = "usb_otg_hs_xclk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
.clkdm_name = "l3_init_clkdm",
.parent = &otg_60m_gfclk,
.recalc = &followparent_recalc,
};
static struct clk stm_clk_div_ck = {
.name = "stm_clk_div_ck",
.parent = &pmd_stm_clock_mux_ck,
.clksel = stm_clk_div_div,
.clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
static struct clk usb_otg_hs_ick = {
.name = "usb_otg_hs_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "l3_init_clkdm",
.parent = &l3_div_ck,
.recalc = &followparent_recalc,
};
static const struct clksel trace_clk_div_div[] = {
{ .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
{ .parent = NULL },
static struct clk usb_phy_cm_clk32k = {
.name = "usb_phy_cm_clk32k",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
.clkdm_name = "l4_ao_clkdm",
.parent = &sys_32k_ck,
.recalc = &followparent_recalc,
};
static struct clk trace_clk_div_ck = {
.name = "trace_clk_div_ck",
.parent = &pmd_trace_clk_mux_ck,
.clksel = trace_clk_div_div,
.clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
static struct clk usb_tll_hs_usb_ch2_clk = {
.name = "usb_tll_hs_usb_ch2_clk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
.clkdm_name = "l3_init_clkdm",
.parent = &init_60m_fclk,
.recalc = &followparent_recalc,
};
static struct clk usb_tll_hs_usb_ch0_clk = {
.name = "usb_tll_hs_usb_ch0_clk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
.clkdm_name = "l3_init_clkdm",
.parent = &init_60m_fclk,
.recalc = &followparent_recalc,
};
static struct clk usb_tll_hs_usb_ch1_clk = {
.name = "usb_tll_hs_usb_ch1_clk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
.clkdm_name = "l3_init_clkdm",
.parent = &init_60m_fclk,
.recalc = &followparent_recalc,
};
static struct clk usb_tll_hs_ick = {
.name = "usb_tll_hs_ick",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "l3_init_clkdm",
.parent = &l4_div_ck,
.recalc = &followparent_recalc,
};
static const struct clksel_rate div2_14to18_rates[] = {
......@@ -2418,8 +2660,8 @@ static const struct clksel usim_fclk_div[] = {
{ .parent = NULL },
};
static struct clk usim_fclk = {
.name = "usim_fclk",
static struct clk usim_ck = {
.name = "usim_ck",
.parent = &dpll_per_m4_ck,
.clksel = usim_fclk_div,
.clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
......@@ -2430,38 +2672,79 @@ static struct clk usim_fclk = {
.set_rate = &omap2_clksel_set_rate,
};
static const struct clksel utmi_p1_gfclk_sel[] = {
{ .parent = &init_60m_fclk, .rates = div_1_0_rates },
{ .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
static struct clk usim_fclk = {
.name = "usim_fclk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
.enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
.clkdm_name = "l4_wkup_clkdm",
.parent = &usim_ck,
.recalc = &followparent_recalc,
};
static struct clk usim_fck = {
.name = "usim_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "l4_wkup_clkdm",
.parent = &sys_32k_ck,
.recalc = &followparent_recalc,
};
static struct clk wd_timer2_fck = {
.name = "wd_timer2_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "l4_wkup_clkdm",
.parent = &sys_32k_ck,
.recalc = &followparent_recalc,
};
static struct clk wd_timer3_fck = {
.name = "wd_timer3_fck",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_SWCTRL,
.clkdm_name = "abe_clkdm",
.parent = &sys_32k_ck,
.recalc = &followparent_recalc,
};
/* Remaining optional clocks */
static const struct clksel stm_clk_div_div[] = {
{ .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
{ .parent = NULL },
};
static struct clk utmi_p1_gfclk_ck = {
.name = "utmi_p1_gfclk_ck",
.parent = &init_60m_fclk,
.clksel = utmi_p1_gfclk_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
static struct clk stm_clk_div_ck = {
.name = "stm_clk_div_ck",
.parent = &pmd_stm_clock_mux_ck,
.clksel = stm_clk_div_div,
.clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
};
static const struct clksel utmi_p2_gfclk_sel[] = {
{ .parent = &init_60m_fclk, .rates = div_1_0_rates },
{ .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
static const struct clksel trace_clk_div_div[] = {
{ .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
{ .parent = NULL },
};
static struct clk utmi_p2_gfclk_ck = {
.name = "utmi_p2_gfclk_ck",
.parent = &init_60m_fclk,
.clksel = utmi_p2_gfclk_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
static struct clk trace_clk_div_ck = {
.name = "trace_clk_div_ck",
.parent = &pmd_trace_clk_mux_ck,
.clksel = trace_clk_div_div,
.clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
};
/*
......@@ -2483,11 +2766,12 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X),
CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X),
CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X),
CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X),
CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X),
CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X),
CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X),
CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X),
CLK(NULL, "dpll_sys_ref_clk", &dpll_sys_ref_clk, CK_443X),
CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X),
CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
......@@ -2557,46 +2841,48 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
CLK(NULL, "aess_fck", &aess_fck, CK_443X),
CLK(NULL, "cust_efuse_fck", &cust_efuse_fck, CK_443X),
CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
CLK(NULL, "dss_fck", &dss_fck, CK_443X),
CLK(NULL, "ducati_ick", &ducati_ick, CK_443X),
CLK(NULL, "emif1_ick", &emif1_ick, CK_443X),
CLK(NULL, "emif2_ick", &emif2_ick, CK_443X),
CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X),
CLK(NULL, "gfx_fck", &gfx_fck, CK_443X),
CLK(NULL, "fpka_fck", &fpka_fck, CK_443X),
CLK(NULL, "gpio1_dbck", &gpio1_dbclk, CK_443X),
CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
CLK(NULL, "gpio2_dbck", &gpio2_dbclk, CK_443X),
CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
CLK(NULL, "gpio3_dbck", &gpio3_dbclk, CK_443X),
CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
CLK(NULL, "gpio4_dbck", &gpio4_dbclk, CK_443X),
CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
CLK(NULL, "gpio5_dbck", &gpio5_dbclk, CK_443X),
CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
CLK(NULL, "gpio6_dbck", &gpio6_dbclk, CK_443X),
CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_443X),
CLK(NULL, "gpt10_fck", &gpt10_fck, CK_443X),
CLK(NULL, "gpt11_fck", &gpt11_fck, CK_443X),
CLK(NULL, "gpt2_fck", &gpt2_fck, CK_443X),
CLK(NULL, "gpt3_fck", &gpt3_fck, CK_443X),
CLK(NULL, "gpt4_fck", &gpt4_fck, CK_443X),
CLK(NULL, "gpt5_fck", &gpt5_fck, CK_443X),
CLK(NULL, "gpt6_fck", &gpt6_fck, CK_443X),
CLK(NULL, "gpt7_fck", &gpt7_fck, CK_443X),
CLK(NULL, "gpt8_fck", &gpt8_fck, CK_443X),
CLK(NULL, "gpt9_fck", &gpt9_fck, CK_443X),
CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X),
CLK(NULL, "hsi_ick", &hsi_ick, CK_443X),
CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X),
CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X),
CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X),
CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X),
CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
CLK(NULL, "iss_fck", &iss_fck, CK_443X),
CLK(NULL, "ivahd_ick", &ivahd_ick, CK_443X),
CLK(NULL, "keyboard_fck", &keyboard_fck, CK_443X),
CLK(NULL, "l3_instr_interconnect_ick", &l3_instr_interconnect_ick, CK_443X),
CLK(NULL, "l3_interconnect_3_ick", &l3_interconnect_3_ick, CK_443X),
CLK(NULL, "iva_fck", &iva_fck, CK_443X),
CLK(NULL, "kbd_fck", &kbd_fck, CK_443X),
CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X),
CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X),
CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
......@@ -2607,6 +2893,7 @@ static struct omap_clk omap44xx_clks[] = {
CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X),
CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X),
CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X),
CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X),
CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X),
......@@ -2616,43 +2903,66 @@ static struct omap_clk omap44xx_clks[] = {
CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X),
CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X),
CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X),
CLK(NULL, "ocp_wp1_ick", &ocp_wp1_ick, CK_443X),
CLK(NULL, "pdm_fck", &pdm_fck, CK_443X),
CLK(NULL, "pkaeip29_fck", &pkaeip29_fck, CK_443X),
CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
CLK("omap_rng", "ick", &rng_ick, CK_443X),
CLK(NULL, "sha2md51_fck", &sha2md51_fck, CK_443X),
CLK(NULL, "sl2_ick", &sl2_ick, CK_443X),
CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X),
CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X),
CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X),
CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
CLK(NULL, "sr_core_fck", &sr_core_fck, CK_443X),
CLK(NULL, "sr_iva_fck", &sr_iva_fck, CK_443X),
CLK(NULL, "sr_mpu_fck", &sr_mpu_fck, CK_443X),
CLK(NULL, "tesla_ick", &tesla_ick, CK_443X),
CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X),
CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X),
CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X),
CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X),
CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X),
CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X),
CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X),
CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X),
CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X),
CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X),
CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X),
CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
CLK(NULL, "unipro1_fck", &unipro1_fck, CK_443X),
CLK(NULL, "usb_host_fck", &usb_host_fck, CK_443X),
CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
CLK("musb_hdrc", "ick", &usb_otg_ick, CK_443X),
CLK(NULL, "usb_tll_ick", &usb_tll_ick, CK_443X),
CLK(NULL, "usbphyocp2scp_ick", &usbphyocp2scp_ick, CK_443X),
CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X),
CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
CLK("musb_hdrc", "ick", &usb_otg_hs_ick, CK_443X),
CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
CLK(NULL, "usim_ck", &usim_ck, CK_443X),
CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
CLK(NULL, "usim_fck", &usim_fck, CK_443X),
CLK("omap_wdt", "fck", &wdt2_fck, CK_443X),
CLK(NULL, "wdt3_fck", &wdt3_fck, CK_443X),
CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X),
CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X),
CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X),
CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X),
CLK(NULL, "gpio1_dbck", &dummy_ck, CK_443X),
CLK(NULL, "gpio2_dbck", &dummy_ck, CK_443X),
CLK(NULL, "gpio3_dbck", &dummy_ck, CK_443X),
CLK(NULL, "gpio4_dbck", &dummy_ck, CK_443X),
CLK(NULL, "gpio5_dbck", &dummy_ck, CK_443X),
CLK(NULL, "gpio6_dbck", &dummy_ck, CK_443X),
CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
......@@ -2669,19 +2979,19 @@ static struct omap_clk omap44xx_clks[] = {
CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X),
CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X),
CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X),
CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X),
CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X),
CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X),
CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X),
CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X),
CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X),
CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X),
CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X),
CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X),
CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X),
CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X),
CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X),
CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X),
CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
......
arch/arm/mach-omap2/cm-regbits-44xx.h
View file @ 91f6c90c
/*
* OMAP44xx Clock Management register bits
*
* Copyright (C) 2009 Texas Instruments, Inc.
* Copyright (C) 2009 Nokia Corporation
* Copyright (C) 2009-2010 Texas Instruments, Inc.
* Copyright (C) 2009-2010 Nokia Corporation
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
......@@ -25,453 +25,459 @@
#include "cm.h"
/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
/*
* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP,
* CM_TESLA_DYNAMICDEP
*/
#define OMAP4430_ABE_DYNDEP_SHIFT 3
#define OMAP4430_ABE_DYNDEP_MASK BITFIELD(3, 3)
#define OMAP4430_ABE_DYNDEP_MASK (1 << 3)
/*
* Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
* CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP,
* CM_TESLA_STATICDEP
* Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
* CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
* CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
*/
#define OMAP4430_ABE_STATDEP_SHIFT 3
#define OMAP4430_ABE_STATDEP_MASK BITFIELD(3, 3)
#define OMAP4430_ABE_STATDEP_MASK (1 << 3)
/* Used by CM_L4CFG_DYNAMICDEP */
/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16
#define OMAP4430_ALWONCORE_DYNDEP_MASK BITFIELD(16, 16)
#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16)
/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
#define OMAP4430_ALWONCORE_STATDEP_SHIFT 16
#define OMAP4430_ALWONCORE_STATDEP_MASK BITFIELD(16, 16)
#define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16)
/*
* Used by CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB,
* CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
* CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU
* Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
* CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY,
* CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER,
* CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
*/
#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0
#define OMAP4430_AUTO_DPLL_MODE_MASK BITFIELD(0, 2)
#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0)
/* Used by CM_L4CFG_DYNAMICDEP */
/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17
#define OMAP4430_CEFUSE_DYNDEP_MASK BITFIELD(17, 17)
#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17)
/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
#define OMAP4430_CEFUSE_STATDEP_SHIFT 17
#define OMAP4430_CEFUSE_STATDEP_MASK BITFIELD(17, 17)
#define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17)
/* Used by CM1_ABE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13
#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK BITFIELD(13, 13)
#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13)
/* Used by CM1_ABE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK BITFIELD(12, 12)
#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12)
/* Used by CM_WKUP_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK BITFIELD(9, 9)
#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9)
/* Used by CM1_ABE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK BITFIELD(11, 11)
#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11)
/* Used by CM1_ABE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8)
/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK BITFIELD(11, 11)
#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11)
/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK BITFIELD(12, 12)
#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12)
/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13
#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK BITFIELD(13, 13)
#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13)
/* Used by CM_CAM_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK BITFIELD(9, 9)
#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9)
/* Used by CM_ALWON_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12)
/* Used by CM_EMU_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK BITFIELD(9, 9)
#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9)
/* Used by CM_CEFUSE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK BITFIELD(9, 9)
#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK BITFIELD(9, 9)
#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK BITFIELD(9, 9)
#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK BITFIELD(10, 10)
#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK BITFIELD(11, 11)
#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK BITFIELD(12, 12)
#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13
#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK BITFIELD(13, 13)
#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14
#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK BITFIELD(14, 14)
#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14)
/* Used by CM_DSS_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK BITFIELD(10, 10)
#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK (1 << 10)
/* Used by CM_DSS_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK BITFIELD(9, 9)
#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK (1 << 9)
/* Used by CM_DUCATI_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK BITFIELD(8, 8)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_MASK BITFIELD(10, 10)
#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK (1 << 8)
/* Used by CM_EMU_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8)
/* Used by CM_CAM_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK BITFIELD(10, 10)
#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15
#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK BITFIELD(15, 15)
#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15)
/* Used by CM1_ABE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK BITFIELD(10, 10)
#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10)
/* Used by CM_DSS_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK BITFIELD(11, 11)
#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20
#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK BITFIELD(20, 20)
#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26
#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK BITFIELD(26, 26)
#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21
#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK BITFIELD(21, 21)
#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27
#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK BITFIELD(27, 27)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT 31
#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_MASK BITFIELD(31, 31)
#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13
#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK BITFIELD(13, 13)
#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK BITFIELD(12, 12)
#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28
#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK BITFIELD(28, 28)
#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29
#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK BITFIELD(29, 29)
#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK BITFIELD(11, 11)
#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16
#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK BITFIELD(16, 16)
#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17
#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK BITFIELD(17, 17)
#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18
#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK BITFIELD(18, 18)
#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19
#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK BITFIELD(19, 19)
#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19)
/* Used by CM_CAM_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK (1 << 8)
/* Used by CM_IVAHD_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK (1 << 8)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT 14
#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_MASK BITFIELD(14, 14)
/* Used by CM_D2D_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10)
/* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8)
/* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8)
/* Used by CM_D2D_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK (1 << 8)
/* Used by CM_SDMA_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK (1 << 8)
/* Used by CM_DSS_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8)
/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8)
/* Used by CM_GFX_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8)
/* Used by CM_L3INSTR_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK (1 << 8)
/* Used by CM_L4SEC_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK (1 << 8)
/* Used by CM_ALWON_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK (1 << 8)
/* Used by CM_CEFUSE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
/* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8)
/* Used by CM_D2D_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK BITFIELD(9, 9)
#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK BITFIELD(9, 9)
#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8)
/* Used by CM_L4SEC_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK BITFIELD(9, 9)
#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK (1 << 9)
/* Used by CM_WKUP_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK BITFIELD(12, 12)
#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12)
/* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8)
/* Used by CM1_ABE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK BITFIELD(9, 9)
#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16
#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK BITFIELD(16, 16)
#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17
#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK BITFIELD(17, 17)
#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18
#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK BITFIELD(18, 18)
#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19
#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK BITFIELD(19, 19)
#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25
#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK BITFIELD(25, 25)
/* Used by CM_EMU_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_MASK BITFIELD(10, 10)
#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20
#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK BITFIELD(20, 20)
#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21
#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK BITFIELD(21, 21)
#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22
#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK BITFIELD(22, 22)
#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22)
/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24
#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK BITFIELD(24, 24)
#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24)
/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK BITFIELD(10, 10)
#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10)
/* Used by CM_GFX_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK BITFIELD(9, 9)
#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK (1 << 9)
/* Used by CM_ALWON_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK BITFIELD(11, 11)
#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK (1 << 11)
/* Used by CM_ALWON_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK BITFIELD(10, 10)
#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK (1 << 10)
/* Used by CM_ALWON_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK BITFIELD(9, 9)
#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK (1 << 9)
/* Used by CM_WKUP_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK (1 << 8)
/* Used by CM_TESLA_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK BITFIELD(8, 8)
#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22
#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK BITFIELD(22, 22)
#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23
#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK BITFIELD(23, 23)
#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24
#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK BITFIELD(24, 24)
#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14
#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15
#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK BITFIELD(15, 15)
#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15)
/* Used by CM_WKUP_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK BITFIELD(10, 10)
#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30
#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK BITFIELD(30, 30)
#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30)
/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25
#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK BITFIELD(25, 25)
#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25)
/* Used by CM_WKUP_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK BITFIELD(11, 11)
#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11)
/*
* Used by CM_WKUP_TIMER1_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
* Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
* CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
* CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
* CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
* CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
* CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
* CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL,
* CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
* CM1_ABE_TIMER8_CLKCTRL
* CM_WKUP_TIMER1_CLKCTRL
*/
#define OMAP4430_CLKSEL_SHIFT 24
#define OMAP4430_CLKSEL_MASK BITFIELD(24, 24)
#define OMAP4430_CLKSEL_MASK (1 << 24)
/*
* Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
* CM_DPLL_SYS_REF_CLKSEL, CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT,
* CM_CLKSEL_USB_60MHZ
* CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ
*/
#define OMAP4430_CLKSEL_0_0_SHIFT 0
#define OMAP4430_CLKSEL_0_0_MASK BITFIELD(0, 0)
#define OMAP4430_CLKSEL_0_0_MASK (1 << 0)
/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
#define OMAP4430_CLKSEL_0_1_SHIFT 0
#define OMAP4430_CLKSEL_0_1_MASK BITFIELD(0, 1)
#define OMAP4430_CLKSEL_0_1_MASK (0x3 << 0)
/* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
#define OMAP4430_CLKSEL_24_25_SHIFT 24
#define OMAP4430_CLKSEL_24_25_MASK BITFIELD(24, 25)
#define OMAP4430_CLKSEL_24_25_MASK (0x3 << 24)
/* Used by CM_L3INIT_USB_OTG_CLKCTRL */
#define OMAP4430_CLKSEL_60M_SHIFT 24
#define OMAP4430_CLKSEL_60M_MASK BITFIELD(24, 24)
#define OMAP4430_CLKSEL_60M_MASK (1 << 24)
/* Used by CM1_ABE_AESS_CLKCTRL */
#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24
#define OMAP4430_CLKSEL_AESS_FCLK_MASK BITFIELD(24, 24)
#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24)
/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
#define OMAP4430_CLKSEL_CORE_SHIFT 0
#define OMAP4430_CLKSEL_CORE_MASK BITFIELD(0, 0)
#define OMAP4430_CLKSEL_CORE_MASK (1 << 0)
/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
/*
* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
* CM_SHADOW_FREQ_CONFIG2
*/
#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1
#define OMAP4430_CLKSEL_CORE_1_1_MASK BITFIELD(1, 1)
#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1)
/* Used by CM_WKUP_USIM_CLKCTRL */
#define OMAP4430_CLKSEL_DIV_SHIFT 24
#define OMAP4430_CLKSEL_DIV_MASK BITFIELD(24, 24)
#define OMAP4430_CLKSEL_DIV_MASK (1 << 24)
/* Used by CM_CAM_FDIF_CLKCTRL */
#define OMAP4430_CLKSEL_FCLK_SHIFT 24
#define OMAP4430_CLKSEL_FCLK_MASK BITFIELD(24, 25)
#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24)
/* Used by CM_L4PER_MCBSP4_CLKCTRL */
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK BITFIELD(25, 25)
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK (1 << 25)
/*
* Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL,
......@@ -479,836 +485,869 @@
* CM1_ABE_MCBSP3_CLKCTRL
*/
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK BITFIELD(26, 27)
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26)
/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
#define OMAP4430_CLKSEL_L3_SHIFT 4
#define OMAP4430_CLKSEL_L3_MASK BITFIELD(4, 4)
#define OMAP4430_CLKSEL_L3_MASK (1 << 4)
/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
/*
* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
* CM_SHADOW_FREQ_CONFIG2
*/
#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2
#define OMAP4430_CLKSEL_L3_SHADOW_MASK BITFIELD(2, 2)
#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2)
/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
#define OMAP4430_CLKSEL_L4_SHIFT 8
#define OMAP4430_CLKSEL_L4_MASK BITFIELD(8, 8)
#define OMAP4430_CLKSEL_L4_MASK (1 << 8)
/* Used by CM_CLKSEL_ABE */
#define OMAP4430_CLKSEL_OPP_SHIFT 0
#define OMAP4430_CLKSEL_OPP_MASK BITFIELD(0, 1)
/* Used by CM_GFX_GFX_CLKCTRL */
#define OMAP4430_CLKSEL_PER_192M_SHIFT 25
#define OMAP4430_CLKSEL_PER_192M_MASK BITFIELD(25, 26)
#define OMAP4430_CLKSEL_OPP_MASK (0x3 << 0)
/* Used by CM_EMU_DEBUGSS_CLKCTRL */
#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27
#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK BITFIELD(27, 29)
#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK (0x7 << 27)
/* Used by CM_EMU_DEBUGSS_CLKCTRL */
#define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24
#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK BITFIELD(24, 26)
#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24)
/* Used by CM_GFX_GFX_CLKCTRL */
#define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24
#define OMAP4430_CLKSEL_SGX_FCLK_MASK BITFIELD(24, 24)
#define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24)
/*
* Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL,
* CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
*/
#define OMAP4430_CLKSEL_SOURCE_SHIFT 24
#define OMAP4430_CLKSEL_SOURCE_MASK BITFIELD(24, 25)
#define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24)
/* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24
#define OMAP4430_CLKSEL_SOURCE_24_24_MASK BITFIELD(24, 24)
#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24
#define OMAP4430_CLKSEL_UTMI_P1_MASK BITFIELD(24, 24)
#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25
#define OMAP4430_CLKSEL_UTMI_P2_MASK BITFIELD(25, 25)
#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25)
/*
* Used by CM_WKUP_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_D2D_CLKSTCTRL,
* CM_DUCATI_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
* CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_MEMIF_CLKSTCTRL,
* CM_SDMA_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL,
* CM_L3INIT_CLKSTCTRL, CM_CAM_CLKSTCTRL, CM_CEFUSE_CLKSTCTRL,
* CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3_1_CLKSTCTRL_RESTORE,
* CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL_RESTORE,
* CM_L4PER_CLKSTCTRL_RESTORE, CM_MEMIF_CLKSTCTRL_RESTORE, CM_ALWON_CLKSTCTRL,
* CM_IVAHD_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
* CM1_ABE_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE
* Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
* CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
* CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
* CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL,
* CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL,
* CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE,
* CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL,
* CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL,
* CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
* CM_WKUP_CLKSTCTRL
*/
#define OMAP4430_CLKTRCTRL_SHIFT 0
#define OMAP4430_CLKTRCTRL_MASK BITFIELD(0, 1)
#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0)
/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
#define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0
#define OMAP4430_CORE_DPLL_EMU_DIV_MASK BITFIELD(0, 6)
#define OMAP4430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)
/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
#define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8
#define OMAP4430_CORE_DPLL_EMU_MULT_MASK BITFIELD(8, 18)
#define OMAP4430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)
/* Used by REVISION_CM1, REVISION_CM2 */
#define OMAP4430_CUSTOM_SHIFT 6
#define OMAP4430_CUSTOM_MASK (0x3 << 6)
/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
/*
* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
* CM_L4CFG_DYNAMICDEP_RESTORE
*/
#define OMAP4430_D2D_DYNDEP_SHIFT 18
#define OMAP4430_D2D_DYNDEP_MASK BITFIELD(18, 18)
#define OMAP4430_D2D_DYNDEP_MASK (1 << 18)
/* Used by CM_MPU_STATICDEP */
#define OMAP4430_D2D_STATDEP_SHIFT 18
#define OMAP4430_D2D_STATDEP_MASK BITFIELD(18, 18)
#define OMAP4430_D2D_STATDEP_MASK (1 << 18)
/*
* Used by CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO,
* CM_SSC_DELTAMSTEP_DPLL_USB, CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE,
* CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
* CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
* CM_SSC_DELTAMSTEP_DPLL_MPU
* Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
* CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY,
* CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
* CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO,
* CM_SSC_DELTAMSTEP_DPLL_USB
*/
#define OMAP4430_DELTAMSTEP_SHIFT 0
#define OMAP4430_DELTAMSTEP_MASK BITFIELD(0, 19)
#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0)
/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
#define OMAP4430_DLL_OVERRIDE_SHIFT 2
#define OMAP4430_DLL_OVERRIDE_MASK BITFIELD(2, 2)
#define OMAP4430_DLL_OVERRIDE_MASK (1 << 2)
/* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */
#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT 0
#define OMAP4430_DLL_OVERRIDE_0_0_MASK BITFIELD(0, 0)
#define OMAP4430_DLL_OVERRIDE_0_0_MASK (1 << 0)
/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
#define OMAP4430_DLL_RESET_SHIFT 3
#define OMAP4430_DLL_RESET_MASK BITFIELD(3, 3)
#define OMAP4430_DLL_RESET_MASK (1 << 3)
/*
* Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB,
* CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
* CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
* CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
* CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
* CM_CLKSEL_DPLL_USB
*/
#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23
#define OMAP4430_DPLL_BYP_CLKSEL_MASK BITFIELD(23, 23)
#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23)
/* Used by CM_CLKDCOLDO_DPLL_USB */
#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK BITFIELD(8, 8)
#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
/* Used by CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_CORE */
/* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */
#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK BITFIELD(20, 20)
#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20)
/*
* Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
* CM_DIV_M3_DPLL_CORE
* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
* CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
*/
#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0
#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK BITFIELD(0, 4)
#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0)
/*
* Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
* CM_DIV_M3_DPLL_CORE
* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
* CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
*/
#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5
#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK BITFIELD(5, 5)
#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5)
/*
* Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
* CM_DIV_M3_DPLL_CORE
* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
* CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
*/
#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8
#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK BITFIELD(8, 8)
#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8)
/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */
/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10
#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BITFIELD(10, 10)
#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
/*
* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO,
* CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
* CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU
* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
* CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
* CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
*/
#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0
#define OMAP4430_DPLL_CLKOUT_DIV_MASK BITFIELD(0, 4)
#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0
#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK BITFIELD(0, 6)
#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
/*
* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO,
* CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
* CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU
* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
* CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
* CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
*/
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK BITFIELD(5, 5)
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK BITFIELD(7, 7)
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7)
/*
* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE,
* CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
* CM_DIV_M2_DPLL_MPU
* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
* CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
* CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
*/
#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BITFIELD(8, 8)
#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8
#define OMAP4430_DPLL_CORE_DPLL_EN_MASK BITFIELD(8, 10)
#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8)
/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11
#define OMAP4430_DPLL_CORE_M2_DIV_MASK BITFIELD(11, 15)
#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11)
/* Used by CM_SHADOW_FREQ_CONFIG2 */
/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3
#define OMAP4430_DPLL_CORE_M5_DIV_MASK BITFIELD(3, 7)
/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT 1
#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_MASK BITFIELD(1, 1)
#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3)
/*
* Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
* CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
* CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
* CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
* CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
*/
#define OMAP4430_DPLL_DIV_SHIFT 0
#define OMAP4430_DPLL_DIV_MASK BITFIELD(0, 6)
#define OMAP4430_DPLL_DIV_MASK (0x7f << 0)
/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
#define OMAP4430_DPLL_DIV_0_7_SHIFT 0
#define OMAP4430_DPLL_DIV_0_7_MASK BITFIELD(0, 7)
#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0)
/*
* Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8
#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK BITFIELD(8, 8)
#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
/* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3
#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK BITFIELD(3, 3)
#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3)
/*
* Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
* CM_CLKMODE_DPLL_USB
*/
#define OMAP4430_DPLL_EN_SHIFT 0
#define OMAP4430_DPLL_EN_MASK BITFIELD(0, 2)
#define OMAP4430_DPLL_EN_MASK (0x7 << 0)
/*
* Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
*/
#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10
#define OMAP4430_DPLL_LPMODE_EN_MASK BITFIELD(10, 10)
#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10)
/*
* Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
* CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
* CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
* CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
* CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
*/
#define OMAP4430_DPLL_MULT_SHIFT 8
#define OMAP4430_DPLL_MULT_MASK BITFIELD(8, 18)
#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8)
/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
#define OMAP4430_DPLL_MULT_USB_SHIFT 8
#define OMAP4430_DPLL_MULT_USB_MASK BITFIELD(8, 19)
#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8)
/*
* Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
*/
#define OMAP4430_DPLL_REGM4XEN_SHIFT 11
#define OMAP4430_DPLL_REGM4XEN_MASK BITFIELD(11, 11)
#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
/* Used by CM_CLKSEL_DPLL_USB */
#define OMAP4430_DPLL_SD_DIV_SHIFT 24
#define OMAP4430_DPLL_SD_DIV_MASK BITFIELD(24, 31)
#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24)
/*
* Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
* CM_CLKMODE_DPLL_USB
*/
#define OMAP4430_DPLL_SSC_ACK_SHIFT 13
#define OMAP4430_DPLL_SSC_ACK_MASK BITFIELD(13, 13)
#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13)
/*
* Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
* CM_CLKMODE_DPLL_USB
*/
#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14
#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK BITFIELD(14, 14)
#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
/*
* Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
* CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
* CM_CLKMODE_DPLL_USB
*/
#define OMAP4430_DPLL_SSC_EN_SHIFT 12
#define OMAP4430_DPLL_SSC_EN_MASK BITFIELD(12, 12)
#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12)
/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
/*
* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
* CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
*/
#define OMAP4430_DSS_DYNDEP_SHIFT 8
#define OMAP4430_DSS_DYNDEP_MASK BITFIELD(8, 8)
#define OMAP4430_DSS_DYNDEP_MASK (1 << 8)
/*
* Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
* CM_MPU_STATICDEP
* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
* CM_SDMA_STATICDEP_RESTORE
*/
#define OMAP4430_DSS_STATDEP_SHIFT 8
#define OMAP4430_DSS_STATDEP_MASK BITFIELD(8, 8)
#define OMAP4430_DSS_STATDEP_MASK (1 << 8)
/* Used by CM_L3_2_DYNAMICDEP */
/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
#define OMAP4430_DUCATI_DYNDEP_SHIFT 0
#define OMAP4430_DUCATI_DYNDEP_MASK BITFIELD(0, 0)
#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0)
/* Used by CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */
/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */
#define OMAP4430_DUCATI_STATDEP_SHIFT 0
#define OMAP4430_DUCATI_STATDEP_MASK BITFIELD(0, 0)
#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0)
/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
#define OMAP4430_FREQ_UPDATE_SHIFT 0
#define OMAP4430_FREQ_UPDATE_MASK BITFIELD(0, 0)
#define OMAP4430_FREQ_UPDATE_MASK (1 << 0)
/* Used by REVISION_CM1, REVISION_CM2 */
#define OMAP4430_FUNC_SHIFT 16
#define OMAP4430_FUNC_MASK (0xfff << 16)
/* Used by CM_L3_2_DYNAMICDEP */
/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
#define OMAP4430_GFX_DYNDEP_SHIFT 10
#define OMAP4430_GFX_DYNDEP_MASK BITFIELD(10, 10)
#define OMAP4430_GFX_DYNDEP_MASK (1 << 10)
/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
#define OMAP4430_GFX_STATDEP_SHIFT 10
#define OMAP4430_GFX_STATDEP_MASK BITFIELD(10, 10)
#define OMAP4430_GFX_STATDEP_MASK (1 << 10)
/* Used by CM_SHADOW_FREQ_CONFIG2 */
/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0
#define OMAP4430_GPMC_FREQ_UPDATE_MASK BITFIELD(0, 0)
#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0)
/*
* Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
* CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
* Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
* CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK BITFIELD(0, 4)
#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
/*
* Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
* CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
* Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
* CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK BITFIELD(5, 5)
#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
/*
* Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
* CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
* Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
* CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK BITFIELD(8, 8)
#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
/*
* Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
* CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
* Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
* CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK BITFIELD(12, 12)
#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
/*
* Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
* CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
* Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
* CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK BITFIELD(0, 4)
#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
/*
* Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
* CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
* Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
* CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK BITFIELD(5, 5)
#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
/*
* Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
* CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
* Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
* CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK BITFIELD(8, 8)
#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
/*
* Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
* CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
* Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
* CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK BITFIELD(12, 12)
#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
/*
* Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
* CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
* CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK BITFIELD(0, 4)
#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
/*
* Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
* CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
* CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK BITFIELD(5, 5)
#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
/*
* Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
* CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
* CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK BITFIELD(8, 8)
#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
/*
* Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
* CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
* CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK BITFIELD(12, 12)
#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
/*
* Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
* CM_DIV_M7_DPLL_CORE
* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
* CM_DIV_M7_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0
#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK BITFIELD(0, 4)
#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0)
/*
* Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
* CM_DIV_M7_DPLL_CORE
* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
* CM_DIV_M7_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5
#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK BITFIELD(5, 5)
#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5)
/*
* Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
* CM_DIV_M7_DPLL_CORE
* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
* CM_DIV_M7_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8
#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK BITFIELD(8, 8)
#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8)
/*
* Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
* CM_DIV_M7_DPLL_CORE
* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
* CM_DIV_M7_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12
#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK BITFIELD(12, 12)
/*
* Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL,
* CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL,
* CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL,
* CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL,
* CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL,
* CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
* CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
* CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
* CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
* CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
* CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
* CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
* CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL,
* CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
* CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
* CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
* CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
* CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
* CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL,
* CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
* CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
* CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
* CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
* CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL,
* CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL,
* CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
* CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
* CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL,
* CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
* CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12)
/*
* Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
* CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
* CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
* CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
* CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
* CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
* CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
* CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
* CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
* CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
* CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
* CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
* CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
* CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
* CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
* CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
* CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
* CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
* CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
* CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
* CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE,
* CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
* CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
* CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
* CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
* CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL,
* CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL,
* CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
* CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL,
* CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL,
* CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL,
* CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL,
* CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL,
* CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL
* CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
* CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
* CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
* CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
* CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
* CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
* CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
* CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
* CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
* CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
* CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
* CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
* CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
* CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
* CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
* CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
* CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
* CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
* CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
* CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
* CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
* CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
* CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
* CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
* CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
* CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
* CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
* CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
* CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
* CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
* CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
* CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
* CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
* CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
* CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
*/
#define OMAP4430_IDLEST_SHIFT 16
#define OMAP4430_IDLEST_MASK BITFIELD(16, 17)
#define OMAP4430_IDLEST_MASK (0x3 << 16)
/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
/*
* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
* CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE
*/
#define OMAP4430_ISS_DYNDEP_SHIFT 9
#define OMAP4430_ISS_DYNDEP_MASK BITFIELD(9, 9)
#define OMAP4430_ISS_DYNDEP_MASK (1 << 9)
/*
* Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
* CM_MPU_STATICDEP, CM_TESLA_STATICDEP
* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
* CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
*/
#define OMAP4430_ISS_STATDEP_SHIFT 9
#define OMAP4430_ISS_STATDEP_MASK BITFIELD(9, 9)
#define OMAP4430_ISS_STATDEP_MASK (1 << 9)
/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */
#define OMAP4430_IVAHD_DYNDEP_SHIFT 2
#define OMAP4430_IVAHD_DYNDEP_MASK BITFIELD(2, 2)
#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2)
/*
* Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
* CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
* CM_SDMA_STATICDEP_RESTORE, CM_DSS_STATICDEP, CM_MPU_STATICDEP,
* CM_TESLA_STATICDEP
* Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
* CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP,
* CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
* CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
*/
#define OMAP4430_IVAHD_STATDEP_SHIFT 2
#define OMAP4430_IVAHD_STATDEP_MASK BITFIELD(2, 2)
#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2)
/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
/*
* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
* CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
*/
#define OMAP4430_L3INIT_DYNDEP_SHIFT 7
#define OMAP4430_L3INIT_DYNDEP_MASK BITFIELD(7, 7)
#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7)
/*
* Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
* CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP
* Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
* CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
* CM_TESLA_STATICDEP
*/
#define OMAP4430_L3INIT_STATDEP_SHIFT 7
#define OMAP4430_L3INIT_STATDEP_MASK BITFIELD(7, 7)
#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7)
/*
* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
* CM_DSS_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
* Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
* CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
* CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
*/
#define OMAP4430_L3_1_DYNDEP_SHIFT 5
#define OMAP4430_L3_1_DYNDEP_MASK BITFIELD(5, 5)
#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5)
/*
* Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
* CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
* CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
* CM_MPU_STATICDEP, CM_TESLA_STATICDEP
* Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
* CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
* CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
* CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
*/
#define OMAP4430_L3_1_STATDEP_SHIFT 5
#define OMAP4430_L3_1_STATDEP_MASK BITFIELD(5, 5)
#define OMAP4430_L3_1_STATDEP_MASK (1 << 5)
/*
* Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
* CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_SDMA_DYNAMICDEP,
* CM_GFX_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
* CM_CAM_DYNAMICDEP, CM_IVAHD_DYNAMICDEP
* Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE,
* CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP,
* CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP,
* CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
* CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
*/
#define OMAP4430_L3_2_DYNDEP_SHIFT 6
#define OMAP4430_L3_2_DYNDEP_MASK BITFIELD(6, 6)
#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6)
/*
* Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
* CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
* CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
* CM_MPU_STATICDEP, CM_TESLA_STATICDEP
* Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
* CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
* CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
* CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
*/
#define OMAP4430_L3_2_STATDEP_SHIFT 6
#define OMAP4430_L3_2_STATDEP_MASK BITFIELD(6, 6)
#define OMAP4430_L3_2_STATDEP_MASK (1 << 6)
/* Used by CM_L3_1_DYNAMICDEP */
/* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */
#define OMAP4430_L4CFG_DYNDEP_SHIFT 12
#define OMAP4430_L4CFG_DYNDEP_MASK BITFIELD(12, 12)
#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12)
/*
* Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
* CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP,
* CM_TESLA_STATICDEP
* Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
* CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
* CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
*/
#define OMAP4430_L4CFG_STATDEP_SHIFT 12
#define OMAP4430_L4CFG_STATDEP_MASK BITFIELD(12, 12)
#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12)
/* Used by CM_L3_2_DYNAMICDEP */
/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
#define OMAP4430_L4PER_DYNDEP_SHIFT 13
#define OMAP4430_L4PER_DYNDEP_MASK BITFIELD(13, 13)
#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13)
/*
* Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
* CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
* CM_MPU_STATICDEP, CM_TESLA_STATICDEP
* Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
* CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
* CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
*/
#define OMAP4430_L4PER_STATDEP_SHIFT 13
#define OMAP4430_L4PER_STATDEP_MASK BITFIELD(13, 13)
#define OMAP4430_L4PER_STATDEP_MASK (1 << 13)
/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
/*
* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
* CM_L4PER_DYNAMICDEP_RESTORE
*/
#define OMAP4430_L4SEC_DYNDEP_SHIFT 14
#define OMAP4430_L4SEC_DYNDEP_MASK BITFIELD(14, 14)
#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14)
/*
* Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP,
* CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP
* Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
* CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE
*/
#define OMAP4430_L4SEC_STATDEP_SHIFT 14
#define OMAP4430_L4SEC_STATDEP_MASK BITFIELD(14, 14)
#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14)
/* Used by CM_L4CFG_DYNAMICDEP */
/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15
#define OMAP4430_L4WKUP_DYNDEP_MASK BITFIELD(15, 15)
#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15)
/*
* Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP,
* CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP
* Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
* CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
*/
#define OMAP4430_L4WKUP_STATDEP_SHIFT 15
#define OMAP4430_L4WKUP_STATDEP_MASK BITFIELD(15, 15)
#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15)
/*
* Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
* CM_MPU_DYNAMICDEP
* Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP,
* CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
* CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP
*/
#define OMAP4430_MEMIF_DYNDEP_SHIFT 4
#define OMAP4430_MEMIF_DYNDEP_MASK BITFIELD(4, 4)
#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4)
/*
* Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
* CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
* CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
* CM_MPU_STATICDEP, CM_TESLA_STATICDEP
* Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
* CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
* CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
* CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
*/
#define OMAP4430_MEMIF_STATDEP_SHIFT 4
#define OMAP4430_MEMIF_STATDEP_MASK BITFIELD(4, 4)
#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4)
/*
* Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
* CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE,
* CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
* CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
* CM_SSC_MODFREQDIV_DPLL_MPU
* Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
* CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
* CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
* CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
* CM_SSC_MODFREQDIV_DPLL_USB
*/
#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8
#define OMAP4430_MODFREQDIV_EXPONENT_MASK BITFIELD(8, 10)
#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
/*
* Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
* CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE,
* CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
* CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
* CM_SSC_MODFREQDIV_DPLL_MPU
* Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
* CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
* CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
* CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
* CM_SSC_MODFREQDIV_DPLL_USB
*/
#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0
#define OMAP4430_MODFREQDIV_MANTISSA_MASK BITFIELD(0, 6)
/*
* Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL,
* CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL,
* CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL,
* CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL,
* CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL,
* CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
* CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
* CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
* CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
* CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
* CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
* CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
* CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL,
* CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
* CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
* CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
* CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
* CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
* CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL,
* CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
* CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
* CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
* CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
* CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL,
* CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL,
* CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
* CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
* CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL,
* CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
* CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
/*
* Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
* CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
* CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
* CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
* CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
* CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
* CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
* CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
* CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
* CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
* CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
* CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
* CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
* CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
* CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
* CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
* CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
* CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
* CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
* CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
* CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE,
* CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
* CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
* CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
* CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
* CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL,
* CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL,
* CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
* CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL,
* CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL,
* CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL,
* CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL,
* CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL,
* CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL
* CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
* CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
* CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
* CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
* CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
* CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
* CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
* CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
* CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
* CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
* CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
* CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
* CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
* CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
* CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
* CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
* CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
* CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
* CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
* CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
* CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
* CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
* CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
* CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
* CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
* CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
* CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
* CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
* CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
* CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
* CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
* CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
* CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
* CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
* CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
*/
#define OMAP4430_MODULEMODE_SHIFT 0
#define OMAP4430_MODULEMODE_MASK BITFIELD(0, 1)
#define OMAP4430_MODULEMODE_MASK (0x3 << 0)
/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK BITFIELD(9, 9)
#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9)
/* Used by CM_WKUP_BANDGAP_CLKCTRL */
#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8
#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK BITFIELD(8, 8)
#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK (1 << 8)
/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 9
#define OMAP4430_OPTFCLKEN_CLK32K_MASK BITFIELD(9, 9)
/* Used by CM_ALWON_USBPHY_CLKCTRL */
#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8
#define OMAP4430_OPTFCLKEN_CLK32K_MASK (1 << 8)
/* Used by CM_CAM_ISS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK BITFIELD(8, 8)
#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8)
/*
* Used by CM_WKUP_GPIO1_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
* CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
* CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
* CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
* CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE
* Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
* CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
* CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
* CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
* CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL
*/
#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_DBCLK_MASK BITFIELD(8, 8)
#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8)
/* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
#define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK BITFIELD(8, 8)
#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK (1 << 8)
/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_DSSCLK_MASK BITFIELD(8, 8)
#define OMAP4430_OPTFCLKEN_DSSCLK_MASK (1 << 8)
/* Used by CM_WKUP_USIM_CLKCTRL */
#define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_FCLK_MASK (1 << 8)
/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8
#define OMAP4430_OPTFCLKEN_FCLK0_MASK BITFIELD(8, 8)
#define OMAP4430_OPTFCLKEN_FCLK0_MASK (1 << 8)
/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9
#define OMAP4430_OPTFCLKEN_FCLK1_MASK BITFIELD(9, 9)
#define OMAP4430_OPTFCLKEN_FCLK1_MASK (1 << 9)
/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10
#define OMAP4430_OPTFCLKEN_FCLK2_MASK BITFIELD(10, 10)
#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15
#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK BITFIELD(15, 15)
#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK BITFIELD(13, 13)
#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK BITFIELD(14, 14)
#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK BITFIELD(11, 11)
#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK BITFIELD(12, 12)
#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12)
/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK BITFIELD(8, 8)
#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK (1 << 8)
/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK BITFIELD(9, 9)
#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK (1 << 9)
/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8
#define OMAP4430_OPTFCLKEN_PHY_48M_MASK BITFIELD(8, 8)
#define OMAP4430_OPTFCLKEN_PHY_48M_MASK (1 << 8)
/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK BITFIELD(10, 10)
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 10)
/* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK BITFIELD(11, 11)
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK (1 << 11)
/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10
#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK BITFIELD(10, 10)
#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10)
/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11
#define OMAP4430_OPTFCLKEN_TV_CLK_MASK BITFIELD(11, 11)
#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11)
/* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK BITFIELD(8, 8)
#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8)
/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK BITFIELD(8, 8)
#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8)
/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK BITFIELD(9, 9)
#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9)
/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK BITFIELD(10, 10)
#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK BITFIELD(8, 8)
#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK BITFIELD(9, 9)
#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK BITFIELD(10, 10)
#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10)
/* Used by CM_L3INIT_USB_OTG_CLKCTRL */
#define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_XCLK_MASK BITFIELD(8, 8)
#define OMAP4430_OPTFCLKEN_XCLK_MASK (1 << 8)
/* Used by CM_EMU_OVERRIDE_DPLL_PER, CM_EMU_OVERRIDE_DPLL_CORE */
/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
#define OMAP4430_OVERRIDE_ENABLE_SHIFT 19
#define OMAP4430_OVERRIDE_ENABLE_MASK BITFIELD(19, 19)
#define OMAP4430_OVERRIDE_ENABLE_MASK (1 << 19)
/* Used by CM_CLKSEL_ABE */
#define OMAP4430_PAD_CLKS_GATE_SHIFT 8
#define OMAP4430_PAD_CLKS_GATE_MASK BITFIELD(8, 8)
#define OMAP4430_PAD_CLKS_GATE_MASK (1 << 8)
/* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
#define OMAP4430_PERF_CURRENT_SHIFT 0
#define OMAP4430_PERF_CURRENT_MASK BITFIELD(0, 7)
#define OMAP4430_PERF_CURRENT_MASK (0xff << 0)
/*
* Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3,
......@@ -1316,159 +1355,173 @@
* CM_IVA_DVFS_PERF_TESLA
*/
#define OMAP4430_PERF_REQ_SHIFT 0
#define OMAP4430_PERF_REQ_MASK BITFIELD(0, 7)
/* Used by CM_EMU_OVERRIDE_DPLL_PER */
#define OMAP4430_PER_DPLL_EMU_DIV_SHIFT 0
#define OMAP4430_PER_DPLL_EMU_DIV_MASK BITFIELD(0, 6)
/* Used by CM_EMU_OVERRIDE_DPLL_PER */
#define OMAP4430_PER_DPLL_EMU_MULT_SHIFT 8
#define OMAP4430_PER_DPLL_EMU_MULT_MASK BITFIELD(8, 18)
#define OMAP4430_PERF_REQ_MASK (0xff << 0)
/* Used by CM_RESTORE_ST */
#define OMAP4430_PHASE1_COMPLETED_SHIFT 0
#define OMAP4430_PHASE1_COMPLETED_MASK BITFIELD(0, 0)
#define OMAP4430_PHASE1_COMPLETED_MASK (1 << 0)
/* Used by CM_RESTORE_ST */
#define OMAP4430_PHASE2A_COMPLETED_SHIFT 1
#define OMAP4430_PHASE2A_COMPLETED_MASK BITFIELD(1, 1)
#define OMAP4430_PHASE2A_COMPLETED_MASK (1 << 1)
/* Used by CM_RESTORE_ST */
#define OMAP4430_PHASE2B_COMPLETED_SHIFT 2
#define OMAP4430_PHASE2B_COMPLETED_MASK BITFIELD(2, 2)
#define OMAP4430_PHASE2B_COMPLETED_MASK (1 << 2)
/* Used by CM_EMU_DEBUGSS_CLKCTRL */
#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20
#define OMAP4430_PMD_STM_MUX_CTRL_MASK BITFIELD(20, 21)
#define OMAP4430_PMD_STM_MUX_CTRL_MASK (0x3 << 20)
/* Used by CM_EMU_DEBUGSS_CLKCTRL */
#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22
#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK BITFIELD(22, 23)
#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22)
/* Used by CM_DYN_DEP_PRESCAL */
/* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */
#define OMAP4430_PRESCAL_SHIFT 0
#define OMAP4430_PRESCAL_MASK BITFIELD(0, 5)
#define OMAP4430_PRESCAL_MASK (0x3f << 0)
/* Used by REVISION_CM2, REVISION_CM1 */
#define OMAP4430_REV_SHIFT 0
#define OMAP4430_REV_MASK BITFIELD(0, 7)
/* Used by REVISION_CM1, REVISION_CM2 */
#define OMAP4430_R_RTL_SHIFT 11
#define OMAP4430_R_RTL_MASK (0x1f << 11)
/*
* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
* CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
* CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
*/
#define OMAP4430_SAR_MODE_SHIFT 4
#define OMAP4430_SAR_MODE_MASK BITFIELD(4, 4)
#define OMAP4430_SAR_MODE_MASK (1 << 4)
/* Used by CM_SCALE_FCLK */
#define OMAP4430_SCALE_FCLK_SHIFT 0
#define OMAP4430_SCALE_FCLK_MASK BITFIELD(0, 0)
#define OMAP4430_SCALE_FCLK_MASK (1 << 0)
/* Used by REVISION_CM1, REVISION_CM2 */
#define OMAP4430_SCHEME_SHIFT 30
#define OMAP4430_SCHEME_MASK (0x3 << 30)
/* Used by CM_L4CFG_DYNAMICDEP */
/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
#define OMAP4430_SDMA_DYNDEP_SHIFT 11
#define OMAP4430_SDMA_DYNDEP_MASK BITFIELD(11, 11)
#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11)
/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
#define OMAP4430_SDMA_STATDEP_SHIFT 11
#define OMAP4430_SDMA_STATDEP_MASK BITFIELD(11, 11)
#define OMAP4430_SDMA_STATDEP_MASK (1 << 11)
/* Used by CM_CLKSEL_ABE */
#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10
#define OMAP4430_SLIMBUS_CLK_GATE_MASK BITFIELD(10, 10)
#define OMAP4430_SLIMBUS_CLK_GATE_MASK (1 << 10)
/*
* Used by CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
* CM_DUCATI_DUCATI_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL,
* CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
* Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL,
* CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
* CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL,
* CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
* CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
* CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
* CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
* CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
* CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
* CM_CAM_ISS_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
* CM_IVAHD_IVAHD_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
* CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL
* CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
* CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
* CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL,
* CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL
*/
#define OMAP4430_STBYST_SHIFT 18
#define OMAP4430_STBYST_MASK BITFIELD(18, 18)
#define OMAP4430_STBYST_MASK (1 << 18)
/*
* Used by CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB,
* CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
* CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU
* Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
* CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
* CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
*/
#define OMAP4430_ST_DPLL_CLK_SHIFT 0
#define OMAP4430_ST_DPLL_CLK_MASK BITFIELD(0, 0)
#define OMAP4430_ST_DPLL_CLK_MASK (1 << 0)
/* Used by CM_CLKDCOLDO_DPLL_USB */
#define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9
#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK BITFIELD(9, 9)
#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9)
/*
* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE,
* CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
* CM_DIV_M2_DPLL_MPU
* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
* CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
* CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
*/
#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9
#define OMAP4430_ST_DPLL_CLKOUT_MASK BITFIELD(9, 9)
#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9)
/*
* Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
* CM_DIV_M3_DPLL_CORE
* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
* CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
*/
#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9
#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK BITFIELD(9, 9)
#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9)
/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */
/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
#define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11
#define OMAP4430_ST_DPLL_CLKOUTX2_MASK BITFIELD(11, 11)
#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11)
/*
* Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
* CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
* Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
* CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
*/
#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9
#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK BITFIELD(9, 9)
#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
/*
* Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
* CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
* Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
* CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
*/
#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9
#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK BITFIELD(9, 9)
#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
/*
* Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
* CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
* CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
*/
#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9
#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK BITFIELD(9, 9)
#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
/*
* Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
* CM_DIV_M7_DPLL_CORE
* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
* CM_DIV_M7_DPLL_PER
*/
#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9
#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK BITFIELD(9, 9)
#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9)
/*
* Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
* CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
* CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
*/
#define OMAP4430_ST_MN_BYPASS_SHIFT 8
#define OMAP4430_ST_MN_BYPASS_MASK (1 << 8)
/* Used by CM_SYS_CLKSEL */
#define OMAP4430_SYS_CLKSEL_SHIFT 0
#define OMAP4430_SYS_CLKSEL_MASK BITFIELD(0, 2)
#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0)
/* Used by CM_L4CFG_DYNAMICDEP */
/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
#define OMAP4430_TESLA_DYNDEP_SHIFT 1
#define OMAP4430_TESLA_DYNDEP_MASK BITFIELD(1, 1)
#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1)
/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
#define OMAP4430_TESLA_STATDEP_SHIFT 1
#define OMAP4430_TESLA_STATDEP_MASK BITFIELD(1, 1)
#define OMAP4430_TESLA_STATDEP_MASK (1 << 1)
/*
* Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
* CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
* CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
* Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP,
* CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE,
* CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
* CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
* CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
*/
#define OMAP4430_WINDOWSIZE_SHIFT 24
#define OMAP4430_WINDOWSIZE_MASK BITFIELD(24, 27)
#define OMAP4430_WINDOWSIZE_MASK (0xf << 24)
/* Used by REVISION_CM1, REVISION_CM2 */
#define OMAP4430_X_MAJOR_SHIFT 8
#define OMAP4430_X_MAJOR_MASK (0x7 << 8)
/* Used by REVISION_CM1, REVISION_CM2 */
#define OMAP4430_Y_MINOR_SHIFT 0
#define OMAP4430_Y_MINOR_MASK (0x3f << 0)
#endif
arch/arm/mach-omap2/cm44xx.h
View file @ 91f6c90c
......@@ -195,6 +195,42 @@
#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088)
/* CM1.RESTORE_CM1 register offsets */
#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000
#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000)
#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004
#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004)
#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008
#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008)
#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c
#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c)
#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010
#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010)
#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014
#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014)
#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018
#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018)
#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c
#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020)
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024)
#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028
#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028)
#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c
#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c)
#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030
#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030)
#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034
#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034)
#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038
#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0038)
#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c
#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x003c)
#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040
#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0040)
/* CM2 */
/* CM2.OCP_SOCKET_CM2 register offsets */
......@@ -252,8 +288,6 @@
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068)
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c)
#define OMAP4_CM_EMU_OVERRIDE_DPLL_PER_OFFSET 0x0070
#define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070)
#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080)
#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084
......@@ -296,6 +330,8 @@
#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030)
#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038
#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038)
#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040
#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0040)
/* CM2.CORE_CM2 register offsets */
#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000
......@@ -578,4 +614,54 @@
#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000)
#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020)
/* CM2.RESTORE_CM2 register offsets */
#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000
#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000)
#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004
#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004)
#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008
#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008)
#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c
#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c)
#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010
#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010)
#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014
#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014)
#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018
#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018)
#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c
#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c)
#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020
#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020)
#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024
#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024)
#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028
#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028)
#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c
#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c)
#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030
#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030)
#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034
#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034)
#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038
#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038)
#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c
#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c)
#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040
#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040)
#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044
#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0044)
#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048
#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0048)
#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c
#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x004c)
#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050
#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0050)
#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054
#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0054)
#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058
#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0058)
#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c
#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x005c)
#endif
arch/arm/mach-omap2/control.c
View file @ 91f6c90c
......@@ -25,6 +25,7 @@
#include "sdrc.h"
static void __iomem *omap2_ctrl_base;
static void __iomem *omap4_ctrl_pad_base;
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
struct omap3_scratchpad {
......@@ -137,6 +138,7 @@ static struct omap3_control_regs control_context;
#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
#define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg))
void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
{
......@@ -145,6 +147,12 @@ void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);
WARN_ON(!omap2_ctrl_base);
}
/* Static mapping, never released */
if (omap2_globals->ctrl_pad) {
omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K);
WARN_ON(!omap4_ctrl_pad_base);
}
}
void __iomem *omap_ctrl_base_get(void)
......@@ -182,6 +190,23 @@ void omap_ctrl_writel(u32 val, u16 offset)
__raw_writel(val, OMAP_CTRL_REGADDR(offset));
}
/*
* On OMAP4 control pad are not addressable from control
* core base. So the common omap_ctrl_read/write APIs breaks
* Hence export separate APIs to manage the omap4 pad control
* registers. This APIs will work only for OMAP4
*/
u32 omap4_ctrl_pad_readl(u16 offset)
{
return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
}
void omap4_ctrl_pad_writel(u32 val, u16 offset)
{
__raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
}
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
/*
* Clears the scratchpad contents in case of cold boot-
......
arch/arm/mach-omap2/hsmmc.c
View file @ 91f6c90c
......@@ -135,10 +135,11 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
*
* FIXME handle VMMC1A as needed ...
*/
reg = omap_ctrl_readl(control_pbias_offset);
reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ |
OMAP4_USBC1_ICUSB_PWRDNZ);
omap_ctrl_writel(reg, control_pbias_offset);
reg = omap4_ctrl_pad_readl(control_pbias_offset);
reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
OMAP4_MMC1_PWRDNZ_MASK |
OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
omap4_ctrl_pad_writel(reg, control_pbias_offset);
}
static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
......@@ -147,30 +148,33 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
u32 reg;
if (power_on) {
reg = omap_ctrl_readl(control_pbias_offset);
reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ;
reg = omap4_ctrl_pad_readl(control_pbias_offset);
reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
if ((1 << vdd) <= MMC_VDD_165_195)
reg &= ~OMAP4_MMC1_PBIASLITE_VMODE;
reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
else
reg |= OMAP4_MMC1_PBIASLITE_VMODE;
reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ |
OMAP4_USBC1_ICUSB_PWRDNZ);
omap_ctrl_writel(reg, control_pbias_offset);
reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
OMAP4_MMC1_PWRDNZ_MASK |
OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
omap4_ctrl_pad_writel(reg, control_pbias_offset);
/* 4 microsec delay for comparator to generate an error*/
udelay(4);
reg = omap_ctrl_readl(control_pbias_offset);
if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR) {
reg = omap4_ctrl_pad_readl(control_pbias_offset);
if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
pr_err("Pbias Voltage is not same as LDO\n");
/* Caution : On VMODE_ERROR Power Down MMC IO */
reg &= ~(OMAP4_MMC1_PWRDNZ | OMAP4_USBC1_ICUSB_PWRDNZ);
omap_ctrl_writel(reg, control_pbias_offset);
reg &= ~(OMAP4_MMC1_PWRDNZ_MASK |
OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
omap4_ctrl_pad_writel(reg, control_pbias_offset);
}
} else {
reg = omap_ctrl_readl(control_pbias_offset);
reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ |
OMAP4_MMC1_PBIASLITE_VMODE | OMAP4_MMC1_PWRDNZ |
OMAP4_USBC1_ICUSB_PWRDNZ);
omap_ctrl_writel(reg, control_pbias_offset);
reg = omap4_ctrl_pad_readl(control_pbias_offset);
reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
OMAP4_MMC1_PWRDNZ_MASK |
OMAP4_MMC1_PBIASLITE_VMODE_MASK |
OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
omap4_ctrl_pad_writel(reg, control_pbias_offset);
}
}
......@@ -218,17 +222,18 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
}
} else {
control_pbias_offset = OMAP44XX_CONTROL_PBIAS_LITE;
control_mmc1 = OMAP44XX_CONTROL_MMC1;
reg = omap_ctrl_readl(control_mmc1);
reg |= (OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 |
OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1);
reg &= ~(OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 |
OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3);
reg |= (OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL |
OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL |
OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL);
omap_ctrl_writel(reg, control_mmc1);
control_pbias_offset =
OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
reg = omap4_ctrl_pad_readl(control_mmc1);
reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
omap4_ctrl_pad_writel(reg, control_mmc1);
}
for (c = controllers; c->mmc; c++) {
......
arch/arm/mach-omap2/id.c
View file @ 91f6c90c
......@@ -60,7 +60,7 @@ int omap_type(void)
} else if (cpu_is_omap34xx()) {
val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
} else if (cpu_is_omap44xx()) {
val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS);
val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
} else {
pr_err("Cannot detect omap type!\n");
goto out;
......
arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h 0 → 100644
View file @ 91f6c90c
/*
* OMAP44xx CTRL_MODULE_CORE registers and bitfields
*
* Copyright (C) 2009-2010 Texas Instruments, Inc.
*
* Benoit Cousson (b-cousson@ti.com)
* Santosh Shilimkar (santosh.shilimkar@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
/* Base address */
#define OMAP4_CTRL_MODULE_CORE 0x4a002000
/* Registers offset */
#define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000
#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004
#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200
#define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264
#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268
#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300
#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314
#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318
#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320
#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324
#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328
#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c
#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330
#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334
#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c
#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340
#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350
#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400
#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408
#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c
#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430
#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434
#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438
#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440
#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444
#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448
#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c
#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450
#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8
#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc
/* Registers shifts and masks */
/* IP_REVISION */
#define OMAP4_IP_REV_SCHEME_SHIFT 30
#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
#define OMAP4_IP_REV_FUNC_SHIFT 16
#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
#define OMAP4_IP_REV_RTL_SHIFT 11
#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
#define OMAP4_IP_REV_MAJOR_SHIFT 8
#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
#define OMAP4_IP_REV_CUSTOM_SHIFT 6
#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
#define OMAP4_IP_REV_MINOR_SHIFT 0
#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
/* IP_HWINFO */
#define OMAP4_IP_HWINFO_SHIFT 0
#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
/* IP_SYSCONFIG */
#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
/* STD_FUSE_DIE_ID_0 */
#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0
#define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0)
/* ID_CODE */
#define OMAP4_STD_FUSE_IDCODE_SHIFT 0
#define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0)
/* STD_FUSE_DIE_ID_1 */
#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0
#define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0)
/* STD_FUSE_DIE_ID_2 */
#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0
#define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0)
/* STD_FUSE_DIE_ID_3 */
#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0
#define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0)
/* STD_FUSE_PROD_ID_0 */
#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0
#define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0)
/* STD_FUSE_PROD_ID_1 */
#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0
#define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0)
/* STD_FUSE_USB_CONF */
#define OMAP4_USB_PROD_ID_SHIFT 16
#define OMAP4_USB_PROD_ID_MASK (0xffff << 16)
#define OMAP4_USB_VENDOR_ID_SHIFT 0
#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0)
/* STD_FUSE_OPP_VDD_WKUP */
#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0
#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0)
/* STD_FUSE_OPP_BGAP */
#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0
#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0)
/* STD_FUSE_OPP_DPLL_0 */
#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0
#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0)
/* STD_FUSE_OPP_DPLL_1 */
#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0
#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0)
/* STATUS */
#define OMAP4_ATTILA_CONF_SHIFT 11
#define OMAP4_ATTILA_CONF_MASK (0x3 << 11)
#define OMAP4_DEVICE_TYPE_SHIFT 8
#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8)
#define OMAP4_SYS_BOOT_SHIFT 0
#define OMAP4_SYS_BOOT_MASK (0xff << 0)
/* DEV_CONF */
#define OMAP4_DEV_CONF_SHIFT 1
#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1)
#define OMAP4_USBPHY_PD_SHIFT 0
#define OMAP4_USBPHY_PD_MASK (1 << 0)
/* LDOVBB_IVA_VOLTAGE_CTRL */
#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26
#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26)
#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21
#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21)
#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16
#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16)
#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10
#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10)
#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5
#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5)
#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0
#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0)
/* LDOVBB_MPU_VOLTAGE_CTRL */
#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26
#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26)
#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21
#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21)
#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16
#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16)
#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10
#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10)
#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5
#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5)
#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0
#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0)
/* LDOSRAM_IVA_VOLTAGE_CTRL */
#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26
#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26)
#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21
#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21)
#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16
#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16)
#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10
#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10)
#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5
#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5)
#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0
#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0)
/* LDOSRAM_MPU_VOLTAGE_CTRL */
#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26
#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26)
#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21
#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21)
#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16
#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16)
#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10
#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10)
#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5
#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5)
#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0
#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0)
/* LDOSRAM_CORE_VOLTAGE_CTRL */
#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26
#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26)
#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21
#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21)
#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16
#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16)
#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10
#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10)
#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5
#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5)
#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0
#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0)
/* TEMP_SENSOR */
#define OMAP4_BGAP_TEMPSOFF_SHIFT 12
#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12)
#define OMAP4_BGAP_TSHUT_SHIFT 11
#define OMAP4_BGAP_TSHUT_MASK (1 << 11)
#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10
#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10)
#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9
#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9)
#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8
#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8)
#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0)
/* DPLL_NWELL_TRIM_0 */
#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29
#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24
#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24)
#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23
#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18
#define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18)
#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17
#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12
#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12)
#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11
#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6
#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6)
#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5
#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0
#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0)
/* DPLL_NWELL_TRIM_1 */
#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29
#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24
#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24)
#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23
#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18
#define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18)
#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17
#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12
#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12)
#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11
#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6
#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6)
#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5
#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0
#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0)
/* USBOTGHS_CONTROL */
#define OMAP4_DISCHRGVBUS_SHIFT 8
#define OMAP4_DISCHRGVBUS_MASK (1 << 8)
#define OMAP4_CHRGVBUS_SHIFT 7
#define OMAP4_CHRGVBUS_MASK (1 << 7)
#define OMAP4_DRVVBUS_SHIFT 6
#define OMAP4_DRVVBUS_MASK (1 << 6)
#define OMAP4_IDPULLUP_SHIFT 5
#define OMAP4_IDPULLUP_MASK (1 << 5)
#define OMAP4_IDDIG_SHIFT 4
#define OMAP4_IDDIG_MASK (1 << 4)
#define OMAP4_SESSEND_SHIFT 3
#define OMAP4_SESSEND_MASK (1 << 3)
#define OMAP4_VBUSVALID_SHIFT 2
#define OMAP4_VBUSVALID_MASK (1 << 2)
#define OMAP4_BVALID_SHIFT 1
#define OMAP4_BVALID_MASK (1 << 1)
#define OMAP4_AVALID_SHIFT 0
#define OMAP4_AVALID_MASK (1 << 0)
/* DSS_CONTROL */
#define OMAP4_DSS_MUX6_SELECT_SHIFT 0
#define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0)
/* HWOBS_CONTROL */
#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3
#define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3)
#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2
#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2)
#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1
#define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1)
#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0
#define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0)
/* DEBOBS_FINAL_MUX_SEL */
#define OMAP4_SELECT_SHIFT 0
#define OMAP4_SELECT_MASK (0xffffffff << 0)
/* DEBOBS_MMR_MPU */
#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0
#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0)
/* CONF_SDMA_REQ_SEL0 */
#define OMAP4_MULT_SHIFT 0
#define OMAP4_MULT_MASK (0x7f << 0)
/* CONF_CLK_SEL0 */
#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0
#define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0)
/* CONF_CLK_SEL1 */
#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0
#define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0)
/* CONF_CLK_SEL2 */
#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0
#define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0)
/* CONF_DPLL_FREQLOCK_SEL */
#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0
#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0)
/* CONF_DPLL_TINITZ_SEL */
#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0
#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0)
/* CONF_DPLL_PHASELOCK_SEL */
#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0
#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0)
/* CONF_DEBUG_SEL_TST_0 */
#define OMAP4_MODE_SHIFT 0
#define OMAP4_MODE_MASK (0xf << 0)
#endif
arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h 0 → 100644
View file @ 91f6c90c
/*
* OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields
*
* Copyright (C) 2009-2010 Texas Instruments, Inc.
*
* Benoit Cousson (b-cousson@ti.com)
* Santosh Shilimkar (santosh.shilimkar@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
/* Base address */
#define OMAP4_CTRL_MODULE_PAD_CORE 0x4a100000
/* Registers offset */
#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION 0x0000
#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO 0x0004
#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG 0x0010
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0 0x01d8
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1 0x01dc
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2 0x01e0
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3 0x01e4
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4 0x01e8
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5 0x01ec
#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6 0x01f0
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL 0x05a0
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE 0x05a4
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0 0x05a8
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1 0x05ac
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0 0x05b0
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1 0x05b4
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0 0x05b8
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1 0x05bc
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2 0x05c0
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC 0x05c4
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS 0x05c8
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0 0x0604
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC 0x060c
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY 0x0610
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2 0x0614
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE 0x0620
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI 0x062c
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB 0x0630
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ 0x0634
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0 0x0638
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1 0x063c
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2 0x0640
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3 0x0644
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0 0x0648
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1 0x064c
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2 0x0650
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3 0x0654
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD 0x0658
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C 0x065c
#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW 0x0660
#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R 0x0664
#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0 0x0668
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1 0x0700
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2 0x0704
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3 0x0708
#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4 0x070c
/* Registers shifts and masks */
/* IP_REVISION */
#define OMAP4_IP_REV_SCHEME_SHIFT 30
#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
#define OMAP4_IP_REV_FUNC_SHIFT 16
#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
#define OMAP4_IP_REV_RTL_SHIFT 11
#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
#define OMAP4_IP_REV_MAJOR_SHIFT 8
#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
#define OMAP4_IP_REV_CUSTOM_SHIFT 6
#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
#define OMAP4_IP_REV_MINOR_SHIFT 0
#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
/* IP_HWINFO */
#define OMAP4_IP_HWINFO_SHIFT 0
#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
/* IP_SYSCONFIG */
#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
/* PADCONF_WAKEUPEVENT_0 */
#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT 31
#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT 30
#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT 29
#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT 28
#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT 27
#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT 26
#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT 25
#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT 24
#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT 23
#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT 22
#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT 21
#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT 20
#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT 19
#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT 18
#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT 17
#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT 16
#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT 15
#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT 14
#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT 13
#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT 12
#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT 11
#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT 10
#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT 9
#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT 8
#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT 7
#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT 6
#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT 5
#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT 4
#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT 3
#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT 2
#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT 1
#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT 0
#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
/* PADCONF_WAKEUPEVENT_1 */
#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 31
#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT 30
#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT 29
#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT 28
#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT 27
#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT 26
#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT 25
#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT 24
#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT 23
#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT 22
#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT 21
#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT 20
#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT 19
#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT 18
#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT 17
#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT 16
#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT 15
#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT 14
#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT 13
#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT 12
#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT 11
#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT 10
#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT 9
#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT 8
#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT 7
#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT 6
#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT 5
#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT 4
#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT 3
#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT 2
#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT 1
#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT 0
#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
/* PADCONF_WAKEUPEVENT_2 */
#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 31
#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT 30
#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT 29
#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT 28
#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 27
#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 26
#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 25
#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 24
#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 23
#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 22
#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 21
#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 20
#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 19
#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT 18
#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 17
#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT 16
#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT 15
#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 14
#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 13
#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 12
#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 11
#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 10
#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 9
#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 8
#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 7
#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 6
#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 5
#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 4
#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 3
#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 2
#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT 0
#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
/* PADCONF_WAKEUPEVENT_3 */
#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT 31
#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT 30
#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT 29
#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT 28
#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 27
#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 26
#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 25
#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT 24
#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT 23
#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT 22
#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT 21
#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT 20
#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT 19
#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT 18
#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT 17
#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT 16
#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT 15
#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT 14
#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT 13
#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT 12
#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT 11
#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT 10
#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT 9
#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT 8
#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT 7
#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT 6
#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT 5
#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 4
#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 3
#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT 2
#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT 1
#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT 0
#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
/* PADCONF_WAKEUPEVENT_4 */
#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT 31
#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT 30
#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 29
#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 28
#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 27
#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 26
#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 25
#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 24
#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 23
#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 22
#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 21
#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 20
#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 19
#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 18
#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 17
#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 16
#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT 15
#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT 14
#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT 13
#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 12
#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 11
#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT 10
#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 9
#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 8
#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 7
#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 6
#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT 5
#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT 4
#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT 3
#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT 2
#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT 1
#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT 0
#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
/* PADCONF_WAKEUPEVENT_5 */
#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT 31
#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT 30
#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT 29
#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT 28
#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT 27
#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT 26
#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT 25
#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT 24
#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT 23
#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT 22
#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT 21
#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT 20
#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT 19
#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT 18
#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT 17
#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT 16
#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT 15
#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT 14
#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT 13
#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT 12
#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT 11
#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT 9
#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT 8
#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT 7
#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT 6
#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT 5
#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT 4
#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT 3
#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT 2
#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT 1
#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT 0
#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
/* PADCONF_WAKEUPEVENT_6 */
#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT 7
#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT 6
#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT 5
#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT 4
#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT 3
#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT 2
#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT 1
#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT 0
#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
/* CONTROL_PADCONF_GLOBAL */
#define OMAP4_FORCE_OFFMODE_EN_SHIFT 31
#define OMAP4_FORCE_OFFMODE_EN_MASK (1 << 31)
/* CONTROL_PADCONF_MODE */
#define OMAP4_VDDS_DV_BANK0_SHIFT 31
#define OMAP4_VDDS_DV_BANK0_MASK (1 << 31)
#define OMAP4_VDDS_DV_BANK1_SHIFT 30
#define OMAP4_VDDS_DV_BANK1_MASK (1 << 30)
#define OMAP4_VDDS_DV_BANK3_SHIFT 29
#define OMAP4_VDDS_DV_BANK3_MASK (1 << 29)
#define OMAP4_VDDS_DV_BANK4_SHIFT 28
#define OMAP4_VDDS_DV_BANK4_MASK (1 << 28)
#define OMAP4_VDDS_DV_BANK5_SHIFT 27
#define OMAP4_VDDS_DV_BANK5_MASK (1 << 27)
#define OMAP4_VDDS_DV_BANK6_SHIFT 26
#define OMAP4_VDDS_DV_BANK6_MASK (1 << 26)
#define OMAP4_VDDS_DV_C2C_SHIFT 25
#define OMAP4_VDDS_DV_C2C_MASK (1 << 25)
#define OMAP4_VDDS_DV_CAM_SHIFT 24
#define OMAP4_VDDS_DV_CAM_MASK (1 << 24)
#define OMAP4_VDDS_DV_GPMC_SHIFT 23
#define OMAP4_VDDS_DV_GPMC_MASK (1 << 23)
#define OMAP4_VDDS_DV_SDMMC2_SHIFT 22
#define OMAP4_VDDS_DV_SDMMC2_MASK (1 << 22)
/* CONTROL_SMART1IO_PADCONF_0 */
#define OMAP4_ABE_DR0_SC_SHIFT 30
#define OMAP4_ABE_DR0_SC_MASK (0x3 << 30)
#define OMAP4_CAM_DR0_SC_SHIFT 28
#define OMAP4_CAM_DR0_SC_MASK (0x3 << 28)
#define OMAP4_FREF_DR2_SC_SHIFT 26
#define OMAP4_FREF_DR2_SC_MASK (0x3 << 26)
#define OMAP4_FREF_DR3_SC_SHIFT 24
#define OMAP4_FREF_DR3_SC_MASK (0x3 << 24)
#define OMAP4_GPIO_DR8_SC_SHIFT 22
#define OMAP4_GPIO_DR8_SC_MASK (0x3 << 22)
#define OMAP4_GPIO_DR9_SC_SHIFT 20
#define OMAP4_GPIO_DR9_SC_MASK (0x3 << 20)
#define OMAP4_GPMC_DR2_SC_SHIFT 18
#define OMAP4_GPMC_DR2_SC_MASK (0x3 << 18)
#define OMAP4_GPMC_DR3_SC_SHIFT 16
#define OMAP4_GPMC_DR3_SC_MASK (0x3 << 16)
#define OMAP4_GPMC_DR6_SC_SHIFT 14
#define OMAP4_GPMC_DR6_SC_MASK (0x3 << 14)
#define OMAP4_HDMI_DR0_SC_SHIFT 12
#define OMAP4_HDMI_DR0_SC_MASK (0x3 << 12)
#define OMAP4_MCSPI1_DR0_SC_SHIFT 10
#define OMAP4_MCSPI1_DR0_SC_MASK (0x3 << 10)
#define OMAP4_UART1_DR0_SC_SHIFT 8
#define OMAP4_UART1_DR0_SC_MASK (0x3 << 8)
#define OMAP4_UART3_DR0_SC_SHIFT 6
#define OMAP4_UART3_DR0_SC_MASK (0x3 << 6)
#define OMAP4_UART3_DR1_SC_SHIFT 4
#define OMAP4_UART3_DR1_SC_MASK (0x3 << 4)
#define OMAP4_UNIPRO_DR0_SC_SHIFT 2
#define OMAP4_UNIPRO_DR0_SC_MASK (0x3 << 2)
#define OMAP4_UNIPRO_DR1_SC_SHIFT 0
#define OMAP4_UNIPRO_DR1_SC_MASK (0x3 << 0)
/* CONTROL_SMART1IO_PADCONF_1 */
#define OMAP4_ABE_DR0_LB_SHIFT 30
#define OMAP4_ABE_DR0_LB_MASK (0x3 << 30)
#define OMAP4_CAM_DR0_LB_SHIFT 28
#define OMAP4_CAM_DR0_LB_MASK (0x3 << 28)
#define OMAP4_FREF_DR2_LB_SHIFT 26
#define OMAP4_FREF_DR2_LB_MASK (0x3 << 26)
#define OMAP4_FREF_DR3_LB_SHIFT 24
#define OMAP4_FREF_DR3_LB_MASK (0x3 << 24)
#define OMAP4_GPIO_DR8_LB_SHIFT 22
#define OMAP4_GPIO_DR8_LB_MASK (0x3 << 22)
#define OMAP4_GPIO_DR9_LB_SHIFT 20
#define OMAP4_GPIO_DR9_LB_MASK (0x3 << 20)
#define OMAP4_GPMC_DR2_LB_SHIFT 18
#define OMAP4_GPMC_DR2_LB_MASK (0x3 << 18)
#define OMAP4_GPMC_DR3_LB_SHIFT 16
#define OMAP4_GPMC_DR3_LB_MASK (0x3 << 16)
#define OMAP4_GPMC_DR6_LB_SHIFT 14
#define OMAP4_GPMC_DR6_LB_MASK (0x3 << 14)
#define OMAP4_HDMI_DR0_LB_SHIFT 12
#define OMAP4_HDMI_DR0_LB_MASK (0x3 << 12)
#define OMAP4_MCSPI1_DR0_LB_SHIFT 10
#define OMAP4_MCSPI1_DR0_LB_MASK (0x3 << 10)
#define OMAP4_UART1_DR0_LB_SHIFT 8
#define OMAP4_UART1_DR0_LB_MASK (0x3 << 8)
#define OMAP4_UART3_DR0_LB_SHIFT 6
#define OMAP4_UART3_DR0_LB_MASK (0x3 << 6)
#define OMAP4_UART3_DR1_LB_SHIFT 4
#define OMAP4_UART3_DR1_LB_MASK (0x3 << 4)
#define OMAP4_UNIPRO_DR0_LB_SHIFT 2
#define OMAP4_UNIPRO_DR0_LB_MASK (0x3 << 2)
#define OMAP4_UNIPRO_DR1_LB_SHIFT 0
#define OMAP4_UNIPRO_DR1_LB_MASK (0x3 << 0)
/* CONTROL_SMART2IO_PADCONF_0 */
#define OMAP4_C2C_DR0_LB_SHIFT 31
#define OMAP4_C2C_DR0_LB_MASK (1 << 31)
#define OMAP4_DPM_DR1_LB_SHIFT 30
#define OMAP4_DPM_DR1_LB_MASK (1 << 30)
#define OMAP4_DPM_DR2_LB_SHIFT 29
#define OMAP4_DPM_DR2_LB_MASK (1 << 29)
#define OMAP4_DPM_DR3_LB_SHIFT 28
#define OMAP4_DPM_DR3_LB_MASK (1 << 28)
#define OMAP4_GPIO_DR0_LB_SHIFT 27
#define OMAP4_GPIO_DR0_LB_MASK (1 << 27)
#define OMAP4_GPIO_DR1_LB_SHIFT 26
#define OMAP4_GPIO_DR1_LB_MASK (1 << 26)
#define OMAP4_GPIO_DR10_LB_SHIFT 25
#define OMAP4_GPIO_DR10_LB_MASK (1 << 25)
#define OMAP4_GPIO_DR2_LB_SHIFT 24
#define OMAP4_GPIO_DR2_LB_MASK (1 << 24)
#define OMAP4_GPMC_DR0_LB_SHIFT 23
#define OMAP4_GPMC_DR0_LB_MASK (1 << 23)
#define OMAP4_GPMC_DR1_LB_SHIFT 22
#define OMAP4_GPMC_DR1_LB_MASK (1 << 22)
#define OMAP4_GPMC_DR4_LB_SHIFT 21
#define OMAP4_GPMC_DR4_LB_MASK (1 << 21)
#define OMAP4_GPMC_DR5_LB_SHIFT 20
#define OMAP4_GPMC_DR5_LB_MASK (1 << 20)
#define OMAP4_GPMC_DR7_LB_SHIFT 19
#define OMAP4_GPMC_DR7_LB_MASK (1 << 19)
#define OMAP4_HSI2_DR0_LB_SHIFT 18
#define OMAP4_HSI2_DR0_LB_MASK (1 << 18)
#define OMAP4_HSI2_DR1_LB_SHIFT 17
#define OMAP4_HSI2_DR1_LB_MASK (1 << 17)
#define OMAP4_HSI2_DR2_LB_SHIFT 16
#define OMAP4_HSI2_DR2_LB_MASK (1 << 16)
#define OMAP4_KPD_DR0_LB_SHIFT 15
#define OMAP4_KPD_DR0_LB_MASK (1 << 15)
#define OMAP4_KPD_DR1_LB_SHIFT 14
#define OMAP4_KPD_DR1_LB_MASK (1 << 14)
#define OMAP4_PDM_DR0_LB_SHIFT 13
#define OMAP4_PDM_DR0_LB_MASK (1 << 13)
#define OMAP4_SDMMC2_DR0_LB_SHIFT 12
#define OMAP4_SDMMC2_DR0_LB_MASK (1 << 12)
#define OMAP4_SDMMC3_DR0_LB_SHIFT 11
#define OMAP4_SDMMC3_DR0_LB_MASK (1 << 11)
#define OMAP4_SDMMC4_DR0_LB_SHIFT 10
#define OMAP4_SDMMC4_DR0_LB_MASK (1 << 10)
#define OMAP4_SDMMC4_DR1_LB_SHIFT 9
#define OMAP4_SDMMC4_DR1_LB_MASK (1 << 9)
#define OMAP4_SPI3_DR0_LB_SHIFT 8
#define OMAP4_SPI3_DR0_LB_MASK (1 << 8)
#define OMAP4_SPI3_DR1_LB_SHIFT 7
#define OMAP4_SPI3_DR1_LB_MASK (1 << 7)
#define OMAP4_UART3_DR2_LB_SHIFT 6
#define OMAP4_UART3_DR2_LB_MASK (1 << 6)
#define OMAP4_UART3_DR3_LB_SHIFT 5
#define OMAP4_UART3_DR3_LB_MASK (1 << 5)
#define OMAP4_UART3_DR4_LB_SHIFT 4
#define OMAP4_UART3_DR4_LB_MASK (1 << 4)
#define OMAP4_UART3_DR5_LB_SHIFT 3
#define OMAP4_UART3_DR5_LB_MASK (1 << 3)
#define OMAP4_USBA0_DR1_LB_SHIFT 2
#define OMAP4_USBA0_DR1_LB_MASK (1 << 2)
#define OMAP4_USBA_DR2_LB_SHIFT 1
#define OMAP4_USBA_DR2_LB_MASK (1 << 1)
/* CONTROL_SMART2IO_PADCONF_1 */
#define OMAP4_USBB1_DR0_LB_SHIFT 31
#define OMAP4_USBB1_DR0_LB_MASK (1 << 31)
#define OMAP4_USBB2_DR0_LB_SHIFT 30
#define OMAP4_USBB2_DR0_LB_MASK (1 << 30)
#define OMAP4_USBA0_DR0_LB_SHIFT 29
#define OMAP4_USBA0_DR0_LB_MASK (1 << 29)
/* CONTROL_SMART3IO_PADCONF_0 */
#define OMAP4_DMIC_DR0_MB_SHIFT 30
#define OMAP4_DMIC_DR0_MB_MASK (0x3 << 30)
#define OMAP4_GPIO_DR3_MB_SHIFT 28
#define OMAP4_GPIO_DR3_MB_MASK (0x3 << 28)
#define OMAP4_GPIO_DR4_MB_SHIFT 26
#define OMAP4_GPIO_DR4_MB_MASK (0x3 << 26)
#define OMAP4_GPIO_DR5_MB_SHIFT 24
#define OMAP4_GPIO_DR5_MB_MASK (0x3 << 24)
#define OMAP4_GPIO_DR6_MB_SHIFT 22
#define OMAP4_GPIO_DR6_MB_MASK (0x3 << 22)
#define OMAP4_HSI_DR1_MB_SHIFT 20
#define OMAP4_HSI_DR1_MB_MASK (0x3 << 20)
#define OMAP4_HSI_DR2_MB_SHIFT 18
#define OMAP4_HSI_DR2_MB_MASK (0x3 << 18)
#define OMAP4_HSI_DR3_MB_SHIFT 16
#define OMAP4_HSI_DR3_MB_MASK (0x3 << 16)
#define OMAP4_MCBSP2_DR0_MB_SHIFT 14
#define OMAP4_MCBSP2_DR0_MB_MASK (0x3 << 14)
#define OMAP4_MCSPI4_DR0_MB_SHIFT 12
#define OMAP4_MCSPI4_DR0_MB_MASK (0x3 << 12)
#define OMAP4_MCSPI4_DR1_MB_SHIFT 10
#define OMAP4_MCSPI4_DR1_MB_MASK (0x3 << 10)
#define OMAP4_SDMMC3_DR0_MB_SHIFT 8
#define OMAP4_SDMMC3_DR0_MB_MASK (0x3 << 8)
#define OMAP4_SPI2_DR0_MB_SHIFT 0
#define OMAP4_SPI2_DR0_MB_MASK (0x3 << 0)
/* CONTROL_SMART3IO_PADCONF_1 */
#define OMAP4_SPI2_DR1_MB_SHIFT 30
#define OMAP4_SPI2_DR1_MB_MASK (0x3 << 30)
#define OMAP4_SPI2_DR2_MB_SHIFT 28
#define OMAP4_SPI2_DR2_MB_MASK (0x3 << 28)
#define OMAP4_UART2_DR0_MB_SHIFT 26
#define OMAP4_UART2_DR0_MB_MASK (0x3 << 26)
#define OMAP4_UART2_DR1_MB_SHIFT 24
#define OMAP4_UART2_DR1_MB_MASK (0x3 << 24)
#define OMAP4_UART4_DR0_MB_SHIFT 22
#define OMAP4_UART4_DR0_MB_MASK (0x3 << 22)
#define OMAP4_HSI_DR0_MB_SHIFT 20
#define OMAP4_HSI_DR0_MB_MASK (0x3 << 20)
/* CONTROL_SMART3IO_PADCONF_2 */
#define OMAP4_DMIC_DR0_LB_SHIFT 31
#define OMAP4_DMIC_DR0_LB_MASK (1 << 31)
#define OMAP4_GPIO_DR3_LB_SHIFT 30
#define OMAP4_GPIO_DR3_LB_MASK (1 << 30)
#define OMAP4_GPIO_DR4_LB_SHIFT 29
#define OMAP4_GPIO_DR4_LB_MASK (1 << 29)
#define OMAP4_GPIO_DR5_LB_SHIFT 28
#define OMAP4_GPIO_DR5_LB_MASK (1 << 28)
#define OMAP4_GPIO_DR6_LB_SHIFT 27
#define OMAP4_GPIO_DR6_LB_MASK (1 << 27)
#define OMAP4_HSI_DR1_LB_SHIFT 26
#define OMAP4_HSI_DR1_LB_MASK (1 << 26)
#define OMAP4_HSI_DR2_LB_SHIFT 25
#define OMAP4_HSI_DR2_LB_MASK (1 << 25)
#define OMAP4_HSI_DR3_LB_SHIFT 24
#define OMAP4_HSI_DR3_LB_MASK (1 << 24)
#define OMAP4_MCBSP2_DR0_LB_SHIFT 23
#define OMAP4_MCBSP2_DR0_LB_MASK (1 << 23)
#define OMAP4_MCSPI4_DR0_LB_SHIFT 22
#define OMAP4_MCSPI4_DR0_LB_MASK (1 << 22)
#define OMAP4_MCSPI4_DR1_LB_SHIFT 21
#define OMAP4_MCSPI4_DR1_LB_MASK (1 << 21)
#define OMAP4_SLIMBUS2_DR0_LB_SHIFT 18
#define OMAP4_SLIMBUS2_DR0_LB_MASK (1 << 18)
#define OMAP4_SPI2_DR0_LB_SHIFT 16
#define OMAP4_SPI2_DR0_LB_MASK (1 << 16)
#define OMAP4_SPI2_DR1_LB_SHIFT 15
#define OMAP4_SPI2_DR1_LB_MASK (1 << 15)
#define OMAP4_SPI2_DR2_LB_SHIFT 14
#define OMAP4_SPI2_DR2_LB_MASK (1 << 14)
#define OMAP4_UART2_DR0_LB_SHIFT 13
#define OMAP4_UART2_DR0_LB_MASK (1 << 13)
#define OMAP4_UART2_DR1_LB_SHIFT 12
#define OMAP4_UART2_DR1_LB_MASK (1 << 12)
#define OMAP4_UART4_DR0_LB_SHIFT 11
#define OMAP4_UART4_DR0_LB_MASK (1 << 11)
#define OMAP4_HSI_DR0_LB_SHIFT 10
#define OMAP4_HSI_DR0_LB_MASK (1 << 10)
/* CONTROL_USBB_HSIC */
#define OMAP4_USBB2_DR1_SR_SHIFT 30
#define OMAP4_USBB2_DR1_SR_MASK (0x3 << 30)
#define OMAP4_USBB2_DR1_I_SHIFT 27
#define OMAP4_USBB2_DR1_I_MASK (0x7 << 27)
#define OMAP4_USBB1_DR1_SR_SHIFT 25
#define OMAP4_USBB1_DR1_SR_MASK (0x3 << 25)
#define OMAP4_USBB1_DR1_I_SHIFT 22
#define OMAP4_USBB1_DR1_I_MASK (0x7 << 22)
#define OMAP4_USBB1_HSIC_DATA_WD_SHIFT 20
#define OMAP4_USBB1_HSIC_DATA_WD_MASK (0x3 << 20)
#define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT 18
#define OMAP4_USBB1_HSIC_STROBE_WD_MASK (0x3 << 18)
#define OMAP4_USBB2_HSIC_DATA_WD_SHIFT 16
#define OMAP4_USBB2_HSIC_DATA_WD_MASK (0x3 << 16)
#define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT 14
#define OMAP4_USBB2_HSIC_STROBE_WD_MASK (0x3 << 14)
#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 13
#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 13)
#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT 11
#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 11)
#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 10
#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 10)
#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT 8
#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 8)
#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 7
#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 7)
#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT 5
#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 5)
#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 4
#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 4)
#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT 2
#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 2)
/* CONTROL_SLIMBUS */
#define OMAP4_SLIMBUS1_DR0_MB_SHIFT 30
#define OMAP4_SLIMBUS1_DR0_MB_MASK (0x3 << 30)
#define OMAP4_SLIMBUS1_DR1_MB_SHIFT 28
#define OMAP4_SLIMBUS1_DR1_MB_MASK (0x3 << 28)
#define OMAP4_SLIMBUS2_DR0_MB_SHIFT 26
#define OMAP4_SLIMBUS2_DR0_MB_MASK (0x3 << 26)
#define OMAP4_SLIMBUS2_DR1_MB_SHIFT 24
#define OMAP4_SLIMBUS2_DR1_MB_MASK (0x3 << 24)
#define OMAP4_SLIMBUS2_DR2_MB_SHIFT 22
#define OMAP4_SLIMBUS2_DR2_MB_MASK (0x3 << 22)
#define OMAP4_SLIMBUS2_DR3_MB_SHIFT 20
#define OMAP4_SLIMBUS2_DR3_MB_MASK (0x3 << 20)
#define OMAP4_SLIMBUS1_DR0_LB_SHIFT 19
#define OMAP4_SLIMBUS1_DR0_LB_MASK (1 << 19)
#define OMAP4_SLIMBUS2_DR1_LB_SHIFT 18
#define OMAP4_SLIMBUS2_DR1_LB_MASK (1 << 18)
/* CONTROL_PBIASLITE */
#define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT 31
#define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK (1 << 31)
#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT 30
#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 30)
#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT 29
#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK (1 << 29)
#define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT 28
#define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK (1 << 28)
#define OMAP4_USIM_PBIASLITE_VMODE_SHIFT 27
#define OMAP4_USIM_PBIASLITE_VMODE_MASK (1 << 27)
#define OMAP4_MMC1_PWRDNZ_SHIFT 26
#define OMAP4_MMC1_PWRDNZ_MASK (1 << 26)
#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT 25
#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK (1 << 25)
#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT 24
#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 24)
#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT 23
#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23)
#define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT 22
#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22)
#define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT 21
#define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21)
#define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT 20
#define OMAP4_USBC1_ICUSB_PWRDNZ_MASK (1 << 20)
/* CONTROL_I2C_0 */
#define OMAP4_I2C4_SDA_GLFENB_SHIFT 31
#define OMAP4_I2C4_SDA_GLFENB_MASK (1 << 31)
#define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT 29
#define OMAP4_I2C4_SDA_LOAD_BITS_MASK (0x3 << 29)
#define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT 28
#define OMAP4_I2C4_SDA_PULLUPRESX_MASK (1 << 28)
#define OMAP4_I2C3_SDA_GLFENB_SHIFT 27
#define OMAP4_I2C3_SDA_GLFENB_MASK (1 << 27)
#define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT 25
#define OMAP4_I2C3_SDA_LOAD_BITS_MASK (0x3 << 25)
#define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT 24
#define OMAP4_I2C3_SDA_PULLUPRESX_MASK (1 << 24)
#define OMAP4_I2C2_SDA_GLFENB_SHIFT 23
#define OMAP4_I2C2_SDA_GLFENB_MASK (1 << 23)
#define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT 21
#define OMAP4_I2C2_SDA_LOAD_BITS_MASK (0x3 << 21)
#define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT 20
#define OMAP4_I2C2_SDA_PULLUPRESX_MASK (1 << 20)
#define OMAP4_I2C1_SDA_GLFENB_SHIFT 19
#define OMAP4_I2C1_SDA_GLFENB_MASK (1 << 19)
#define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT 17
#define OMAP4_I2C1_SDA_LOAD_BITS_MASK (0x3 << 17)
#define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT 16
#define OMAP4_I2C1_SDA_PULLUPRESX_MASK (1 << 16)
#define OMAP4_I2C4_SCL_GLFENB_SHIFT 15
#define OMAP4_I2C4_SCL_GLFENB_MASK (1 << 15)
#define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT 13
#define OMAP4_I2C4_SCL_LOAD_BITS_MASK (0x3 << 13)
#define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT 12
#define OMAP4_I2C4_SCL_PULLUPRESX_MASK (1 << 12)
#define OMAP4_I2C3_SCL_GLFENB_SHIFT 11
#define OMAP4_I2C3_SCL_GLFENB_MASK (1 << 11)
#define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT 9
#define OMAP4_I2C3_SCL_LOAD_BITS_MASK (0x3 << 9)
#define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT 8
#define OMAP4_I2C3_SCL_PULLUPRESX_MASK (1 << 8)
#define OMAP4_I2C2_SCL_GLFENB_SHIFT 7
#define OMAP4_I2C2_SCL_GLFENB_MASK (1 << 7)
#define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT 5
#define OMAP4_I2C2_SCL_LOAD_BITS_MASK (0x3 << 5)
#define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT 4
#define OMAP4_I2C2_SCL_PULLUPRESX_MASK (1 << 4)
#define OMAP4_I2C1_SCL_GLFENB_SHIFT 3
#define OMAP4_I2C1_SCL_GLFENB_MASK (1 << 3)
#define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT 1
#define OMAP4_I2C1_SCL_LOAD_BITS_MASK (0x3 << 1)
#define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT 0
#define OMAP4_I2C1_SCL_PULLUPRESX_MASK (1 << 0)
/* CONTROL_CAMERA_RX */
#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT 31
#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK (1 << 31)
#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29
#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29)
#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24
#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24)
#define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT 22
#define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK (0x3 << 22)
#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21
#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21)
#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19
#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19)
#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18
#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18)
#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16
#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16)
/* CONTROL_AVDAC */
#define OMAP4_AVDAC_ACEN_SHIFT 31
#define OMAP4_AVDAC_ACEN_MASK (1 << 31)
#define OMAP4_AVDAC_TVOUTBYPASS_SHIFT 30
#define OMAP4_AVDAC_TVOUTBYPASS_MASK (1 << 30)
#define OMAP4_AVDAC_INPUTINV_SHIFT 29
#define OMAP4_AVDAC_INPUTINV_MASK (1 << 29)
#define OMAP4_AVDAC_CTL_SHIFT 13
#define OMAP4_AVDAC_CTL_MASK (0xffff << 13)
#define OMAP4_AVDAC_CTL_WR_ACK_SHIFT 12
#define OMAP4_AVDAC_CTL_WR_ACK_MASK (1 << 12)
/* CONTROL_HDMI_TX_PHY */
#define OMAP4_HDMITXPHY_PADORDER_SHIFT 31
#define OMAP4_HDMITXPHY_PADORDER_MASK (1 << 31)
#define OMAP4_HDMITXPHY_TXVALID_SHIFT 30
#define OMAP4_HDMITXPHY_TXVALID_MASK (1 << 30)
#define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT 29
#define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK (1 << 29)
#define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT 28
#define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK (1 << 28)
/* CONTROL_MMC2 */
#define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT 31
#define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK (1 << 31)
/* CONTROL_DSIPHY */
#define OMAP4_DSI2_LANEENABLE_SHIFT 29
#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
#define OMAP4_DSI1_LANEENABLE_SHIFT 24
#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
#define OMAP4_DSI1_PIPD_SHIFT 19
#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
#define OMAP4_DSI2_PIPD_SHIFT 14
#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
/* CONTROL_MCBSPLP */
#define OMAP4_ALBCTRLRX_FSX_SHIFT 31
#define OMAP4_ALBCTRLRX_FSX_MASK (1 << 31)
#define OMAP4_ALBCTRLRX_CLKX_SHIFT 30
#define OMAP4_ALBCTRLRX_CLKX_MASK (1 << 30)
#define OMAP4_ABE_MCBSP1_DR_EN_SHIFT 29
#define OMAP4_ABE_MCBSP1_DR_EN_MASK (1 << 29)
/* CONTROL_USB2PHYCORE */
#define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT 31
#define OMAP4_USB2PHY_AUTORESUME_EN_MASK (1 << 31)
#define OMAP4_USB2PHY_DISCHGDET_SHIFT 30
#define OMAP4_USB2PHY_DISCHGDET_MASK (1 << 30)
#define OMAP4_USB2PHY_GPIOMODE_SHIFT 29
#define OMAP4_USB2PHY_GPIOMODE_MASK (1 << 29)
#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT 28
#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK (1 << 28)
#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT 27
#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK (1 << 27)
#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT 26
#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK (1 << 26)
#define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT 25
#define OMAP4_USB2PHY_CHG_VSRC_EN_MASK (1 << 25)
#define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT 24
#define OMAP4_USB2PHY_CHG_ISINK_EN_MASK (1 << 24)
#define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT 21
#define OMAP4_USB2PHY_CHG_DET_STATUS_MASK (0x7 << 21)
#define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT 20
#define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK (1 << 20)
#define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT 19
#define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK (1 << 19)
#define OMAP4_USB2PHY_DATADET_SHIFT 18
#define OMAP4_USB2PHY_DATADET_MASK (1 << 18)
#define OMAP4_USB2PHY_SINKONDP_SHIFT 17
#define OMAP4_USB2PHY_SINKONDP_MASK (1 << 17)
#define OMAP4_USB2PHY_SRCONDM_SHIFT 16
#define OMAP4_USB2PHY_SRCONDM_MASK (1 << 16)
#define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT 15
#define OMAP4_USB2PHY_RESTARTCHGDET_MASK (1 << 15)
#define OMAP4_USB2PHY_CHGDETDONE_SHIFT 14
#define OMAP4_USB2PHY_CHGDETDONE_MASK (1 << 14)
#define OMAP4_USB2PHY_CHGDETECTED_SHIFT 13
#define OMAP4_USB2PHY_CHGDETECTED_MASK (1 << 13)
#define OMAP4_USB2PHY_MCPCPUEN_SHIFT 12
#define OMAP4_USB2PHY_MCPCPUEN_MASK (1 << 12)
#define OMAP4_USB2PHY_MCPCMODEEN_SHIFT 11
#define OMAP4_USB2PHY_MCPCMODEEN_MASK (1 << 11)
#define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT 10
#define OMAP4_USB2PHY_RESETDONEMCLK_MASK (1 << 10)
#define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT 9
#define OMAP4_USB2PHY_UTMIRESETDONE_MASK (1 << 9)
#define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT 8
#define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK (1 << 8)
#define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT 7
#define OMAP4_USB2PHY_DATAPOLARITYN_MASK (1 << 7)
#define OMAP4_USBDPLL_FREQLOCK_SHIFT 6
#define OMAP4_USBDPLL_FREQLOCK_MASK (1 << 6)
#define OMAP4_USB2PHY_RESETDONETCLK_SHIFT 5
#define OMAP4_USB2PHY_RESETDONETCLK_MASK (1 << 5)
/* CONTROL_I2C_1 */
#define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT 31
#define OMAP4_HDMI_DDC_SDA_GLFENB_MASK (1 << 31)
#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT 29
#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK (0x3 << 29)
#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT 28
#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28)
#define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT 27
#define OMAP4_HDMI_DDC_SCL_GLFENB_MASK (1 << 27)
#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT 25
#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK (0x3 << 25)
#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT 24
#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24)
#define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT 23
#define OMAP4_HDMI_DDC_SDA_HSMODE_MASK (1 << 23)
#define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT 22
#define OMAP4_HDMI_DDC_SDA_NMODE_MASK (1 << 22)
#define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT 21
#define OMAP4_HDMI_DDC_SCL_HSMODE_MASK (1 << 21)
#define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT 20
#define OMAP4_HDMI_DDC_SCL_NMODE_MASK (1 << 20)
/* CONTROL_MMC1 */
#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT 31
#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31)
#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT 30
#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30)
#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT 29
#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29)
#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT 28
#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28)
#define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT 27
#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27)
#define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT 26
#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26)
#define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT 25
#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25)
#define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT 24
#define OMAP4_USBC1_DR0_SPEEDCTRL_MASK (1 << 24)
#define OMAP4_USB_FD_CDEN_SHIFT 23
#define OMAP4_USB_FD_CDEN_MASK (1 << 23)
#define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT 22
#define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK (1 << 22)
#define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT 21
#define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK (1 << 21)
/* CONTROL_HSI */
#define OMAP4_HSI1_CALLOOP_SEL_SHIFT 31
#define OMAP4_HSI1_CALLOOP_SEL_MASK (1 << 31)
#define OMAP4_HSI1_CALMUX_SEL_SHIFT 30
#define OMAP4_HSI1_CALMUX_SEL_MASK (1 << 30)
#define OMAP4_HSI2_CALLOOP_SEL_SHIFT 29
#define OMAP4_HSI2_CALLOOP_SEL_MASK (1 << 29)
#define OMAP4_HSI2_CALMUX_SEL_SHIFT 28
#define OMAP4_HSI2_CALMUX_SEL_MASK (1 << 28)
/* CONTROL_USB */
#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT 31
#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK (1 << 31)
#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT 30
#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK (1 << 30)
/* CONTROL_HDQ */
#define OMAP4_HDQ_SIO_PWRDNZ_SHIFT 31
#define OMAP4_HDQ_SIO_PWRDNZ_MASK (1 << 31)
/* CONTROL_LPDDR2IO1_0 */
#define OMAP4_LPDDR2IO1_GR4_SR_SHIFT 30
#define OMAP4_LPDDR2IO1_GR4_SR_MASK (0x3 << 30)
#define OMAP4_LPDDR2IO1_GR4_I_SHIFT 27
#define OMAP4_LPDDR2IO1_GR4_I_MASK (0x7 << 27)
#define OMAP4_LPDDR2IO1_GR4_WD_SHIFT 25
#define OMAP4_LPDDR2IO1_GR4_WD_MASK (0x3 << 25)
#define OMAP4_LPDDR2IO1_GR3_SR_SHIFT 22
#define OMAP4_LPDDR2IO1_GR3_SR_MASK (0x3 << 22)
#define OMAP4_LPDDR2IO1_GR3_I_SHIFT 19
#define OMAP4_LPDDR2IO1_GR3_I_MASK (0x7 << 19)
#define OMAP4_LPDDR2IO1_GR3_WD_SHIFT 17
#define OMAP4_LPDDR2IO1_GR3_WD_MASK (0x3 << 17)
#define OMAP4_LPDDR2IO1_GR2_SR_SHIFT 14
#define OMAP4_LPDDR2IO1_GR2_SR_MASK (0x3 << 14)
#define OMAP4_LPDDR2IO1_GR2_I_SHIFT 11
#define OMAP4_LPDDR2IO1_GR2_I_MASK (0x7 << 11)
#define OMAP4_LPDDR2IO1_GR2_WD_SHIFT 9
#define OMAP4_LPDDR2IO1_GR2_WD_MASK (0x3 << 9)
#define OMAP4_LPDDR2IO1_GR1_SR_SHIFT 6
#define OMAP4_LPDDR2IO1_GR1_SR_MASK (0x3 << 6)
#define OMAP4_LPDDR2IO1_GR1_I_SHIFT 3
#define OMAP4_LPDDR2IO1_GR1_I_MASK (0x7 << 3)
#define OMAP4_LPDDR2IO1_GR1_WD_SHIFT 1
#define OMAP4_LPDDR2IO1_GR1_WD_MASK (0x3 << 1)
/* CONTROL_LPDDR2IO1_1 */
#define OMAP4_LPDDR2IO1_GR8_SR_SHIFT 30
#define OMAP4_LPDDR2IO1_GR8_SR_MASK (0x3 << 30)
#define OMAP4_LPDDR2IO1_GR8_I_SHIFT 27
#define OMAP4_LPDDR2IO1_GR8_I_MASK (0x7 << 27)
#define OMAP4_LPDDR2IO1_GR8_WD_SHIFT 25
#define OMAP4_LPDDR2IO1_GR8_WD_MASK (0x3 << 25)
#define OMAP4_LPDDR2IO1_GR7_SR_SHIFT 22
#define OMAP4_LPDDR2IO1_GR7_SR_MASK (0x3 << 22)
#define OMAP4_LPDDR2IO1_GR7_I_SHIFT 19
#define OMAP4_LPDDR2IO1_GR7_I_MASK (0x7 << 19)
#define OMAP4_LPDDR2IO1_GR7_WD_SHIFT 17
#define OMAP4_LPDDR2IO1_GR7_WD_MASK (0x3 << 17)
#define OMAP4_LPDDR2IO1_GR6_SR_SHIFT 14
#define OMAP4_LPDDR2IO1_GR6_SR_MASK (0x3 << 14)
#define OMAP4_LPDDR2IO1_GR6_I_SHIFT 11
#define OMAP4_LPDDR2IO1_GR6_I_MASK (0x7 << 11)
#define OMAP4_LPDDR2IO1_GR6_WD_SHIFT 9
#define OMAP4_LPDDR2IO1_GR6_WD_MASK (0x3 << 9)
#define OMAP4_LPDDR2IO1_GR5_SR_SHIFT 6
#define OMAP4_LPDDR2IO1_GR5_SR_MASK (0x3 << 6)
#define OMAP4_LPDDR2IO1_GR5_I_SHIFT 3
#define OMAP4_LPDDR2IO1_GR5_I_MASK (0x7 << 3)
#define OMAP4_LPDDR2IO1_GR5_WD_SHIFT 1
#define OMAP4_LPDDR2IO1_GR5_WD_MASK (0x3 << 1)
/* CONTROL_LPDDR2IO1_2 */
#define OMAP4_LPDDR2IO1_GR11_SR_SHIFT 30
#define OMAP4_LPDDR2IO1_GR11_SR_MASK (0x3 << 30)
#define OMAP4_LPDDR2IO1_GR11_I_SHIFT 27
#define OMAP4_LPDDR2IO1_GR11_I_MASK (0x7 << 27)
#define OMAP4_LPDDR2IO1_GR11_WD_SHIFT 25
#define OMAP4_LPDDR2IO1_GR11_WD_MASK (0x3 << 25)
#define OMAP4_LPDDR2IO1_GR10_SR_SHIFT 22
#define OMAP4_LPDDR2IO1_GR10_SR_MASK (0x3 << 22)
#define OMAP4_LPDDR2IO1_GR10_I_SHIFT 19
#define OMAP4_LPDDR2IO1_GR10_I_MASK (0x7 << 19)
#define OMAP4_LPDDR2IO1_GR10_WD_SHIFT 17
#define OMAP4_LPDDR2IO1_GR10_WD_MASK (0x3 << 17)
#define OMAP4_LPDDR2IO1_GR9_SR_SHIFT 14
#define OMAP4_LPDDR2IO1_GR9_SR_MASK (0x3 << 14)
#define OMAP4_LPDDR2IO1_GR9_I_SHIFT 11
#define OMAP4_LPDDR2IO1_GR9_I_MASK (0x7 << 11)
#define OMAP4_LPDDR2IO1_GR9_WD_SHIFT 9
#define OMAP4_LPDDR2IO1_GR9_WD_MASK (0x3 << 9)
/* CONTROL_LPDDR2IO1_3 */
#define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT 31
#define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK (1 << 31)
#define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT 30
#define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK (1 << 30)
#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT 29
#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK (1 << 29)
#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT 28
#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK (1 << 28)
#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT 27
#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK (1 << 27)
#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT 26
#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK (1 << 26)
#define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT 25
#define OMAP4_LPDDR21_VREF_CA_TAP0_MASK (1 << 25)
#define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT 24
#define OMAP4_LPDDR21_VREF_CA_TAP1_MASK (1 << 24)
#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT 23
#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK (1 << 23)
#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT 22
#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK (1 << 22)
#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT 21
#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK (1 << 21)
#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT 20
#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK (1 << 20)
#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT 19
#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK (1 << 19)
#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT 18
#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK (1 << 18)
#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT 17
#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK (1 << 17)
#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT 16
#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK (1 << 16)
#define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT 15
#define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK (1 << 15)
#define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT 14
#define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK (1 << 14)
#define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT 13
#define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK (1 << 13)
#define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT 12
#define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK (1 << 12)
/* CONTROL_LPDDR2IO2_0 */
#define OMAP4_LPDDR2IO2_GR4_SR_SHIFT 30
#define OMAP4_LPDDR2IO2_GR4_SR_MASK (0x3 << 30)
#define OMAP4_LPDDR2IO2_GR4_I_SHIFT 27
#define OMAP4_LPDDR2IO2_GR4_I_MASK (0x7 << 27)
#define OMAP4_LPDDR2IO2_GR4_WD_SHIFT 25
#define OMAP4_LPDDR2IO2_GR4_WD_MASK (0x3 << 25)
#define OMAP4_LPDDR2IO2_GR3_SR_SHIFT 22
#define OMAP4_LPDDR2IO2_GR3_SR_MASK (0x3 << 22)
#define OMAP4_LPDDR2IO2_GR3_I_SHIFT 19
#define OMAP4_LPDDR2IO2_GR3_I_MASK (0x7 << 19)
#define OMAP4_LPDDR2IO2_GR3_WD_SHIFT 17
#define OMAP4_LPDDR2IO2_GR3_WD_MASK (0x3 << 17)
#define OMAP4_LPDDR2IO2_GR2_SR_SHIFT 14
#define OMAP4_LPDDR2IO2_GR2_SR_MASK (0x3 << 14)
#define OMAP4_LPDDR2IO2_GR2_I_SHIFT 11
#define OMAP4_LPDDR2IO2_GR2_I_MASK (0x7 << 11)
#define OMAP4_LPDDR2IO2_GR2_WD_SHIFT 9
#define OMAP4_LPDDR2IO2_GR2_WD_MASK (0x3 << 9)
#define OMAP4_LPDDR2IO2_GR1_SR_SHIFT 6
#define OMAP4_LPDDR2IO2_GR1_SR_MASK (0x3 << 6)
#define OMAP4_LPDDR2IO2_GR1_I_SHIFT 3
#define OMAP4_LPDDR2IO2_GR1_I_MASK (0x7 << 3)
#define OMAP4_LPDDR2IO2_GR1_WD_SHIFT 1
#define OMAP4_LPDDR2IO2_GR1_WD_MASK (0x3 << 1)
/* CONTROL_LPDDR2IO2_1 */
#define OMAP4_LPDDR2IO2_GR8_SR_SHIFT 30
#define OMAP4_LPDDR2IO2_GR8_SR_MASK (0x3 << 30)
#define OMAP4_LPDDR2IO2_GR8_I_SHIFT 27
#define OMAP4_LPDDR2IO2_GR8_I_MASK (0x7 << 27)
#define OMAP4_LPDDR2IO2_GR8_WD_SHIFT 25
#define OMAP4_LPDDR2IO2_GR8_WD_MASK (0x3 << 25)
#define OMAP4_LPDDR2IO2_GR7_SR_SHIFT 22
#define OMAP4_LPDDR2IO2_GR7_SR_MASK (0x3 << 22)
#define OMAP4_LPDDR2IO2_GR7_I_SHIFT 19
#define OMAP4_LPDDR2IO2_GR7_I_MASK (0x7 << 19)
#define OMAP4_LPDDR2IO2_GR7_WD_SHIFT 17
#define OMAP4_LPDDR2IO2_GR7_WD_MASK (0x3 << 17)
#define OMAP4_LPDDR2IO2_GR6_SR_SHIFT 14
#define OMAP4_LPDDR2IO2_GR6_SR_MASK (0x3 << 14)
#define OMAP4_LPDDR2IO2_GR6_I_SHIFT 11
#define OMAP4_LPDDR2IO2_GR6_I_MASK (0x7 << 11)
#define OMAP4_LPDDR2IO2_GR6_WD_SHIFT 9
#define OMAP4_LPDDR2IO2_GR6_WD_MASK (0x3 << 9)
#define OMAP4_LPDDR2IO2_GR5_SR_SHIFT 6
#define OMAP4_LPDDR2IO2_GR5_SR_MASK (0x3 << 6)
#define OMAP4_LPDDR2IO2_GR5_I_SHIFT 3
#define OMAP4_LPDDR2IO2_GR5_I_MASK (0x7 << 3)
#define OMAP4_LPDDR2IO2_GR5_WD_SHIFT 1
#define OMAP4_LPDDR2IO2_GR5_WD_MASK (0x3 << 1)
/* CONTROL_LPDDR2IO2_2 */
#define OMAP4_LPDDR2IO2_GR11_SR_SHIFT 30
#define OMAP4_LPDDR2IO2_GR11_SR_MASK (0x3 << 30)
#define OMAP4_LPDDR2IO2_GR11_I_SHIFT 27
#define OMAP4_LPDDR2IO2_GR11_I_MASK (0x7 << 27)
#define OMAP4_LPDDR2IO2_GR11_WD_SHIFT 25
#define OMAP4_LPDDR2IO2_GR11_WD_MASK (0x3 << 25)
#define OMAP4_LPDDR2IO2_GR10_SR_SHIFT 22
#define OMAP4_LPDDR2IO2_GR10_SR_MASK (0x3 << 22)
#define OMAP4_LPDDR2IO2_GR10_I_SHIFT 19
#define OMAP4_LPDDR2IO2_GR10_I_MASK (0x7 << 19)
#define OMAP4_LPDDR2IO2_GR10_WD_SHIFT 17
#define OMAP4_LPDDR2IO2_GR10_WD_MASK (0x3 << 17)
#define OMAP4_LPDDR2IO2_GR9_SR_SHIFT 14
#define OMAP4_LPDDR2IO2_GR9_SR_MASK (0x3 << 14)
#define OMAP4_LPDDR2IO2_GR9_I_SHIFT 11
#define OMAP4_LPDDR2IO2_GR9_I_MASK (0x7 << 11)
#define OMAP4_LPDDR2IO2_GR9_WD_SHIFT 9
#define OMAP4_LPDDR2IO2_GR9_WD_MASK (0x3 << 9)
/* CONTROL_LPDDR2IO2_3 */
#define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT 31
#define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK (1 << 31)
#define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT 30
#define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK (1 << 30)
#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT 29
#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK (1 << 29)
#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT 28
#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK (1 << 28)
#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT 27
#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK (1 << 27)
#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT 26
#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK (1 << 26)
#define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT 25
#define OMAP4_LPDDR22_VREF_CA_TAP0_MASK (1 << 25)
#define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT 24
#define OMAP4_LPDDR22_VREF_CA_TAP1_MASK (1 << 24)
#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT 23
#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK (1 << 23)
#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT 22
#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK (1 << 22)
#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT 21
#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK (1 << 21)
#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT 20
#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK (1 << 20)
#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT 19
#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK (1 << 19)
#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT 18
#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK (1 << 18)
#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT 17
#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK (1 << 17)
#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT 16
#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK (1 << 16)
#define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT 15
#define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK (1 << 15)
#define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT 14
#define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK (1 << 14)
#define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT 13
#define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK (1 << 13)
#define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT 12
#define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK (1 << 12)
/* CONTROL_BUS_HOLD */
#define OMAP4_ABE_DMIC_DIN3_EN_SHIFT 31
#define OMAP4_ABE_DMIC_DIN3_EN_MASK (1 << 31)
#define OMAP4_MCSPI1_CS3_EN_SHIFT 30
#define OMAP4_MCSPI1_CS3_EN_MASK (1 << 30)
/* CONTROL_C2C */
#define OMAP4_MIRROR_MODE_EN_SHIFT 31
#define OMAP4_MIRROR_MODE_EN_MASK (1 << 31)
#define OMAP4_C2C_SPARE_SHIFT 24
#define OMAP4_C2C_SPARE_MASK (0x7f << 24)
/* CORE_CONTROL_SPARE_RW */
#define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT 0
#define OMAP4_CORE_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
/* CORE_CONTROL_SPARE_R */
#define OMAP4_CORE_CONTROL_SPARE_R_SHIFT 0
#define OMAP4_CORE_CONTROL_SPARE_R_MASK (0xffffffff << 0)
/* CORE_CONTROL_SPARE_R_C0 */
#define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT 31
#define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK (1 << 31)
#define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT 30
#define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK (1 << 30)
#define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT 29
#define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK (1 << 29)
#define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT 28
#define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK (1 << 28)
#define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT 27
#define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK (1 << 27)
#define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT 26
#define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK (1 << 26)
#define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT 25
#define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK (1 << 25)
#define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT 24
#define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK (1 << 24)
/* CONTROL_EFUSE_1 */
#define OMAP4_AVDAC_TRIM_BYTE3_SHIFT 24
#define OMAP4_AVDAC_TRIM_BYTE3_MASK (0x7f << 24)
#define OMAP4_AVDAC_TRIM_BYTE2_SHIFT 16
#define OMAP4_AVDAC_TRIM_BYTE2_MASK (0xff << 16)
#define OMAP4_AVDAC_TRIM_BYTE1_SHIFT 8
#define OMAP4_AVDAC_TRIM_BYTE1_MASK (0xff << 8)
#define OMAP4_AVDAC_TRIM_BYTE0_SHIFT 0
#define OMAP4_AVDAC_TRIM_BYTE0_MASK (0xff << 0)
/* CONTROL_EFUSE_2 */
#define OMAP4_EFUSE_SMART2TEST_P0_SHIFT 31
#define OMAP4_EFUSE_SMART2TEST_P0_MASK (1 << 31)
#define OMAP4_EFUSE_SMART2TEST_P1_SHIFT 30
#define OMAP4_EFUSE_SMART2TEST_P1_MASK (1 << 30)
#define OMAP4_EFUSE_SMART2TEST_P2_SHIFT 29
#define OMAP4_EFUSE_SMART2TEST_P2_MASK (1 << 29)
#define OMAP4_EFUSE_SMART2TEST_P3_SHIFT 28
#define OMAP4_EFUSE_SMART2TEST_P3_MASK (1 << 28)
#define OMAP4_EFUSE_SMART2TEST_N0_SHIFT 27
#define OMAP4_EFUSE_SMART2TEST_N0_MASK (1 << 27)
#define OMAP4_EFUSE_SMART2TEST_N1_SHIFT 26
#define OMAP4_EFUSE_SMART2TEST_N1_MASK (1 << 26)
#define OMAP4_EFUSE_SMART2TEST_N2_SHIFT 25
#define OMAP4_EFUSE_SMART2TEST_N2_MASK (1 << 25)
#define OMAP4_EFUSE_SMART2TEST_N3_SHIFT 24
#define OMAP4_EFUSE_SMART2TEST_N3_MASK (1 << 24)
#define OMAP4_LPDDR2_PTV_N1_SHIFT 23
#define OMAP4_LPDDR2_PTV_N1_MASK (1 << 23)
#define OMAP4_LPDDR2_PTV_N2_SHIFT 22
#define OMAP4_LPDDR2_PTV_N2_MASK (1 << 22)
#define OMAP4_LPDDR2_PTV_N3_SHIFT 21
#define OMAP4_LPDDR2_PTV_N3_MASK (1 << 21)
#define OMAP4_LPDDR2_PTV_N4_SHIFT 20
#define OMAP4_LPDDR2_PTV_N4_MASK (1 << 20)
#define OMAP4_LPDDR2_PTV_N5_SHIFT 19
#define OMAP4_LPDDR2_PTV_N5_MASK (1 << 19)
#define OMAP4_LPDDR2_PTV_P1_SHIFT 18
#define OMAP4_LPDDR2_PTV_P1_MASK (1 << 18)
#define OMAP4_LPDDR2_PTV_P2_SHIFT 17
#define OMAP4_LPDDR2_PTV_P2_MASK (1 << 17)
#define OMAP4_LPDDR2_PTV_P3_SHIFT 16
#define OMAP4_LPDDR2_PTV_P3_MASK (1 << 16)
#define OMAP4_LPDDR2_PTV_P4_SHIFT 15
#define OMAP4_LPDDR2_PTV_P4_MASK (1 << 15)
#define OMAP4_LPDDR2_PTV_P5_SHIFT 14
#define OMAP4_LPDDR2_PTV_P5_MASK (1 << 14)
/* CONTROL_EFUSE_3 */
#define OMAP4_STD_FUSE_SPARE_1_SHIFT 24
#define OMAP4_STD_FUSE_SPARE_1_MASK (0xff << 24)
#define OMAP4_STD_FUSE_SPARE_2_SHIFT 16
#define OMAP4_STD_FUSE_SPARE_2_MASK (0xff << 16)
#define OMAP4_STD_FUSE_SPARE_3_SHIFT 8
#define OMAP4_STD_FUSE_SPARE_3_MASK (0xff << 8)
#define OMAP4_STD_FUSE_SPARE_4_SHIFT 0
#define OMAP4_STD_FUSE_SPARE_4_MASK (0xff << 0)
/* CONTROL_EFUSE_4 */
#define OMAP4_STD_FUSE_SPARE_5_SHIFT 24
#define OMAP4_STD_FUSE_SPARE_5_MASK (0xff << 24)
#define OMAP4_STD_FUSE_SPARE_6_SHIFT 16
#define OMAP4_STD_FUSE_SPARE_6_MASK (0xff << 16)
#define OMAP4_STD_FUSE_SPARE_7_SHIFT 8
#define OMAP4_STD_FUSE_SPARE_7_MASK (0xff << 8)
#define OMAP4_STD_FUSE_SPARE_8_SHIFT 0
#define OMAP4_STD_FUSE_SPARE_8_MASK (0xff << 0)
#endif
arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h 0 → 100644
View file @ 91f6c90c
/*
* OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields
*
* Copyright (C) 2009-2010 Texas Instruments, Inc.
*
* Benoit Cousson (b-cousson@ti.com)
* Santosh Shilimkar (santosh.shilimkar@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
/* Base address */
#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000
/* Registers offset */
#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000
#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004
#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010
#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608
#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c
#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614
#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618
#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c
/* Registers shifts and masks */
/* IP_REVISION */
#define OMAP4_IP_REV_SCHEME_SHIFT 30
#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
#define OMAP4_IP_REV_FUNC_SHIFT 16
#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
#define OMAP4_IP_REV_RTL_SHIFT 11
#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
#define OMAP4_IP_REV_MAJOR_SHIFT 8
#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
#define OMAP4_IP_REV_CUSTOM_SHIFT 6
#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
#define OMAP4_IP_REV_MINOR_SHIFT 0
#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
/* IP_HWINFO */
#define OMAP4_IP_HWINFO_SHIFT 0
#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
/* IP_SYSCONFIG */
#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
/* PADCONF_WAKEUPEVENT_0 */
#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24
#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23
#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22
#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21
#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20
#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19
#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18
#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17
#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16
#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15
#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14
#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13
#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12
#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11
#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9
#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8
#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7
#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6
#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5
#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4
#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3
#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2
#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0
#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
/* CONTROL_SMART1NOPMIO_PADCONF_0 */
#define OMAP4_FREF_DR0_SC_SHIFT 30
#define OMAP4_FREF_DR0_SC_MASK (0x3 << 30)
#define OMAP4_FREF_DR1_SC_SHIFT 28
#define OMAP4_FREF_DR1_SC_MASK (0x3 << 28)
#define OMAP4_FREF_DR4_SC_SHIFT 26
#define OMAP4_FREF_DR4_SC_MASK (0x3 << 26)
#define OMAP4_FREF_DR5_SC_SHIFT 24
#define OMAP4_FREF_DR5_SC_MASK (0x3 << 24)
#define OMAP4_FREF_DR6_SC_SHIFT 22
#define OMAP4_FREF_DR6_SC_MASK (0x3 << 22)
#define OMAP4_FREF_DR7_SC_SHIFT 20
#define OMAP4_FREF_DR7_SC_MASK (0x3 << 20)
#define OMAP4_GPIO_DR7_SC_SHIFT 18
#define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18)
#define OMAP4_DPM_DR0_SC_SHIFT 14
#define OMAP4_DPM_DR0_SC_MASK (0x3 << 14)
#define OMAP4_SIM_DR0_SC_SHIFT 12
#define OMAP4_SIM_DR0_SC_MASK (0x3 << 12)
/* CONTROL_SMART1NOPMIO_PADCONF_1 */
#define OMAP4_FREF_DR0_LB_SHIFT 30
#define OMAP4_FREF_DR0_LB_MASK (0x3 << 30)
#define OMAP4_FREF_DR1_LB_SHIFT 28
#define OMAP4_FREF_DR1_LB_MASK (0x3 << 28)
#define OMAP4_FREF_DR4_LB_SHIFT 26
#define OMAP4_FREF_DR4_LB_MASK (0x3 << 26)
#define OMAP4_FREF_DR5_LB_SHIFT 24
#define OMAP4_FREF_DR5_LB_MASK (0x3 << 24)
#define OMAP4_FREF_DR6_LB_SHIFT 22
#define OMAP4_FREF_DR6_LB_MASK (0x3 << 22)
#define OMAP4_FREF_DR7_LB_SHIFT 20
#define OMAP4_FREF_DR7_LB_MASK (0x3 << 20)
#define OMAP4_GPIO_DR7_LB_SHIFT 18
#define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18)
#define OMAP4_DPM_DR0_LB_SHIFT 14
#define OMAP4_DPM_DR0_LB_MASK (0x3 << 14)
#define OMAP4_SIM_DR0_LB_SHIFT 12
#define OMAP4_SIM_DR0_LB_MASK (0x3 << 12)
/* CONTROL_PADCONF_MODE */
#define OMAP4_VDDS_DV_FREF_SHIFT 31
#define OMAP4_VDDS_DV_FREF_MASK (1 << 31)
#define OMAP4_VDDS_DV_BANK2_SHIFT 30
#define OMAP4_VDDS_DV_BANK2_MASK (1 << 30)
/* CONTROL_XTAL_OSCILLATOR */
#define OMAP4_OSCILLATOR_BOOST_SHIFT 31
#define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31)
#define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30
#define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30)
/* CONTROL_USIMIO */
#define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31
#define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31)
#define OMAP4_PAD_USIM_RST_LOW_SHIFT 29
#define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29)
#define OMAP4_USIM_PWRDNZ_SHIFT 28
#define OMAP4_USIM_PWRDNZ_MASK (1 << 28)
/* CONTROL_I2C_2 */
#define OMAP4_SR_SDA_GLFENB_SHIFT 31
#define OMAP4_SR_SDA_GLFENB_MASK (1 << 31)
#define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29
#define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29)
#define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28
#define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28)
#define OMAP4_SR_SCL_GLFENB_SHIFT 27
#define OMAP4_SR_SCL_GLFENB_MASK (1 << 27)
#define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25
#define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25)
#define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24
#define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24)
/* CONTROL_JTAG */
#define OMAP4_JTAG_NTRST_EN_SHIFT 31
#define OMAP4_JTAG_NTRST_EN_MASK (1 << 31)
#define OMAP4_JTAG_TCK_EN_SHIFT 30
#define OMAP4_JTAG_TCK_EN_MASK (1 << 30)
#define OMAP4_JTAG_RTCK_EN_SHIFT 29
#define OMAP4_JTAG_RTCK_EN_MASK (1 << 29)
#define OMAP4_JTAG_TDI_EN_SHIFT 28
#define OMAP4_JTAG_TDI_EN_MASK (1 << 28)
#define OMAP4_JTAG_TDO_EN_SHIFT 27
#define OMAP4_JTAG_TDO_EN_MASK (1 << 27)
/* CONTROL_SYS */
#define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31
#define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31)
/* WKUP_CONTROL_SPARE_RW */
#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0
#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
/* WKUP_CONTROL_SPARE_R */
#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0
#define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0)
/* WKUP_CONTROL_SPARE_R_C0 */
#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31
#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31)
#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30
#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30)
#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29
#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29)
#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28
#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28)
#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27
#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27)
#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26
#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26)
#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25
#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25)
#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24
#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24)
#endif
arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h 0 → 100644
View file @ 91f6c90c
/*
* OMAP44xx CTRL_MODULE_WKUP registers and bitfields
*
* Copyright (C) 2009-2010 Texas Instruments, Inc.
*
* Benoit Cousson (b-cousson@ti.com)
* Santosh Shilimkar (santosh.shilimkar@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
/* Base address */
#define OMAP4_CTRL_MODULE_WKUP 0x4a30c000
/* Registers offset */
#define OMAP4_CTRL_MODULE_WKUP_IP_REVISION 0x0000
#define OMAP4_CTRL_MODULE_WKUP_IP_HWINFO 0x0004
#define OMAP4_CTRL_MODULE_WKUP_IP_SYSCONFIG 0x0010
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_0 0x0460
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_1 0x0464
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_2 0x0468
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_3 0x046c
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_4 0x0470
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_5 0x0474
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_6 0x0478
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_7 0x047c
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_8 0x0480
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_9 0x0484
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_10 0x0488
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_11 0x048c
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_12 0x0490
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_13 0x0494
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_14 0x0498
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_15 0x049c
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_16 0x04a0
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_17 0x04a4
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_18 0x04a8
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_19 0x04ac
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_20 0x04b0
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_21 0x04b4
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_22 0x04b8
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_23 0x04bc
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_24 0x04c0
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_25 0x04c4
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_26 0x04c8
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_27 0x04cc
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_28 0x04d0
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_29 0x04d4
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_30 0x04d8
#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_31 0x04dc
/* Registers shifts and masks */
/* IP_REVISION */
#define OMAP4_IP_REV_SCHEME_SHIFT 30
#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
#define OMAP4_IP_REV_FUNC_SHIFT 16
#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
#define OMAP4_IP_REV_RTL_SHIFT 11
#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
#define OMAP4_IP_REV_MAJOR_SHIFT 8
#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
#define OMAP4_IP_REV_CUSTOM_SHIFT 6
#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
#define OMAP4_IP_REV_MINOR_SHIFT 0
#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
/* IP_HWINFO */
#define OMAP4_IP_HWINFO_SHIFT 0
#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
/* IP_SYSCONFIG */
#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
/* CONF_DEBUG_SEL_TST_0 */
#define OMAP4_WKUP_MODE_SHIFT 0
#define OMAP4_WKUP_MODE_MASK (1 << 0)
#endif
arch/arm/mach-omap2/powerdomains44xx.h
View file @ 91f6c90c
......@@ -98,7 +98,7 @@ static struct powerdomain dss_44xx_pwrdm = {
.prcm_offs = OMAP4430_PRM_DSS_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.pwrsts_logic_ret = PWRSTS_OFF,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRDM_POWER_OFF, /* dss_mem */
......
arch/arm/mach-omap2/prm-regbits-44xx.h
View file @ 91f6c90c
This source diff could not be displayed because it is too large. You can view the blob instead.
arch/arm/mach-omap2/prm44xx.h
View file @ 91f6c90c
......@@ -44,14 +44,12 @@
#define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030)
#define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038
#define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038)
#define OMAP4_PRM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
#define OMAP4430_PRM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040)
#define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
#define OMAP4430_CM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040)
/* PRM.CKGEN_PRM register offsets */
#define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000
#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000)
#define OMAP4_CM_DPLL_SYS_REF_CLKSEL_OFFSET 0x0004
#define OMAP4430_CM_DPLL_SYS_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004)
#define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008
#define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008)
#define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c
......@@ -686,8 +684,8 @@
#define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8)
#define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc
#define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc)
#define OMAP4_PRM_LDO_BANDGAP_CTRL_OFFSET 0x00e0
#define OMAP4430_PRM_LDO_BANDGAP_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0)
#define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET 0x00e0
#define OMAP4430_PRM_LDO_BANDGAP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0)
#define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4
#define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4)
#define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8
......@@ -698,6 +696,8 @@
#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0)
#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4
#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4)
#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8
#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f8)
/*
* PRCM_MPU
......@@ -715,6 +715,8 @@
/* PRCM_MPU.DEVICE_PRM register offsets */
#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000)
#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004)
/* PRCM_MPU.CPU0 register offsets */
#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
......
arch/arm/mach-omap2/sram34xx.S
View file @ 91f6c90c
......@@ -129,8 +129,11 @@ ENTRY(omap3_sram_configure_core_dpll)
ldr r4, [sp, #80]
str r4, omap_sdrc_mr_1_val
skip_cs1_params:
mrc p15, 0, r8, c1, c0, 0 @ read ctrl register
bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction
mcr p15, 0, r10, c1, c0, 0 @ write ctrl register
dsb @ flush buffered writes to interconnect
isb @ prevent speculative exec past here
cmp r3, #1 @ if increasing SDRC clk rate,
bleq configure_sdrc @ program the SDRC regs early (for RFR)
cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state
......@@ -148,6 +151,7 @@ skip_cs1_params:
beq return_to_sdram @ return to SDRAM code, otherwise,
bl configure_sdrc @ reprogram SDRC regs now
return_to_sdram:
mcr p15, 0, r8, c1, c0, 0 @ restore ctrl register
isb @ prevent speculative exec past here
mov r0, #0 @ return value
ldmfd sp!, {r1-r12, pc} @ restore regs and return
......
arch/arm/plat-omap/common.c
View file @ 91f6c90c
......@@ -336,7 +336,8 @@ void __init omap3_map_io(void)
static struct omap_globals omap4_globals = {
.class = OMAP443X_CLASS,
.tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
.ctrl = OMAP443X_CTRL_BASE,
.ctrl = OMAP443X_SCM_BASE,
.ctrl_pad = OMAP443X_CTRL_BASE,
.prm = OMAP4430_PRM_BASE,
.cm = OMAP4430_CM_BASE,
.cm2 = OMAP4430_CM2_BASE,
......
arch/arm/plat-omap/include/plat/common.h
View file @ 91f6c90c
......@@ -47,6 +47,7 @@ struct omap_globals {
unsigned long sdrc; /* SDRAM Controller */
unsigned long sms; /* SDRAM Memory Scheduler */
unsigned long ctrl; /* System Control Module */
unsigned long ctrl_pad; /* PAD Control Module */
unsigned long prm; /* Power and Reset Management */
unsigned long cm; /* Clock Management */
unsigned long cm2;
......
arch/arm/plat-omap/include/plat/control.h
View file @ 91f6c90c
......@@ -17,6 +17,10 @@
#define __ASM_ARCH_CONTROL_H
#include <mach/io.h>
#include <mach/ctrl_module_core_44xx.h>
#include <mach/ctrl_module_wkup_44xx.h>
#include <mach/ctrl_module_pad_core_44xx.h>
#include <mach/ctrl_module_pad_wkup_44xx.h>
#ifndef __ASSEMBLY__
#define OMAP242X_CTRL_REGADDR(reg) \
......@@ -204,12 +208,6 @@
#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
/* 44xx control status register offset */
#define OMAP44XX_CONTROL_STATUS 0x2c4
/* 44xx-only CONTROL_GENERAL register offsets */
#define OMAP44XX_CONTROL_MMC1 0x628
#define OMAP44XX_CONTROL_PBIAS_LITE 0x600
/*
* REVISIT: This list of registers is not comprehensive - there are more
* that should be added.
......@@ -255,23 +253,6 @@
#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
#define OMAP2_PBIASLITEVMODE0 (1 << 0)
/* CONTROL_PBIAS_LITE bits for OMAP4 */
#define OMAP4_MMC1_PWRDNZ (1 << 26)
#define OMAP4_MMC1_PBIASLITE_HIZ_MODE (1 << 25)
#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT (1 << 24)
#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR (1 << 23)
#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1 << 22)
#define OMAP4_MMC1_PBIASLITE_VMODE (1 << 21)
#define OMAP4_USBC1_ICUSB_PWRDNZ (1 << 20)
#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 (1 << 31)
#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1 (1 << 30)
#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 (1 << 29)
#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3 (1 << 28)
#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL (1 << 27)
#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL (1 << 26)
#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL (1 << 25)
/* CONTROL_PROG_IO1 bits */
#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
......@@ -354,9 +335,11 @@ extern void __iomem *omap_ctrl_base_get(void);
extern u8 omap_ctrl_readb(u16 offset);
extern u16 omap_ctrl_readw(u16 offset);
extern u32 omap_ctrl_readl(u16 offset);
extern u32 omap4_ctrl_pad_readl(u16 offset);
extern void omap_ctrl_writeb(u8 val, u16 offset);
extern void omap_ctrl_writew(u16 val, u16 offset);
extern void omap_ctrl_writel(u32 val, u16 offset);
extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
extern void omap3_save_scratchpad_contents(void);
extern void omap3_clear_scratchpad_contents(void);
......@@ -371,9 +354,11 @@ extern void omap3_control_restore_context(void);
#define omap_ctrl_readb(x) 0
#define omap_ctrl_readw(x) 0
#define omap_ctrl_readl(x) 0
#define omap4_ctrl_pad_readl(x) 0
#define omap_ctrl_writeb(x, y) WARN_ON(1)
#define omap_ctrl_writew(x, y) WARN_ON(1)
#define omap_ctrl_writel(x, y) WARN_ON(1)
#define omap4_ctrl_pad_writel(x, y) WARN_ON(1)
#endif
#endif /* __ASSEMBLY__ */
......
arch/arm/plat-omap/include/plat/powerdomain.h
View file @ 91f6c90c
......@@ -32,6 +32,7 @@
/* Powerdomain allowable state bitfields */
#define PWRSTS_ON (1 << PWRDM_POWER_ON)
#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
(1 << PWRDM_POWER_ON))
......
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