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Commit 9220d7be authored by Boris Brezillon's avatar Boris Brezillon
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Merge tag 'nand/for-5.1' of git://git.infradead.org/linux-mtd into mtd/next 

NAND core changes:
- Fourth batch of fixes/cleanup to the raw NAND core impacting various
  controller drivers (Sunxi, Marvell, MTK, TMIO, OMAP2).
- Checking the return code of nand_reset() and nand_readid_op().
- Removing ->legacy.erase and single_erase().
- Simplifying the locking.
- Several implicit fall through annotations.

Raw NAND controllers drivers changes:
- Fixing various possible object reference leaks (MTK, JZ4780, Atmel).
- ST:
  * Adding support for STM32 FMC2 NAND flash controller.
- Meson:
  * Adding support for Amlogic NAND flash controller.
- Denali:
  * Several cleanup patches.
- Sunxi:
  * Several cleanup patches.
- FSMC:
  * Disabling NAND on remove().
  * Resetting NAND timings on resume().

SPI-NAND drivers changes:
- Toshiba:
  * Adding support for all Toshiba products.
- Macronix:
  * Fixing ECC status read.
- Gigadevice:
  * Adding support for GD5F1GQ4UExxG.
parents dfbd3995 53bcbb83
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Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt 0 → 100644
View file @ 9220d7be
Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs
This file documents the properties in addition to those available in
the MTD NAND bindings.
Required properties:
- compatible : contains one of:
- "amlogic,meson-gxl-nfc"
- "amlogic,meson-axg-nfc"
- clocks :
A list of phandle + clock-specifier pairs for the clocks listed
in clock-names.
- clock-names: Should contain the following:
"core" - NFC module gate clock
"device" - device clock from eMMC sub clock controller
"rx" - rx clock phase
"tx" - tx clock phase
- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC
controller port C
Optional children nodes:
Children nodes represent the available nand chips.
Other properties:
see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
Example demonstrate on AXG SoC:
sd_emmc_c_clkc: mmc@7000 {
compatible = "amlogic,meson-axg-mmc-clkc", "syscon";
reg = <0x0 0x7000 0x0 0x800>;
};
nand-controller@7800 {
compatible = "amlogic,meson-axg-nfc";
reg = <0x0 0x7800 0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_SD_EMMC_C>,
<&sd_emmc_c_clkc CLKID_MMC_DIV>,
<&sd_emmc_c_clkc CLKID_MMC_PHASE_RX>,
<&sd_emmc_c_clkc CLKID_MMC_PHASE_TX>;
clock-names = "core", "device", "rx", "tx";
amlogic,mmc-syscon = <&sd_emmc_c_clkc>;
pinctrl-names = "default";
pinctrl-0 = <&nand_pins>;
nand@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
nand-on-flash-bbt;
};
};
Documentation/devicetree/bindings/mtd/stm32-fmc2-nand.txt 0 → 100644
View file @ 9220d7be
STMicroelectronics Flexible Memory Controller 2 (FMC2)
NAND Interface
Required properties:
- compatible: Should be one of:
* st,stm32mp15-fmc2
- reg: NAND flash controller memory areas.
First region contains the register location.
Regions 2 to 4 respectively contain the data, command,
and address space for CS0.
Regions 5 to 7 contain the same areas for CS1.
- interrupts: The interrupt number
- pinctrl-0: Standard Pinctrl phandle (see: pinctrl/pinctrl-bindings.txt)
- clocks: The clock needed by the NAND flash controller
Optional properties:
- resets: Reference to a reset controller asserting the FMC controller
- dmas: DMA specifiers (see: dma/stm32-mdma.txt)
- dma-names: Must be "tx", "rx" and "ecc"
* NAND device bindings:
Required properties:
- reg: describes the CS lines assigned to the NAND device.
Optional properties:
- nand-on-flash-bbt: see nand.txt
- nand-ecc-strength: see nand.txt
- nand-ecc-step-size: see nand.txt
The following ECC strength and step size are currently supported:
- nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Hamming)
- nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4)
- nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8) (default)
Example:
fmc: nand-controller@58002000 {
compatible = "st,stm32mp15-fmc2";
reg = <0x58002000 0x1000>,
<0x80000000 0x1000>,
<0x88010000 0x1000>,
<0x88020000 0x1000>,
<0x81000000 0x1000>,
<0x89010000 0x1000>,
<0x89020000 0x1000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc FMC_K>;
resets = <&rcc FMC_R>;
pinctrl-names = "default";
pinctrl-0 = <&fmc_pins_a>;
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <1>;
};
};
MAINTAINERS
View file @ 9220d7be
......@@ -9849,6 +9849,13 @@ F: drivers/media/platform/meson/ao-cec.c
F: Documentation/devicetree/bindings/media/meson-ao-cec.txt
T: git git://linuxtv.org/media_tree.git
MESON NAND CONTROLLER DRIVER FOR AMLOGIC SOCS
M: Liang Yang <liang.yang@amlogic.com>
L: linux-mtd@lists.infradead.org
S: Maintained
F: drivers/mtd/nand/raw/meson_*
F: Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
MICROBLAZE ARCHITECTURE
M: Michal Simek <monstr@monstr.eu>
W: http://www.monstr.eu/fdt/
......
drivers/mtd/nand/raw/Kconfig
View file @ 9220d7be
......@@ -541,4 +541,21 @@ config MTD_NAND_TEGRA
is supported. Extra OOB bytes when using HW ECC are currently
not supported.
config MTD_NAND_STM32_FMC2
tristate "Support for NAND controller on STM32MP SoCs"
depends on MACH_STM32MP157 || COMPILE_TEST
help
Enables support for NAND Flash chips on SoCs containing the FMC2
NAND controller. This controller is found on STM32MP SoCs.
The controller supports a maximum 8k page size and supports
a maximum 8-bit correction error per sector of 512 bytes.
config MTD_NAND_MESON
tristate "Support for NAND controller on Amlogic's Meson SoCs"
depends on ARCH_MESON || COMPILE_TEST
select MFD_SYSCON
help
Enables support for NAND controller on Amlogic's Meson SoCs.
This controller is found on Meson SoCs.
endif # MTD_NAND
drivers/mtd/nand/raw/Makefile
View file @ 9220d7be
......@@ -56,6 +56,8 @@ obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o
obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o
obj-$(CONFIG_MTD_NAND_STM32_FMC2) += stm32_fmc2_nand.o
obj-$(CONFIG_MTD_NAND_MESON) += meson_nand.o
nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o
nand-objs += nand_onfi.o
......
drivers/mtd/nand/raw/atmel/pmecc.c
View file @ 9220d7be
......@@ -876,23 +876,32 @@ static struct atmel_pmecc *atmel_pmecc_get_by_node(struct device *userdev,
{
struct platform_device *pdev;
struct atmel_pmecc *pmecc, **ptr;
int ret;
pdev = of_find_device_by_node(np);
if (!pdev || !platform_get_drvdata(pdev))
if (!pdev)
return ERR_PTR(-EPROBE_DEFER);
pmecc = platform_get_drvdata(pdev);
if (!pmecc) {
ret = -EPROBE_DEFER;
goto err_put_device;
}
ptr = devres_alloc(devm_atmel_pmecc_put, sizeof(*ptr), GFP_KERNEL);
if (!ptr)
return ERR_PTR(-ENOMEM);
get_device(&pdev->dev);
pmecc = platform_get_drvdata(pdev);
if (!ptr) {
ret = -ENOMEM;
goto err_put_device;
}
*ptr = pmecc;
devres_add(userdev, ptr);
return pmecc;
err_put_device:
put_device(&pdev->dev);
return ERR_PTR(ret);
}
static const int atmel_pmecc_strengths[] = { 2, 4, 8, 12, 24, 32 };
......
drivers/mtd/nand/raw/denali.c
View file @ 9220d7be
......@@ -37,9 +37,6 @@
#define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */
#define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */
/* MAP10 commands */
#define DENALI_ERASE 0x01
#define DENALI_BANK(denali) ((denali)->active_bank << 24)
#define DENALI_INVALID_BANK -1
......@@ -476,7 +473,7 @@ static void denali_setup_dma32(struct denali_nand_info *denali,
}
static int denali_pio_read(struct denali_nand_info *denali, void *buf,
size_t size, int page, int raw)
size_t size, int page)
{
u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
uint32_t *buf32 = (uint32_t *)buf;
......@@ -504,7 +501,7 @@ static int denali_pio_read(struct denali_nand_info *denali, void *buf,
}
static int denali_pio_write(struct denali_nand_info *denali,
const void *buf, size_t size, int page, int raw)
const void *buf, size_t size, int page)
{
u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
const uint32_t *buf32 = (uint32_t *)buf;
......@@ -525,16 +522,16 @@ static int denali_pio_write(struct denali_nand_info *denali,
}
static int denali_pio_xfer(struct denali_nand_info *denali, void *buf,
size_t size, int page, int raw, int write)
size_t size, int page, int write)
{
if (write)
return denali_pio_write(denali, buf, size, page, raw);
return denali_pio_write(denali, buf, size, page);
else
return denali_pio_read(denali, buf, size, page, raw);
return denali_pio_read(denali, buf, size, page);
}
static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
size_t size, int page, int raw, int write)
size_t size, int page, int write)
{
dma_addr_t dma_addr;
uint32_t irq_mask, irq_status, ecc_err_mask;
......@@ -544,7 +541,7 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
dma_addr = dma_map_single(denali->dev, buf, size, dir);
if (dma_mapping_error(denali->dev, dma_addr)) {
dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n");
return denali_pio_xfer(denali, buf, size, page, raw, write);
return denali_pio_xfer(denali, buf, size, page, write);
}
if (write) {
......@@ -598,9 +595,9 @@ static int denali_data_xfer(struct denali_nand_info *denali, void *buf,
denali->reg + TRANSFER_SPARE_REG);
if (denali->dma_avail)
return denali_dma_xfer(denali, buf, size, page, raw, write);
return denali_dma_xfer(denali, buf, size, page, write);
else
return denali_pio_xfer(denali, buf, size, page, raw, write);
return denali_pio_xfer(denali, buf, size, page, write);
}
static void denali_oob_xfer(struct mtd_info *mtd, struct nand_chip *chip,
......@@ -754,9 +751,6 @@ static int denali_read_oob(struct nand_chip *chip, int page)
static int denali_write_oob(struct nand_chip *chip, int page)
{
struct mtd_info *mtd = nand_to_mtd(chip);
struct denali_nand_info *denali = mtd_to_denali(mtd);
denali_reset_irq(denali);
denali_oob_xfer(mtd, chip, page, 1);
......@@ -903,23 +897,6 @@ static int denali_waitfunc(struct nand_chip *chip)
return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL;
}
static int denali_erase(struct nand_chip *chip, int page)
{
struct denali_nand_info *denali = mtd_to_denali(nand_to_mtd(chip));
uint32_t irq_status;
denali_reset_irq(denali);
denali->host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page,
DENALI_ERASE);
/* wait for erase to complete or failure to occur */
irq_status = denali_wait_for_irq(denali,
INTR__ERASE_COMP | INTR__ERASE_FAIL);
return irq_status & INTR__ERASE_COMP ? 0 : -EIO;
}
static int denali_setup_data_interface(struct nand_chip *chip, int chipnr,
const struct nand_data_interface *conf)
{
......@@ -1244,7 +1221,6 @@ static int denali_attach_chip(struct nand_chip *chip)
chip->ecc.write_page_raw = denali_write_page_raw;
chip->ecc.read_oob = denali_read_oob;
chip->ecc.write_oob = denali_write_oob;
chip->legacy.erase = denali_erase;
ret = denali_multidev_fixup(denali);
if (ret)
......
drivers/mtd/nand/raw/denali.h
View file @ 9220d7be
......@@ -304,7 +304,6 @@ struct denali_nand_info {
u32 irq_status; /* interrupts that have happened */
int irq;
void *buf; /* for syndrome layout conversion */
dma_addr_t dma_addr;
int dma_avail; /* can support DMA? */
int devs_per_cs; /* devices connected in parallel */
int oob_skip_bytes; /* number of bytes reserved for BBM */
......
drivers/mtd/nand/raw/denali_dt.c
View file @ 9220d7be
......@@ -109,25 +109,17 @@ static int denali_dt_probe(struct platform_device *pdev)
if (IS_ERR(denali->host))
return PTR_ERR(denali->host);
/*
* A single anonymous clock is supported for the backward compatibility.
* New platforms should support all the named clocks.
*/
dt->clk = devm_clk_get(dev, "nand");
if (IS_ERR(dt->clk))
dt->clk = devm_clk_get(dev, NULL);
if (IS_ERR(dt->clk)) {
dev_err(dev, "no clk available\n");
return PTR_ERR(dt->clk);
}
dt->clk_x = devm_clk_get(dev, "nand_x");
if (IS_ERR(dt->clk_x))
dt->clk_x = NULL;
return PTR_ERR(dt->clk_x);
dt->clk_ecc = devm_clk_get(dev, "ecc");
if (IS_ERR(dt->clk_ecc))
dt->clk_ecc = NULL;
return PTR_ERR(dt->clk_ecc);
ret = clk_prepare_enable(dt->clk);
if (ret)
......@@ -141,19 +133,8 @@ static int denali_dt_probe(struct platform_device *pdev)
if (ret)
goto out_disable_clk_x;
if (dt->clk_x) {
denali->clk_rate = clk_get_rate(dt->clk);
denali->clk_x_rate = clk_get_rate(dt->clk_x);
} else {
/*
* Hardcode the clock rates for the backward compatibility.
* This works for both SOCFPGA and UniPhier.
*/
dev_notice(dev,
"necessary clock is missing. default clock rates are used.\n");
denali->clk_rate = 50000000;
denali->clk_x_rate = 200000000;
}
ret = denali_init(denali);
if (ret)
......
drivers/mtd/nand/raw/fsmc_nand.c
View file @ 9220d7be
......@@ -986,6 +986,19 @@ static const struct nand_controller_ops fsmc_nand_controller_ops = {
.setup_data_interface = fsmc_setup_data_interface,
};
/**
* fsmc_nand_disable() - Disables the NAND bank
* @host: The instance to disable
*/
static void fsmc_nand_disable(struct fsmc_nand_data *host)
{
u32 val;
val = readl(host->regs_va + FSMC_PC);
val &= ~FSMC_ENABLE;
writel(val, host->regs_va + FSMC_PC);
}
/*
* fsmc_nand_probe - Probe function
* @pdev: platform device structure
......@@ -1141,6 +1154,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
if (host->mode == USE_DMA_ACCESS)
dma_release_channel(host->read_dma_chan);
disable_clk:
fsmc_nand_disable(host);
clk_disable_unprepare(host->clk);
return ret;
......@@ -1155,6 +1169,7 @@ static int fsmc_nand_remove(struct platform_device *pdev)
if (host) {
nand_release(&host->nand);
fsmc_nand_disable(host);
if (host->mode == USE_DMA_ACCESS) {
dma_release_channel(host->write_dma_chan);
......@@ -1185,6 +1200,7 @@ static int fsmc_nand_resume(struct device *dev)
clk_prepare_enable(host->clk);
if (host->dev_timings)
fsmc_nand_setup(host, host->dev_timings);
nand_reset(&host->nand, 0);
}
return 0;
......
drivers/mtd/nand/raw/jz4780_bch.c
View file @ 9220d7be
......@@ -281,12 +281,15 @@ static struct jz4780_bch *jz4780_bch_get(struct device_node *np)
struct jz4780_bch *bch;
pdev = of_find_device_by_node(np);
if (!pdev || !platform_get_drvdata(pdev))
if (!pdev)
return ERR_PTR(-EPROBE_DEFER);
get_device(&pdev->dev);
bch = platform_get_drvdata(pdev);
if (!bch) {
put_device(&pdev->dev);
return ERR_PTR(-EPROBE_DEFER);
}
clk_prepare_enable(bch->clk);
return bch;
......
drivers/mtd/nand/raw/marvell_nand.c
View file @ 9220d7be
......@@ -2550,9 +2550,8 @@ static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc,
}
/* Alloc the nand chip structure */
marvell_nand = devm_kzalloc(dev, sizeof(*marvell_nand) +
(nsels *
sizeof(struct marvell_nand_chip_sel)),
marvell_nand = devm_kzalloc(dev,
struct_size(marvell_nand, sels, nsels),
GFP_KERNEL);
if (!marvell_nand) {
dev_err(dev, "could not allocate chip structure\n");
......
drivers/mtd/nand/raw/meson_nand.c 0 → 100644
View file @ 9220d7be
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Amlogic Meson Nand Flash Controller Driver
*
* Copyright (c) 2018 Amlogic, inc.
* Author: Liang Yang <liang.yang@amlogic.com>
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/mtd.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/iopoll.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/sched/task_stack.h>
#define NFC_REG_CMD 0x00
#define NFC_CMD_IDLE (0xc << 14)
#define NFC_CMD_CLE (0x5 << 14)
#define NFC_CMD_ALE (0x6 << 14)
#define NFC_CMD_ADL ((0 << 16) | (3 << 20))
#define NFC_CMD_ADH ((1 << 16) | (3 << 20))
#define NFC_CMD_AIL ((2 << 16) | (3 << 20))
#define NFC_CMD_AIH ((3 << 16) | (3 << 20))
#define NFC_CMD_SEED ((8 << 16) | (3 << 20))
#define NFC_CMD_M2N ((0 << 17) | (2 << 20))
#define NFC_CMD_N2M ((1 << 17) | (2 << 20))
#define NFC_CMD_RB BIT(20)
#define NFC_CMD_SCRAMBLER_ENABLE BIT(19)
#define NFC_CMD_SCRAMBLER_DISABLE 0
#define NFC_CMD_SHORTMODE_DISABLE 0
#define NFC_CMD_RB_INT BIT(14)
#define NFC_CMD_GET_SIZE(x) (((x) >> 22) & GENMASK(4, 0))
#define NFC_REG_CFG 0x04
#define NFC_REG_DADR 0x08
#define NFC_REG_IADR 0x0c
#define NFC_REG_BUF 0x10
#define NFC_REG_INFO 0x14
#define NFC_REG_DC 0x18
#define NFC_REG_ADR 0x1c
#define NFC_REG_DL 0x20
#define NFC_REG_DH 0x24
#define NFC_REG_CADR 0x28
#define NFC_REG_SADR 0x2c
#define NFC_REG_PINS 0x30
#define NFC_REG_VER 0x38
#define NFC_RB_IRQ_EN BIT(21)
#define CMDRWGEN(cmd_dir, ran, bch, short_mode, page_size, pages) \
( \
(cmd_dir) | \
((ran) << 19) | \
((bch) << 14) | \
((short_mode) << 13) | \
(((page_size) & 0x7f) << 6) | \
((pages) & 0x3f) \
)
#define GENCMDDADDRL(adl, addr) ((adl) | ((addr) & 0xffff))
#define GENCMDDADDRH(adh, addr) ((adh) | (((addr) >> 16) & 0xffff))
#define GENCMDIADDRL(ail, addr) ((ail) | ((addr) & 0xffff))
#define GENCMDIADDRH(aih, addr) ((aih) | (((addr) >> 16) & 0xffff))
#define DMA_DIR(dir) ((dir) ? NFC_CMD_N2M : NFC_CMD_M2N)
#define ECC_CHECK_RETURN_FF (-1)
#define NAND_CE0 (0xe << 10)
#define NAND_CE1 (0xd << 10)
#define DMA_BUSY_TIMEOUT 0x100000
#define CMD_FIFO_EMPTY_TIMEOUT 1000
#define MAX_CE_NUM 2
/* eMMC clock register, misc control */
#define CLK_SELECT_NAND BIT(31)
#define NFC_CLK_CYCLE 6
/* nand flash controller delay 3 ns */
#define NFC_DEFAULT_DELAY 3000
#define ROW_ADDER(page, index) (((page) >> (8 * (index))) & 0xff)
#define MAX_CYCLE_ADDRS 5
#define DIRREAD 1
#define DIRWRITE 0
#define ECC_PARITY_BCH8_512B 14
#define ECC_COMPLETE BIT(31)
#define ECC_ERR_CNT(x) (((x) >> 24) & GENMASK(5, 0))
#define ECC_ZERO_CNT(x) (((x) >> 16) & GENMASK(5, 0))
#define ECC_UNCORRECTABLE 0x3f
#define PER_INFO_BYTE 8
struct meson_nfc_nand_chip {
struct list_head node;
struct nand_chip nand;
unsigned long clk_rate;
unsigned long level1_divider;
u32 bus_timing;
u32 twb;
u32 tadl;
u32 tbers_max;
u32 bch_mode;
u8 *data_buf;
__le64 *info_buf;
u32 nsels;
u8 sels[0];
};
struct meson_nand_ecc {
u32 bch;
u32 strength;
};
struct meson_nfc_data {
const struct nand_ecc_caps *ecc_caps;
};
struct meson_nfc_param {
u32 chip_select;
u32 rb_select;
};
struct nand_rw_cmd {
u32 cmd0;
u32 addrs[MAX_CYCLE_ADDRS];
u32 cmd1;
};
struct nand_timing {
u32 twb;
u32 tadl;
u32 tbers_max;
};
struct meson_nfc {
struct nand_controller controller;
struct clk *core_clk;
struct clk *device_clk;
struct clk *phase_tx;
struct clk *phase_rx;
unsigned long clk_rate;
u32 bus_timing;
struct device *dev;
void __iomem *reg_base;
struct regmap *reg_clk;
struct completion completion;
struct list_head chips;
const struct meson_nfc_data *data;
struct meson_nfc_param param;
struct nand_timing timing;
union {
int cmd[32];
struct nand_rw_cmd rw;
} cmdfifo;
dma_addr_t daddr;
dma_addr_t iaddr;
unsigned long assigned_cs;
};
enum {
NFC_ECC_BCH8_1K = 2,
NFC_ECC_BCH24_1K,
NFC_ECC_BCH30_1K,
NFC_ECC_BCH40_1K,
NFC_ECC_BCH50_1K,
NFC_ECC_BCH60_1K,
};
#define MESON_ECC_DATA(b, s) { .bch = (b), .strength = (s)}
static struct meson_nand_ecc meson_ecc[] = {
MESON_ECC_DATA(NFC_ECC_BCH8_1K, 8),
MESON_ECC_DATA(NFC_ECC_BCH24_1K, 24),
MESON_ECC_DATA(NFC_ECC_BCH30_1K, 30),
MESON_ECC_DATA(NFC_ECC_BCH40_1K, 40),
MESON_ECC_DATA(NFC_ECC_BCH50_1K, 50),
MESON_ECC_DATA(NFC_ECC_BCH60_1K, 60),
};
static int meson_nand_calc_ecc_bytes(int step_size, int strength)
{
int ecc_bytes;
if (step_size == 512 && strength == 8)
return ECC_PARITY_BCH8_512B;
ecc_bytes = DIV_ROUND_UP(strength * fls(step_size * 8), 8);
ecc_bytes = ALIGN(ecc_bytes, 2);
return ecc_bytes;
}
NAND_ECC_CAPS_SINGLE(meson_gxl_ecc_caps,
meson_nand_calc_ecc_bytes, 1024, 8, 24, 30, 40, 50, 60);
NAND_ECC_CAPS_SINGLE(meson_axg_ecc_caps,
meson_nand_calc_ecc_bytes, 1024, 8);
static struct meson_nfc_nand_chip *to_meson_nand(struct nand_chip *nand)
{
return container_of(nand, struct meson_nfc_nand_chip, nand);
}
static void meson_nfc_select_chip(struct nand_chip *nand, int chip)
{
struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
struct meson_nfc *nfc = nand_get_controller_data(nand);
int ret, value;
if (chip < 0 || WARN_ON_ONCE(chip >= meson_chip->nsels))
return;
nfc->param.chip_select = meson_chip->sels[chip] ? NAND_CE1 : NAND_CE0;
nfc->param.rb_select = nfc->param.chip_select;
nfc->timing.twb = meson_chip->twb;
nfc->timing.tadl = meson_chip->tadl;
nfc->timing.tbers_max = meson_chip->tbers_max;
if (nfc->clk_rate != meson_chip->clk_rate) {
ret = clk_set_rate(nfc->device_clk, meson_chip->clk_rate);
if (ret) {
dev_err(nfc->dev, "failed to set clock rate\n");
return;
}
nfc->clk_rate = meson_chip->clk_rate;
}
if (nfc->bus_timing != meson_chip->bus_timing) {
value = (NFC_CLK_CYCLE - 1) | (meson_chip->bus_timing << 5);
writel(value, nfc->reg_base + NFC_REG_CFG);
writel((1 << 31), nfc->reg_base + NFC_REG_CMD);
nfc->bus_timing = meson_chip->bus_timing;
}
}
static void meson_nfc_cmd_idle(struct meson_nfc *nfc, u32 time)
{
writel(nfc->param.chip_select | NFC_CMD_IDLE | (time & 0x3ff),
nfc->reg_base + NFC_REG_CMD);
}
static void meson_nfc_cmd_seed(struct meson_nfc *nfc, u32 seed)
{
writel(NFC_CMD_SEED | (0xc2 + (seed & 0x7fff)),
nfc->reg_base + NFC_REG_CMD);
}
static void meson_nfc_cmd_access(struct nand_chip *nand, int raw, bool dir,
int scrambler)
{
struct mtd_info *mtd = nand_to_mtd(nand);
struct meson_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
u32 bch = meson_chip->bch_mode, cmd;
int len = mtd->writesize, pagesize, pages;
pagesize = nand->ecc.size;
if (raw) {
len = mtd->writesize + mtd->oobsize;
cmd = (len & GENMASK(5, 0)) | scrambler | DMA_DIR(dir);
writel(cmd, nfc->reg_base + NFC_REG_CMD);
return;
}
pages = len / nand->ecc.size;
cmd = CMDRWGEN(DMA_DIR(dir), scrambler, bch,
NFC_CMD_SHORTMODE_DISABLE, pagesize, pages);
writel(cmd, nfc->reg_base + NFC_REG_CMD);
}
static void meson_nfc_drain_cmd(struct meson_nfc *nfc)
{
/*
* Insert two commands to make sure all valid commands are finished.
*
* The Nand flash controller is designed as two stages pipleline -
* a) fetch and b) excute.
* There might be cases when the driver see command queue is empty,
* but the Nand flash controller still has two commands buffered,
* one is fetched into NFC request queue (ready to run), and another
* is actively executing. So pushing 2 "IDLE" commands guarantees that
* the pipeline is emptied.
*/
meson_nfc_cmd_idle(nfc, 0);
meson_nfc_cmd_idle(nfc, 0);
}
static int meson_nfc_wait_cmd_finish(struct meson_nfc *nfc,
unsigned int timeout_ms)
{
u32 cmd_size = 0;
int ret;
/* wait cmd fifo is empty */
ret = readl_relaxed_poll_timeout(nfc->reg_base + NFC_REG_CMD, cmd_size,
!NFC_CMD_GET_SIZE(cmd_size),
10, timeout_ms * 1000);
if (ret)
dev_err(nfc->dev, "wait for empty CMD FIFO time out\n");
return ret;
}
static int meson_nfc_wait_dma_finish(struct meson_nfc *nfc)
{
meson_nfc_drain_cmd(nfc);
return meson_nfc_wait_cmd_finish(nfc, DMA_BUSY_TIMEOUT);
}
static u8 *meson_nfc_oob_ptr(struct nand_chip *nand, int i)
{
struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
int len;
len = nand->ecc.size * (i + 1) + (nand->ecc.bytes + 2) * i;
return meson_chip->data_buf + len;
}
static u8 *meson_nfc_data_ptr(struct nand_chip *nand, int i)
{
struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
int len, temp;
temp = nand->ecc.size + nand->ecc.bytes;
len = (temp + 2) * i;
return meson_chip->data_buf + len;
}
static void meson_nfc_get_data_oob(struct nand_chip *nand,
u8 *buf, u8 *oobbuf)
{
int i, oob_len = 0;
u8 *dsrc, *osrc;
oob_len = nand->ecc.bytes + 2;
for (i = 0; i < nand->ecc.steps; i++) {
if (buf) {
dsrc = meson_nfc_data_ptr(nand, i);
memcpy(buf, dsrc, nand->ecc.size);
buf += nand->ecc.size;
}
osrc = meson_nfc_oob_ptr(nand, i);
memcpy(oobbuf, osrc, oob_len);
oobbuf += oob_len;
}
}
static void meson_nfc_set_data_oob(struct nand_chip *nand,
const u8 *buf, u8 *oobbuf)
{
int i, oob_len = 0;
u8 *dsrc, *osrc;
oob_len = nand->ecc.bytes + 2;
for (i = 0; i < nand->ecc.steps; i++) {
if (buf) {
dsrc = meson_nfc_data_ptr(nand, i);
memcpy(dsrc, buf, nand->ecc.size);
buf += nand->ecc.size;
}
osrc = meson_nfc_oob_ptr(nand, i);
memcpy(osrc, oobbuf, oob_len);
oobbuf += oob_len;
}
}
static int meson_nfc_queue_rb(struct meson_nfc *nfc, int timeout_ms)
{
u32 cmd, cfg;
int ret = 0;
meson_nfc_cmd_idle(nfc, nfc->timing.twb);
meson_nfc_drain_cmd(nfc);
meson_nfc_wait_cmd_finish(nfc, CMD_FIFO_EMPTY_TIMEOUT);
cfg = readl(nfc->reg_base + NFC_REG_CFG);
cfg |= NFC_RB_IRQ_EN;
writel(cfg, nfc->reg_base + NFC_REG_CFG);
init_completion(&nfc->completion);
/* use the max erase time as the maximum clock for waiting R/B */
cmd = NFC_CMD_RB | NFC_CMD_RB_INT
| nfc->param.chip_select | nfc->timing.tbers_max;
writel(cmd, nfc->reg_base + NFC_REG_CMD);
ret = wait_for_completion_timeout(&nfc->completion,
msecs_to_jiffies(timeout_ms));
if (ret == 0)
ret = -1;
return ret;
}
static void meson_nfc_set_user_byte(struct nand_chip *nand, u8 *oob_buf)
{
struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
__le64 *info;
int i, count;
for (i = 0, count = 0; i < nand->ecc.steps; i++, count += 2) {
info = &meson_chip->info_buf[i];
*info |= oob_buf[count];
*info |= oob_buf[count + 1] << 8;
}
}
static void meson_nfc_get_user_byte(struct nand_chip *nand, u8 *oob_buf)
{
struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
__le64 *info;
int i, count;
for (i = 0, count = 0; i < nand->ecc.steps; i++, count += 2) {
info = &meson_chip->info_buf[i];
oob_buf[count] = *info;
oob_buf[count + 1] = *info >> 8;
}
}
static int meson_nfc_ecc_correct(struct nand_chip *nand, u32 *bitflips,
u64 *correct_bitmap)
{
struct mtd_info *mtd = nand_to_mtd(nand);
struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
__le64 *info;
int ret = 0, i;
for (i = 0; i < nand->ecc.steps; i++) {
info = &meson_chip->info_buf[i];
if (ECC_ERR_CNT(*info) != ECC_UNCORRECTABLE) {
mtd->ecc_stats.corrected += ECC_ERR_CNT(*info);
*bitflips = max_t(u32, *bitflips, ECC_ERR_CNT(*info));
*correct_bitmap |= 1 >> i;
continue;
}
if ((nand->options & NAND_NEED_SCRAMBLING) &&
ECC_ZERO_CNT(*info) < nand->ecc.strength) {
mtd->ecc_stats.corrected += ECC_ZERO_CNT(*info);
*bitflips = max_t(u32, *bitflips,
ECC_ZERO_CNT(*info));
ret = ECC_CHECK_RETURN_FF;
} else {
ret = -EBADMSG;
}
}
return ret;
}
static int meson_nfc_dma_buffer_setup(struct nand_chip *nand, u8 *databuf,
int datalen, u8 *infobuf, int infolen,
enum dma_data_direction dir)
{
struct meson_nfc *nfc = nand_get_controller_data(nand);
u32 cmd;
int ret = 0;
nfc->daddr = dma_map_single(nfc->dev, (void *)databuf, datalen, dir);
ret = dma_mapping_error(nfc->dev, nfc->daddr);
if (ret) {
dev_err(nfc->dev, "DMA mapping error\n");
return ret;
}
cmd = GENCMDDADDRL(NFC_CMD_ADL, nfc->daddr);
writel(cmd, nfc->reg_base + NFC_REG_CMD);
cmd = GENCMDDADDRH(NFC_CMD_ADH, nfc->daddr);
writel(cmd, nfc->reg_base + NFC_REG_CMD);
if (infobuf) {
nfc->iaddr = dma_map_single(nfc->dev, infobuf, infolen, dir);
ret = dma_mapping_error(nfc->dev, nfc->iaddr);
if (ret) {
dev_err(nfc->dev, "DMA mapping error\n");
dma_unmap_single(nfc->dev,
nfc->daddr, datalen, dir);
return ret;
}
cmd = GENCMDIADDRL(NFC_CMD_AIL, nfc->iaddr);
writel(cmd, nfc->reg_base + NFC_REG_CMD);
cmd = GENCMDIADDRH(NFC_CMD_AIH, nfc->iaddr);
writel(cmd, nfc->reg_base + NFC_REG_CMD);
}
return ret;
}
static void meson_nfc_dma_buffer_release(struct nand_chip *nand,
int infolen, int datalen,
enum dma_data_direction dir)
{
struct meson_nfc *nfc = nand_get_controller_data(nand);
dma_unmap_single(nfc->dev, nfc->daddr, datalen, dir);
if (infolen)
dma_unmap_single(nfc->dev, nfc->iaddr, infolen, dir);
}
static int meson_nfc_read_buf(struct nand_chip *nand, u8 *buf, int len)
{
struct meson_nfc *nfc = nand_get_controller_data(nand);
int ret = 0;
u32 cmd;
u8 *info;
info = kzalloc(PER_INFO_BYTE, GFP_KERNEL);
ret = meson_nfc_dma_buffer_setup(nand, buf, len, info,
PER_INFO_BYTE, DMA_FROM_DEVICE);
if (ret)
return ret;
cmd = NFC_CMD_N2M | (len & GENMASK(5, 0));
writel(cmd, nfc->reg_base + NFC_REG_CMD);
meson_nfc_drain_cmd(nfc);
meson_nfc_wait_cmd_finish(nfc, 1000);
meson_nfc_dma_buffer_release(nand, len, PER_INFO_BYTE, DMA_FROM_DEVICE);
kfree(info);
return ret;
}
static int meson_nfc_write_buf(struct nand_chip *nand, u8 *buf, int len)
{
struct meson_nfc *nfc = nand_get_controller_data(nand);
int ret = 0;
u32 cmd;
ret = meson_nfc_dma_buffer_setup(nand, buf, len, NULL,
0, DMA_TO_DEVICE);
if (ret)
return ret;
cmd = NFC_CMD_M2N | (len & GENMASK(5, 0));
writel(cmd, nfc->reg_base + NFC_REG_CMD);
meson_nfc_drain_cmd(nfc);
meson_nfc_wait_cmd_finish(nfc, 1000);
meson_nfc_dma_buffer_release(nand, len, 0, DMA_TO_DEVICE);
return ret;
}
static int meson_nfc_rw_cmd_prepare_and_execute(struct nand_chip *nand,
int page, bool in)
{
struct mtd_info *mtd = nand_to_mtd(nand);
struct meson_nfc *nfc = nand_get_controller_data(nand);
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(&nand->data_interface);
u32 *addrs = nfc->cmdfifo.rw.addrs;
u32 cs = nfc->param.chip_select;
u32 cmd0, cmd_num, row_start;
int ret = 0, i;
cmd_num = sizeof(struct nand_rw_cmd) / sizeof(int);
cmd0 = in ? NAND_CMD_READ0 : NAND_CMD_SEQIN;
nfc->cmdfifo.rw.cmd0 = cs | NFC_CMD_CLE | cmd0;
addrs[0] = cs | NFC_CMD_ALE | 0;
if (mtd->writesize <= 512) {
cmd_num--;
row_start = 1;
} else {
addrs[1] = cs | NFC_CMD_ALE | 0;
row_start = 2;
}
addrs[row_start] = cs | NFC_CMD_ALE | ROW_ADDER(page, 0);
addrs[row_start + 1] = cs | NFC_CMD_ALE | ROW_ADDER(page, 1);
if (nand->options & NAND_ROW_ADDR_3)
addrs[row_start + 2] =
cs | NFC_CMD_ALE | ROW_ADDER(page, 2);
else
cmd_num--;
/* subtract cmd1 */
cmd_num--;
for (i = 0; i < cmd_num; i++)
writel_relaxed(nfc->cmdfifo.cmd[i],
nfc->reg_base + NFC_REG_CMD);
if (in) {
nfc->cmdfifo.rw.cmd1 = cs | NFC_CMD_CLE | NAND_CMD_READSTART;
writel(nfc->cmdfifo.rw.cmd1, nfc->reg_base + NFC_REG_CMD);
meson_nfc_queue_rb(nfc, PSEC_TO_MSEC(sdr->tR_max));
} else {
meson_nfc_cmd_idle(nfc, nfc->timing.tadl);
}
return ret;
}
static int meson_nfc_write_page_sub(struct nand_chip *nand,
int page, int raw)
{
struct mtd_info *mtd = nand_to_mtd(nand);
const struct nand_sdr_timings *sdr =
nand_get_sdr_timings(&nand->data_interface);
struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
struct meson_nfc *nfc = nand_get_controller_data(nand);
int data_len, info_len;
u32 cmd;
int ret;
meson_nfc_select_chip(nand, nand->cur_cs);
data_len = mtd->writesize + mtd->oobsize;
info_len = nand->ecc.steps * PER_INFO_BYTE;
ret = meson_nfc_rw_cmd_prepare_and_execute(nand, page, DIRWRITE);
if (ret)
return ret;
ret = meson_nfc_dma_buffer_setup(nand, meson_chip->data_buf,
data_len, (u8 *)meson_chip->info_buf,
info_len, DMA_TO_DEVICE);
if (ret)
return ret;
if (nand->options & NAND_NEED_SCRAMBLING) {
meson_nfc_cmd_seed(nfc, page);
meson_nfc_cmd_access(nand, raw, DIRWRITE,
NFC_CMD_SCRAMBLER_ENABLE);
} else {
meson_nfc_cmd_access(nand, raw, DIRWRITE,
NFC_CMD_SCRAMBLER_DISABLE);
}
cmd = nfc->param.chip_select | NFC_CMD_CLE | NAND_CMD_PAGEPROG;
writel(cmd, nfc->reg_base + NFC_REG_CMD);
meson_nfc_queue_rb(nfc, PSEC_TO_MSEC(sdr->tPROG_max));
meson_nfc_dma_buffer_release(nand, data_len, info_len, DMA_TO_DEVICE);
return ret;
}
static int meson_nfc_write_page_raw(struct nand_chip *nand, const u8 *buf,
int oob_required, int page)
{
u8 *oob_buf = nand->oob_poi;
meson_nfc_set_data_oob(nand, buf, oob_buf);
return meson_nfc_write_page_sub(nand, page, 1);
}
static int meson_nfc_write_page_hwecc(struct nand_chip *nand,
const u8 *buf, int oob_required, int page)
{
struct mtd_info *mtd = nand_to_mtd(nand);
struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
u8 *oob_buf = nand->oob_poi;
memcpy(meson_chip->data_buf, buf, mtd->writesize);
memset(meson_chip->info_buf, 0, nand->ecc.steps * PER_INFO_BYTE);
meson_nfc_set_user_byte(nand, oob_buf);
return meson_nfc_write_page_sub(nand, page, 0);
}
static void meson_nfc_check_ecc_pages_valid(struct meson_nfc *nfc,
struct nand_chip *nand, int raw)
{
struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
__le64 *info;
u32 neccpages;
int ret;
neccpages = raw ? 1 : nand->ecc.steps;
info = &meson_chip->info_buf[neccpages - 1];
do {
usleep_range(10, 15);
/* info is updated by nfc dma engine*/
smp_rmb();
ret = *info & ECC_COMPLETE;
} while (!ret);
}
static int meson_nfc_read_page_sub(struct nand_chip *nand,
int page, int raw)
{
struct mtd_info *mtd = nand_to_mtd(nand);
struct meson_nfc *nfc = nand_get_controller_data(nand);
struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
int data_len, info_len;
int ret;
meson_nfc_select_chip(nand, nand->cur_cs);
data_len = mtd->writesize + mtd->oobsize;
info_len = nand->ecc.steps * PER_INFO_BYTE;
ret = meson_nfc_rw_cmd_prepare_and_execute(nand, page, DIRREAD);
if (ret)
return ret;
ret = meson_nfc_dma_buffer_setup(nand, meson_chip->data_buf,
data_len, (u8 *)meson_chip->info_buf,
info_len, DMA_FROM_DEVICE);
if (ret)
return ret;
if (nand->options & NAND_NEED_SCRAMBLING) {
meson_nfc_cmd_seed(nfc, page);
meson_nfc_cmd_access(nand, raw, DIRREAD,
NFC_CMD_SCRAMBLER_ENABLE);
} else {
meson_nfc_cmd_access(nand, raw, DIRREAD,
NFC_CMD_SCRAMBLER_DISABLE);
}
ret = meson_nfc_wait_dma_finish(nfc);
meson_nfc_check_ecc_pages_valid(nfc, nand, raw);
meson_nfc_dma_buffer_release(nand, data_len, info_len, DMA_FROM_DEVICE);
return ret;
}
static int meson_nfc_read_page_raw(struct nand_chip *nand, u8 *buf,
int oob_required, int page)
{
u8 *oob_buf = nand->oob_poi;
int ret;
ret = meson_nfc_read_page_sub(nand, page, 1);
if (ret)
return ret;
meson_nfc_get_data_oob(nand, buf, oob_buf);
return 0;
}
static int meson_nfc_read_page_hwecc(struct nand_chip *nand, u8 *buf,
int oob_required, int page)
{
struct mtd_info *mtd = nand_to_mtd(nand);
struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
struct nand_ecc_ctrl *ecc = &nand->ecc;
u64 correct_bitmap = 0;
u32 bitflips = 0;
u8 *oob_buf = nand->oob_poi;
int ret, i;
ret = meson_nfc_read_page_sub(nand, page, 0);
if (ret)
return ret;
meson_nfc_get_user_byte(nand, oob_buf);
ret = meson_nfc_ecc_correct(nand, &bitflips, &correct_bitmap);
if (ret == ECC_CHECK_RETURN_FF) {
if (buf)
memset(buf, 0xff, mtd->writesize);
memset(oob_buf, 0xff, mtd->oobsize);
} else if (ret < 0) {
if ((nand->options & NAND_NEED_SCRAMBLING) || !buf) {
mtd->ecc_stats.failed++;
return bitflips;
}
ret = meson_nfc_read_page_raw(nand, buf, 0, page);
if (ret)
return ret;
for (i = 0; i < nand->ecc.steps ; i++) {
u8 *data = buf + i * ecc->size;
u8 *oob = nand->oob_poi + i * (ecc->bytes + 2);
if (correct_bitmap & (1 << i))
continue;
ret = nand_check_erased_ecc_chunk(data, ecc->size,
oob, ecc->bytes + 2,
NULL, 0,
ecc->strength);
if (ret < 0) {
mtd->ecc_stats.failed++;
} else {
mtd->ecc_stats.corrected += ret;
bitflips = max_t(u32, bitflips, ret);
}
}
} else if (buf && buf != meson_chip->data_buf) {
memcpy(buf, meson_chip->data_buf, mtd->writesize);
}
return bitflips;
}
static int meson_nfc_read_oob_raw(struct nand_chip *nand, int page)
{
return meson_nfc_read_page_raw(nand, NULL, 1, page);
}
static int meson_nfc_read_oob(struct nand_chip *nand, int page)
{
return meson_nfc_read_page_hwecc(nand, NULL, 1, page);
}
static bool meson_nfc_is_buffer_dma_safe(const void *buffer)
{
if (virt_addr_valid(buffer) && (!object_is_on_stack(buffer)))
return true;
return false;
}
static void *
meson_nand_op_get_dma_safe_input_buf(const struct nand_op_instr *instr)
{
if (WARN_ON(instr->type != NAND_OP_DATA_IN_INSTR))
return NULL;
if (meson_nfc_is_buffer_dma_safe(instr->ctx.data.buf.in))
return instr->ctx.data.buf.in;
return kzalloc(instr->ctx.data.len, GFP_KERNEL);
}
static void
meson_nand_op_put_dma_safe_input_buf(const struct nand_op_instr *instr,
void *buf)
{
if (WARN_ON(instr->type != NAND_OP_DATA_IN_INSTR) ||
WARN_ON(!buf))
return;
if (buf == instr->ctx.data.buf.in)
return;
memcpy(instr->ctx.data.buf.in, buf, instr->ctx.data.len);
kfree(buf);
}
static void *
meson_nand_op_get_dma_safe_output_buf(const struct nand_op_instr *instr)
{
if (WARN_ON(instr->type != NAND_OP_DATA_OUT_INSTR))
return NULL;
if (meson_nfc_is_buffer_dma_safe(instr->ctx.data.buf.out))
return (void *)instr->ctx.data.buf.out;
return kmemdup(instr->ctx.data.buf.out,
instr->ctx.data.len, GFP_KERNEL);
}
static void
meson_nand_op_put_dma_safe_output_buf(const struct nand_op_instr *instr,
const void *buf)
{
if (WARN_ON(instr->type != NAND_OP_DATA_OUT_INSTR) ||
WARN_ON(!buf))
return;
if (buf != instr->ctx.data.buf.out)
kfree(buf);
}
static int meson_nfc_exec_op(struct nand_chip *nand,
const struct nand_operation *op, bool check_only)
{
struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
struct meson_nfc *nfc = nand_get_controller_data(nand);
const struct nand_op_instr *instr = NULL;
void *buf;
u32 op_id, delay_idle, cmd;
int i;
meson_nfc_select_chip(nand, op->cs);
for (op_id = 0; op_id < op->ninstrs; op_id++) {
instr = &op->instrs[op_id];
delay_idle = DIV_ROUND_UP(PSEC_TO_NSEC(instr->delay_ns),
meson_chip->level1_divider *
NFC_CLK_CYCLE);
switch (instr->type) {
case NAND_OP_CMD_INSTR:
cmd = nfc->param.chip_select | NFC_CMD_CLE;
cmd |= instr->ctx.cmd.opcode & 0xff;
writel(cmd, nfc->reg_base + NFC_REG_CMD);
meson_nfc_cmd_idle(nfc, delay_idle);
break;
case NAND_OP_ADDR_INSTR:
for (i = 0; i < instr->ctx.addr.naddrs; i++) {
cmd = nfc->param.chip_select | NFC_CMD_ALE;
cmd |= instr->ctx.addr.addrs[i] & 0xff;
writel(cmd, nfc->reg_base + NFC_REG_CMD);
}
meson_nfc_cmd_idle(nfc, delay_idle);
break;
case NAND_OP_DATA_IN_INSTR:
buf = meson_nand_op_get_dma_safe_input_buf(instr);
if (!buf)
return -ENOMEM;
meson_nfc_read_buf(nand, buf, instr->ctx.data.len);
meson_nand_op_put_dma_safe_input_buf(instr, buf);
break;
case NAND_OP_DATA_OUT_INSTR:
buf = meson_nand_op_get_dma_safe_output_buf(instr);
if (!buf)
return -ENOMEM;
meson_nfc_write_buf(nand, buf, instr->ctx.data.len);
meson_nand_op_put_dma_safe_output_buf(instr, buf);
break;
case NAND_OP_WAITRDY_INSTR:
meson_nfc_queue_rb(nfc, instr->ctx.waitrdy.timeout_ms);
if (instr->delay_ns)
meson_nfc_cmd_idle(nfc, delay_idle);
break;
}
}
meson_nfc_wait_cmd_finish(nfc, 1000);
return 0;
}
static int meson_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *oobregion)
{
struct nand_chip *nand = mtd_to_nand(mtd);
if (section >= nand->ecc.steps)
return -ERANGE;
oobregion->offset = 2 + (section * (2 + nand->ecc.bytes));
oobregion->length = nand->ecc.bytes;
return 0;
}
static int meson_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *oobregion)
{
struct nand_chip *nand = mtd_to_nand(mtd);
if (section >= nand->ecc.steps)
return -ERANGE;
oobregion->offset = section * (2 + nand->ecc.bytes);
oobregion->length = 2;
return 0;
}
static const struct mtd_ooblayout_ops meson_ooblayout_ops = {
.ecc = meson_ooblayout_ecc,
.free = meson_ooblayout_free,
};
static int meson_nfc_clk_init(struct meson_nfc *nfc)
{
int ret;
/* request core clock */
nfc->core_clk = devm_clk_get(nfc->dev, "core");
if (IS_ERR(nfc->core_clk)) {
dev_err(nfc->dev, "failed to get core clock\n");
return PTR_ERR(nfc->core_clk);
}
nfc->device_clk = devm_clk_get(nfc->dev, "device");
if (IS_ERR(nfc->device_clk)) {
dev_err(nfc->dev, "failed to get device clock\n");
return PTR_ERR(nfc->device_clk);
}
nfc->phase_tx = devm_clk_get(nfc->dev, "tx");
if (IS_ERR(nfc->phase_tx)) {
dev_err(nfc->dev, "failed to get TX clk\n");
return PTR_ERR(nfc->phase_tx);
}
nfc->phase_rx = devm_clk_get(nfc->dev, "rx");
if (IS_ERR(nfc->phase_rx)) {
dev_err(nfc->dev, "failed to get RX clk\n");
return PTR_ERR(nfc->phase_rx);
}
/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
regmap_update_bits(nfc->reg_clk,
0, CLK_SELECT_NAND, CLK_SELECT_NAND);
ret = clk_prepare_enable(nfc->core_clk);
if (ret) {
dev_err(nfc->dev, "failed to enable core clock\n");
return ret;
}
ret = clk_prepare_enable(nfc->device_clk);
if (ret) {
dev_err(nfc->dev, "failed to enable device clock\n");
goto err_device_clk;
}
ret = clk_prepare_enable(nfc->phase_tx);
if (ret) {
dev_err(nfc->dev, "failed to enable TX clock\n");
goto err_phase_tx;
}
ret = clk_prepare_enable(nfc->phase_rx);
if (ret) {
dev_err(nfc->dev, "failed to enable RX clock\n");
goto err_phase_rx;
}
ret = clk_set_rate(nfc->device_clk, 24000000);
if (ret)
goto err_phase_rx;
return 0;
err_phase_rx:
clk_disable_unprepare(nfc->phase_tx);
err_phase_tx:
clk_disable_unprepare(nfc->device_clk);
err_device_clk:
clk_disable_unprepare(nfc->core_clk);
return ret;
}
static void meson_nfc_disable_clk(struct meson_nfc *nfc)
{
clk_disable_unprepare(nfc->phase_rx);
clk_disable_unprepare(nfc->phase_tx);
clk_disable_unprepare(nfc->device_clk);
clk_disable_unprepare(nfc->core_clk);
}
static void meson_nfc_free_buffer(struct nand_chip *nand)
{
struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
kfree(meson_chip->info_buf);
kfree(meson_chip->data_buf);
}
static int meson_chip_buffer_init(struct nand_chip *nand)
{
struct mtd_info *mtd = nand_to_mtd(nand);
struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
u32 page_bytes, info_bytes, nsectors;
nsectors = mtd->writesize / nand->ecc.size;
page_bytes = mtd->writesize + mtd->oobsize;
info_bytes = nsectors * PER_INFO_BYTE;
meson_chip->data_buf = kmalloc(page_bytes, GFP_KERNEL);
if (!meson_chip->data_buf)
return -ENOMEM;
meson_chip->info_buf = kmalloc(info_bytes, GFP_KERNEL);
if (!meson_chip->info_buf) {
kfree(meson_chip->data_buf);
return -ENOMEM;
}
return 0;
}
static
int meson_nfc_setup_data_interface(struct nand_chip *nand, int csline,
const struct nand_data_interface *conf)
{
struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
const struct nand_sdr_timings *timings;
u32 div, bt_min, bt_max, tbers_clocks;
timings = nand_get_sdr_timings(conf);
if (IS_ERR(timings))
return -ENOTSUPP;
if (csline == NAND_DATA_IFACE_CHECK_ONLY)
return 0;
div = DIV_ROUND_UP((timings->tRC_min / 1000), NFC_CLK_CYCLE);
bt_min = (timings->tREA_max + NFC_DEFAULT_DELAY) / div;
bt_max = (NFC_DEFAULT_DELAY + timings->tRHOH_min +
timings->tRC_min / 2) / div;
meson_chip->twb = DIV_ROUND_UP(PSEC_TO_NSEC(timings->tWB_max),
div * NFC_CLK_CYCLE);
meson_chip->tadl = DIV_ROUND_UP(PSEC_TO_NSEC(timings->tADL_min),
div * NFC_CLK_CYCLE);
tbers_clocks = DIV_ROUND_UP_ULL(PSEC_TO_NSEC(timings->tBERS_max),
div * NFC_CLK_CYCLE);
meson_chip->tbers_max = ilog2(tbers_clocks);
if (!is_power_of_2(tbers_clocks))
meson_chip->tbers_max++;
bt_min = DIV_ROUND_UP(bt_min, 1000);
bt_max = DIV_ROUND_UP(bt_max, 1000);
if (bt_max < bt_min)
return -EINVAL;
meson_chip->level1_divider = div;
meson_chip->clk_rate = 1000000000 / meson_chip->level1_divider;
meson_chip->bus_timing = (bt_min + bt_max) / 2 + 1;
return 0;
}
static int meson_nand_bch_mode(struct nand_chip *nand)
{
struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
int i;
if (nand->ecc.strength > 60 || nand->ecc.strength < 8)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(meson_ecc); i++) {
if (meson_ecc[i].strength == nand->ecc.strength) {
meson_chip->bch_mode = meson_ecc[i].bch;
return 0;
}
}
return -EINVAL;
}
static void meson_nand_detach_chip(struct nand_chip *nand)
{
meson_nfc_free_buffer(nand);
}
static int meson_nand_attach_chip(struct nand_chip *nand)
{
struct meson_nfc *nfc = nand_get_controller_data(nand);
struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
struct mtd_info *mtd = nand_to_mtd(nand);
int nsectors = mtd->writesize / 1024;
int ret;
if (!mtd->name) {
mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
"%s:nand%d",
dev_name(nfc->dev),
meson_chip->sels[0]);
if (!mtd->name)
return -ENOMEM;
}
if (nand->bbt_options & NAND_BBT_USE_FLASH)
nand->bbt_options |= NAND_BBT_NO_OOB;
nand->options |= NAND_NO_SUBPAGE_WRITE;
ret = nand_ecc_choose_conf(nand, nfc->data->ecc_caps,
mtd->oobsize - 2 * nsectors);
if (ret) {
dev_err(nfc->dev, "failed to ECC init\n");
return -EINVAL;
}
ret = meson_nand_bch_mode(nand);
if (ret)
return -EINVAL;
nand->ecc.mode = NAND_ECC_HW;
nand->ecc.write_page_raw = meson_nfc_write_page_raw;
nand->ecc.write_page = meson_nfc_write_page_hwecc;
nand->ecc.write_oob_raw = nand_write_oob_std;
nand->ecc.write_oob = nand_write_oob_std;
nand->ecc.read_page_raw = meson_nfc_read_page_raw;
nand->ecc.read_page = meson_nfc_read_page_hwecc;
nand->ecc.read_oob_raw = meson_nfc_read_oob_raw;
nand->ecc.read_oob = meson_nfc_read_oob;
if (nand->options & NAND_BUSWIDTH_16) {
dev_err(nfc->dev, "16bits bus width not supported");
return -EINVAL;
}
ret = meson_chip_buffer_init(nand);
if (ret)
return -ENOMEM;
return ret;
}
static const struct nand_controller_ops meson_nand_controller_ops = {
.attach_chip = meson_nand_attach_chip,
.detach_chip = meson_nand_detach_chip,
.setup_data_interface = meson_nfc_setup_data_interface,
.exec_op = meson_nfc_exec_op,
};
static int
meson_nfc_nand_chip_init(struct device *dev,
struct meson_nfc *nfc, struct device_node *np)
{
struct meson_nfc_nand_chip *meson_chip;
struct nand_chip *nand;
struct mtd_info *mtd;
int ret, i;
u32 tmp, nsels;
if (!of_get_property(np, "reg", &nsels))
return -EINVAL;
nsels /= sizeof(u32);
if (!nsels || nsels > MAX_CE_NUM) {
dev_err(dev, "invalid register property size\n");
return -EINVAL;
}
meson_chip = devm_kzalloc(dev,
sizeof(*meson_chip) + (nsels * sizeof(u8)),
GFP_KERNEL);
if (!meson_chip)
return -ENOMEM;
meson_chip->nsels = nsels;
for (i = 0; i < nsels; i++) {
ret = of_property_read_u32_index(np, "reg", i, &tmp);
if (ret) {
dev_err(dev, "could not retrieve register property: %d\n",
ret);
return ret;
}
if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
dev_err(dev, "CS %d already assigned\n", tmp);
return -EINVAL;
}
}
nand = &meson_chip->nand;
nand->controller = &nfc->controller;
nand->controller->ops = &meson_nand_controller_ops;
nand_set_flash_node(nand, np);
nand_set_controller_data(nand, nfc);
nand->options |= NAND_USE_BOUNCE_BUFFER;
mtd = nand_to_mtd(nand);
mtd->owner = THIS_MODULE;
mtd->dev.parent = dev;
ret = nand_scan(nand, nsels);
if (ret)
return ret;
ret = mtd_device_register(mtd, NULL, 0);
if (ret) {
dev_err(dev, "failed to register MTD device: %d\n", ret);
nand_cleanup(nand);
return ret;
}
list_add_tail(&meson_chip->node, &nfc->chips);
return 0;
}
static int meson_nfc_nand_chip_cleanup(struct meson_nfc *nfc)
{
struct meson_nfc_nand_chip *meson_chip;
struct mtd_info *mtd;
int ret;
while (!list_empty(&nfc->chips)) {
meson_chip = list_first_entry(&nfc->chips,
struct meson_nfc_nand_chip, node);
mtd = nand_to_mtd(&meson_chip->nand);
ret = mtd_device_unregister(mtd);
if (ret)
return ret;
meson_nfc_free_buffer(&meson_chip->nand);
nand_cleanup(&meson_chip->nand);
list_del(&meson_chip->node);
}
return 0;
}
static int meson_nfc_nand_chips_init(struct device *dev,
struct meson_nfc *nfc)
{
struct device_node *np = dev->of_node;
struct device_node *nand_np;
int ret;
for_each_child_of_node(np, nand_np) {
ret = meson_nfc_nand_chip_init(dev, nfc, nand_np);
if (ret) {
meson_nfc_nand_chip_cleanup(nfc);
return ret;
}
}
return 0;
}
static irqreturn_t meson_nfc_irq(int irq, void *id)
{
struct meson_nfc *nfc = id;
u32 cfg;
cfg = readl(nfc->reg_base + NFC_REG_CFG);
if (!(cfg & NFC_RB_IRQ_EN))
return IRQ_NONE;
cfg &= ~(NFC_RB_IRQ_EN);
writel(cfg, nfc->reg_base + NFC_REG_CFG);
complete(&nfc->completion);
return IRQ_HANDLED;
}
static const struct meson_nfc_data meson_gxl_data = {
.ecc_caps = &meson_gxl_ecc_caps,
};
static const struct meson_nfc_data meson_axg_data = {
.ecc_caps = &meson_axg_ecc_caps,
};
static const struct of_device_id meson_nfc_id_table[] = {
{
.compatible = "amlogic,meson-gxl-nfc",
.data = &meson_gxl_data,
}, {
.compatible = "amlogic,meson-axg-nfc",
.data = &meson_axg_data,
},
{}
};
MODULE_DEVICE_TABLE(of, meson_nfc_id_table);
static int meson_nfc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct meson_nfc *nfc;
struct resource *res;
int ret, irq;
nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
if (!nfc)
return -ENOMEM;
nfc->data = of_device_get_match_data(&pdev->dev);
if (!nfc->data)
return -ENODEV;
nand_controller_init(&nfc->controller);
INIT_LIST_HEAD(&nfc->chips);
nfc->dev = dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
nfc->reg_base = devm_ioremap_resource(dev, res);
if (IS_ERR(nfc->reg_base))
return PTR_ERR(nfc->reg_base);
nfc->reg_clk =
syscon_regmap_lookup_by_phandle(dev->of_node,
"amlogic,mmc-syscon");
if (IS_ERR(nfc->reg_clk)) {
dev_err(dev, "Failed to lookup clock base\n");
return PTR_ERR(nfc->reg_clk);
}
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(dev, "no NFC IRQ resource\n");
return -EINVAL;
}
ret = meson_nfc_clk_init(nfc);
if (ret) {
dev_err(dev, "failed to initialize NAND clock\n");
return ret;
}
writel(0, nfc->reg_base + NFC_REG_CFG);
ret = devm_request_irq(dev, irq, meson_nfc_irq, 0, dev_name(dev), nfc);
if (ret) {
dev_err(dev, "failed to request NFC IRQ\n");
ret = -EINVAL;
goto err_clk;
}
ret = dma_set_mask(dev, DMA_BIT_MASK(32));
if (ret) {
dev_err(dev, "failed to set DMA mask\n");
goto err_clk;
}
platform_set_drvdata(pdev, nfc);
ret = meson_nfc_nand_chips_init(dev, nfc);
if (ret) {
dev_err(dev, "failed to init NAND chips\n");
goto err_clk;
}
return 0;
err_clk:
meson_nfc_disable_clk(nfc);
return ret;
}
static int meson_nfc_remove(struct platform_device *pdev)
{
struct meson_nfc *nfc = platform_get_drvdata(pdev);
int ret;
ret = meson_nfc_nand_chip_cleanup(nfc);
if (ret)
return ret;
meson_nfc_disable_clk(nfc);
platform_set_drvdata(pdev, NULL);
return 0;
}
static struct platform_driver meson_nfc_driver = {
.probe = meson_nfc_probe,
.remove = meson_nfc_remove,
.driver = {
.name = "meson-nand",
.of_match_table = meson_nfc_id_table,
},
};
module_platform_driver(meson_nfc_driver);
MODULE_LICENSE("Dual MIT/GPL");
MODULE_AUTHOR("Liang Yang <liang.yang@amlogic.com>");
MODULE_DESCRIPTION("Amlogic's Meson NAND Flash Controller driver");
drivers/mtd/nand/raw/mtk_ecc.c
View file @ 9220d7be
......@@ -267,11 +267,15 @@ static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
struct mtk_ecc *ecc;
pdev = of_find_device_by_node(np);
if (!pdev || !platform_get_drvdata(pdev))
if (!pdev)
return ERR_PTR(-EPROBE_DEFER);
get_device(&pdev->dev);
ecc = platform_get_drvdata(pdev);
if (!ecc) {
put_device(&pdev->dev);
return ERR_PTR(-EPROBE_DEFER);
}
clk_prepare_enable(ecc->clk);
mtk_ecc_hw_init(ecc);
......
drivers/mtd/nand/raw/mtk_nand.c
View file @ 9220d7be
......@@ -1451,8 +1451,7 @@ static int mtk_nfc_probe(struct platform_device *pdev)
if (!nfc)
return -ENOMEM;
spin_lock_init(&nfc->controller.lock);
init_waitqueue_head(&nfc->controller.wq);
nand_controller_init(&nfc->controller);
INIT_LIST_HEAD(&nfc->chips);
nfc->controller.ops = &mtk_nfc_controller_ops;
......
drivers/mtd/nand/raw/nand_base.c
View file @ 9220d7be
......@@ -278,11 +278,8 @@ EXPORT_SYMBOL_GPL(nand_deselect_target);
static void nand_release_device(struct nand_chip *chip)
{
/* Release the controller and the chip */
spin_lock(&chip->controller->lock);
chip->controller->active = NULL;
chip->state = FL_READY;
wake_up(&chip->controller->wq);
spin_unlock(&chip->controller->lock);
mutex_unlock(&chip->controller->lock);
mutex_unlock(&chip->lock);
}
/**
......@@ -330,58 +327,24 @@ static int nand_isbad_bbm(struct nand_chip *chip, loff_t ofs)
return nand_block_bad(chip, ofs);
}
/**
* panic_nand_get_device - [GENERIC] Get chip for selected access
* @chip: the nand chip descriptor
* @new_state: the state which is requested
*
* Used when in panic, no locks are taken.
*/
static void panic_nand_get_device(struct nand_chip *chip, int new_state)
{
/* Hardware controller shared among independent devices */
chip->controller->active = chip;
chip->state = new_state;
}
/**
* nand_get_device - [GENERIC] Get chip for selected access
* @chip: NAND chip structure
* @new_state: the state which is requested
*
* Get the device and lock it for exclusive access
* Lock the device and its controller for exclusive access
*
* Return: -EBUSY if the chip has been suspended, 0 otherwise
*/
static int
nand_get_device(struct nand_chip *chip, int new_state)
static int nand_get_device(struct nand_chip *chip)
{
spinlock_t *lock = &chip->controller->lock;
wait_queue_head_t *wq = &chip->controller->wq;
DECLARE_WAITQUEUE(wait, current);
retry:
spin_lock(lock);
/* Hardware controller shared among independent devices */
if (!chip->controller->active)
chip->controller->active = chip;
if (chip->controller->active == chip && chip->state == FL_READY) {
chip->state = new_state;
spin_unlock(lock);
return 0;
mutex_lock(&chip->lock);
if (chip->suspended) {
mutex_unlock(&chip->lock);
return -EBUSY;
}
if (new_state == FL_PM_SUSPENDED) {
if (chip->controller->active->state == FL_PM_SUSPENDED) {
chip->state = FL_PM_SUSPENDED;
spin_unlock(lock);
mutex_lock(&chip->controller->lock);
return 0;
}
}
set_current_state(TASK_UNINTERRUPTIBLE);
add_wait_queue(wq, &wait);
spin_unlock(lock);
schedule();
remove_wait_queue(wq, &wait);
goto retry;
}
/**
......@@ -457,7 +420,7 @@ static int nand_do_write_oob(struct nand_chip *chip, loff_t to,
struct mtd_oob_ops *ops)
{
struct mtd_info *mtd = nand_to_mtd(chip);
int chipnr, page, status, len;
int chipnr, page, status, len, ret;
pr_debug("%s: to = 0x%08x, len = %i\n",
__func__, (unsigned int)to, (int)ops->ooblen);
......@@ -479,7 +442,9 @@ static int nand_do_write_oob(struct nand_chip *chip, loff_t to,
* if we don't do this. I have no clue why, but I seem to have 'fixed'
* it in the doc2000 driver in August 1999. dwmw2.
*/
nand_reset(chip, chipnr);
ret = nand_reset(chip, chipnr);
if (ret)
return ret;
nand_select_target(chip, chipnr);
......@@ -602,7 +567,10 @@ static int nand_block_markbad_lowlevel(struct nand_chip *chip, loff_t ofs)
nand_erase_nand(chip, &einfo, 0);
/* Write bad block marker to OOB */
nand_get_device(chip, FL_WRITING);
ret = nand_get_device(chip);
if (ret)
return ret;
ret = nand_markbad_bbm(chip, ofs);
nand_release_device(chip);
}
......@@ -3580,7 +3548,9 @@ static int nand_read_oob(struct mtd_info *mtd, loff_t from,
ops->mode != MTD_OPS_RAW)
return -ENOTSUPP;
nand_get_device(chip, FL_READING);
ret = nand_get_device(chip);
if (ret)
return ret;
if (!ops->datbuf)
ret = nand_do_read_oob(chip, from, ops);
......@@ -4099,9 +4069,6 @@ static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
struct mtd_oob_ops ops;
int ret;
/* Grab the device */
panic_nand_get_device(chip, FL_WRITING);
nand_select_target(chip, chipnr);
/* Wait for the device to get ready */
......@@ -4132,7 +4099,9 @@ static int nand_write_oob(struct mtd_info *mtd, loff_t to,
ops->retlen = 0;
nand_get_device(chip, FL_WRITING);
ret = nand_get_device(chip);
if (ret)
return ret;
switch (ops->mode) {
case MTD_OPS_PLACE_OOB:
......@@ -4154,23 +4123,6 @@ static int nand_write_oob(struct mtd_info *mtd, loff_t to,
return ret;
}
/**
* single_erase - [GENERIC] NAND standard block erase command function
* @chip: NAND chip object
* @page: the page address of the block which will be erased
*
* Standard erase command for NAND chips. Returns NAND status.
*/
static int single_erase(struct nand_chip *chip, int page)
{
unsigned int eraseblock;
/* Send commands to erase a block */
eraseblock = page >> (chip->phys_erase_shift - chip->page_shift);
return nand_erase_op(chip, eraseblock);
}
/**
* nand_erase - [MTD Interface] erase block(s)
* @mtd: MTD device structure
......@@ -4194,7 +4146,7 @@ static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr,
int allowbbt)
{
int page, status, pages_per_block, ret, chipnr;
int page, pages_per_block, ret, chipnr;
loff_t len;
pr_debug("%s: start = 0x%012llx, len = %llu\n",
......@@ -4205,7 +4157,9 @@ int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr,
return -EINVAL;
/* Grab the lock and see if the device is available */
nand_get_device(chip, FL_ERASING);
ret = nand_get_device(chip);
if (ret)
return ret;
/* Shift to get first page */
page = (int)(instr->addr >> chip->page_shift);
......@@ -4246,17 +4200,11 @@ int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr,
(page + pages_per_block))
chip->pagebuf = -1;
if (chip->legacy.erase)
status = chip->legacy.erase(chip,
page & chip->pagemask);
else
status = single_erase(chip, page & chip->pagemask);
/* See if block erase succeeded */
if (status) {
ret = nand_erase_op(chip, (page & chip->pagemask) >>
(chip->phys_erase_shift - chip->page_shift));
if (ret) {
pr_debug("%s: failed erase, page 0x%08x\n",
__func__, page);
ret = -EIO;
instr->fail_addr =
((loff_t)page << chip->page_shift);
goto erase_exit;
......@@ -4298,7 +4246,7 @@ static void nand_sync(struct mtd_info *mtd)
pr_debug("%s: called\n", __func__);
/* Grab the lock and see if the device is available */
nand_get_device(chip, FL_SYNCING);
WARN_ON(nand_get_device(chip));
/* Release it and go back */
nand_release_device(chip);
}
......@@ -4315,7 +4263,10 @@ static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
int ret;
/* Select the NAND device */
nand_get_device(chip, FL_READING);
ret = nand_get_device(chip);
if (ret)
return ret;
nand_select_target(chip, chipnr);
ret = nand_block_checkbad(chip, offs, 0);
......@@ -4388,7 +4339,13 @@ static int nand_max_bad_blocks(struct mtd_info *mtd, loff_t ofs, size_t len)
*/
static int nand_suspend(struct mtd_info *mtd)
{
return nand_get_device(mtd_to_nand(mtd), FL_PM_SUSPENDED);
struct nand_chip *chip = mtd_to_nand(mtd);
mutex_lock(&chip->lock);
chip->suspended = 1;
mutex_unlock(&chip->lock);
return 0;
}
/**
......@@ -4399,11 +4356,13 @@ static void nand_resume(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd_to_nand(mtd);
if (chip->state == FL_PM_SUSPENDED)
nand_release_device(chip);
mutex_lock(&chip->lock);
if (chip->suspended)
chip->suspended = 0;
else
pr_err("%s called for a chip which is not in suspended state\n",
__func__);
mutex_unlock(&chip->lock);
}
/**
......@@ -4413,7 +4372,7 @@ static void nand_resume(struct mtd_info *mtd)
*/
static void nand_shutdown(struct mtd_info *mtd)
{
nand_get_device(mtd_to_nand(mtd), FL_PM_SUSPENDED);
nand_suspend(mtd);
}
/* Set default functions */
......@@ -5018,6 +4977,8 @@ static int nand_scan_ident(struct nand_chip *chip, unsigned int maxchips,
/* Assume all dies are deselected when we enter nand_scan_ident(). */
chip->cur_cs = -1;
mutex_init(&chip->lock);
/* Enforce the right timings for reset/detection */
onfi_fill_data_interface(chip, NAND_SDR_IFACE, 0);
......@@ -5060,11 +5021,15 @@ static int nand_scan_ident(struct nand_chip *chip, unsigned int maxchips,
u8 id[2];
/* See comment in nand_get_flash_type for reset */
nand_reset(chip, i);
ret = nand_reset(chip, i);
if (ret)
break;
nand_select_target(chip, i);
/* Send the command for reading device ID */
nand_readid_op(chip, 0, id, sizeof(id));
ret = nand_readid_op(chip, 0, id, sizeof(id));
if (ret)
break;
/* Read manufacturer and device IDs */
if (nand_maf_id != id[0] || nand_dev_id != id[1]) {
nand_deselect_target(chip);
......@@ -5555,6 +5520,7 @@ static int nand_scan_tail(struct nand_chip *chip)
}
if (!ecc->read_page)
ecc->read_page = nand_read_page_hwecc_oob_first;
/* fall through */
case NAND_ECC_HW:
/* Use standard hwecc read page function? */
......@@ -5574,6 +5540,7 @@ static int nand_scan_tail(struct nand_chip *chip)
ecc->read_subpage = nand_read_subpage;
if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
ecc->write_subpage = nand_write_subpage_hwecc;
/* fall through */
case NAND_ECC_HW_SYNDROME:
if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
......@@ -5611,6 +5578,7 @@ static int nand_scan_tail(struct nand_chip *chip)
ecc->size, mtd->writesize);
ecc->mode = NAND_ECC_SOFT;
ecc->algo = NAND_ECC_HAMMING;
/* fall through */
case NAND_ECC_SOFT:
ret = nand_set_ecc_soft_ops(chip);
......@@ -5717,9 +5685,6 @@ static int nand_scan_tail(struct nand_chip *chip)
}
chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
/* Initialize state */
chip->state = FL_READY;
/* Invalidate the pagebuffer reference */
chip->pagebuf = -1;
......
drivers/mtd/nand/raw/nand_legacy.c
View file @ 9220d7be
......@@ -331,6 +331,7 @@ static void nand_command(struct nand_chip *chip, unsigned int command,
*/
if (column == -1 && page_addr == -1)
return;
/* fall through */
default:
/*
......@@ -483,7 +484,7 @@ static void nand_command_lp(struct nand_chip *chip, unsigned int command,
chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
NAND_NCE | NAND_CTRL_CHANGE);
/* This applies to read commands */
/* fall through - This applies to read commands */
default:
/*
* If we don't have access to the busy pin, we apply the given
......
drivers/mtd/nand/raw/omap2.c
View file @ 9220d7be
......@@ -994,12 +994,9 @@ static int omap_wait(struct nand_chip *this)
{
struct omap_nand_info *info = mtd_to_omap(nand_to_mtd(this));
unsigned long timeo = jiffies;
int status, state = this->state;
int status;
if (state == FL_ERASING)
timeo += msecs_to_jiffies(400);
else
timeo += msecs_to_jiffies(20);
writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
while (time_before(jiffies, timeo)) {
......@@ -2173,11 +2170,8 @@ static const struct nand_controller_ops omap_nand_controller_ops = {
};
/* Shared among all NAND instances to synchronize access to the ECC Engine */
static struct nand_controller omap_gpmc_controller = {
.lock = __SPIN_LOCK_UNLOCKED(omap_gpmc_controller.lock),
.wq = __WAIT_QUEUE_HEAD_INITIALIZER(omap_gpmc_controller.wq),
.ops = &omap_nand_controller_ops,
};
static struct nand_controller omap_gpmc_controller;
static bool omap_gpmc_controller_initialized;
static int omap_nand_probe(struct platform_device *pdev)
{
......@@ -2227,6 +2221,12 @@ static int omap_nand_probe(struct platform_device *pdev)
info->phys_base = res->start;
if (!omap_gpmc_controller_initialized) {
omap_gpmc_controller.ops = &omap_nand_controller_ops;
nand_controller_init(&omap_gpmc_controller);
omap_gpmc_controller_initialized = true;
}
nand_chip->controller = &omap_gpmc_controller;
nand_chip->legacy.IO_ADDR_W = nand_chip->legacy.IO_ADDR_R;
......
drivers/mtd/nand/raw/r852.c
View file @ 9220d7be
......@@ -369,8 +369,7 @@ static int r852_wait(struct nand_chip *chip)
unsigned long timeout;
u8 status;
timeout = jiffies + (chip->state == FL_ERASING ?
msecs_to_jiffies(400) : msecs_to_jiffies(20));
timeout = jiffies + msecs_to_jiffies(400);
while (time_before(jiffies, timeout))
if (chip->legacy.dev_ready(chip))
......
drivers/mtd/nand/raw/stm32_fmc2_nand.c 0 → 100644
View file @ 9220d7be
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) STMicroelectronics 2018
* Author: Christophe Kerello <christophe.kerello@st.com>
*/
#include <linux/clk.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/mtd/rawnand.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
/* Bad block marker length */
#define FMC2_BBM_LEN 2
/* ECC step size */
#define FMC2_ECC_STEP_SIZE 512
/* BCHDSRx registers length */
#define FMC2_BCHDSRS_LEN 20
/* HECCR length */
#define FMC2_HECCR_LEN 4
/* Max requests done for a 8k nand page size */
#define FMC2_MAX_SG 16
/* Max chip enable */
#define FMC2_MAX_CE 2
/* Max ECC buffer length */
#define FMC2_MAX_ECC_BUF_LEN (FMC2_BCHDSRS_LEN * FMC2_MAX_SG)
/* Timings */
#define FMC2_THIZ 1
#define FMC2_TIO 8000
#define FMC2_TSYNC 3000
#define FMC2_PCR_TIMING_MASK 0xf
#define FMC2_PMEM_PATT_TIMING_MASK 0xff
/* FMC2 Controller Registers */
#define FMC2_BCR1 0x0
#define FMC2_PCR 0x80
#define FMC2_SR 0x84
#define FMC2_PMEM 0x88
#define FMC2_PATT 0x8c
#define FMC2_HECCR 0x94
#define FMC2_CSQCR 0x200
#define FMC2_CSQCFGR1 0x204
#define FMC2_CSQCFGR2 0x208
#define FMC2_CSQCFGR3 0x20c
#define FMC2_CSQAR1 0x210
#define FMC2_CSQAR2 0x214
#define FMC2_CSQIER 0x220
#define FMC2_CSQISR 0x224
#define FMC2_CSQICR 0x228
#define FMC2_CSQEMSR 0x230
#define FMC2_BCHIER 0x250
#define FMC2_BCHISR 0x254
#define FMC2_BCHICR 0x258
#define FMC2_BCHPBR1 0x260
#define FMC2_BCHPBR2 0x264
#define FMC2_BCHPBR3 0x268
#define FMC2_BCHPBR4 0x26c
#define FMC2_BCHDSR0 0x27c
#define FMC2_BCHDSR1 0x280
#define FMC2_BCHDSR2 0x284
#define FMC2_BCHDSR3 0x288
#define FMC2_BCHDSR4 0x28c
/* Register: FMC2_BCR1 */
#define FMC2_BCR1_FMC2EN BIT(31)
/* Register: FMC2_PCR */
#define FMC2_PCR_PWAITEN BIT(1)
#define FMC2_PCR_PBKEN BIT(2)
#define FMC2_PCR_PWID_MASK GENMASK(5, 4)
#define FMC2_PCR_PWID(x) (((x) & 0x3) << 4)
#define FMC2_PCR_PWID_BUSWIDTH_8 0
#define FMC2_PCR_PWID_BUSWIDTH_16 1
#define FMC2_PCR_ECCEN BIT(6)
#define FMC2_PCR_ECCALG BIT(8)
#define FMC2_PCR_TCLR_MASK GENMASK(12, 9)
#define FMC2_PCR_TCLR(x) (((x) & 0xf) << 9)
#define FMC2_PCR_TCLR_DEFAULT 0xf
#define FMC2_PCR_TAR_MASK GENMASK(16, 13)
#define FMC2_PCR_TAR(x) (((x) & 0xf) << 13)
#define FMC2_PCR_TAR_DEFAULT 0xf
#define FMC2_PCR_ECCSS_MASK GENMASK(19, 17)
#define FMC2_PCR_ECCSS(x) (((x) & 0x7) << 17)
#define FMC2_PCR_ECCSS_512 1
#define FMC2_PCR_ECCSS_2048 3
#define FMC2_PCR_BCHECC BIT(24)
#define FMC2_PCR_WEN BIT(25)
/* Register: FMC2_SR */
#define FMC2_SR_NWRF BIT(6)
/* Register: FMC2_PMEM */
#define FMC2_PMEM_MEMSET(x) (((x) & 0xff) << 0)
#define FMC2_PMEM_MEMWAIT(x) (((x) & 0xff) << 8)
#define FMC2_PMEM_MEMHOLD(x) (((x) & 0xff) << 16)
#define FMC2_PMEM_MEMHIZ(x) (((x) & 0xff) << 24)
#define FMC2_PMEM_DEFAULT 0x0a0a0a0a
/* Register: FMC2_PATT */
#define FMC2_PATT_ATTSET(x) (((x) & 0xff) << 0)
#define FMC2_PATT_ATTWAIT(x) (((x) & 0xff) << 8)
#define FMC2_PATT_ATTHOLD(x) (((x) & 0xff) << 16)
#define FMC2_PATT_ATTHIZ(x) (((x) & 0xff) << 24)
#define FMC2_PATT_DEFAULT 0x0a0a0a0a
/* Register: FMC2_CSQCR */
#define FMC2_CSQCR_CSQSTART BIT(0)
/* Register: FMC2_CSQCFGR1 */
#define FMC2_CSQCFGR1_CMD2EN BIT(1)
#define FMC2_CSQCFGR1_DMADEN BIT(2)
#define FMC2_CSQCFGR1_ACYNBR(x) (((x) & 0x7) << 4)
#define FMC2_CSQCFGR1_CMD1(x) (((x) & 0xff) << 8)
#define FMC2_CSQCFGR1_CMD2(x) (((x) & 0xff) << 16)
#define FMC2_CSQCFGR1_CMD1T BIT(24)
#define FMC2_CSQCFGR1_CMD2T BIT(25)
/* Register: FMC2_CSQCFGR2 */
#define FMC2_CSQCFGR2_SQSDTEN BIT(0)
#define FMC2_CSQCFGR2_RCMD2EN BIT(1)
#define FMC2_CSQCFGR2_DMASEN BIT(2)
#define FMC2_CSQCFGR2_RCMD1(x) (((x) & 0xff) << 8)
#define FMC2_CSQCFGR2_RCMD2(x) (((x) & 0xff) << 16)
#define FMC2_CSQCFGR2_RCMD1T BIT(24)
#define FMC2_CSQCFGR2_RCMD2T BIT(25)
/* Register: FMC2_CSQCFGR3 */
#define FMC2_CSQCFGR3_SNBR(x) (((x) & 0x1f) << 8)
#define FMC2_CSQCFGR3_AC1T BIT(16)
#define FMC2_CSQCFGR3_AC2T BIT(17)
#define FMC2_CSQCFGR3_AC3T BIT(18)
#define FMC2_CSQCFGR3_AC4T BIT(19)
#define FMC2_CSQCFGR3_AC5T BIT(20)
#define FMC2_CSQCFGR3_SDT BIT(21)
#define FMC2_CSQCFGR3_RAC1T BIT(22)
#define FMC2_CSQCFGR3_RAC2T BIT(23)
/* Register: FMC2_CSQCAR1 */
#define FMC2_CSQCAR1_ADDC1(x) (((x) & 0xff) << 0)
#define FMC2_CSQCAR1_ADDC2(x) (((x) & 0xff) << 8)
#define FMC2_CSQCAR1_ADDC3(x) (((x) & 0xff) << 16)
#define FMC2_CSQCAR1_ADDC4(x) (((x) & 0xff) << 24)
/* Register: FMC2_CSQCAR2 */
#define FMC2_CSQCAR2_ADDC5(x) (((x) & 0xff) << 0)
#define FMC2_CSQCAR2_NANDCEN(x) (((x) & 0x3) << 10)
#define FMC2_CSQCAR2_SAO(x) (((x) & 0xffff) << 16)
/* Register: FMC2_CSQIER */
#define FMC2_CSQIER_TCIE BIT(0)
/* Register: FMC2_CSQICR */
#define FMC2_CSQICR_CLEAR_IRQ GENMASK(4, 0)
/* Register: FMC2_CSQEMSR */
#define FMC2_CSQEMSR_SEM GENMASK(15, 0)
/* Register: FMC2_BCHIER */
#define FMC2_BCHIER_DERIE BIT(1)
#define FMC2_BCHIER_EPBRIE BIT(4)
/* Register: FMC2_BCHICR */
#define FMC2_BCHICR_CLEAR_IRQ GENMASK(4, 0)
/* Register: FMC2_BCHDSR0 */
#define FMC2_BCHDSR0_DUE BIT(0)
#define FMC2_BCHDSR0_DEF BIT(1)
#define FMC2_BCHDSR0_DEN_MASK GENMASK(7, 4)
#define FMC2_BCHDSR0_DEN_SHIFT 4
/* Register: FMC2_BCHDSR1 */
#define FMC2_BCHDSR1_EBP1_MASK GENMASK(12, 0)
#define FMC2_BCHDSR1_EBP2_MASK GENMASK(28, 16)
#define FMC2_BCHDSR1_EBP2_SHIFT 16
/* Register: FMC2_BCHDSR2 */
#define FMC2_BCHDSR2_EBP3_MASK GENMASK(12, 0)
#define FMC2_BCHDSR2_EBP4_MASK GENMASK(28, 16)
#define FMC2_BCHDSR2_EBP4_SHIFT 16
/* Register: FMC2_BCHDSR3 */
#define FMC2_BCHDSR3_EBP5_MASK GENMASK(12, 0)
#define FMC2_BCHDSR3_EBP6_MASK GENMASK(28, 16)
#define FMC2_BCHDSR3_EBP6_SHIFT 16
/* Register: FMC2_BCHDSR4 */
#define FMC2_BCHDSR4_EBP7_MASK GENMASK(12, 0)
#define FMC2_BCHDSR4_EBP8_MASK GENMASK(28, 16)
#define FMC2_BCHDSR4_EBP8_SHIFT 16
enum stm32_fmc2_ecc {
FMC2_ECC_HAM = 1,
FMC2_ECC_BCH4 = 4,
FMC2_ECC_BCH8 = 8
};
enum stm32_fmc2_irq_state {
FMC2_IRQ_UNKNOWN = 0,
FMC2_IRQ_BCH,
FMC2_IRQ_SEQ
};
struct stm32_fmc2_timings {
u8 tclr;
u8 tar;
u8 thiz;
u8 twait;
u8 thold_mem;
u8 tset_mem;
u8 thold_att;
u8 tset_att;
};
struct stm32_fmc2_nand {
struct nand_chip chip;
struct stm32_fmc2_timings timings;
int ncs;
int cs_used[FMC2_MAX_CE];
};
static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip)
{
return container_of(chip, struct stm32_fmc2_nand, chip);
}
struct stm32_fmc2_nfc {
struct nand_controller base;
struct stm32_fmc2_nand nand;
struct device *dev;
void __iomem *io_base;
void __iomem *data_base[FMC2_MAX_CE];
void __iomem *cmd_base[FMC2_MAX_CE];
void __iomem *addr_base[FMC2_MAX_CE];
phys_addr_t io_phys_addr;
phys_addr_t data_phys_addr[FMC2_MAX_CE];
struct clk *clk;
u8 irq_state;
struct dma_chan *dma_tx_ch;
struct dma_chan *dma_rx_ch;
struct dma_chan *dma_ecc_ch;
struct sg_table dma_data_sg;
struct sg_table dma_ecc_sg;
u8 *ecc_buf;
int dma_ecc_len;
struct completion complete;
struct completion dma_data_complete;
struct completion dma_ecc_complete;
u8 cs_assigned;
int cs_sel;
};
static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_controller *base)
{
return container_of(base, struct stm32_fmc2_nfc, base);
}
/* Timings configuration */
static void stm32_fmc2_timings_init(struct nand_chip *chip)
{
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
struct stm32_fmc2_timings *timings = &nand->timings;
u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
u32 pmem, patt;
/* Set tclr/tar timings */
pcr &= ~FMC2_PCR_TCLR_MASK;
pcr |= FMC2_PCR_TCLR(timings->tclr);
pcr &= ~FMC2_PCR_TAR_MASK;
pcr |= FMC2_PCR_TAR(timings->tar);
/* Set tset/twait/thold/thiz timings in common bank */
pmem = FMC2_PMEM_MEMSET(timings->tset_mem);
pmem |= FMC2_PMEM_MEMWAIT(timings->twait);
pmem |= FMC2_PMEM_MEMHOLD(timings->thold_mem);
pmem |= FMC2_PMEM_MEMHIZ(timings->thiz);
/* Set tset/twait/thold/thiz timings in attribut bank */
patt = FMC2_PATT_ATTSET(timings->tset_att);
patt |= FMC2_PATT_ATTWAIT(timings->twait);
patt |= FMC2_PATT_ATTHOLD(timings->thold_att);
patt |= FMC2_PATT_ATTHIZ(timings->thiz);
writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
writel_relaxed(pmem, fmc2->io_base + FMC2_PMEM);
writel_relaxed(patt, fmc2->io_base + FMC2_PATT);
}
/* Controller configuration */
static void stm32_fmc2_setup(struct nand_chip *chip)
{
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
/* Configure ECC algorithm (default configuration is Hamming) */
pcr &= ~FMC2_PCR_ECCALG;
pcr &= ~FMC2_PCR_BCHECC;
if (chip->ecc.strength == FMC2_ECC_BCH8) {
pcr |= FMC2_PCR_ECCALG;
pcr |= FMC2_PCR_BCHECC;
} else if (chip->ecc.strength == FMC2_ECC_BCH4) {
pcr |= FMC2_PCR_ECCALG;
}
/* Set buswidth */
pcr &= ~FMC2_PCR_PWID_MASK;
if (chip->options & NAND_BUSWIDTH_16)
pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_BUSWIDTH_16);
/* Set ECC sector size */
pcr &= ~FMC2_PCR_ECCSS_MASK;
pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_512);
writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
}
/* Select target */
static int stm32_fmc2_select_chip(struct nand_chip *chip, int chipnr)
{
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
struct dma_slave_config dma_cfg;
int ret;
if (nand->cs_used[chipnr] == fmc2->cs_sel)
return 0;
fmc2->cs_sel = nand->cs_used[chipnr];
/* FMC2 setup routine */
stm32_fmc2_setup(chip);
/* Apply timings */
stm32_fmc2_timings_init(chip);
if (fmc2->dma_tx_ch && fmc2->dma_rx_ch) {
memset(&dma_cfg, 0, sizeof(dma_cfg));
dma_cfg.src_addr = fmc2->data_phys_addr[fmc2->cs_sel];
dma_cfg.dst_addr = fmc2->data_phys_addr[fmc2->cs_sel];
dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dma_cfg.src_maxburst = 32;
dma_cfg.dst_maxburst = 32;
ret = dmaengine_slave_config(fmc2->dma_tx_ch, &dma_cfg);
if (ret) {
dev_err(fmc2->dev, "tx DMA engine slave config failed\n");
return ret;
}
ret = dmaengine_slave_config(fmc2->dma_rx_ch, &dma_cfg);
if (ret) {
dev_err(fmc2->dev, "rx DMA engine slave config failed\n");
return ret;
}
}
if (fmc2->dma_ecc_ch) {
/*
* Hamming: we read HECCR register
* BCH4/BCH8: we read BCHDSRSx registers
*/
memset(&dma_cfg, 0, sizeof(dma_cfg));
dma_cfg.src_addr = fmc2->io_phys_addr;
dma_cfg.src_addr += chip->ecc.strength == FMC2_ECC_HAM ?
FMC2_HECCR : FMC2_BCHDSR0;
dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
ret = dmaengine_slave_config(fmc2->dma_ecc_ch, &dma_cfg);
if (ret) {
dev_err(fmc2->dev, "ECC DMA engine slave config failed\n");
return ret;
}
/* Calculate ECC length needed for one sector */
fmc2->dma_ecc_len = chip->ecc.strength == FMC2_ECC_HAM ?
FMC2_HECCR_LEN : FMC2_BCHDSRS_LEN;
}
return 0;
}
/* Set bus width to 16-bit or 8-bit */
static void stm32_fmc2_set_buswidth_16(struct stm32_fmc2_nfc *fmc2, bool set)
{
u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
pcr &= ~FMC2_PCR_PWID_MASK;
if (set)
pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_BUSWIDTH_16);
writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
}
/* Enable/disable ECC */
static void stm32_fmc2_set_ecc(struct stm32_fmc2_nfc *fmc2, bool enable)
{
u32 pcr = readl(fmc2->io_base + FMC2_PCR);
pcr &= ~FMC2_PCR_ECCEN;
if (enable)
pcr |= FMC2_PCR_ECCEN;
writel(pcr, fmc2->io_base + FMC2_PCR);
}
/* Enable irq sources in case of the sequencer is used */
static inline void stm32_fmc2_enable_seq_irq(struct stm32_fmc2_nfc *fmc2)
{
u32 csqier = readl_relaxed(fmc2->io_base + FMC2_CSQIER);
csqier |= FMC2_CSQIER_TCIE;
fmc2->irq_state = FMC2_IRQ_SEQ;
writel_relaxed(csqier, fmc2->io_base + FMC2_CSQIER);
}
/* Disable irq sources in case of the sequencer is used */
static inline void stm32_fmc2_disable_seq_irq(struct stm32_fmc2_nfc *fmc2)
{
u32 csqier = readl_relaxed(fmc2->io_base + FMC2_CSQIER);
csqier &= ~FMC2_CSQIER_TCIE;
writel_relaxed(csqier, fmc2->io_base + FMC2_CSQIER);
fmc2->irq_state = FMC2_IRQ_UNKNOWN;
}
/* Clear irq sources in case of the sequencer is used */
static inline void stm32_fmc2_clear_seq_irq(struct stm32_fmc2_nfc *fmc2)
{
writel_relaxed(FMC2_CSQICR_CLEAR_IRQ, fmc2->io_base + FMC2_CSQICR);
}
/* Enable irq sources in case of bch is used */
static inline void stm32_fmc2_enable_bch_irq(struct stm32_fmc2_nfc *fmc2,
int mode)
{
u32 bchier = readl_relaxed(fmc2->io_base + FMC2_BCHIER);
if (mode == NAND_ECC_WRITE)
bchier |= FMC2_BCHIER_EPBRIE;
else
bchier |= FMC2_BCHIER_DERIE;
fmc2->irq_state = FMC2_IRQ_BCH;
writel_relaxed(bchier, fmc2->io_base + FMC2_BCHIER);
}
/* Disable irq sources in case of bch is used */
static inline void stm32_fmc2_disable_bch_irq(struct stm32_fmc2_nfc *fmc2)
{
u32 bchier = readl_relaxed(fmc2->io_base + FMC2_BCHIER);
bchier &= ~FMC2_BCHIER_DERIE;
bchier &= ~FMC2_BCHIER_EPBRIE;
writel_relaxed(bchier, fmc2->io_base + FMC2_BCHIER);
fmc2->irq_state = FMC2_IRQ_UNKNOWN;
}
/* Clear irq sources in case of bch is used */
static inline void stm32_fmc2_clear_bch_irq(struct stm32_fmc2_nfc *fmc2)
{
writel_relaxed(FMC2_BCHICR_CLEAR_IRQ, fmc2->io_base + FMC2_BCHICR);
}
/*
* Enable ECC logic and reset syndrome/parity bits previously calculated
* Syndrome/parity bits is cleared by setting the ECCEN bit to 0
*/
static void stm32_fmc2_hwctl(struct nand_chip *chip, int mode)
{
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
stm32_fmc2_set_ecc(fmc2, false);
if (chip->ecc.strength != FMC2_ECC_HAM) {
u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
if (mode == NAND_ECC_WRITE)
pcr |= FMC2_PCR_WEN;
else
pcr &= ~FMC2_PCR_WEN;
writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
reinit_completion(&fmc2->complete);
stm32_fmc2_clear_bch_irq(fmc2);
stm32_fmc2_enable_bch_irq(fmc2, mode);
}
stm32_fmc2_set_ecc(fmc2, true);
}
/*
* ECC Hamming calculation
* ECC is 3 bytes for 512 bytes of data (supports error correction up to
* max of 1-bit)
*/
static inline void stm32_fmc2_ham_set_ecc(const u32 ecc_sta, u8 *ecc)
{
ecc[0] = ecc_sta;
ecc[1] = ecc_sta >> 8;
ecc[2] = ecc_sta >> 16;
}
static int stm32_fmc2_ham_calculate(struct nand_chip *chip, const u8 *data,
u8 *ecc)
{
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
u32 sr, heccr;
int ret;
ret = readl_relaxed_poll_timeout(fmc2->io_base + FMC2_SR,
sr, sr & FMC2_SR_NWRF, 10, 1000);
if (ret) {
dev_err(fmc2->dev, "ham timeout\n");
return ret;
}
heccr = readl_relaxed(fmc2->io_base + FMC2_HECCR);
stm32_fmc2_ham_set_ecc(heccr, ecc);
/* Disable ECC */
stm32_fmc2_set_ecc(fmc2, false);
return 0;
}
static int stm32_fmc2_ham_correct(struct nand_chip *chip, u8 *dat,
u8 *read_ecc, u8 *calc_ecc)
{
u8 bit_position = 0, b0, b1, b2;
u32 byte_addr = 0, b;
u32 i, shifting = 1;
/* Indicate which bit and byte is faulty (if any) */
b0 = read_ecc[0] ^ calc_ecc[0];
b1 = read_ecc[1] ^ calc_ecc[1];
b2 = read_ecc[2] ^ calc_ecc[2];
b = b0 | (b1 << 8) | (b2 << 16);
/* No errors */
if (likely(!b))
return 0;
/* Calculate bit position */
for (i = 0; i < 3; i++) {
switch (b % 4) {
case 2:
bit_position += shifting;
case 1:
break;
default:
return -EBADMSG;
}
shifting <<= 1;
b >>= 2;
}
/* Calculate byte position */
shifting = 1;
for (i = 0; i < 9; i++) {
switch (b % 4) {
case 2:
byte_addr += shifting;
case 1:
break;
default:
return -EBADMSG;
}
shifting <<= 1;
b >>= 2;
}
/* Flip the bit */
dat[byte_addr] ^= (1 << bit_position);
return 1;
}
/*
* ECC BCH calculation and correction
* ECC is 7/13 bytes for 512 bytes of data (supports error correction up to
* max of 4-bit/8-bit)
*/
static int stm32_fmc2_bch_calculate(struct nand_chip *chip, const u8 *data,
u8 *ecc)
{
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
u32 bchpbr;
/* Wait until the BCH code is ready */
if (!wait_for_completion_timeout(&fmc2->complete,
msecs_to_jiffies(1000))) {
dev_err(fmc2->dev, "bch timeout\n");
stm32_fmc2_disable_bch_irq(fmc2);
return -ETIMEDOUT;
}
/* Read parity bits */
bchpbr = readl_relaxed(fmc2->io_base + FMC2_BCHPBR1);
ecc[0] = bchpbr;
ecc[1] = bchpbr >> 8;
ecc[2] = bchpbr >> 16;
ecc[3] = bchpbr >> 24;
bchpbr = readl_relaxed(fmc2->io_base + FMC2_BCHPBR2);
ecc[4] = bchpbr;
ecc[5] = bchpbr >> 8;
ecc[6] = bchpbr >> 16;
if (chip->ecc.strength == FMC2_ECC_BCH8) {
ecc[7] = bchpbr >> 24;
bchpbr = readl_relaxed(fmc2->io_base + FMC2_BCHPBR3);
ecc[8] = bchpbr;
ecc[9] = bchpbr >> 8;
ecc[10] = bchpbr >> 16;
ecc[11] = bchpbr >> 24;
bchpbr = readl_relaxed(fmc2->io_base + FMC2_BCHPBR4);
ecc[12] = bchpbr;
}
/* Disable ECC */
stm32_fmc2_set_ecc(fmc2, false);
return 0;
}
/* BCH algorithm correction */
static int stm32_fmc2_bch_decode(int eccsize, u8 *dat, u32 *ecc_sta)
{
u32 bchdsr0 = ecc_sta[0];
u32 bchdsr1 = ecc_sta[1];
u32 bchdsr2 = ecc_sta[2];
u32 bchdsr3 = ecc_sta[3];
u32 bchdsr4 = ecc_sta[4];
u16 pos[8];
int i, den;
unsigned int nb_errs = 0;
/* No errors found */
if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF)))
return 0;
/* Too many errors detected */
if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE))
return -EBADMSG;
pos[0] = bchdsr1 & FMC2_BCHDSR1_EBP1_MASK;
pos[1] = (bchdsr1 & FMC2_BCHDSR1_EBP2_MASK) >> FMC2_BCHDSR1_EBP2_SHIFT;
pos[2] = bchdsr2 & FMC2_BCHDSR2_EBP3_MASK;
pos[3] = (bchdsr2 & FMC2_BCHDSR2_EBP4_MASK) >> FMC2_BCHDSR2_EBP4_SHIFT;
pos[4] = bchdsr3 & FMC2_BCHDSR3_EBP5_MASK;
pos[5] = (bchdsr3 & FMC2_BCHDSR3_EBP6_MASK) >> FMC2_BCHDSR3_EBP6_SHIFT;
pos[6] = bchdsr4 & FMC2_BCHDSR4_EBP7_MASK;
pos[7] = (bchdsr4 & FMC2_BCHDSR4_EBP8_MASK) >> FMC2_BCHDSR4_EBP8_SHIFT;
den = (bchdsr0 & FMC2_BCHDSR0_DEN_MASK) >> FMC2_BCHDSR0_DEN_SHIFT;
for (i = 0; i < den; i++) {
if (pos[i] < eccsize * 8) {
change_bit(pos[i], (unsigned long *)dat);
nb_errs++;
}
}
return nb_errs;
}
static int stm32_fmc2_bch_correct(struct nand_chip *chip, u8 *dat,
u8 *read_ecc, u8 *calc_ecc)
{
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
u32 ecc_sta[5];
/* Wait until the decoding error is ready */
if (!wait_for_completion_timeout(&fmc2->complete,
msecs_to_jiffies(1000))) {
dev_err(fmc2->dev, "bch timeout\n");
stm32_fmc2_disable_bch_irq(fmc2);
return -ETIMEDOUT;
}
ecc_sta[0] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR0);
ecc_sta[1] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR1);
ecc_sta[2] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR2);
ecc_sta[3] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR3);
ecc_sta[4] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR4);
/* Disable ECC */
stm32_fmc2_set_ecc(fmc2, false);
return stm32_fmc2_bch_decode(chip->ecc.size, dat, ecc_sta);
}
static int stm32_fmc2_read_page(struct nand_chip *chip, u8 *buf,
int oob_required, int page)
{
struct mtd_info *mtd = nand_to_mtd(chip);
int ret, i, s, stat, eccsize = chip->ecc.size;
int eccbytes = chip->ecc.bytes;
int eccsteps = chip->ecc.steps;
int eccstrength = chip->ecc.strength;
u8 *p = buf;
u8 *ecc_calc = chip->ecc.calc_buf;
u8 *ecc_code = chip->ecc.code_buf;
unsigned int max_bitflips = 0;
ret = nand_read_page_op(chip, page, 0, NULL, 0);
if (ret)
return ret;
for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps;
s++, i += eccbytes, p += eccsize) {
chip->ecc.hwctl(chip, NAND_ECC_READ);
/* Read the nand page sector (512 bytes) */
ret = nand_change_read_column_op(chip, s * eccsize, p,
eccsize, false);
if (ret)
return ret;
/* Read the corresponding ECC bytes */
ret = nand_change_read_column_op(chip, i, ecc_code,
eccbytes, false);
if (ret)
return ret;
/* Correct the data */
stat = chip->ecc.correct(chip, p, ecc_code, ecc_calc);
if (stat == -EBADMSG)
/* Check for empty pages with bitflips */
stat = nand_check_erased_ecc_chunk(p, eccsize,
ecc_code, eccbytes,
NULL, 0,
eccstrength);
if (stat < 0) {
mtd->ecc_stats.failed++;
} else {
mtd->ecc_stats.corrected += stat;
max_bitflips = max_t(unsigned int, max_bitflips, stat);
}
}
/* Read oob */
if (oob_required) {
ret = nand_change_read_column_op(chip, mtd->writesize,
chip->oob_poi, mtd->oobsize,
false);
if (ret)
return ret;
}
return max_bitflips;
}
/* Sequencer read/write configuration */
static void stm32_fmc2_rw_page_init(struct nand_chip *chip, int page,
int raw, bool write_data)
{
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
struct mtd_info *mtd = nand_to_mtd(chip);
u32 csqcfgr1, csqcfgr2, csqcfgr3;
u32 csqar1, csqar2;
u32 ecc_offset = mtd->writesize + FMC2_BBM_LEN;
u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
if (write_data)
pcr |= FMC2_PCR_WEN;
else
pcr &= ~FMC2_PCR_WEN;
writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
/*
* - Set Program Page/Page Read command
* - Enable DMA request data
* - Set timings
*/
csqcfgr1 = FMC2_CSQCFGR1_DMADEN | FMC2_CSQCFGR1_CMD1T;
if (write_data)
csqcfgr1 |= FMC2_CSQCFGR1_CMD1(NAND_CMD_SEQIN);
else
csqcfgr1 |= FMC2_CSQCFGR1_CMD1(NAND_CMD_READ0) |
FMC2_CSQCFGR1_CMD2EN |
FMC2_CSQCFGR1_CMD2(NAND_CMD_READSTART) |
FMC2_CSQCFGR1_CMD2T;
/*
* - Set Random Data Input/Random Data Read command
* - Enable the sequencer to access the Spare data area
* - Enable DMA request status decoding for read
* - Set timings
*/
if (write_data)
csqcfgr2 = FMC2_CSQCFGR2_RCMD1(NAND_CMD_RNDIN);
else
csqcfgr2 = FMC2_CSQCFGR2_RCMD1(NAND_CMD_RNDOUT) |
FMC2_CSQCFGR2_RCMD2EN |
FMC2_CSQCFGR2_RCMD2(NAND_CMD_RNDOUTSTART) |
FMC2_CSQCFGR2_RCMD1T |
FMC2_CSQCFGR2_RCMD2T;
if (!raw) {
csqcfgr2 |= write_data ? 0 : FMC2_CSQCFGR2_DMASEN;
csqcfgr2 |= FMC2_CSQCFGR2_SQSDTEN;
}
/*
* - Set the number of sectors to be written
* - Set timings
*/
csqcfgr3 = FMC2_CSQCFGR3_SNBR(chip->ecc.steps - 1);
if (write_data) {
csqcfgr3 |= FMC2_CSQCFGR3_RAC2T;
if (chip->options & NAND_ROW_ADDR_3)
csqcfgr3 |= FMC2_CSQCFGR3_AC5T;
else
csqcfgr3 |= FMC2_CSQCFGR3_AC4T;
}
/*
* Set the fourth first address cycles
* Byte 1 and byte 2 => column, we start at 0x0
* Byte 3 and byte 4 => page
*/
csqar1 = FMC2_CSQCAR1_ADDC3(page);
csqar1 |= FMC2_CSQCAR1_ADDC4(page >> 8);
/*
* - Set chip enable number
* - Set ECC byte offset in the spare area
* - Calculate the number of address cycles to be issued
* - Set byte 5 of address cycle if needed
*/
csqar2 = FMC2_CSQCAR2_NANDCEN(fmc2->cs_sel);
if (chip->options & NAND_BUSWIDTH_16)
csqar2 |= FMC2_CSQCAR2_SAO(ecc_offset >> 1);
else
csqar2 |= FMC2_CSQCAR2_SAO(ecc_offset);
if (chip->options & NAND_ROW_ADDR_3) {
csqcfgr1 |= FMC2_CSQCFGR1_ACYNBR(5);
csqar2 |= FMC2_CSQCAR2_ADDC5(page >> 16);
} else {
csqcfgr1 |= FMC2_CSQCFGR1_ACYNBR(4);
}
writel_relaxed(csqcfgr1, fmc2->io_base + FMC2_CSQCFGR1);
writel_relaxed(csqcfgr2, fmc2->io_base + FMC2_CSQCFGR2);
writel_relaxed(csqcfgr3, fmc2->io_base + FMC2_CSQCFGR3);
writel_relaxed(csqar1, fmc2->io_base + FMC2_CSQAR1);
writel_relaxed(csqar2, fmc2->io_base + FMC2_CSQAR2);
}
static void stm32_fmc2_dma_callback(void *arg)
{
complete((struct completion *)arg);
}
/* Read/write data from/to a page */
static int stm32_fmc2_xfer(struct nand_chip *chip, const u8 *buf,
int raw, bool write_data)
{
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
struct dma_async_tx_descriptor *desc_data, *desc_ecc;
struct scatterlist *sg;
struct dma_chan *dma_ch = fmc2->dma_rx_ch;
enum dma_data_direction dma_data_dir = DMA_FROM_DEVICE;
enum dma_transfer_direction dma_transfer_dir = DMA_DEV_TO_MEM;
u32 csqcr = readl_relaxed(fmc2->io_base + FMC2_CSQCR);
int eccsteps = chip->ecc.steps;
int eccsize = chip->ecc.size;
const u8 *p = buf;
int s, ret;
/* Configure DMA data */
if (write_data) {
dma_data_dir = DMA_TO_DEVICE;
dma_transfer_dir = DMA_MEM_TO_DEV;
dma_ch = fmc2->dma_tx_ch;
}
for_each_sg(fmc2->dma_data_sg.sgl, sg, eccsteps, s) {
sg_set_buf(sg, p, eccsize);
p += eccsize;
}
ret = dma_map_sg(fmc2->dev, fmc2->dma_data_sg.sgl,
eccsteps, dma_data_dir);
if (ret < 0)
return ret;
desc_data = dmaengine_prep_slave_sg(dma_ch, fmc2->dma_data_sg.sgl,
eccsteps, dma_transfer_dir,
DMA_PREP_INTERRUPT);
if (!desc_data) {
ret = -ENOMEM;
goto err_unmap_data;
}
reinit_completion(&fmc2->dma_data_complete);
reinit_completion(&fmc2->complete);
desc_data->callback = stm32_fmc2_dma_callback;
desc_data->callback_param = &fmc2->dma_data_complete;
ret = dma_submit_error(dmaengine_submit(desc_data));
if (ret)
goto err_unmap_data;
dma_async_issue_pending(dma_ch);
if (!write_data && !raw) {
/* Configure DMA ECC status */
p = fmc2->ecc_buf;
for_each_sg(fmc2->dma_ecc_sg.sgl, sg, eccsteps, s) {
sg_set_buf(sg, p, fmc2->dma_ecc_len);
p += fmc2->dma_ecc_len;
}
ret = dma_map_sg(fmc2->dev, fmc2->dma_ecc_sg.sgl,
eccsteps, dma_data_dir);
if (ret < 0)
goto err_unmap_data;
desc_ecc = dmaengine_prep_slave_sg(fmc2->dma_ecc_ch,
fmc2->dma_ecc_sg.sgl,
eccsteps, dma_transfer_dir,
DMA_PREP_INTERRUPT);
if (!desc_ecc) {
ret = -ENOMEM;
goto err_unmap_ecc;
}
reinit_completion(&fmc2->dma_ecc_complete);
desc_ecc->callback = stm32_fmc2_dma_callback;
desc_ecc->callback_param = &fmc2->dma_ecc_complete;
ret = dma_submit_error(dmaengine_submit(desc_ecc));
if (ret)
goto err_unmap_ecc;
dma_async_issue_pending(fmc2->dma_ecc_ch);
}
stm32_fmc2_clear_seq_irq(fmc2);
stm32_fmc2_enable_seq_irq(fmc2);
/* Start the transfer */
csqcr |= FMC2_CSQCR_CSQSTART;
writel_relaxed(csqcr, fmc2->io_base + FMC2_CSQCR);
/* Wait end of sequencer transfer */
if (!wait_for_completion_timeout(&fmc2->complete,
msecs_to_jiffies(1000))) {
dev_err(fmc2->dev, "seq timeout\n");
stm32_fmc2_disable_seq_irq(fmc2);
dmaengine_terminate_all(dma_ch);
if (!write_data && !raw)
dmaengine_terminate_all(fmc2->dma_ecc_ch);
ret = -ETIMEDOUT;
goto err_unmap_ecc;
}
/* Wait DMA data transfer completion */
if (!wait_for_completion_timeout(&fmc2->dma_data_complete,
msecs_to_jiffies(100))) {
dev_err(fmc2->dev, "data DMA timeout\n");
dmaengine_terminate_all(dma_ch);
ret = -ETIMEDOUT;
}
/* Wait DMA ECC transfer completion */
if (!write_data && !raw) {
if (!wait_for_completion_timeout(&fmc2->dma_ecc_complete,
msecs_to_jiffies(100))) {
dev_err(fmc2->dev, "ECC DMA timeout\n");
dmaengine_terminate_all(fmc2->dma_ecc_ch);
ret = -ETIMEDOUT;
}
}
err_unmap_ecc:
if (!write_data && !raw)
dma_unmap_sg(fmc2->dev, fmc2->dma_ecc_sg.sgl,
eccsteps, dma_data_dir);
err_unmap_data:
dma_unmap_sg(fmc2->dev, fmc2->dma_data_sg.sgl, eccsteps, dma_data_dir);
return ret;
}
static int stm32_fmc2_sequencer_write(struct nand_chip *chip,
const u8 *buf, int oob_required,
int page, int raw)
{
struct mtd_info *mtd = nand_to_mtd(chip);
int ret;
/* Configure the sequencer */
stm32_fmc2_rw_page_init(chip, page, raw, true);
/* Write the page */
ret = stm32_fmc2_xfer(chip, buf, raw, true);
if (ret)
return ret;
/* Write oob */
if (oob_required) {
ret = nand_change_write_column_op(chip, mtd->writesize,
chip->oob_poi, mtd->oobsize,
false);
if (ret)
return ret;
}
return nand_prog_page_end_op(chip);
}
static int stm32_fmc2_sequencer_write_page(struct nand_chip *chip,
const u8 *buf,
int oob_required,
int page)
{
int ret;
/* Select the target */
ret = stm32_fmc2_select_chip(chip, chip->cur_cs);
if (ret)
return ret;
return stm32_fmc2_sequencer_write(chip, buf, oob_required, page, false);
}
static int stm32_fmc2_sequencer_write_page_raw(struct nand_chip *chip,
const u8 *buf,
int oob_required,
int page)
{
int ret;
/* Select the target */
ret = stm32_fmc2_select_chip(chip, chip->cur_cs);
if (ret)
return ret;
return stm32_fmc2_sequencer_write(chip, buf, oob_required, page, true);
}
/* Get a status indicating which sectors have errors */
static inline u16 stm32_fmc2_get_mapping_status(struct stm32_fmc2_nfc *fmc2)
{
u32 csqemsr = readl_relaxed(fmc2->io_base + FMC2_CSQEMSR);
return csqemsr & FMC2_CSQEMSR_SEM;
}
static int stm32_fmc2_sequencer_correct(struct nand_chip *chip, u8 *dat,
u8 *read_ecc, u8 *calc_ecc)
{
struct mtd_info *mtd = nand_to_mtd(chip);
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
int eccbytes = chip->ecc.bytes;
int eccsteps = chip->ecc.steps;
int eccstrength = chip->ecc.strength;
int i, s, eccsize = chip->ecc.size;
u32 *ecc_sta = (u32 *)fmc2->ecc_buf;
u16 sta_map = stm32_fmc2_get_mapping_status(fmc2);
unsigned int max_bitflips = 0;
for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, dat += eccsize) {
int stat = 0;
if (eccstrength == FMC2_ECC_HAM) {
/* Ecc_sta = FMC2_HECCR */
if (sta_map & BIT(s)) {
stm32_fmc2_ham_set_ecc(*ecc_sta, &calc_ecc[i]);
stat = stm32_fmc2_ham_correct(chip, dat,
&read_ecc[i],
&calc_ecc[i]);
}
ecc_sta++;
} else {
/*
* Ecc_sta[0] = FMC2_BCHDSR0
* Ecc_sta[1] = FMC2_BCHDSR1
* Ecc_sta[2] = FMC2_BCHDSR2
* Ecc_sta[3] = FMC2_BCHDSR3
* Ecc_sta[4] = FMC2_BCHDSR4
*/
if (sta_map & BIT(s))
stat = stm32_fmc2_bch_decode(eccsize, dat,
ecc_sta);
ecc_sta += 5;
}
if (stat == -EBADMSG)
/* Check for empty pages with bitflips */
stat = nand_check_erased_ecc_chunk(dat, eccsize,
&read_ecc[i],
eccbytes,
NULL, 0,
eccstrength);
if (stat < 0) {
mtd->ecc_stats.failed++;
} else {
mtd->ecc_stats.corrected += stat;
max_bitflips = max_t(unsigned int, max_bitflips, stat);
}
}
return max_bitflips;
}
static int stm32_fmc2_sequencer_read_page(struct nand_chip *chip, u8 *buf,
int oob_required, int page)
{
struct mtd_info *mtd = nand_to_mtd(chip);
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
u8 *ecc_calc = chip->ecc.calc_buf;
u8 *ecc_code = chip->ecc.code_buf;
u16 sta_map;
int ret;
/* Select the target */
ret = stm32_fmc2_select_chip(chip, chip->cur_cs);
if (ret)
return ret;
/* Configure the sequencer */
stm32_fmc2_rw_page_init(chip, page, 0, false);
/* Read the page */
ret = stm32_fmc2_xfer(chip, buf, 0, false);
if (ret)
return ret;
sta_map = stm32_fmc2_get_mapping_status(fmc2);
/* Check if errors happen */
if (likely(!sta_map)) {
if (oob_required)
return nand_change_read_column_op(chip, mtd->writesize,
chip->oob_poi,
mtd->oobsize, false);
return 0;
}
/* Read oob */
ret = nand_change_read_column_op(chip, mtd->writesize,
chip->oob_poi, mtd->oobsize, false);
if (ret)
return ret;
ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
chip->ecc.total);
if (ret)
return ret;
/* Correct data */
return chip->ecc.correct(chip, buf, ecc_code, ecc_calc);
}
static int stm32_fmc2_sequencer_read_page_raw(struct nand_chip *chip, u8 *buf,
int oob_required, int page)
{
struct mtd_info *mtd = nand_to_mtd(chip);
int ret;
/* Select the target */
ret = stm32_fmc2_select_chip(chip, chip->cur_cs);
if (ret)
return ret;
/* Configure the sequencer */
stm32_fmc2_rw_page_init(chip, page, 1, false);
/* Read the page */
ret = stm32_fmc2_xfer(chip, buf, 1, false);
if (ret)
return ret;
/* Read oob */
if (oob_required)
return nand_change_read_column_op(chip, mtd->writesize,
chip->oob_poi, mtd->oobsize,
false);
return 0;
}
static irqreturn_t stm32_fmc2_irq(int irq, void *dev_id)
{
struct stm32_fmc2_nfc *fmc2 = (struct stm32_fmc2_nfc *)dev_id;
if (fmc2->irq_state == FMC2_IRQ_SEQ)
/* Sequencer is used */
stm32_fmc2_disable_seq_irq(fmc2);
else if (fmc2->irq_state == FMC2_IRQ_BCH)
/* BCH is used */
stm32_fmc2_disable_bch_irq(fmc2);
complete(&fmc2->complete);
return IRQ_HANDLED;
}
static void stm32_fmc2_read_data(struct nand_chip *chip, void *buf,
unsigned int len, bool force_8bit)
{
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
void __iomem *io_addr_r = fmc2->data_base[fmc2->cs_sel];
if (force_8bit && chip->options & NAND_BUSWIDTH_16)
/* Reconfigure bus width to 8-bit */
stm32_fmc2_set_buswidth_16(fmc2, false);
if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) {
if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16)) && len) {
*(u8 *)buf = readb_relaxed(io_addr_r);
buf += sizeof(u8);
len -= sizeof(u8);
}
if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
len >= sizeof(u16)) {
*(u16 *)buf = readw_relaxed(io_addr_r);
buf += sizeof(u16);
len -= sizeof(u16);
}
}
/* Buf is aligned */
while (len >= sizeof(u32)) {
*(u32 *)buf = readl_relaxed(io_addr_r);
buf += sizeof(u32);
len -= sizeof(u32);
}
/* Read remaining bytes */
if (len >= sizeof(u16)) {
*(u16 *)buf = readw_relaxed(io_addr_r);
buf += sizeof(u16);
len -= sizeof(u16);
}
if (len)
*(u8 *)buf = readb_relaxed(io_addr_r);
if (force_8bit && chip->options & NAND_BUSWIDTH_16)
/* Reconfigure bus width to 16-bit */
stm32_fmc2_set_buswidth_16(fmc2, true);
}
static void stm32_fmc2_write_data(struct nand_chip *chip, const void *buf,
unsigned int len, bool force_8bit)
{
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
void __iomem *io_addr_w = fmc2->data_base[fmc2->cs_sel];
if (force_8bit && chip->options & NAND_BUSWIDTH_16)
/* Reconfigure bus width to 8-bit */
stm32_fmc2_set_buswidth_16(fmc2, false);
if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) {
if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16)) && len) {
writeb_relaxed(*(u8 *)buf, io_addr_w);
buf += sizeof(u8);
len -= sizeof(u8);
}
if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
len >= sizeof(u16)) {
writew_relaxed(*(u16 *)buf, io_addr_w);
buf += sizeof(u16);
len -= sizeof(u16);
}
}
/* Buf is aligned */
while (len >= sizeof(u32)) {
writel_relaxed(*(u32 *)buf, io_addr_w);
buf += sizeof(u32);
len -= sizeof(u32);
}
/* Write remaining bytes */
if (len >= sizeof(u16)) {
writew_relaxed(*(u16 *)buf, io_addr_w);
buf += sizeof(u16);
len -= sizeof(u16);
}
if (len)
writeb_relaxed(*(u8 *)buf, io_addr_w);
if (force_8bit && chip->options & NAND_BUSWIDTH_16)
/* Reconfigure bus width to 16-bit */
stm32_fmc2_set_buswidth_16(fmc2, true);
}
static int stm32_fmc2_exec_op(struct nand_chip *chip,
const struct nand_operation *op,
bool check_only)
{
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
const struct nand_op_instr *instr = NULL;
unsigned int op_id, i;
int ret;
ret = stm32_fmc2_select_chip(chip, op->cs);
if (ret)
return ret;
if (check_only)
return ret;
for (op_id = 0; op_id < op->ninstrs; op_id++) {
instr = &op->instrs[op_id];
switch (instr->type) {
case NAND_OP_CMD_INSTR:
writeb_relaxed(instr->ctx.cmd.opcode,
fmc2->cmd_base[fmc2->cs_sel]);
break;
case NAND_OP_ADDR_INSTR:
for (i = 0; i < instr->ctx.addr.naddrs; i++)
writeb_relaxed(instr->ctx.addr.addrs[i],
fmc2->addr_base[fmc2->cs_sel]);
break;
case NAND_OP_DATA_IN_INSTR:
stm32_fmc2_read_data(chip, instr->ctx.data.buf.in,
instr->ctx.data.len,
instr->ctx.data.force_8bit);
break;
case NAND_OP_DATA_OUT_INSTR:
stm32_fmc2_write_data(chip, instr->ctx.data.buf.out,
instr->ctx.data.len,
instr->ctx.data.force_8bit);
break;
case NAND_OP_WAITRDY_INSTR:
ret = nand_soft_waitrdy(chip,
instr->ctx.waitrdy.timeout_ms);
break;
}
}
return ret;
}
/* Controller initialization */
static void stm32_fmc2_init(struct stm32_fmc2_nfc *fmc2)
{
u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
u32 bcr1 = readl_relaxed(fmc2->io_base + FMC2_BCR1);
/* Set CS used to undefined */
fmc2->cs_sel = -1;
/* Enable wait feature and nand flash memory bank */
pcr |= FMC2_PCR_PWAITEN;
pcr |= FMC2_PCR_PBKEN;
/* Set buswidth to 8 bits mode for identification */
pcr &= ~FMC2_PCR_PWID_MASK;
/* ECC logic is disabled */
pcr &= ~FMC2_PCR_ECCEN;
/* Default mode */
pcr &= ~FMC2_PCR_ECCALG;
pcr &= ~FMC2_PCR_BCHECC;
pcr &= ~FMC2_PCR_WEN;
/* Set default ECC sector size */
pcr &= ~FMC2_PCR_ECCSS_MASK;
pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_2048);
/* Set default tclr/tar timings */
pcr &= ~FMC2_PCR_TCLR_MASK;
pcr |= FMC2_PCR_TCLR(FMC2_PCR_TCLR_DEFAULT);
pcr &= ~FMC2_PCR_TAR_MASK;
pcr |= FMC2_PCR_TAR(FMC2_PCR_TAR_DEFAULT);
/* Enable FMC2 controller */
bcr1 |= FMC2_BCR1_FMC2EN;
writel_relaxed(bcr1, fmc2->io_base + FMC2_BCR1);
writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
writel_relaxed(FMC2_PMEM_DEFAULT, fmc2->io_base + FMC2_PMEM);
writel_relaxed(FMC2_PATT_DEFAULT, fmc2->io_base + FMC2_PATT);
}
/* Controller timings */
static void stm32_fmc2_calc_timings(struct nand_chip *chip,
const struct nand_sdr_timings *sdrt)
{
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
struct stm32_fmc2_timings *tims = &nand->timings;
unsigned long hclk = clk_get_rate(fmc2->clk);
unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
int tar, tclr, thiz, twait, tset_mem, tset_att, thold_mem, thold_att;
tar = hclkp;
if (tar < sdrt->tAR_min)
tar = sdrt->tAR_min;
tims->tar = DIV_ROUND_UP(tar, hclkp) - 1;
if (tims->tar > FMC2_PCR_TIMING_MASK)
tims->tar = FMC2_PCR_TIMING_MASK;
tclr = hclkp;
if (tclr < sdrt->tCLR_min)
tclr = sdrt->tCLR_min;
tims->tclr = DIV_ROUND_UP(tclr, hclkp) - 1;
if (tims->tclr > FMC2_PCR_TIMING_MASK)
tims->tclr = FMC2_PCR_TIMING_MASK;
tims->thiz = FMC2_THIZ;
thiz = (tims->thiz + 1) * hclkp;
/*
* tWAIT > tRP
* tWAIT > tWP
* tWAIT > tREA + tIO
*/
twait = hclkp;
if (twait < sdrt->tRP_min)
twait = sdrt->tRP_min;
if (twait < sdrt->tWP_min)
twait = sdrt->tWP_min;
if (twait < sdrt->tREA_max + FMC2_TIO)
twait = sdrt->tREA_max + FMC2_TIO;
tims->twait = DIV_ROUND_UP(twait, hclkp);
if (tims->twait == 0)
tims->twait = 1;
else if (tims->twait > FMC2_PMEM_PATT_TIMING_MASK)
tims->twait = FMC2_PMEM_PATT_TIMING_MASK;
/*
* tSETUP_MEM > tCS - tWAIT
* tSETUP_MEM > tALS - tWAIT
* tSETUP_MEM > tDS - (tWAIT - tHIZ)
*/
tset_mem = hclkp;
if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait))
tset_mem = sdrt->tCS_min - twait;
if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait))
tset_mem = sdrt->tALS_min - twait;
if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
(tset_mem < sdrt->tDS_min - (twait - thiz)))
tset_mem = sdrt->tDS_min - (twait - thiz);
tims->tset_mem = DIV_ROUND_UP(tset_mem, hclkp);
if (tims->tset_mem == 0)
tims->tset_mem = 1;
else if (tims->tset_mem > FMC2_PMEM_PATT_TIMING_MASK)
tims->tset_mem = FMC2_PMEM_PATT_TIMING_MASK;
/*
* tHOLD_MEM > tCH
* tHOLD_MEM > tREH - tSETUP_MEM
* tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
*/
thold_mem = hclkp;
if (thold_mem < sdrt->tCH_min)
thold_mem = sdrt->tCH_min;
if (sdrt->tREH_min > tset_mem &&
(thold_mem < sdrt->tREH_min - tset_mem))
thold_mem = sdrt->tREH_min - tset_mem;
if ((sdrt->tRC_min > tset_mem + twait) &&
(thold_mem < sdrt->tRC_min - (tset_mem + twait)))
thold_mem = sdrt->tRC_min - (tset_mem + twait);
if ((sdrt->tWC_min > tset_mem + twait) &&
(thold_mem < sdrt->tWC_min - (tset_mem + twait)))
thold_mem = sdrt->tWC_min - (tset_mem + twait);
tims->thold_mem = DIV_ROUND_UP(thold_mem, hclkp);
if (tims->thold_mem == 0)
tims->thold_mem = 1;
else if (tims->thold_mem > FMC2_PMEM_PATT_TIMING_MASK)
tims->thold_mem = FMC2_PMEM_PATT_TIMING_MASK;
/*
* tSETUP_ATT > tCS - tWAIT
* tSETUP_ATT > tCLS - tWAIT
* tSETUP_ATT > tALS - tWAIT
* tSETUP_ATT > tRHW - tHOLD_MEM
* tSETUP_ATT > tDS - (tWAIT - tHIZ)
*/
tset_att = hclkp;
if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait))
tset_att = sdrt->tCS_min - twait;
if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait))
tset_att = sdrt->tCLS_min - twait;
if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait))
tset_att = sdrt->tALS_min - twait;
if (sdrt->tRHW_min > thold_mem &&
(tset_att < sdrt->tRHW_min - thold_mem))
tset_att = sdrt->tRHW_min - thold_mem;
if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
(tset_att < sdrt->tDS_min - (twait - thiz)))
tset_att = sdrt->tDS_min - (twait - thiz);
tims->tset_att = DIV_ROUND_UP(tset_att, hclkp);
if (tims->tset_att == 0)
tims->tset_att = 1;
else if (tims->tset_att > FMC2_PMEM_PATT_TIMING_MASK)
tims->tset_att = FMC2_PMEM_PATT_TIMING_MASK;
/*
* tHOLD_ATT > tALH
* tHOLD_ATT > tCH
* tHOLD_ATT > tCLH
* tHOLD_ATT > tCOH
* tHOLD_ATT > tDH
* tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM
* tHOLD_ATT > tADL - tSETUP_MEM
* tHOLD_ATT > tWH - tSETUP_MEM
* tHOLD_ATT > tWHR - tSETUP_MEM
* tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
* tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
*/
thold_att = hclkp;
if (thold_att < sdrt->tALH_min)
thold_att = sdrt->tALH_min;
if (thold_att < sdrt->tCH_min)
thold_att = sdrt->tCH_min;
if (thold_att < sdrt->tCLH_min)
thold_att = sdrt->tCLH_min;
if (thold_att < sdrt->tCOH_min)
thold_att = sdrt->tCOH_min;
if (thold_att < sdrt->tDH_min)
thold_att = sdrt->tDH_min;
if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) &&
(thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem))
thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem;
if (sdrt->tADL_min > tset_mem &&
(thold_att < sdrt->tADL_min - tset_mem))
thold_att = sdrt->tADL_min - tset_mem;
if (sdrt->tWH_min > tset_mem &&
(thold_att < sdrt->tWH_min - tset_mem))
thold_att = sdrt->tWH_min - tset_mem;
if (sdrt->tWHR_min > tset_mem &&
(thold_att < sdrt->tWHR_min - tset_mem))
thold_att = sdrt->tWHR_min - tset_mem;
if ((sdrt->tRC_min > tset_att + twait) &&
(thold_att < sdrt->tRC_min - (tset_att + twait)))
thold_att = sdrt->tRC_min - (tset_att + twait);
if ((sdrt->tWC_min > tset_att + twait) &&
(thold_att < sdrt->tWC_min - (tset_att + twait)))
thold_att = sdrt->tWC_min - (tset_att + twait);
tims->thold_att = DIV_ROUND_UP(thold_att, hclkp);
if (tims->thold_att == 0)
tims->thold_att = 1;
else if (tims->thold_att > FMC2_PMEM_PATT_TIMING_MASK)
tims->thold_att = FMC2_PMEM_PATT_TIMING_MASK;
}
static int stm32_fmc2_setup_interface(struct nand_chip *chip, int chipnr,
const struct nand_data_interface *conf)
{
const struct nand_sdr_timings *sdrt;
sdrt = nand_get_sdr_timings(conf);
if (IS_ERR(sdrt))
return PTR_ERR(sdrt);
if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
return 0;
stm32_fmc2_calc_timings(chip, sdrt);
/* Apply timings */
stm32_fmc2_timings_init(chip);
return 0;
}
/* DMA configuration */
static int stm32_fmc2_dma_setup(struct stm32_fmc2_nfc *fmc2)
{
int ret;
fmc2->dma_tx_ch = dma_request_slave_channel(fmc2->dev, "tx");
fmc2->dma_rx_ch = dma_request_slave_channel(fmc2->dev, "rx");
fmc2->dma_ecc_ch = dma_request_slave_channel(fmc2->dev, "ecc");
if (!fmc2->dma_tx_ch || !fmc2->dma_rx_ch || !fmc2->dma_ecc_ch) {
dev_warn(fmc2->dev, "DMAs not defined in the device tree, polling mode is used\n");
return 0;
}
ret = sg_alloc_table(&fmc2->dma_ecc_sg, FMC2_MAX_SG, GFP_KERNEL);
if (ret)
return ret;
/* Allocate a buffer to store ECC status registers */
fmc2->ecc_buf = devm_kzalloc(fmc2->dev, FMC2_MAX_ECC_BUF_LEN,
GFP_KERNEL);
if (!fmc2->ecc_buf)
return -ENOMEM;
ret = sg_alloc_table(&fmc2->dma_data_sg, FMC2_MAX_SG, GFP_KERNEL);
if (ret)
return ret;
init_completion(&fmc2->dma_data_complete);
init_completion(&fmc2->dma_ecc_complete);
return 0;
}
/* NAND callbacks setup */
static void stm32_fmc2_nand_callbacks_setup(struct nand_chip *chip)
{
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
/*
* Specific callbacks to read/write a page depending on
* the mode (polling/sequencer) and the algo used (Hamming, BCH).
*/
if (fmc2->dma_tx_ch && fmc2->dma_rx_ch && fmc2->dma_ecc_ch) {
/* DMA => use sequencer mode callbacks */
chip->ecc.correct = stm32_fmc2_sequencer_correct;
chip->ecc.write_page = stm32_fmc2_sequencer_write_page;
chip->ecc.read_page = stm32_fmc2_sequencer_read_page;
chip->ecc.write_page_raw = stm32_fmc2_sequencer_write_page_raw;
chip->ecc.read_page_raw = stm32_fmc2_sequencer_read_page_raw;
} else {
/* No DMA => use polling mode callbacks */
chip->ecc.hwctl = stm32_fmc2_hwctl;
if (chip->ecc.strength == FMC2_ECC_HAM) {
/* Hamming is used */
chip->ecc.calculate = stm32_fmc2_ham_calculate;
chip->ecc.correct = stm32_fmc2_ham_correct;
chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK;
} else {
/* BCH is used */
chip->ecc.calculate = stm32_fmc2_bch_calculate;
chip->ecc.correct = stm32_fmc2_bch_correct;
chip->ecc.read_page = stm32_fmc2_read_page;
}
}
/* Specific configurations depending on the algo used */
if (chip->ecc.strength == FMC2_ECC_HAM)
chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3;
else if (chip->ecc.strength == FMC2_ECC_BCH8)
chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13;
else
chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
}
/* FMC2 layout */
static int stm32_fmc2_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *oobregion)
{
struct nand_chip *chip = mtd_to_nand(mtd);
struct nand_ecc_ctrl *ecc = &chip->ecc;
if (section)
return -ERANGE;
oobregion->length = ecc->total;
oobregion->offset = FMC2_BBM_LEN;
return 0;
}
static int stm32_fmc2_nand_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *oobregion)
{
struct nand_chip *chip = mtd_to_nand(mtd);
struct nand_ecc_ctrl *ecc = &chip->ecc;
if (section)
return -ERANGE;
oobregion->length = mtd->oobsize - ecc->total - FMC2_BBM_LEN;
oobregion->offset = ecc->total + FMC2_BBM_LEN;
return 0;
}
static const struct mtd_ooblayout_ops stm32_fmc2_nand_ooblayout_ops = {
.ecc = stm32_fmc2_nand_ooblayout_ecc,
.free = stm32_fmc2_nand_ooblayout_free,
};
/* FMC2 caps */
static int stm32_fmc2_calc_ecc_bytes(int step_size, int strength)
{
/* Hamming */
if (strength == FMC2_ECC_HAM)
return 4;
/* BCH8 */
if (strength == FMC2_ECC_BCH8)
return 14;
/* BCH4 */
return 8;
}
NAND_ECC_CAPS_SINGLE(stm32_fmc2_ecc_caps, stm32_fmc2_calc_ecc_bytes,
FMC2_ECC_STEP_SIZE,
FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);
/* FMC2 controller ops */
static int stm32_fmc2_attach_chip(struct nand_chip *chip)
{
struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
struct mtd_info *mtd = nand_to_mtd(chip);
int ret;
/*
* Only NAND_ECC_HW mode is actually supported
* Hamming => ecc.strength = 1
* BCH4 => ecc.strength = 4
* BCH8 => ecc.strength = 8
* ECC sector size = 512
*/
if (chip->ecc.mode != NAND_ECC_HW) {
dev_err(fmc2->dev, "nand_ecc_mode is not well defined in the DT\n");
return -EINVAL;
}
ret = nand_ecc_choose_conf(chip, &stm32_fmc2_ecc_caps,
mtd->oobsize - FMC2_BBM_LEN);
if (ret) {
dev_err(fmc2->dev, "no valid ECC settings set\n");
return ret;
}
if (mtd->writesize / chip->ecc.size > FMC2_MAX_SG) {
dev_err(fmc2->dev, "nand page size is not supported\n");
return -EINVAL;
}
if (chip->bbt_options & NAND_BBT_USE_FLASH)
chip->bbt_options |= NAND_BBT_NO_OOB;
/* NAND callbacks setup */
stm32_fmc2_nand_callbacks_setup(chip);
/* Define ECC layout */
mtd_set_ooblayout(mtd, &stm32_fmc2_nand_ooblayout_ops);
/* Configure bus width to 16-bit */
if (chip->options & NAND_BUSWIDTH_16)
stm32_fmc2_set_buswidth_16(fmc2, true);
return 0;
}
static const struct nand_controller_ops stm32_fmc2_nand_controller_ops = {
.attach_chip = stm32_fmc2_attach_chip,
.exec_op = stm32_fmc2_exec_op,
.setup_data_interface = stm32_fmc2_setup_interface,
};
/* FMC2 probe */
static int stm32_fmc2_parse_child(struct stm32_fmc2_nfc *fmc2,
struct device_node *dn)
{
struct stm32_fmc2_nand *nand = &fmc2->nand;
u32 cs;
int ret, i;
if (!of_get_property(dn, "reg", &nand->ncs))
return -EINVAL;
nand->ncs /= sizeof(u32);
if (!nand->ncs) {
dev_err(fmc2->dev, "invalid reg property size\n");
return -EINVAL;
}
for (i = 0; i < nand->ncs; i++) {
ret = of_property_read_u32_index(dn, "reg", i, &cs);
if (ret) {
dev_err(fmc2->dev, "could not retrieve reg property: %d\n",
ret);
return ret;
}
if (cs > FMC2_MAX_CE) {
dev_err(fmc2->dev, "invalid reg value: %d\n", cs);
return -EINVAL;
}
if (fmc2->cs_assigned & BIT(cs)) {
dev_err(fmc2->dev, "cs already assigned: %d\n", cs);
return -EINVAL;
}
fmc2->cs_assigned |= BIT(cs);
nand->cs_used[i] = cs;
}
nand_set_flash_node(&nand->chip, dn);
return 0;
}
static int stm32_fmc2_parse_dt(struct stm32_fmc2_nfc *fmc2)
{
struct device_node *dn = fmc2->dev->of_node;
struct device_node *child;
int nchips = of_get_child_count(dn);
int ret = 0;
if (!nchips) {
dev_err(fmc2->dev, "NAND chip not defined\n");
return -EINVAL;
}
if (nchips > 1) {
dev_err(fmc2->dev, "too many NAND chips defined\n");
return -EINVAL;
}
for_each_child_of_node(dn, child) {
ret = stm32_fmc2_parse_child(fmc2, child);
if (ret < 0) {
of_node_put(child);
return ret;
}
}
return ret;
}
static int stm32_fmc2_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct reset_control *rstc;
struct stm32_fmc2_nfc *fmc2;
struct stm32_fmc2_nand *nand;
struct resource *res;
struct mtd_info *mtd;
struct nand_chip *chip;
int chip_cs, mem_region, ret, irq;
fmc2 = devm_kzalloc(dev, sizeof(*fmc2), GFP_KERNEL);
if (!fmc2)
return -ENOMEM;
fmc2->dev = dev;
nand_controller_init(&fmc2->base);
fmc2->base.ops = &stm32_fmc2_nand_controller_ops;
ret = stm32_fmc2_parse_dt(fmc2);
if (ret)
return ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
fmc2->io_base = devm_ioremap_resource(dev, res);
if (IS_ERR(fmc2->io_base))
return PTR_ERR(fmc2->io_base);
fmc2->io_phys_addr = res->start;
for (chip_cs = 0, mem_region = 1; chip_cs < FMC2_MAX_CE;
chip_cs++, mem_region += 3) {
if (!(fmc2->cs_assigned & BIT(chip_cs)))
continue;
res = platform_get_resource(pdev, IORESOURCE_MEM, mem_region);
fmc2->data_base[chip_cs] = devm_ioremap_resource(dev, res);
if (IS_ERR(fmc2->data_base[chip_cs]))
return PTR_ERR(fmc2->data_base[chip_cs]);
fmc2->data_phys_addr[chip_cs] = res->start;
res = platform_get_resource(pdev, IORESOURCE_MEM,
mem_region + 1);
fmc2->cmd_base[chip_cs] = devm_ioremap_resource(dev, res);
if (IS_ERR(fmc2->cmd_base[chip_cs]))
return PTR_ERR(fmc2->cmd_base[chip_cs]);
res = platform_get_resource(pdev, IORESOURCE_MEM,
mem_region + 2);
fmc2->addr_base[chip_cs] = devm_ioremap_resource(dev, res);
if (IS_ERR(fmc2->addr_base[chip_cs]))
return PTR_ERR(fmc2->addr_base[chip_cs]);
}
irq = platform_get_irq(pdev, 0);
ret = devm_request_irq(dev, irq, stm32_fmc2_irq, 0,
dev_name(dev), fmc2);
if (ret) {
dev_err(dev, "failed to request irq\n");
return ret;
}
init_completion(&fmc2->complete);
fmc2->clk = devm_clk_get(dev, NULL);
if (IS_ERR(fmc2->clk))
return PTR_ERR(fmc2->clk);
ret = clk_prepare_enable(fmc2->clk);
if (ret) {
dev_err(dev, "can not enable the clock\n");
return ret;
}
rstc = devm_reset_control_get(dev, NULL);
if (!IS_ERR(rstc)) {
reset_control_assert(rstc);
reset_control_deassert(rstc);
}
/* DMA setup */
ret = stm32_fmc2_dma_setup(fmc2);
if (ret)
return ret;
/* FMC2 init routine */
stm32_fmc2_init(fmc2);
nand = &fmc2->nand;
chip = &nand->chip;
mtd = nand_to_mtd(chip);
mtd->dev.parent = dev;
chip->controller = &fmc2->base;
chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
NAND_USE_BOUNCE_BUFFER;
/* Default ECC settings */
chip->ecc.mode = NAND_ECC_HW;
chip->ecc.size = FMC2_ECC_STEP_SIZE;
chip->ecc.strength = FMC2_ECC_BCH8;
/* Scan to find existence of the device */
ret = nand_scan(chip, nand->ncs);
if (ret)
goto err_scan;
ret = mtd_device_register(mtd, NULL, 0);
if (ret)
goto err_device_register;
platform_set_drvdata(pdev, fmc2);
return 0;
err_device_register:
nand_cleanup(chip);
err_scan:
if (fmc2->dma_ecc_ch)
dma_release_channel(fmc2->dma_ecc_ch);
if (fmc2->dma_tx_ch)
dma_release_channel(fmc2->dma_tx_ch);
if (fmc2->dma_rx_ch)
dma_release_channel(fmc2->dma_rx_ch);
sg_free_table(&fmc2->dma_data_sg);
sg_free_table(&fmc2->dma_ecc_sg);
clk_disable_unprepare(fmc2->clk);
return ret;
}
static int stm32_fmc2_remove(struct platform_device *pdev)
{
struct stm32_fmc2_nfc *fmc2 = platform_get_drvdata(pdev);
struct stm32_fmc2_nand *nand = &fmc2->nand;
nand_release(&nand->chip);
if (fmc2->dma_ecc_ch)
dma_release_channel(fmc2->dma_ecc_ch);
if (fmc2->dma_tx_ch)
dma_release_channel(fmc2->dma_tx_ch);
if (fmc2->dma_rx_ch)
dma_release_channel(fmc2->dma_rx_ch);
sg_free_table(&fmc2->dma_data_sg);
sg_free_table(&fmc2->dma_ecc_sg);
clk_disable_unprepare(fmc2->clk);
return 0;
}
static int __maybe_unused stm32_fmc2_suspend(struct device *dev)
{
struct stm32_fmc2_nfc *fmc2 = dev_get_drvdata(dev);
clk_disable_unprepare(fmc2->clk);
pinctrl_pm_select_sleep_state(dev);
return 0;
}
static int __maybe_unused stm32_fmc2_resume(struct device *dev)
{
struct stm32_fmc2_nfc *fmc2 = dev_get_drvdata(dev);
struct stm32_fmc2_nand *nand = &fmc2->nand;
int chip_cs, ret;
pinctrl_pm_select_default_state(dev);
ret = clk_prepare_enable(fmc2->clk);
if (ret) {
dev_err(dev, "can not enable the clock\n");
return ret;
}
stm32_fmc2_init(fmc2);
for (chip_cs = 0; chip_cs < FMC2_MAX_CE; chip_cs++) {
if (!(fmc2->cs_assigned & BIT(chip_cs)))
continue;
nand_reset(&nand->chip, chip_cs);
}
return 0;
}
static SIMPLE_DEV_PM_OPS(stm32_fmc2_pm_ops, stm32_fmc2_suspend,
stm32_fmc2_resume);
static const struct of_device_id stm32_fmc2_match[] = {
{.compatible = "st,stm32mp15-fmc2"},
{}
};
MODULE_DEVICE_TABLE(of, stm32_fmc2_match);
static struct platform_driver stm32_fmc2_driver = {
.probe = stm32_fmc2_probe,
.remove = stm32_fmc2_remove,
.driver = {
.name = "stm32_fmc2_nand",
.of_match_table = stm32_fmc2_match,
.pm = &stm32_fmc2_pm_ops,
},
};
module_platform_driver(stm32_fmc2_driver);
MODULE_ALIAS("platform:stm32_fmc2_nand");
MODULE_AUTHOR("Christophe Kerello <christophe.kerello@st.com>");
MODULE_DESCRIPTION("STMicroelectronics STM32 FMC2 nand driver");
MODULE_LICENSE("GPL v2");
drivers/mtd/nand/raw/sunxi_nand.c
View file @ 9220d7be
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
*
......@@ -10,16 +11,6 @@
*
* Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
* Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/dma-mapping.h>
......@@ -163,20 +154,19 @@
#define NFC_MAX_CS 7
/*
* Chip Select structure: stores information related to NAND Chip Select
/**
* struct sunxi_nand_chip_sel - stores information related to NAND Chip Select
*
* @cs: the NAND CS id used to communicate with a NAND Chip
* @rb: the Ready/Busy pin ID. -1 means no R/B pin connected to the
* NFC
* @rb: the Ready/Busy pin ID. -1 means no R/B pin connected to the NFC
*/
struct sunxi_nand_chip_sel {
u8 cs;
s8 rb;
};
/*
* sunxi HW ECC infos: stores information related to HW ECC support
/**
* struct sunxi_nand_hw_ecc - stores information related to HW ECC support
*
* @mode: the sunxi ECC mode field deduced from ECC requirements
*/
......@@ -184,15 +174,14 @@ struct sunxi_nand_hw_ecc {
int mode;
};
/*
* NAND chip structure: stores NAND chip device related information
/**
* struct sunxi_nand_chip - stores NAND chip device related information
*
* @node: used to store NAND chips into a list
* @nand: base NAND chip structure
* @mtd: base MTD structure
* @clk_rate: clk_rate required for this NAND chip
* @timing_cfg TIMING_CFG register value for this NAND chip
* @selected: current active CS
* @timing_cfg: TIMING_CFG register value for this NAND chip
* @timing_ctl: TIMING_CTL register value for this NAND chip
* @nsels: number of CS lines required by the NAND chip
* @sels: array of CS lines descriptions
*/
......@@ -202,11 +191,6 @@ struct sunxi_nand_chip {
unsigned long clk_rate;
u32 timing_cfg;
u32 timing_ctl;
int selected;
int addr_cycles;
u32 addr[2];
int cmd_cycles;
u8 cmd[2];
int nsels;
struct sunxi_nand_chip_sel sels[0];
};
......@@ -216,20 +200,21 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
return container_of(nand, struct sunxi_nand_chip, nand);
}
/*
* NAND Controller structure: stores sunxi NAND controller information
/**
* struct sunxi_nfc - stores sunxi NAND controller information
*
* @controller: base controller structure
* @dev: parent device (used to print error messages)
* @regs: NAND controller registers
* @ahb_clk: NAND Controller AHB clock
* @mod_clk: NAND Controller mod clock
* @ahb_clk: NAND controller AHB clock
* @mod_clk: NAND controller mod clock
* @reset: NAND controller reset line
* @assigned_cs: bitmask describing already assigned CS lines
* @clk_rate: NAND controller current clock rate
* @chips: a list containing all the NAND chips attached to
* this NAND controller
* @complete: a completion object used to wait for NAND
* controller events
* @chips: a list containing all the NAND chips attached to this NAND
* controller
* @complete: a completion object used to wait for NAND controller events
* @dmac: the DMA channel attached to the NAND controller
*/
struct sunxi_nfc {
struct nand_controller controller;
......@@ -339,13 +324,11 @@ static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
return ret;
}
static int sunxi_nfc_dma_op_prepare(struct mtd_info *mtd, const void *buf,
static int sunxi_nfc_dma_op_prepare(struct sunxi_nfc *nfc, const void *buf,
int chunksize, int nchunks,
enum dma_data_direction ddir,
struct scatterlist *sg)
{
struct nand_chip *nand = mtd_to_nand(mtd);
struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
struct dma_async_tx_descriptor *dmad;
enum dma_transfer_direction tdir;
dma_cookie_t dmat;
......@@ -388,38 +371,16 @@ static int sunxi_nfc_dma_op_prepare(struct mtd_info *mtd, const void *buf,
return ret;
}
static void sunxi_nfc_dma_op_cleanup(struct mtd_info *mtd,
static void sunxi_nfc_dma_op_cleanup(struct sunxi_nfc *nfc,
enum dma_data_direction ddir,
struct scatterlist *sg)
{
struct nand_chip *nand = mtd_to_nand(mtd);
struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
dma_unmap_sg(nfc->dev, sg, 1, ddir);
writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
nfc->regs + NFC_REG_CTL);
}
static int sunxi_nfc_dev_ready(struct nand_chip *nand)
{
struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
u32 mask;
if (sunxi_nand->selected < 0)
return 0;
if (sunxi_nand->sels[sunxi_nand->selected].rb < 0) {
dev_err(nfc->dev, "cannot check R/B NAND status!\n");
return 0;
}
mask = NFC_RB_STATE(sunxi_nand->sels[sunxi_nand->selected].rb);
return !!(readl(nfc->regs + NFC_REG_ST) & mask);
}
static void sunxi_nfc_select_chip(struct nand_chip *nand, int chip)
static void sunxi_nfc_select_chip(struct nand_chip *nand, unsigned int cs)
{
struct mtd_info *mtd = nand_to_mtd(nand);
struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
......@@ -427,26 +388,16 @@ static void sunxi_nfc_select_chip(struct nand_chip *nand, int chip)
struct sunxi_nand_chip_sel *sel;
u32 ctl;
if (chip > 0 && chip >= sunxi_nand->nsels)
return;
if (chip == sunxi_nand->selected)
if (cs > 0 && cs >= sunxi_nand->nsels)
return;
ctl = readl(nfc->regs + NFC_REG_CTL) &
~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN);
if (chip >= 0) {
sel = &sunxi_nand->sels[chip];
ctl |= NFC_CE_SEL(sel->cs) | NFC_EN |
NFC_PAGE_SHIFT(nand->page_shift);
if (sel->rb < 0) {
nand->legacy.dev_ready = NULL;
} else {
nand->legacy.dev_ready = sunxi_nfc_dev_ready;
sel = &sunxi_nand->sels[cs];
ctl |= NFC_CE_SEL(sel->cs) | NFC_EN | NFC_PAGE_SHIFT(nand->page_shift);
if (sel->rb >= 0)
ctl |= NFC_RB_SEL(sel->rb);
}
writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
......@@ -454,13 +405,10 @@ static void sunxi_nfc_select_chip(struct nand_chip *nand, int chip)
clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate);
nfc->clk_rate = sunxi_nand->clk_rate;
}
}
writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
writel(ctl, nfc->regs + NFC_REG_CTL);
sunxi_nand->selected = chip;
}
static void sunxi_nfc_read_buf(struct nand_chip *nand, uint8_t *buf, int len)
......@@ -537,71 +485,6 @@ static void sunxi_nfc_write_buf(struct nand_chip *nand, const uint8_t *buf,
}
}
static uint8_t sunxi_nfc_read_byte(struct nand_chip *nand)
{
uint8_t ret = 0;
sunxi_nfc_read_buf(nand, &ret, 1);
return ret;
}
static void sunxi_nfc_cmd_ctrl(struct nand_chip *nand, int dat,
unsigned int ctrl)
{
struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
int ret;
if (dat == NAND_CMD_NONE && (ctrl & NAND_NCE) &&
!(ctrl & (NAND_CLE | NAND_ALE))) {
u32 cmd = 0;
if (!sunxi_nand->addr_cycles && !sunxi_nand->cmd_cycles)
return;
if (sunxi_nand->cmd_cycles--)
cmd |= NFC_SEND_CMD1 | sunxi_nand->cmd[0];
if (sunxi_nand->cmd_cycles--) {
cmd |= NFC_SEND_CMD2;
writel(sunxi_nand->cmd[1],
nfc->regs + NFC_REG_RCMD_SET);
}
sunxi_nand->cmd_cycles = 0;
if (sunxi_nand->addr_cycles) {
cmd |= NFC_SEND_ADR |
NFC_ADR_NUM(sunxi_nand->addr_cycles);
writel(sunxi_nand->addr[0],
nfc->regs + NFC_REG_ADDR_LOW);
}
if (sunxi_nand->addr_cycles > 4)
writel(sunxi_nand->addr[1],
nfc->regs + NFC_REG_ADDR_HIGH);
ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
if (ret)
return;
writel(cmd, nfc->regs + NFC_REG_CMD);
sunxi_nand->addr[0] = 0;
sunxi_nand->addr[1] = 0;
sunxi_nand->addr_cycles = 0;
sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, true, 0);
}
if (ctrl & NAND_CLE) {
sunxi_nand->cmd[sunxi_nand->cmd_cycles++] = dat;
} else if (ctrl & NAND_ALE) {
sunxi_nand->addr[sunxi_nand->addr_cycles / 4] |=
dat << ((sunxi_nand->addr_cycles % 4) * 8);
sunxi_nand->addr_cycles++;
}
}
/* These seed values have been extracted from Allwinner's BSP */
static const u16 sunxi_nfc_randomizer_page_seeds[] = {
0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
......@@ -684,8 +567,10 @@ static u16 sunxi_nfc_randomizer_step(u16 state, int count)
return state;
}
static u16 sunxi_nfc_randomizer_state(struct mtd_info *mtd, int page, bool ecc)
static u16 sunxi_nfc_randomizer_state(struct nand_chip *nand, int page,
bool ecc)
{
struct mtd_info *mtd = nand_to_mtd(nand);
const u16 *seeds = sunxi_nfc_randomizer_page_seeds;
int mod = mtd_div_by_ws(mtd->erasesize, mtd);
......@@ -702,10 +587,9 @@ static u16 sunxi_nfc_randomizer_state(struct mtd_info *mtd, int page, bool ecc)
return seeds[page % mod];
}
static void sunxi_nfc_randomizer_config(struct mtd_info *mtd,
int page, bool ecc)
static void sunxi_nfc_randomizer_config(struct nand_chip *nand, int page,
bool ecc)
{
struct nand_chip *nand = mtd_to_nand(mtd);
struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
u32 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
u16 state;
......@@ -714,14 +598,13 @@ static void sunxi_nfc_randomizer_config(struct mtd_info *mtd,
return;
ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
state = sunxi_nfc_randomizer_state(mtd, page, ecc);
state = sunxi_nfc_randomizer_state(nand, page, ecc);
ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK;
writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL);
}
static void sunxi_nfc_randomizer_enable(struct mtd_info *mtd)
static void sunxi_nfc_randomizer_enable(struct nand_chip *nand)
{
struct nand_chip *nand = mtd_to_nand(mtd);
struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
if (!(nand->options & NAND_NEED_SCRAMBLING))
......@@ -731,9 +614,8 @@ static void sunxi_nfc_randomizer_enable(struct mtd_info *mtd)
nfc->regs + NFC_REG_ECC_CTL);
}
static void sunxi_nfc_randomizer_disable(struct mtd_info *mtd)
static void sunxi_nfc_randomizer_disable(struct nand_chip *nand)
{
struct nand_chip *nand = mtd_to_nand(mtd);
struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
if (!(nand->options & NAND_NEED_SCRAMBLING))
......@@ -743,36 +625,35 @@ static void sunxi_nfc_randomizer_disable(struct mtd_info *mtd)
nfc->regs + NFC_REG_ECC_CTL);
}
static void sunxi_nfc_randomize_bbm(struct mtd_info *mtd, int page, u8 *bbm)
static void sunxi_nfc_randomize_bbm(struct nand_chip *nand, int page, u8 *bbm)
{
u16 state = sunxi_nfc_randomizer_state(mtd, page, true);
u16 state = sunxi_nfc_randomizer_state(nand, page, true);
bbm[0] ^= state;
bbm[1] ^= sunxi_nfc_randomizer_step(state, 8);
}
static void sunxi_nfc_randomizer_write_buf(struct mtd_info *mtd,
static void sunxi_nfc_randomizer_write_buf(struct nand_chip *nand,
const uint8_t *buf, int len,
bool ecc, int page)
{
sunxi_nfc_randomizer_config(mtd, page, ecc);
sunxi_nfc_randomizer_enable(mtd);
sunxi_nfc_write_buf(mtd_to_nand(mtd), buf, len);
sunxi_nfc_randomizer_disable(mtd);
sunxi_nfc_randomizer_config(nand, page, ecc);
sunxi_nfc_randomizer_enable(nand);
sunxi_nfc_write_buf(nand, buf, len);
sunxi_nfc_randomizer_disable(nand);
}
static void sunxi_nfc_randomizer_read_buf(struct mtd_info *mtd, uint8_t *buf,
static void sunxi_nfc_randomizer_read_buf(struct nand_chip *nand, uint8_t *buf,
int len, bool ecc, int page)
{
sunxi_nfc_randomizer_config(mtd, page, ecc);
sunxi_nfc_randomizer_enable(mtd);
sunxi_nfc_read_buf(mtd_to_nand(mtd), buf, len);
sunxi_nfc_randomizer_disable(mtd);
sunxi_nfc_randomizer_config(nand, page, ecc);
sunxi_nfc_randomizer_enable(nand);
sunxi_nfc_read_buf(nand, buf, len);
sunxi_nfc_randomizer_disable(nand);
}
static void sunxi_nfc_hw_ecc_enable(struct mtd_info *mtd)
static void sunxi_nfc_hw_ecc_enable(struct nand_chip *nand)
{
struct nand_chip *nand = mtd_to_nand(mtd);
struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
struct sunxi_nand_hw_ecc *data = nand->ecc.priv;
u32 ecc_ctl;
......@@ -789,9 +670,8 @@ static void sunxi_nfc_hw_ecc_enable(struct mtd_info *mtd)
writel(ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
}
static void sunxi_nfc_hw_ecc_disable(struct mtd_info *mtd)
static void sunxi_nfc_hw_ecc_disable(struct nand_chip *nand)
{
struct nand_chip *nand = mtd_to_nand(mtd);
struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
......@@ -811,10 +691,9 @@ static inline u32 sunxi_nfc_buf_to_user_data(const u8 *buf)
return buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
}
static void sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct mtd_info *mtd, u8 *oob,
static void sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct nand_chip *nand, u8 *oob,
int step, bool bbm, int page)
{
struct nand_chip *nand = mtd_to_nand(mtd);
struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
sunxi_nfc_user_data_to_buf(readl(nfc->regs + NFC_REG_USER_DATA(step)),
......@@ -822,21 +701,20 @@ static void sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct mtd_info *mtd, u8 *oob,
/* De-randomize the Bad Block Marker. */
if (bbm && (nand->options & NAND_NEED_SCRAMBLING))
sunxi_nfc_randomize_bbm(mtd, page, oob);
sunxi_nfc_randomize_bbm(nand, page, oob);
}
static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct mtd_info *mtd,
static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct nand_chip *nand,
const u8 *oob, int step,
bool bbm, int page)
{
struct nand_chip *nand = mtd_to_nand(mtd);
struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
u8 user_data[4];
/* Randomize the Bad Block Marker. */
if (bbm && (nand->options & NAND_NEED_SCRAMBLING)) {
memcpy(user_data, oob, sizeof(user_data));
sunxi_nfc_randomize_bbm(mtd, page, user_data);
sunxi_nfc_randomize_bbm(nand, page, user_data);
oob = user_data;
}
......@@ -844,9 +722,11 @@ static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct mtd_info *mtd,
nfc->regs + NFC_REG_USER_DATA(step));
}
static void sunxi_nfc_hw_ecc_update_stats(struct mtd_info *mtd,
static void sunxi_nfc_hw_ecc_update_stats(struct nand_chip *nand,
unsigned int *max_bitflips, int ret)
{
struct mtd_info *mtd = nand_to_mtd(nand);
if (ret < 0) {
mtd->ecc_stats.failed++;
} else {
......@@ -855,10 +735,9 @@ static void sunxi_nfc_hw_ecc_update_stats(struct mtd_info *mtd,
}
}
static int sunxi_nfc_hw_ecc_correct(struct mtd_info *mtd, u8 *data, u8 *oob,
static int sunxi_nfc_hw_ecc_correct(struct nand_chip *nand, u8 *data, u8 *oob,
int step, u32 status, bool *erased)
{
struct nand_chip *nand = mtd_to_nand(mtd);
struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
struct nand_ecc_ctrl *ecc = &nand->ecc;
u32 tmp;
......@@ -892,14 +771,13 @@ static int sunxi_nfc_hw_ecc_correct(struct mtd_info *mtd, u8 *data, u8 *oob,
return NFC_ECC_ERR_CNT(step, tmp);
}
static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
static int sunxi_nfc_hw_ecc_read_chunk(struct nand_chip *nand,
u8 *data, int data_off,
u8 *oob, int oob_off,
int *cur_off,
unsigned int *max_bitflips,
bool bbm, bool oob_required, int page)
{
struct nand_chip *nand = mtd_to_nand(mtd);
struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
struct nand_ecc_ctrl *ecc = &nand->ecc;
int raw_mode = 0;
......@@ -909,7 +787,7 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
if (*cur_off != data_off)
nand_change_read_column_op(nand, data_off, NULL, 0, false);
sunxi_nfc_randomizer_read_buf(mtd, NULL, ecc->size, false, page);
sunxi_nfc_randomizer_read_buf(nand, NULL, ecc->size, false, page);
if (data_off + ecc->size != oob_off)
nand_change_read_column_op(nand, oob_off, NULL, 0, false);
......@@ -918,18 +796,18 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
if (ret)
return ret;
sunxi_nfc_randomizer_enable(mtd);
sunxi_nfc_randomizer_enable(nand);
writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
nfc->regs + NFC_REG_CMD);
ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, false, 0);
sunxi_nfc_randomizer_disable(mtd);
sunxi_nfc_randomizer_disable(nand);
if (ret)
return ret;
*cur_off = oob_off + ecc->bytes + 4;
ret = sunxi_nfc_hw_ecc_correct(mtd, data, oob_required ? oob : NULL, 0,
ret = sunxi_nfc_hw_ecc_correct(nand, data, oob_required ? oob : NULL, 0,
readl(nfc->regs + NFC_REG_ECC_ST),
&erased);
if (erased)
......@@ -961,24 +839,24 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
if (oob_required) {
nand_change_read_column_op(nand, oob_off, NULL, 0,
false);
sunxi_nfc_randomizer_read_buf(mtd, oob, ecc->bytes + 4,
sunxi_nfc_randomizer_read_buf(nand, oob, ecc->bytes + 4,
true, page);
sunxi_nfc_hw_ecc_get_prot_oob_bytes(mtd, oob, 0,
sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, 0,
bbm, page);
}
}
sunxi_nfc_hw_ecc_update_stats(mtd, max_bitflips, ret);
sunxi_nfc_hw_ecc_update_stats(nand, max_bitflips, ret);
return raw_mode;
}
static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info *mtd,
static void sunxi_nfc_hw_ecc_read_extra_oob(struct nand_chip *nand,
u8 *oob, int *cur_off,
bool randomize, int page)
{
struct nand_chip *nand = mtd_to_nand(mtd);
struct mtd_info *mtd = nand_to_mtd(nand);
struct nand_ecc_ctrl *ecc = &nand->ecc;
int offset = ((ecc->bytes + 4) * ecc->steps);
int len = mtd->oobsize - offset;
......@@ -993,20 +871,20 @@ static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info *mtd,
if (!randomize)
sunxi_nfc_read_buf(nand, oob + offset, len);
else
sunxi_nfc_randomizer_read_buf(mtd, oob + offset, len,
sunxi_nfc_randomizer_read_buf(nand, oob + offset, len,
false, page);
if (cur_off)
*cur_off = mtd->oobsize + mtd->writesize;
}
static int sunxi_nfc_hw_ecc_read_chunks_dma(struct mtd_info *mtd, uint8_t *buf,
static int sunxi_nfc_hw_ecc_read_chunks_dma(struct nand_chip *nand, uint8_t *buf,
int oob_required, int page,
int nchunks)
{
struct nand_chip *nand = mtd_to_nand(mtd);
bool randomized = nand->options & NAND_NEED_SCRAMBLING;
struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
struct mtd_info *mtd = nand_to_mtd(nand);
struct nand_ecc_ctrl *ecc = &nand->ecc;
unsigned int max_bitflips = 0;
int ret, i, raw_mode = 0;
......@@ -1017,14 +895,14 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct mtd_info *mtd, uint8_t *buf,
if (ret)
return ret;
ret = sunxi_nfc_dma_op_prepare(mtd, buf, ecc->size, nchunks,
ret = sunxi_nfc_dma_op_prepare(nfc, buf, ecc->size, nchunks,
DMA_FROM_DEVICE, &sg);
if (ret)
return ret;
sunxi_nfc_hw_ecc_enable(mtd);
sunxi_nfc_randomizer_config(mtd, page, false);
sunxi_nfc_randomizer_enable(mtd);
sunxi_nfc_hw_ecc_enable(nand);
sunxi_nfc_randomizer_config(nand, page, false);
sunxi_nfc_randomizer_enable(nand);
writel((NAND_CMD_RNDOUTSTART << 16) | (NAND_CMD_RNDOUT << 8) |
NAND_CMD_READSTART, nfc->regs + NFC_REG_RCMD_SET);
......@@ -1038,10 +916,10 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct mtd_info *mtd, uint8_t *buf,
if (ret)
dmaengine_terminate_all(nfc->dmac);
sunxi_nfc_randomizer_disable(mtd);
sunxi_nfc_hw_ecc_disable(mtd);
sunxi_nfc_randomizer_disable(nand);
sunxi_nfc_hw_ecc_disable(nand);
sunxi_nfc_dma_op_cleanup(mtd, DMA_FROM_DEVICE, &sg);
sunxi_nfc_dma_op_cleanup(nfc, DMA_FROM_DEVICE, &sg);
if (ret)
return ret;
......@@ -1055,7 +933,7 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct mtd_info *mtd, uint8_t *buf,
u8 *oob = nand->oob_poi + oob_off;
bool erased;
ret = sunxi_nfc_hw_ecc_correct(mtd, randomized ? data : NULL,
ret = sunxi_nfc_hw_ecc_correct(nand, randomized ? data : NULL,
oob_required ? oob : NULL,
i, status, &erased);
......@@ -1069,14 +947,14 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct mtd_info *mtd, uint8_t *buf,
mtd->writesize + oob_off,
oob, ecc->bytes + 4, false);
sunxi_nfc_hw_ecc_get_prot_oob_bytes(mtd, oob, i,
sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, i,
!i, page);
}
if (erased)
raw_mode = 1;
sunxi_nfc_hw_ecc_update_stats(mtd, &max_bitflips, ret);
sunxi_nfc_hw_ecc_update_stats(nand, &max_bitflips, ret);
}
if (status & NFC_ECC_ERR_MSK) {
......@@ -1111,25 +989,24 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct mtd_info *mtd, uint8_t *buf,
if (ret >= 0)
raw_mode = 1;
sunxi_nfc_hw_ecc_update_stats(mtd, &max_bitflips, ret);
sunxi_nfc_hw_ecc_update_stats(nand, &max_bitflips, ret);
}
}
if (oob_required)
sunxi_nfc_hw_ecc_read_extra_oob(mtd, nand->oob_poi,
sunxi_nfc_hw_ecc_read_extra_oob(nand, nand->oob_poi,
NULL, !raw_mode,
page);
return max_bitflips;
}
static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
static int sunxi_nfc_hw_ecc_write_chunk(struct nand_chip *nand,
const u8 *data, int data_off,
const u8 *oob, int oob_off,
int *cur_off, bool bbm,
int page)
{
struct nand_chip *nand = mtd_to_nand(mtd);
struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
struct nand_ecc_ctrl *ecc = &nand->ecc;
int ret;
......@@ -1137,7 +1014,7 @@ static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
if (data_off != *cur_off)
nand_change_write_column_op(nand, data_off, NULL, 0, false);
sunxi_nfc_randomizer_write_buf(mtd, data, ecc->size, false, page);
sunxi_nfc_randomizer_write_buf(nand, data, ecc->size, false, page);
if (data_off + ecc->size != oob_off)
nand_change_write_column_op(nand, oob_off, NULL, 0, false);
......@@ -1146,15 +1023,15 @@ static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
if (ret)
return ret;
sunxi_nfc_randomizer_enable(mtd);
sunxi_nfc_hw_ecc_set_prot_oob_bytes(mtd, oob, 0, bbm, page);
sunxi_nfc_randomizer_enable(nand);
sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, 0, bbm, page);
writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
NFC_ACCESS_DIR | NFC_ECC_OP,
nfc->regs + NFC_REG_CMD);
ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG, false, 0);
sunxi_nfc_randomizer_disable(mtd);
sunxi_nfc_randomizer_disable(nand);
if (ret)
return ret;
......@@ -1163,11 +1040,11 @@ static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
return 0;
}
static void sunxi_nfc_hw_ecc_write_extra_oob(struct mtd_info *mtd,
static void sunxi_nfc_hw_ecc_write_extra_oob(struct nand_chip *nand,
u8 *oob, int *cur_off,
int page)
{
struct nand_chip *nand = mtd_to_nand(mtd);
struct mtd_info *mtd = nand_to_mtd(nand);
struct nand_ecc_ctrl *ecc = &nand->ecc;
int offset = ((ecc->bytes + 4) * ecc->steps);
int len = mtd->oobsize - offset;
......@@ -1179,32 +1056,34 @@ static void sunxi_nfc_hw_ecc_write_extra_oob(struct mtd_info *mtd,
nand_change_write_column_op(nand, offset + mtd->writesize,
NULL, 0, false);
sunxi_nfc_randomizer_write_buf(mtd, oob + offset, len, false, page);
sunxi_nfc_randomizer_write_buf(nand, oob + offset, len, false, page);
if (cur_off)
*cur_off = mtd->oobsize + mtd->writesize;
}
static int sunxi_nfc_hw_ecc_read_page(struct nand_chip *chip, uint8_t *buf,
static int sunxi_nfc_hw_ecc_read_page(struct nand_chip *nand, uint8_t *buf,
int oob_required, int page)
{
struct mtd_info *mtd = nand_to_mtd(chip);
struct nand_ecc_ctrl *ecc = &chip->ecc;
struct mtd_info *mtd = nand_to_mtd(nand);
struct nand_ecc_ctrl *ecc = &nand->ecc;
unsigned int max_bitflips = 0;
int ret, i, cur_off = 0;
bool raw_mode = false;
nand_read_page_op(chip, page, 0, NULL, 0);
sunxi_nfc_select_chip(nand, nand->cur_cs);
nand_read_page_op(nand, page, 0, NULL, 0);
sunxi_nfc_hw_ecc_enable(mtd);
sunxi_nfc_hw_ecc_enable(nand);
for (i = 0; i < ecc->steps; i++) {
int data_off = i * ecc->size;
int oob_off = i * (ecc->bytes + 4);
u8 *data = buf + data_off;
u8 *oob = chip->oob_poi + oob_off;
u8 *oob = nand->oob_poi + oob_off;
ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob,
ret = sunxi_nfc_hw_ecc_read_chunk(nand, data, data_off, oob,
oob_off + mtd->writesize,
&cur_off, &max_bitflips,
!i, oob_required, page);
......@@ -1215,52 +1094,55 @@ static int sunxi_nfc_hw_ecc_read_page(struct nand_chip *chip, uint8_t *buf,
}
if (oob_required)
sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off,
sunxi_nfc_hw_ecc_read_extra_oob(nand, nand->oob_poi, &cur_off,
!raw_mode, page);
sunxi_nfc_hw_ecc_disable(mtd);
sunxi_nfc_hw_ecc_disable(nand);
return max_bitflips;
}
static int sunxi_nfc_hw_ecc_read_page_dma(struct nand_chip *chip, u8 *buf,
static int sunxi_nfc_hw_ecc_read_page_dma(struct nand_chip *nand, u8 *buf,
int oob_required, int page)
{
struct mtd_info *mtd = nand_to_mtd(chip);
int ret;
nand_read_page_op(chip, page, 0, NULL, 0);
sunxi_nfc_select_chip(nand, nand->cur_cs);
nand_read_page_op(nand, page, 0, NULL, 0);
ret = sunxi_nfc_hw_ecc_read_chunks_dma(mtd, buf, oob_required, page,
chip->ecc.steps);
ret = sunxi_nfc_hw_ecc_read_chunks_dma(nand, buf, oob_required, page,
nand->ecc.steps);
if (ret >= 0)
return ret;
/* Fallback to PIO mode */
return sunxi_nfc_hw_ecc_read_page(chip, buf, oob_required, page);
return sunxi_nfc_hw_ecc_read_page(nand, buf, oob_required, page);
}
static int sunxi_nfc_hw_ecc_read_subpage(struct nand_chip *chip,
static int sunxi_nfc_hw_ecc_read_subpage(struct nand_chip *nand,
u32 data_offs, u32 readlen,
u8 *bufpoi, int page)
{
struct mtd_info *mtd = nand_to_mtd(chip);
struct nand_ecc_ctrl *ecc = &chip->ecc;
struct mtd_info *mtd = nand_to_mtd(nand);
struct nand_ecc_ctrl *ecc = &nand->ecc;
int ret, i, cur_off = 0;
unsigned int max_bitflips = 0;
nand_read_page_op(chip, page, 0, NULL, 0);
sunxi_nfc_select_chip(nand, nand->cur_cs);
nand_read_page_op(nand, page, 0, NULL, 0);
sunxi_nfc_hw_ecc_enable(mtd);
sunxi_nfc_hw_ecc_enable(nand);
for (i = data_offs / ecc->size;
i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) {
int data_off = i * ecc->size;
int oob_off = i * (ecc->bytes + 4);
u8 *data = bufpoi + data_off;
u8 *oob = chip->oob_poi + oob_off;
u8 *oob = nand->oob_poi + oob_off;
ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off,
ret = sunxi_nfc_hw_ecc_read_chunk(nand, data, data_off,
oob,
oob_off + mtd->writesize,
&cur_off, &max_bitflips, !i,
......@@ -1269,113 +1151,118 @@ static int sunxi_nfc_hw_ecc_read_subpage(struct nand_chip *chip,
return ret;
}
sunxi_nfc_hw_ecc_disable(mtd);
sunxi_nfc_hw_ecc_disable(nand);
return max_bitflips;
}
static int sunxi_nfc_hw_ecc_read_subpage_dma(struct nand_chip *chip,
static int sunxi_nfc_hw_ecc_read_subpage_dma(struct nand_chip *nand,
u32 data_offs, u32 readlen,
u8 *buf, int page)
{
struct mtd_info *mtd = nand_to_mtd(chip);
int nchunks = DIV_ROUND_UP(data_offs + readlen, chip->ecc.size);
int nchunks = DIV_ROUND_UP(data_offs + readlen, nand->ecc.size);
int ret;
nand_read_page_op(chip, page, 0, NULL, 0);
sunxi_nfc_select_chip(nand, nand->cur_cs);
nand_read_page_op(nand, page, 0, NULL, 0);
ret = sunxi_nfc_hw_ecc_read_chunks_dma(mtd, buf, false, page, nchunks);
ret = sunxi_nfc_hw_ecc_read_chunks_dma(nand, buf, false, page, nchunks);
if (ret >= 0)
return ret;
/* Fallback to PIO mode */
return sunxi_nfc_hw_ecc_read_subpage(chip, data_offs, readlen,
return sunxi_nfc_hw_ecc_read_subpage(nand, data_offs, readlen,
buf, page);
}
static int sunxi_nfc_hw_ecc_write_page(struct nand_chip *chip,
static int sunxi_nfc_hw_ecc_write_page(struct nand_chip *nand,
const uint8_t *buf, int oob_required,
int page)
{
struct mtd_info *mtd = nand_to_mtd(chip);
struct nand_ecc_ctrl *ecc = &chip->ecc;
struct mtd_info *mtd = nand_to_mtd(nand);
struct nand_ecc_ctrl *ecc = &nand->ecc;
int ret, i, cur_off = 0;
nand_prog_page_begin_op(chip, page, 0, NULL, 0);
sunxi_nfc_select_chip(nand, nand->cur_cs);
nand_prog_page_begin_op(nand, page, 0, NULL, 0);
sunxi_nfc_hw_ecc_enable(mtd);
sunxi_nfc_hw_ecc_enable(nand);
for (i = 0; i < ecc->steps; i++) {
int data_off = i * ecc->size;
int oob_off = i * (ecc->bytes + 4);
const u8 *data = buf + data_off;
const u8 *oob = chip->oob_poi + oob_off;
const u8 *oob = nand->oob_poi + oob_off;
ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
ret = sunxi_nfc_hw_ecc_write_chunk(nand, data, data_off, oob,
oob_off + mtd->writesize,
&cur_off, !i, page);
if (ret)
return ret;
}
if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
if (oob_required || (nand->options & NAND_NEED_SCRAMBLING))
sunxi_nfc_hw_ecc_write_extra_oob(nand, nand->oob_poi,
&cur_off, page);
sunxi_nfc_hw_ecc_disable(mtd);
sunxi_nfc_hw_ecc_disable(nand);
return nand_prog_page_end_op(chip);
return nand_prog_page_end_op(nand);
}
static int sunxi_nfc_hw_ecc_write_subpage(struct nand_chip *chip,
static int sunxi_nfc_hw_ecc_write_subpage(struct nand_chip *nand,
u32 data_offs, u32 data_len,
const u8 *buf, int oob_required,
int page)
{
struct mtd_info *mtd = nand_to_mtd(chip);
struct nand_ecc_ctrl *ecc = &chip->ecc;
struct mtd_info *mtd = nand_to_mtd(nand);
struct nand_ecc_ctrl *ecc = &nand->ecc;
int ret, i, cur_off = 0;
nand_prog_page_begin_op(chip, page, 0, NULL, 0);
sunxi_nfc_select_chip(nand, nand->cur_cs);
nand_prog_page_begin_op(nand, page, 0, NULL, 0);
sunxi_nfc_hw_ecc_enable(mtd);
sunxi_nfc_hw_ecc_enable(nand);
for (i = data_offs / ecc->size;
i < DIV_ROUND_UP(data_offs + data_len, ecc->size); i++) {
int data_off = i * ecc->size;
int oob_off = i * (ecc->bytes + 4);
const u8 *data = buf + data_off;
const u8 *oob = chip->oob_poi + oob_off;
const u8 *oob = nand->oob_poi + oob_off;
ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob,
ret = sunxi_nfc_hw_ecc_write_chunk(nand, data, data_off, oob,
oob_off + mtd->writesize,
&cur_off, !i, page);
if (ret)
return ret;
}
sunxi_nfc_hw_ecc_disable(mtd);
sunxi_nfc_hw_ecc_disable(nand);
return nand_prog_page_end_op(chip);
return nand_prog_page_end_op(nand);
}
static int sunxi_nfc_hw_ecc_write_page_dma(struct nand_chip *chip,
static int sunxi_nfc_hw_ecc_write_page_dma(struct nand_chip *nand,
const u8 *buf,
int oob_required,
int page)
{
struct mtd_info *mtd = nand_to_mtd(chip);
struct nand_chip *nand = mtd_to_nand(mtd);
struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
struct nand_ecc_ctrl *ecc = &nand->ecc;
struct scatterlist sg;
int ret, i;
sunxi_nfc_select_chip(nand, nand->cur_cs);
ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
if (ret)
return ret;
ret = sunxi_nfc_dma_op_prepare(mtd, buf, ecc->size, ecc->steps,
ret = sunxi_nfc_dma_op_prepare(nfc, buf, ecc->size, ecc->steps,
DMA_TO_DEVICE, &sg);
if (ret)
goto pio_fallback;
......@@ -1383,14 +1270,14 @@ static int sunxi_nfc_hw_ecc_write_page_dma(struct nand_chip *chip,
for (i = 0; i < ecc->steps; i++) {
const u8 *oob = nand->oob_poi + (i * (ecc->bytes + 4));
sunxi_nfc_hw_ecc_set_prot_oob_bytes(mtd, oob, i, !i, page);
sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, i, !i, page);
}
nand_prog_page_begin_op(chip, page, 0, NULL, 0);
nand_prog_page_begin_op(nand, page, 0, NULL, 0);
sunxi_nfc_hw_ecc_enable(mtd);
sunxi_nfc_randomizer_config(mtd, page, false);
sunxi_nfc_randomizer_enable(mtd);
sunxi_nfc_hw_ecc_enable(nand);
sunxi_nfc_randomizer_config(nand, page, false);
sunxi_nfc_randomizer_enable(nand);
writel((NAND_CMD_RNDIN << 8) | NAND_CMD_PAGEPROG,
nfc->regs + NFC_REG_WCMD_SET);
......@@ -1405,46 +1292,46 @@ static int sunxi_nfc_hw_ecc_write_page_dma(struct nand_chip *chip,
if (ret)
dmaengine_terminate_all(nfc->dmac);
sunxi_nfc_randomizer_disable(mtd);
sunxi_nfc_hw_ecc_disable(mtd);
sunxi_nfc_randomizer_disable(nand);
sunxi_nfc_hw_ecc_disable(nand);
sunxi_nfc_dma_op_cleanup(mtd, DMA_TO_DEVICE, &sg);
sunxi_nfc_dma_op_cleanup(nfc, DMA_TO_DEVICE, &sg);
if (ret)
return ret;
if (oob_required || (chip->options & NAND_NEED_SCRAMBLING))
if (oob_required || (nand->options & NAND_NEED_SCRAMBLING))
/* TODO: use DMA to transfer extra OOB bytes ? */
sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi,
sunxi_nfc_hw_ecc_write_extra_oob(nand, nand->oob_poi,
NULL, page);
return nand_prog_page_end_op(chip);
return nand_prog_page_end_op(nand);
pio_fallback:
return sunxi_nfc_hw_ecc_write_page(chip, buf, oob_required, page);
return sunxi_nfc_hw_ecc_write_page(nand, buf, oob_required, page);
}
static int sunxi_nfc_hw_ecc_read_oob(struct nand_chip *chip, int page)
static int sunxi_nfc_hw_ecc_read_oob(struct nand_chip *nand, int page)
{
chip->pagebuf = -1;
nand->pagebuf = -1;
return chip->ecc.read_page(chip, chip->data_buf, 1, page);
return nand->ecc.read_page(nand, nand->data_buf, 1, page);
}
static int sunxi_nfc_hw_ecc_write_oob(struct nand_chip *chip, int page)
static int sunxi_nfc_hw_ecc_write_oob(struct nand_chip *nand, int page)
{
struct mtd_info *mtd = nand_to_mtd(chip);
struct mtd_info *mtd = nand_to_mtd(nand);
int ret;
chip->pagebuf = -1;
nand->pagebuf = -1;
memset(chip->data_buf, 0xff, mtd->writesize);
ret = chip->ecc.write_page(chip, chip->data_buf, 1, page);
memset(nand->data_buf, 0xff, mtd->writesize);
ret = nand->ecc.write_page(nand, nand->data_buf, 1, page);
if (ret)
return ret;
/* Send command to program the OOB data */
return nand_prog_page_end_op(chip);
return nand_prog_page_end_op(nand);
}
static const s32 tWB_lut[] = {6, 12, 16, 20};
......@@ -1471,8 +1358,8 @@ static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
static int sunxi_nfc_setup_data_interface(struct nand_chip *nand, int csline,
const struct nand_data_interface *conf)
{
struct sunxi_nand_chip *chip = to_sunxi_nand(nand);
struct sunxi_nfc *nfc = to_sunxi_nfc(chip->nand.controller);
struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
const struct nand_sdr_timings *timings;
u32 min_clk_period = 0;
s32 tWB, tADL, tWHR, tRHW, tCAD;
......@@ -1555,6 +1442,20 @@ static int sunxi_nfc_setup_data_interface(struct nand_chip *nand, int csline,
if (timings->tRHW_min > (min_clk_period * 20))
min_clk_period = DIV_ROUND_UP(timings->tRHW_min, 20);
/*
* In non-EDO, tREA should be less than tRP to guarantee that the
* controller does not sample the IO lines too early. Unfortunately,
* the sunxi NAND controller does not allow us to have different
* values for tRP and tREH (tRP = tREH = tRW / 2).
*
* We have 2 options to overcome this limitation:
*
* 1/ Extend tRC to fulfil the tREA <= tRC / 2 constraint
* 2/ Use EDO mode (only works if timings->tRLOH > 0)
*/
if (timings->tREA_max > min_clk_period && !timings->tRLOH_min)
min_clk_period = timings->tREA_max;
tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
min_clk_period);
if (tWB < 0) {
......@@ -1591,7 +1492,7 @@ static int sunxi_nfc_setup_data_interface(struct nand_chip *nand, int csline,
tCAD = 0x7;
/* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
sunxi_nand->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
/* Convert min_clk_period from picoseconds to nanoseconds */
min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
......@@ -1602,21 +1503,24 @@ static int sunxi_nfc_setup_data_interface(struct nand_chip *nand, int csline,
* This new formula was verified with a scope and validated by
* Allwinner engineers.
*/
chip->clk_rate = NSEC_PER_SEC / min_clk_period;
real_clk_rate = clk_round_rate(nfc->mod_clk, chip->clk_rate);
sunxi_nand->clk_rate = NSEC_PER_SEC / min_clk_period;
real_clk_rate = clk_round_rate(nfc->mod_clk, sunxi_nand->clk_rate);
if (real_clk_rate <= 0) {
dev_err(nfc->dev, "Unable to round clk %lu\n", chip->clk_rate);
dev_err(nfc->dev, "Unable to round clk %lu\n",
sunxi_nand->clk_rate);
return -EINVAL;
}
sunxi_nand->timing_ctl = 0;
/*
* ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
* output cycle timings shall be used if the host drives tRC less than
* 30 ns.
* 30 ns. We should also use EDO mode if tREA is bigger than tRP.
*/
min_clk_period = NSEC_PER_SEC / real_clk_rate;
chip->timing_ctl = ((min_clk_period * 2) < 30) ?
NFC_TIMING_CTL_EDO : 0;
if (min_clk_period * 2 < 30 || min_clk_period * 1000 < timings->tREA_max)
sunxi_nand->timing_ctl = NFC_TIMING_CTL_EDO;
return 0;
}
......@@ -1677,14 +1581,13 @@ static void sunxi_nand_hw_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
kfree(ecc->priv);
}
static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
static int sunxi_nand_hw_ecc_ctrl_init(struct nand_chip *nand,
struct nand_ecc_ctrl *ecc,
struct device_node *np)
{
static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
struct nand_chip *nand = mtd_to_nand(mtd);
struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
struct mtd_info *mtd = nand_to_mtd(nand);
struct sunxi_nand_hw_ecc *data;
int nsectors;
int ret;
......@@ -1808,7 +1711,6 @@ static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
static int sunxi_nand_attach_chip(struct nand_chip *nand)
{
struct mtd_info *mtd = nand_to_mtd(nand);
struct nand_ecc_ctrl *ecc = &nand->ecc;
struct device_node *np = nand_get_flash_node(nand);
int ret;
......@@ -1831,7 +1733,7 @@ static int sunxi_nand_attach_chip(struct nand_chip *nand)
switch (ecc->mode) {
case NAND_ECC_HW:
ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc, np);
ret = sunxi_nand_hw_ecc_ctrl_init(nand, ecc, np);
if (ret)
return ret;
break;
......@@ -1845,15 +1747,165 @@ static int sunxi_nand_attach_chip(struct nand_chip *nand)
return 0;
}
static int sunxi_nfc_exec_subop(struct nand_chip *nand,
const struct nand_subop *subop)
{
struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
u32 cmd = 0, extcmd = 0, cnt = 0, addrs[2] = { };
unsigned int i, j, remaining, start;
void *inbuf = NULL;
int ret;
for (i = 0; i < subop->ninstrs; i++) {
const struct nand_op_instr *instr = &subop->instrs[i];
switch (instr->type) {
case NAND_OP_CMD_INSTR:
if (cmd & NFC_SEND_CMD1) {
if (WARN_ON(cmd & NFC_SEND_CMD2))
return -EINVAL;
cmd |= NFC_SEND_CMD2;
extcmd |= instr->ctx.cmd.opcode;
} else {
cmd |= NFC_SEND_CMD1 |
NFC_CMD(instr->ctx.cmd.opcode);
}
break;
case NAND_OP_ADDR_INSTR:
remaining = nand_subop_get_num_addr_cyc(subop, i);
start = nand_subop_get_addr_start_off(subop, i);
for (j = 0; j < 8 && j + start < remaining; j++) {
u32 addr = instr->ctx.addr.addrs[j + start];
addrs[j / 4] |= addr << (j % 4) * 8;
}
if (j)
cmd |= NFC_SEND_ADR | NFC_ADR_NUM(j);
break;
case NAND_OP_DATA_IN_INSTR:
case NAND_OP_DATA_OUT_INSTR:
start = nand_subop_get_data_start_off(subop, i);
remaining = nand_subop_get_data_len(subop, i);
cnt = min_t(u32, remaining, NFC_SRAM_SIZE);
cmd |= NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
if (instr->type == NAND_OP_DATA_OUT_INSTR) {
cmd |= NFC_ACCESS_DIR;
memcpy_toio(nfc->regs + NFC_RAM0_BASE,
instr->ctx.data.buf.out + start,
cnt);
} else {
inbuf = instr->ctx.data.buf.in + start;
}
break;
case NAND_OP_WAITRDY_INSTR:
cmd |= NFC_WAIT_FLAG;
break;
}
}
ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
if (ret)
return ret;
if (cmd & NFC_SEND_ADR) {
writel(addrs[0], nfc->regs + NFC_REG_ADDR_LOW);
writel(addrs[1], nfc->regs + NFC_REG_ADDR_HIGH);
}
if (cmd & NFC_SEND_CMD2)
writel(extcmd,
nfc->regs +
(cmd & NFC_ACCESS_DIR ?
NFC_REG_WCMD_SET : NFC_REG_RCMD_SET));
if (cmd & NFC_DATA_TRANS)
writel(cnt, nfc->regs + NFC_REG_CNT);
writel(cmd, nfc->regs + NFC_REG_CMD);
ret = sunxi_nfc_wait_events(nfc, NFC_CMD_INT_FLAG,
!(cmd & NFC_WAIT_FLAG) && cnt < 64,
0);
if (ret)
return ret;
if (inbuf)
memcpy_fromio(inbuf, nfc->regs + NFC_RAM0_BASE, cnt);
return 0;
}
static int sunxi_nfc_soft_waitrdy(struct nand_chip *nand,
const struct nand_subop *subop)
{
return nand_soft_waitrdy(nand,
subop->instrs[0].ctx.waitrdy.timeout_ms);
}
static const struct nand_op_parser sunxi_nfc_op_parser = NAND_OP_PARSER(
NAND_OP_PARSER_PATTERN(sunxi_nfc_exec_subop,
NAND_OP_PARSER_PAT_CMD_ELEM(true),
NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
NAND_OP_PARSER_PAT_CMD_ELEM(true),
NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, 1024)),
NAND_OP_PARSER_PATTERN(sunxi_nfc_exec_subop,
NAND_OP_PARSER_PAT_CMD_ELEM(true),
NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
NAND_OP_PARSER_PAT_DATA_OUT_ELEM(true, 1024),
NAND_OP_PARSER_PAT_CMD_ELEM(true),
NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
);
static const struct nand_op_parser sunxi_nfc_norb_op_parser = NAND_OP_PARSER(
NAND_OP_PARSER_PATTERN(sunxi_nfc_exec_subop,
NAND_OP_PARSER_PAT_CMD_ELEM(true),
NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
NAND_OP_PARSER_PAT_CMD_ELEM(true),
NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, 1024)),
NAND_OP_PARSER_PATTERN(sunxi_nfc_exec_subop,
NAND_OP_PARSER_PAT_CMD_ELEM(true),
NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
NAND_OP_PARSER_PAT_DATA_OUT_ELEM(true, 1024),
NAND_OP_PARSER_PAT_CMD_ELEM(true)),
NAND_OP_PARSER_PATTERN(sunxi_nfc_soft_waitrdy,
NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
);
static int sunxi_nfc_exec_op(struct nand_chip *nand,
const struct nand_operation *op, bool check_only)
{
struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
const struct nand_op_parser *parser;
sunxi_nfc_select_chip(nand, op->cs);
if (sunxi_nand->sels[op->cs].rb >= 0)
parser = &sunxi_nfc_op_parser;
else
parser = &sunxi_nfc_norb_op_parser;
return nand_op_parser_exec_op(nand, parser, op, check_only);
}
static const struct nand_controller_ops sunxi_nand_controller_ops = {
.attach_chip = sunxi_nand_attach_chip,
.setup_data_interface = sunxi_nfc_setup_data_interface,
.exec_op = sunxi_nfc_exec_op,
};
static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
struct device_node *np)
{
struct sunxi_nand_chip *chip;
struct sunxi_nand_chip *sunxi_nand;
struct mtd_info *mtd;
struct nand_chip *nand;
int nsels;
......@@ -1870,17 +1922,14 @@ static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
return -EINVAL;
}
chip = devm_kzalloc(dev,
sizeof(*chip) +
(nsels * sizeof(struct sunxi_nand_chip_sel)),
sunxi_nand = devm_kzalloc(dev, struct_size(sunxi_nand, sels, nsels),
GFP_KERNEL);
if (!chip) {
if (!sunxi_nand) {
dev_err(dev, "could not allocate chip\n");
return -ENOMEM;
}
chip->nsels = nsels;
chip->selected = -1;
sunxi_nand->nsels = nsels;
for (i = 0; i < nsels; i++) {
ret = of_property_read_u32_index(np, "reg", i, &tmp);
......@@ -1902,18 +1951,17 @@ static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
return -EINVAL;
}
chip->sels[i].cs = tmp;
sunxi_nand->sels[i].cs = tmp;
if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) &&
tmp < 2)
chip->sels[i].rb = tmp;
sunxi_nand->sels[i].rb = tmp;
else
chip->sels[i].rb = -1;
sunxi_nand->sels[i].rb = -1;
}
nand = &chip->nand;
nand = &sunxi_nand->nand;
/* Default tR value specified in the ONFI spec (chapter 4.15.1) */
nand->legacy.chip_delay = 200;
nand->controller = &nfc->controller;
nand->controller->ops = &sunxi_nand_controller_ops;
......@@ -1923,11 +1971,6 @@ static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
*/
nand->ecc.mode = NAND_ECC_HW;
nand_set_flash_node(nand, np);
nand->legacy.select_chip = sunxi_nfc_select_chip;
nand->legacy.cmd_ctrl = sunxi_nfc_cmd_ctrl;
nand->legacy.read_buf = sunxi_nfc_read_buf;
nand->legacy.write_buf = sunxi_nfc_write_buf;
nand->legacy.read_byte = sunxi_nfc_read_byte;
mtd = nand_to_mtd(nand);
mtd->dev.parent = dev;
......@@ -1943,7 +1986,7 @@ static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
return ret;
}
list_add_tail(&chip->node, &nfc->chips);
list_add_tail(&sunxi_nand->node, &nfc->chips);
return 0;
}
......@@ -1973,14 +2016,15 @@ static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
{
struct sunxi_nand_chip *chip;
struct sunxi_nand_chip *sunxi_nand;
while (!list_empty(&nfc->chips)) {
chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip,
sunxi_nand = list_first_entry(&nfc->chips,
struct sunxi_nand_chip,
node);
nand_release(&chip->nand);
sunxi_nand_ecc_cleanup(&chip->nand.ecc);
list_del(&chip->node);
nand_release(&sunxi_nand->nand);
sunxi_nand_ecc_cleanup(&sunxi_nand->nand.ecc);
list_del(&sunxi_nand->node);
}
}
......@@ -2124,7 +2168,7 @@ static struct platform_driver sunxi_nfc_driver = {
};
module_platform_driver(sunxi_nfc_driver);
MODULE_LICENSE("GPL v2");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Boris BREZILLON");
MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
MODULE_ALIAS("platform:sunxi_nand");
drivers/mtd/nand/raw/tmio_nand.c
View file @ 9220d7be
......@@ -104,6 +104,7 @@
struct tmio_nand {
struct nand_chip chip;
struct completion comp;
struct platform_device *dev;
......@@ -168,15 +169,11 @@ static int tmio_nand_dev_ready(struct nand_chip *chip)
static irqreturn_t tmio_irq(int irq, void *__tmio)
{
struct tmio_nand *tmio = __tmio;
struct nand_chip *nand_chip = &tmio->chip;
/* disable RDYREQ interrupt */
tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
complete(&tmio->comp);
if (unlikely(!waitqueue_active(&nand_chip->controller->wq)))
dev_warn(&tmio->dev->dev, "spurious interrupt\n");
wake_up(&nand_chip->controller->wq);
return IRQ_HANDLED;
}
......@@ -193,18 +190,18 @@ static int tmio_nand_wait(struct nand_chip *nand_chip)
u8 status;
/* enable RDYREQ interrupt */
tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);
reinit_completion(&tmio->comp);
tmio_iowrite8(0x81, tmio->fcr + FCR_IMR);
timeout = wait_event_timeout(nand_chip->controller->wq,
tmio_nand_dev_ready(nand_chip),
msecs_to_jiffies(nand_chip->state == FL_ERASING ? 400 : 20));
timeout = 400;
timeout = wait_for_completion_timeout(&tmio->comp,
msecs_to_jiffies(timeout));
if (unlikely(!tmio_nand_dev_ready(nand_chip))) {
tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
dev_warn(&tmio->dev->dev, "still busy with %s after %d ms\n",
nand_chip->state == FL_ERASING ? "erase" : "program",
nand_chip->state == FL_ERASING ? 400 : 20);
dev_warn(&tmio->dev->dev, "still busy after 400 ms\n");
} else if (unlikely(!timeout)) {
tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
......@@ -378,6 +375,8 @@ static int tmio_probe(struct platform_device *dev)
if (!tmio)
return -ENOMEM;
init_completion(&tmio->comp);
tmio->dev = dev;
platform_set_drvdata(dev, tmio);
......
drivers/mtd/nand/spi/gigadevice.c
View file @ 9220d7be
......@@ -12,6 +12,8 @@
#define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4)
#define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4)
#define GD5FXGQ4UEXXG_REG_STATUS2 0xf0
static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
......@@ -81,11 +83,83 @@ static int gd5fxgq4xa_ecc_get_status(struct spinand_device *spinand,
return -EINVAL;
}
static int gd5fxgq4uexxg_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
return -ERANGE;
region->offset = 64;
region->length = 64;
return 0;
}
static int gd5fxgq4uexxg_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
return -ERANGE;
/* Reserve 1 bytes for the BBM. */
region->offset = 1;
region->length = 63;
return 0;
}
static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
u8 status)
{
u8 status2;
struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4UEXXG_REG_STATUS2,
&status2);
int ret;
switch (status & STATUS_ECC_MASK) {
case STATUS_ECC_NO_BITFLIPS:
return 0;
case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS:
/*
* Read status2 register to determine a more fine grained
* bit error status
*/
ret = spi_mem_exec_op(spinand->spimem, &op);
if (ret)
return ret;
/*
* 4 ... 7 bits are flipped (1..4 can't be detected, so
* report the maximum of 4 in this case
*/
/* bits sorted this way (3...0): ECCS1,ECCS0,ECCSE1,ECCSE0 */
return ((status & STATUS_ECC_MASK) >> 2) |
((status2 & STATUS_ECC_MASK) >> 4);
case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS:
return 8;
case STATUS_ECC_UNCOR_ERROR:
return -EBADMSG;
default:
break;
}
return -EINVAL;
}
static const struct mtd_ooblayout_ops gd5fxgq4xa_ooblayout = {
.ecc = gd5fxgq4xa_ooblayout_ecc,
.free = gd5fxgq4xa_ooblayout_free,
};
static const struct mtd_ooblayout_ops gd5fxgq4uexxg_ooblayout = {
.ecc = gd5fxgq4uexxg_ooblayout_ecc,
.free = gd5fxgq4uexxg_ooblayout_free,
};
static const struct spinand_info gigadevice_spinand_table[] = {
SPINAND_INFO("GD5F1GQ4xA", 0xF1,
NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
......@@ -114,6 +188,15 @@ static const struct spinand_info gigadevice_spinand_table[] = {
0,
SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
gd5fxgq4xa_ecc_get_status)),
SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&gd5fxgq4uexxg_ooblayout,
gd5fxgq4uexxg_ecc_get_status)),
};
static int gigadevice_spinand_detect(struct spinand_device *spinand)
......
drivers/mtd/nand/spi/macronix.c
View file @ 9220d7be
......@@ -10,6 +10,7 @@
#include <linux/mtd/spinand.h>
#define SPINAND_MFR_MACRONIX 0xC2
#define MACRONIX_ECCSR_MASK 0x0F
static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
......@@ -55,7 +56,12 @@ static int mx35lf1ge4ab_get_eccsr(struct spinand_device *spinand, u8 *eccsr)
SPI_MEM_OP_DUMMY(1, 1),
SPI_MEM_OP_DATA_IN(1, eccsr, 1));
return spi_mem_exec_op(spinand->spimem, &op);
int ret = spi_mem_exec_op(spinand->spimem, &op);
if (ret)
return ret;
*eccsr &= MACRONIX_ECCSR_MASK;
return 0;
}
static int mx35lf1ge4ab_ecc_get_status(struct spinand_device *spinand,
......
drivers/mtd/nand/spi/toshiba.c
View file @ 9220d7be
......@@ -25,19 +25,19 @@ static SPINAND_OP_VARIANTS(write_cache_variants,
static SPINAND_OP_VARIANTS(update_cache_variants,
SPINAND_PROG_LOAD(false, 0, NULL, 0));
static int tc58cvg2s0h_ooblayout_ecc(struct mtd_info *mtd, int section,
static int tc58cxgxsx_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section > 7)
if (section > 0)
return -ERANGE;
region->offset = 128 + 16 * section;
region->length = 16;
region->offset = mtd->oobsize / 2;
region->length = mtd->oobsize / 2;
return 0;
}
static int tc58cvg2s0h_ooblayout_free(struct mtd_info *mtd, int section,
static int tc58cxgxsx_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section > 0)
......@@ -45,17 +45,17 @@ static int tc58cvg2s0h_ooblayout_free(struct mtd_info *mtd, int section,
/* 2 bytes reserved for BBM */
region->offset = 2;
region->length = 126;
region->length = (mtd->oobsize / 2) - 2;
return 0;
}
static const struct mtd_ooblayout_ops tc58cvg2s0h_ooblayout = {
.ecc = tc58cvg2s0h_ooblayout_ecc,
.free = tc58cvg2s0h_ooblayout_free,
static const struct mtd_ooblayout_ops tc58cxgxsx_ooblayout = {
.ecc = tc58cxgxsx_ooblayout_ecc,
.free = tc58cxgxsx_ooblayout_free,
};
static int tc58cvg2s0h_ecc_get_status(struct spinand_device *spinand,
static int tc58cxgxsx_ecc_get_status(struct spinand_device *spinand,
u8 status)
{
struct nand_device *nand = spinand_to_nand(spinand);
......@@ -94,15 +94,66 @@ static int tc58cvg2s0h_ecc_get_status(struct spinand_device *spinand,
}
static const struct spinand_info toshiba_spinand_table[] = {
SPINAND_INFO("TC58CVG2S0H", 0xCD,
/* 3.3V 1Gb */
SPINAND_INFO("TC58CVG0S3", 0xC2,
NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
tc58cxgxsx_ecc_get_status)),
/* 3.3V 2Gb */
SPINAND_INFO("TC58CVG1S3", 0xCB,
NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
tc58cxgxsx_ecc_get_status)),
/* 3.3V 4Gb */
SPINAND_INFO("TC58CVG2S0", 0xCD,
NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
tc58cxgxsx_ecc_get_status)),
/* 1.8V 1Gb */
SPINAND_INFO("TC58CYG0S3", 0xB2,
NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
tc58cxgxsx_ecc_get_status)),
/* 1.8V 2Gb */
SPINAND_INFO("TC58CYG1S3", 0xBB,
NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
tc58cxgxsx_ecc_get_status)),
/* 1.8V 4Gb */
SPINAND_INFO("TC58CYG2S0", 0xBD,
NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&tc58cvg2s0h_ooblayout,
tc58cvg2s0h_ecc_get_status)),
0,
SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
tc58cxgxsx_ecc_get_status)),
};
static int toshiba_spinand_detect(struct spinand_device *spinand)
......
include/linux/mtd/rawnand.h
View file @ 9220d7be
......@@ -16,13 +16,12 @@
#ifndef __LINUX_MTD_RAWNAND_H
#define __LINUX_MTD_RAWNAND_H
#include <linux/wait.h>
#include <linux/spinlock.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/flashchip.h>
#include <linux/mtd/bbm.h>
#include <linux/mtd/jedec.h>
#include <linux/mtd/onfi.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/types.h>
......@@ -897,25 +896,17 @@ struct nand_controller_ops {
/**
* struct nand_controller - Structure used to describe a NAND controller
*
* @lock: protection lock
* @active: the mtd device which holds the controller currently
* @wq: wait queue to sleep on if a NAND operation is in
* progress used instead of the per chip wait queue
* when a hw controller is available.
* @lock: lock used to serialize accesses to the NAND controller
* @ops: NAND controller operations.
*/
struct nand_controller {
spinlock_t lock;
struct nand_chip *active;
wait_queue_head_t wq;
struct mutex lock;
const struct nand_controller_ops *ops;
};
static inline void nand_controller_init(struct nand_controller *nfc)
{
nfc->active = NULL;
spin_lock_init(&nfc->lock);
init_waitqueue_head(&nfc->wq);
mutex_init(&nfc->lock);
}
/**
......@@ -936,7 +927,6 @@ static inline void nand_controller_init(struct nand_controller *nfc)
* @waitfunc: hardware specific function for wait on ready.
* @block_bad: check if a block is bad, using OOB markers
* @block_markbad: mark a block bad
* @erase: erase function
* @set_features: set the NAND chip features
* @get_features: get the NAND chip features
* @chip_delay: chip dependent delay for transferring data from array to read
......@@ -962,7 +952,6 @@ struct nand_legacy {
int (*waitfunc)(struct nand_chip *chip);
int (*block_bad)(struct nand_chip *chip, loff_t ofs);
int (*block_markbad)(struct nand_chip *chip, loff_t ofs);
int (*erase)(struct nand_chip *chip, int page);
int (*set_features)(struct nand_chip *chip, int feature_addr,
u8 *subfeature_para);
int (*get_features)(struct nand_chip *chip, int feature_addr,
......@@ -983,7 +972,6 @@ struct nand_legacy {
* setting the read-retry mode. Mostly needed for MLC NAND.
* @ecc: [BOARDSPECIFIC] ECC control structure
* @buf_align: minimum buffer alignment required by a platform
* @state: [INTERN] the current state of the NAND device
* @oob_poi: "poison value buffer," used for laying out OOB data
* before writing
* @page_shift: [INTERN] number of address bits in a page (column
......@@ -1034,6 +1022,9 @@ struct nand_legacy {
* cur_cs < numchips. NAND Controller drivers should not
* modify this value, but they're allowed to read it.
* @read_retries: [INTERN] the number of read retry modes supported
* @lock: lock protecting the suspended field. Also used to
* serialize accesses to the NAND device.
* @suspended: set to 1 when the device is suspended, 0 when it's not.
* @bbt: [INTERN] bad block table pointer
* @bbt_td: [REPLACEABLE] bad block table descriptor for flash
* lookup.
......@@ -1088,7 +1079,8 @@ struct nand_chip {
int read_retries;
flstate_t state;
struct mutex lock;
unsigned int suspended : 1;
uint8_t *oob_poi;
struct nand_controller *controller;
......
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