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Commit 92d3a35c authored by Alexandre Torgue's avatar Alexandre Torgue
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ARM: dts: stm32: Adapt stm32mp157 pinctrl to manage STM32MP15xx SOCs family 

This commit modifies stm32mp157 pinctrl files to better manage STM32MP15xx
SOCs diversity. Pin controller and gpio controller are moved to common SOC
dtsi file. Only pin groups remain in the main pinctrl dtsi file.
Signed-off-by: default avatarAlexandre Torgue <alexandre.torgue@st.com>
parent ac4533a8
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arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
View file @ 92d3a35c
...@@ -5,1236 +5,1083 @@ ...@@ -5,1236 +5,1083 @@
*/ */
#include <dt-bindings/pinctrl/stm32-pinfunc.h> #include <dt-bindings/pinctrl/stm32-pinfunc.h>
/ { &pinctrl {
soc { adc1_in6_pins_a: adc1-in6 {
pinctrl: pin-controller@50002000 { pins {
#address-cells = <1>; pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
#size-cells = <1>; };
compatible = "st,stm32mp157-pinctrl"; };
ranges = <0 0x50002000 0xa400>;
interrupt-parent = <&exti>; adc12_ain_pins_a: adc12-ain-0 {
st,syscfg = <&exti 0x60 0xff>; pins {
pins-are-numbered; pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */
<STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
gpioa: gpio@50002000 { <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */
gpio-controller; <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */
#gpio-cells = <2>; };
interrupt-controller; };
#interrupt-cells = <2>;
reg = <0x0 0x400>; adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
clocks = <&rcc GPIOA>; pins {
st,bank-name = "GPIOA"; pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
status = "disabled"; <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
}; };
};
gpiob: gpio@50003000 {
gpio-controller; cec_pins_a: cec-0 {
#gpio-cells = <2>; pins {
interrupt-controller; pinmux = <STM32_PINMUX('A', 15, AF4)>;
#interrupt-cells = <2>; bias-disable;
reg = <0x1000 0x400>; drive-open-drain;
clocks = <&rcc GPIOB>; slew-rate = <0>;
st,bank-name = "GPIOB"; };
status = "disabled"; };
};
cec_pins_sleep_a: cec-sleep-0 {
gpioc: gpio@50004000 { pins {
gpio-controller; pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
#gpio-cells = <2>; };
interrupt-controller; };
#interrupt-cells = <2>;
reg = <0x2000 0x400>; cec_pins_b: cec-1 {
clocks = <&rcc GPIOC>; pins {
st,bank-name = "GPIOC"; pinmux = <STM32_PINMUX('B', 6, AF5)>;
status = "disabled"; bias-disable;
}; drive-open-drain;
slew-rate = <0>;
gpiod: gpio@50005000 { };
gpio-controller; };
#gpio-cells = <2>;
interrupt-controller; cec_pins_sleep_b: cec-sleep-1 {
#interrupt-cells = <2>; pins {
reg = <0x3000 0x400>; pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
clocks = <&rcc GPIOD>; };
st,bank-name = "GPIOD"; };
status = "disabled";
}; dac_ch1_pins_a: dac-ch1 {
pins {
gpioe: gpio@50006000 { pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
gpio-controller; };
#gpio-cells = <2>; };
interrupt-controller;
#interrupt-cells = <2>; dac_ch2_pins_a: dac-ch2 {
reg = <0x4000 0x400>; pins {
clocks = <&rcc GPIOE>; pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
st,bank-name = "GPIOE"; };
status = "disabled"; };
};
dcmi_pins_a: dcmi-0 {
gpiof: gpio@50007000 { pins {
gpio-controller; pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
#gpio-cells = <2>; <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
interrupt-controller; <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
#interrupt-cells = <2>; <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
reg = <0x5000 0x400>; <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
clocks = <&rcc GPIOF>; <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
st,bank-name = "GPIOF"; <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
status = "disabled"; <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
}; <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
<STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
gpiog: gpio@50008000 { <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
gpio-controller; <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
#gpio-cells = <2>; <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
interrupt-controller; <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
#interrupt-cells = <2>; <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
reg = <0x6000 0x400>; bias-disable;
clocks = <&rcc GPIOG>; };
st,bank-name = "GPIOG"; };
status = "disabled";
}; dcmi_sleep_pins_a: dcmi-sleep-0 {
pins {
gpioh: gpio@50009000 { pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
gpio-controller; <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
#gpio-cells = <2>; <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
interrupt-controller; <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
#interrupt-cells = <2>; <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
reg = <0x7000 0x400>; <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
clocks = <&rcc GPIOH>; <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
st,bank-name = "GPIOH"; <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
status = "disabled"; <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
}; <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
<STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
gpioi: gpio@5000a000 { <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
gpio-controller; <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
#gpio-cells = <2>; <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
interrupt-controller; <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
#interrupt-cells = <2>; };
reg = <0x8000 0x400>; };
clocks = <&rcc GPIOI>;
st,bank-name = "GPIOI"; ethernet0_rgmii_pins_a: rgmii-0 {
status = "disabled"; pins1 {
}; pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
gpioj: gpio@5000b000 { <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
gpio-controller; <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
#gpio-cells = <2>; <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
interrupt-controller; <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
#interrupt-cells = <2>; <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
reg = <0x9000 0x400>; <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
clocks = <&rcc GPIOJ>; <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
st,bank-name = "GPIOJ"; bias-disable;
status = "disabled"; drive-push-pull;
}; slew-rate = <3>;
};
gpiok: gpio@5000c000 { pins2 {
gpio-controller; pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
#gpio-cells = <2>; <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
interrupt-controller; <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
#interrupt-cells = <2>; <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
reg = <0xa000 0x400>; <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
clocks = <&rcc GPIOK>; <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
st,bank-name = "GPIOK"; bias-disable;
status = "disabled"; };
}; };
adc1_in6_pins_a: adc1-in6 { ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
pins { pins1 {
pinmux = <STM32_PINMUX('F', 12, ANALOG)>; pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
}; <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
}; <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
adc12_ain_pins_a: adc12-ain-0 { <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
pins { <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
<STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
<STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
<STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
}; <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
}; <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 { <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
pins { <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */ };
<STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */ };
};
}; fmc_pins_a: fmc-0 {
pins1 {
cec_pins_a: cec-0 { pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
pins { <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
pinmux = <STM32_PINMUX('A', 15, AF4)>; <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
bias-disable; <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
drive-open-drain; <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
slew-rate = <0>; <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
}; <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
}; <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
<STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
cec_pins_sleep_a: cec-sleep-0 { <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
pins { <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */ <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
}; <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
}; bias-disable;
drive-push-pull;
cec_pins_b: cec-1 { slew-rate = <1>;
pins { };
pinmux = <STM32_PINMUX('B', 6, AF5)>; pins2 {
bias-disable; pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
drive-open-drain; bias-pull-up;
slew-rate = <0>; };
}; };
};
fmc_sleep_pins_a: fmc-sleep-0 {
cec_pins_sleep_b: cec-sleep-1 { pins {
pins { pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */ <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
}; <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
}; <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
<STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
dac_ch1_pins_a: dac-ch1 { <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
pins { <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
pinmux = <STM32_PINMUX('A', 4, ANALOG)>; <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
}; <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
}; <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
<STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
dac_ch2_pins_a: dac-ch2 { <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
pins { <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
pinmux = <STM32_PINMUX('A', 5, ANALOG)>; <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
}; };
}; };
dcmi_pins_a: dcmi-0 { i2c1_pins_a: i2c1-0 {
pins { pins {
pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */ pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
<STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
<STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ bias-disable;
<STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */ drive-open-drain;
<STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ slew-rate = <0>;
<STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */ };
<STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */ };
<STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
<STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */ i2c1_pins_sleep_a: i2c1-1 {
<STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */ pins {
<STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */ pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
<STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */ <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
<STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */ };
<STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */ };
<STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
bias-disable; i2c1_pins_b: i2c1-2 {
}; pins {
}; pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
<STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
dcmi_sleep_pins_a: dcmi-sleep-0 { bias-disable;
pins { drive-open-drain;
pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */ slew-rate = <0>;
<STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ };
<STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ };
<STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
<STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ i2c1_pins_sleep_b: i2c1-3 {
<STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */ pins {
<STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */ pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
<STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */ <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
<STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */ };
<STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */ };
<STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
<STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */ i2c2_pins_a: i2c2-0 {
<STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */ pins {
<STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */ pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
<STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */ <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
}; bias-disable;
}; drive-open-drain;
slew-rate = <0>;
ethernet0_rgmii_pins_a: rgmii-0 { };
pins1 { };
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ i2c2_pins_sleep_a: i2c2-1 {
<STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ pins {
<STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
<STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
<STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ };
<STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ };
<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
<STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ i2c2_pins_b1: i2c2-2 {
bias-disable; pins {
drive-push-pull; pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
slew-rate = <3>; bias-disable;
}; drive-open-drain;
pins2 { slew-rate = <0>;
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ };
<STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ };
<STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ i2c2_pins_sleep_b1: i2c2-3 {
<STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ pins {
<STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
bias-disable; };
}; };
};
i2c5_pins_a: i2c5-0 {
ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 { pins {
pins1 { pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
<STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ bias-disable;
<STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ drive-open-drain;
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ slew-rate = <0>;
<STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ };
<STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ };
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
<STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ i2c5_pins_sleep_a: i2c5-1 {
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ pins {
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
<STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ };
<STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ };
<STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
}; i2s2_pins_a: i2s2-0 {
}; pins {
pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
fmc_pins_a: fmc-0 { <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
pins1 { <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ slew-rate = <1>;
<STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ drive-push-pull;
<STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */ bias-disable;
<STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */ };
<STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ };
<STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
<STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ i2s2_pins_sleep_a: i2s2-1 {
<STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ pins {
<STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
<STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
<STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
<STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ };
<STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */ };
bias-disable;
drive-push-pull; ltdc_pins_a: ltdc-a-0 {
slew-rate = <1>; pins {
}; pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
pins2 { <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */ <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
bias-pull-up; <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
}; <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
}; <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
<STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
fmc_sleep_pins_a: fmc-sleep-0 { <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
pins { <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
<STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */ <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
<STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */ <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
<STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */ <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
<STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */ <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
<STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */ <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
<STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */ <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
<STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */ <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
<STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */ <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
<STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */ <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
<STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */ <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
<STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */ <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
<STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */ <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
<STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */ <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
}; <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
}; <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
<STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
i2c1_pins_a: i2c1-0 { <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
pins { <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ bias-disable;
<STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ drive-push-pull;
bias-disable; slew-rate = <1>;
drive-open-drain; };
slew-rate = <0>; };
};
}; ltdc_pins_sleep_a: ltdc-a-1 {
pins {
i2c1_pins_sleep_a: i2c1-1 { pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
pins { <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
<STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
}; <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
}; <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
<STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
i2c1_pins_b: i2c1-2 { <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
pins { <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */ <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
<STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
bias-disable; <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
drive-open-drain; <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
slew-rate = <0>; <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
}; <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
}; <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
<STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
i2c1_pins_sleep_b: i2c1-3 { <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
pins { <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */ <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
<STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
}; <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
}; <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
<STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
i2c2_pins_a: i2c2-0 { <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
pins { <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */ <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
<STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
bias-disable; };
drive-open-drain; };
slew-rate = <0>;
}; ltdc_pins_b: ltdc-b-0 {
}; pins {
pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
i2c2_pins_sleep_a: i2c2-1 { <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
pins { <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */ <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
<STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
}; <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
}; <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
<STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
i2c2_pins_b1: i2c2-2 { <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
pins { <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
bias-disable; <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
drive-open-drain; <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
slew-rate = <0>; <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
}; <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
}; <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
<STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
i2c2_pins_sleep_b1: i2c2-3 { <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
pins { <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
}; <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
}; <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
<STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
i2c5_pins_a: i2c5-0 { <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
pins { <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */ <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
<STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */ <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
bias-disable; <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
drive-open-drain; bias-disable;
slew-rate = <0>; drive-push-pull;
}; slew-rate = <1>;
}; };
};
i2c5_pins_sleep_a: i2c5-1 {
pins { ltdc_pins_sleep_b: ltdc-b-1 {
pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */ pins {
<STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */ pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
<STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
}; <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
}; <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
<STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
i2s2_pins_a: i2s2-0 { <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
pins { <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */ <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
<STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */ <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
<STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */ <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
slew-rate = <1>; <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
drive-push-pull; <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
bias-disable; <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
}; <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
}; <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
<STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
i2s2_pins_sleep_a: i2s2-1 { <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
pins { <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */ <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
<STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */ <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
<STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */ <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
}; <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
}; <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
<STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
ltdc_pins_a: ltdc-a-0 { <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
pins { <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */ <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
<STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
<STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ };
<STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */ };
<STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
<STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ m_can1_pins_a: m-can1-0 {
<STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ pins1 {
<STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
<STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */ slew-rate = <1>;
<STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */ drive-push-pull;
<STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ bias-disable;
<STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ };
<STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ pins2 {
<STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */ pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
<STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ bias-disable;
<STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */ };
<STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ };
<STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
<STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */ m_can1_sleep_pins_a: m_can1-sleep-0 {
<STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */ pins {
<STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
<STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
<STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ };
<STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ };
<STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
<STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ pwm1_pins_a: pwm1-0 {
<STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ pins {
<STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */ pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
bias-disable; <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */
drive-push-pull; <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */
slew-rate = <1>; bias-pull-down;
}; drive-push-pull;
}; slew-rate = <0>;
};
ltdc_pins_sleep_a: ltdc-a-1 { };
pins {
pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ pwm1_sleep_pins_a: pwm1-sleep-0 {
<STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ pins {
<STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */
<STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */ <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */
<STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */ <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */
<STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ };
<STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ };
<STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
<STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */ pwm2_pins_a: pwm2-0 {
<STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */ pins {
<STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
<STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ bias-pull-down;
<STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ drive-push-pull;
<STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */ slew-rate = <0>;
<STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ };
<STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */ };
<STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
<STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */ pwm2_sleep_pins_a: pwm2-sleep-0 {
<STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */ pins {
<STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */ pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */
<STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ };
<STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ };
<STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
<STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ pwm3_pins_a: pwm3-0 {
<STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */ pins {
<STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */
<STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ bias-pull-down;
<STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */ drive-push-pull;
}; slew-rate = <0>;
}; };
};
ltdc_pins_b: ltdc-b-0 {
pins { pwm3_sleep_pins_a: pwm3-sleep-0 {
pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */ pins {
<STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */
<STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */ };
<STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */ };
<STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
<STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */ pwm4_pins_a: pwm4-0 {
<STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */ pins {
<STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */ pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */
<STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */ <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */
<STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */ bias-pull-down;
<STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */ drive-push-pull;
<STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */ slew-rate = <0>;
<STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */ };
<STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */ };
<STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
<STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */ pwm4_sleep_pins_a: pwm4-sleep-0 {
<STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */ pins {
<STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */ pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */
<STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */ <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */
<STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */ };
<STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */ };
<STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
<STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */ pwm4_pins_b: pwm4-1 {
<STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */ pins {
<STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */ pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
<STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */ bias-pull-down;
<STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */ drive-push-pull;
<STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */ slew-rate = <0>;
bias-disable; };
drive-push-pull; };
slew-rate = <1>;
}; pwm4_sleep_pins_b: pwm4-sleep-1 {
}; pins {
pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
ltdc_pins_sleep_b: ltdc-b-1 { };
pins { };
pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
<STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */ pwm5_pins_a: pwm5-0 {
<STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */ pins {
<STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */ pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */
<STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */ bias-pull-down;
<STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */ drive-push-pull;
<STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */ slew-rate = <0>;
<STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */ };
<STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */ };
<STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
<STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */ pwm5_sleep_pins_a: pwm5-sleep-0 {
<STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */ pins {
<STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */ pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */
<STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */ };
<STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */ };
<STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
<STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */ pwm8_pins_a: pwm8-0 {
<STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */ pins {
<STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */ pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
<STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */ bias-pull-down;
<STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */ drive-push-pull;
<STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */ slew-rate = <0>;
<STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */ };
<STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */ };
<STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
<STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */ pwm8_sleep_pins_a: pwm8-sleep-0 {
<STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */ pins {
<STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */ pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */
}; };
}; };
m_can1_pins_a: m-can1-0 { pwm12_pins_a: pwm12-0 {
pins1 { pins {
pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
slew-rate = <1>; bias-pull-down;
drive-push-pull; drive-push-pull;
bias-disable; slew-rate = <0>;
}; };
pins2 { };
pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
bias-disable; pwm12_sleep_pins_a: pwm12-sleep-0 {
}; pins {
}; pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */
};
m_can1_sleep_pins_a: m_can1-sleep-0 { };
pins {
pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ qspi_clk_pins_a: qspi-clk-0 {
<STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */ pins {
}; pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
}; bias-disable;
drive-push-pull;
pwm1_pins_a: pwm1-0 { slew-rate = <3>;
pins { };
pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */ };
<STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */
<STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
bias-pull-down; pins {
drive-push-pull; pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
slew-rate = <0>; };
}; };
};
qspi_bk1_pins_a: qspi-bk1-0 {
pwm1_sleep_pins_a: pwm1-sleep-0 { pins1 {
pins { pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */ <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
<STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */ <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
<STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */ <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
}; bias-disable;
}; drive-push-pull;
slew-rate = <1>;
pwm2_pins_a: pwm2-0 { };
pins { pins2 {
pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */ pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
bias-pull-down; bias-pull-up;
drive-push-pull; drive-push-pull;
slew-rate = <0>; slew-rate = <1>;
}; };
}; };
pwm2_sleep_pins_a: pwm2-sleep-0 { qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
pins { pins {
pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */ pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
}; <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
}; <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
<STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
pwm3_pins_a: pwm3-0 { <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
pins { };
pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */ };
bias-pull-down;
drive-push-pull; qspi_bk2_pins_a: qspi-bk2-0 {
slew-rate = <0>; pins1 {
}; pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
}; <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
<STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
pwm3_sleep_pins_a: pwm3-sleep-0 { <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
pins { bias-disable;
pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */ drive-push-pull;
}; slew-rate = <1>;
}; };
pins2 {
pwm4_pins_a: pwm4-0 { pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
pins { bias-pull-up;
pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */ drive-push-pull;
<STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */ slew-rate = <1>;
bias-pull-down; };
drive-push-pull; };
slew-rate = <0>;
}; qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
}; pins {
pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
pwm4_sleep_pins_a: pwm4-sleep-0 { <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
pins { <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */ <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
<STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */ <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
}; };
}; };
pwm4_pins_b: pwm4-1 { sai2a_pins_a: sai2a-0 {
pins { pins {
pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */ pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
bias-pull-down; <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
drive-push-pull; <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
slew-rate = <0>; <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
}; slew-rate = <0>;
}; drive-push-pull;
bias-disable;
pwm4_sleep_pins_b: pwm4-sleep-1 { };
pins { };
pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
}; sai2a_sleep_pins_a: sai2a-1 {
}; pins {
pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
pwm5_pins_a: pwm5-0 { <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
pins { <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */ <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
bias-pull-down; };
drive-push-pull; };
slew-rate = <0>;
}; sai2b_pins_a: sai2b-0 {
}; pins1 {
pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
pwm5_sleep_pins_a: pwm5-sleep-0 { <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
pins { <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */ slew-rate = <0>;
}; drive-push-pull;
}; bias-disable;
};
pwm8_pins_a: pwm8-0 { pins2 {
pins { pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */ bias-disable;
bias-pull-down; };
drive-push-pull; };
slew-rate = <0>;
}; sai2b_sleep_pins_a: sai2b-1 {
}; pins {
pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
pwm8_sleep_pins_a: pwm8-sleep-0 { <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
pins { <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */ <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
}; };
}; };
pwm12_pins_a: pwm12-0 { sai2b_pins_b: sai2b-2 {
pins { pins {
pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */ pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
bias-pull-down; bias-disable;
drive-push-pull; };
slew-rate = <0>; };
};
}; sai2b_sleep_pins_b: sai2b-3 {
pins {
pwm12_sleep_pins_a: pwm12-sleep-0 { pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
pins { };
pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */ };
};
}; sai4a_pins_a: sai4a-0 {
pins {
qspi_clk_pins_a: qspi-clk-0 { pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
pins { slew-rate = <0>;
pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ drive-push-pull;
bias-disable; bias-disable;
drive-push-pull; };
slew-rate = <3>; };
};
}; sai4a_sleep_pins_a: sai4a-1 {
pins {
qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
pins { };
pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */ };
};
}; sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins1 {
qspi_bk1_pins_a: qspi-bk1-0 { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
pins1 { <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
<STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
<STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */ slew-rate = <1>;
bias-disable; drive-push-pull;
drive-push-pull; bias-disable;
slew-rate = <1>; };
}; pins2 {
pins2 { pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ slew-rate = <2>;
bias-pull-up; drive-push-pull;
drive-push-pull; bias-disable;
slew-rate = <1>; };
}; };
};
sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { pins1 {
pins { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */ <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
<STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */ slew-rate = <1>;
<STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ drive-push-pull;
}; bias-disable;
}; };
pins2 {
qspi_bk2_pins_a: qspi-bk2-0 { pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
pins1 { slew-rate = <2>;
pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ drive-push-pull;
<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */ bias-disable;
<STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */ };
<STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */ pins3 {
bias-disable; pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
drive-push-pull; slew-rate = <1>;
slew-rate = <1>; drive-open-drain;
}; bias-disable;
pins2 { };
pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */ };
bias-pull-up;
drive-push-pull; sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
slew-rate = <1>; pins {
}; pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
}; <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
pins { <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
<STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */ };
<STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */ };
<STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
<STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ sdmmc1_dir_pins_a: sdmmc1-dir-0 {
}; pins1 {
}; pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
<STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
sai2a_pins_a: sai2a-0 { <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
pins { slew-rate = <1>;
pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */ drive-push-pull;
<STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ bias-pull-up;
<STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ };
<STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */ pins2{
slew-rate = <0>; pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
drive-push-pull; bias-pull-up;
bias-disable; };
}; };
};
sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
sai2a_sleep_pins_a: sai2a-1 { pins {
pins { pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */ <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
<STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
<STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
<STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */ };
}; };
};
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
sai2b_pins_a: sai2b-0 { pins1 {
pins1 { pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
<STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
<STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
slew-rate = <0>; <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
drive-push-pull; slew-rate = <1>;
bias-disable; drive-push-pull;
}; bias-pull-up;
pins2 { };
pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ pins2 {
bias-disable; pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
}; slew-rate = <2>;
}; drive-push-pull;
bias-pull-up;
sai2b_sleep_pins_a: sai2b-1 { };
pins { };
pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
<STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */ sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
<STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */ pins1 {
<STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
}; <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
}; <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
sai2b_pins_b: sai2b-2 { slew-rate = <1>;
pins { drive-push-pull;
pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ bias-pull-up;
bias-disable; };
}; pins2 {
}; pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
slew-rate = <2>;
sai2b_sleep_pins_b: sai2b-3 { drive-push-pull;
pins { bias-pull-up;
pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ };
}; pins3 {
}; pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
slew-rate = <1>;
sai4a_pins_a: sai4a-0 { drive-open-drain;
pins { bias-pull-up;
pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */ };
slew-rate = <0>; };
drive-push-pull;
bias-disable; sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
}; pins {
}; pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
sai4a_sleep_pins_a: sai4a-1 { <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
pins { <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */ <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
}; <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
}; };
};
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins1 { sdmmc2_b4_pins_b: sdmmc2-b4-1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ pins1 {
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
slew-rate = <1>; <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
drive-push-pull; slew-rate = <1>;
bias-disable; drive-push-pull;
}; bias-disable;
pins2 { };
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ pins2 {
slew-rate = <2>; pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
drive-push-pull; slew-rate = <2>;
bias-disable; drive-push-pull;
}; bias-disable;
}; };
};
sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
pins1 { sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ pins1 {
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
<STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
slew-rate = <1>; <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
drive-push-pull; slew-rate = <1>;
bias-disable; drive-push-pull;
}; bias-disable;
pins2 { };
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ pins2 {
slew-rate = <2>; pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
drive-push-pull; slew-rate = <2>;
bias-disable; drive-push-pull;
}; bias-disable;
pins3 { };
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ pins3 {
slew-rate = <1>; pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
drive-open-drain; slew-rate = <1>;
bias-disable; drive-open-drain;
}; bias-disable;
}; };
};
sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
pins { sdmmc2_d47_pins_a: sdmmc2-d47-0 {
pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ pins {
<STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
<STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
<STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ slew-rate = <1>;
}; drive-push-pull;
}; bias-pull-up;
};
sdmmc1_dir_pins_a: sdmmc1-dir-0 { };
pins1 {
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
<STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ pins {
<STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
slew-rate = <1>; <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
drive-push-pull; <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
bias-pull-up; <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
}; };
pins2{ };
pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
bias-pull-up; sdmmc3_b4_pins_a: sdmmc3-b4-0 {
}; pins1 {
}; pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
<STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
pins { <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
<STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */ slew-rate = <1>;
<STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ drive-push-pull;
<STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ bias-pull-up;
}; };
}; pins2 {
pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
sdmmc2_b4_pins_a: sdmmc2-b4-0 { slew-rate = <2>;
pins1 { drive-push-pull;
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ bias-pull-up;
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ };
<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ };
<STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
slew-rate = <1>; pins1 {
drive-push-pull; pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
bias-pull-up; <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
}; <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
pins2 { <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ slew-rate = <1>;
slew-rate = <2>; drive-push-pull;
drive-push-pull; bias-pull-up;
bias-pull-up; };
}; pins2 {
}; pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
slew-rate = <2>;
sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { drive-push-pull;
pins1 { bias-pull-up;
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ };
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ pins3 {
<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
<STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ slew-rate = <1>;
slew-rate = <1>; drive-open-drain;
drive-push-pull; bias-pull-up;
bias-pull-up; };
}; };
pins2 {
pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
slew-rate = <2>; pins {
drive-push-pull; pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
bias-pull-up; <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
}; <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */
pins3 { <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
slew-rate = <1>; <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
drive-open-drain; };
bias-pull-up; };
};
}; spdifrx_pins_a: spdifrx-0 {
pins {
sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
pins { bias-disable;
pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ };
<STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */ };
<STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ spdifrx_sleep_pins_a: spdifrx-1 {
<STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ pins {
<STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
}; };
}; };
sdmmc2_b4_pins_b: sdmmc2-b4-1 { uart4_pins_a: uart4-0 {
pins1 { pins1 {
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ bias-disable;
<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ drive-push-pull;
<STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ slew-rate = <0>;
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ };
slew-rate = <1>; pins2 {
drive-push-pull; pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-disable; bias-disable;
}; };
pins2 { };
pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
slew-rate = <2>; uart4_pins_b: uart4-1 {
drive-push-pull; pins1 {
bias-disable; pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
}; bias-disable;
}; drive-push-pull;
slew-rate = <0>;
sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 { };
pins1 { pins2 {
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ bias-disable;
<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ };
<STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ };
slew-rate = <1>;
drive-push-pull; uart7_pins_a: uart7-0 {
bias-disable; pins1 {
}; pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
pins2 { bias-disable;
pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ drive-push-pull;
slew-rate = <2>; slew-rate = <0>;
drive-push-pull; };
bias-disable; pins2 {
}; pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
pins3 { <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
slew-rate = <1>; bias-disable;
drive-open-drain; };
bias-disable; };
}; };
};
&pinctrl_z {
sdmmc2_d47_pins_a: sdmmc2-d47-0 { i2c2_pins_b2: i2c2-0 {
pins { pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ bias-disable;
<STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ drive-open-drain;
<STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */ slew-rate = <0>;
slew-rate = <1>; };
drive-push-pull; };
bias-pull-up;
}; i2c2_pins_sleep_b2: i2c2-1 {
}; pins {
pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { };
pins { };
pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ i2c4_pins_a: i2c4-0 {
<STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ pins {
<STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */ pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
}; <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
}; bias-disable;
drive-open-drain;
sdmmc3_b4_pins_a: sdmmc3-b4-0 { slew-rate = <0>;
pins1 { };
pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ };
<STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
<STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ i2c4_pins_sleep_a: i2c4-1 {
<STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ pins {
<STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */ pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
slew-rate = <1>; <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
drive-push-pull; };
bias-pull-up; };
};
pins2 { spi1_pins_a: spi1-0 {
pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ pins1 {
slew-rate = <2>; pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
drive-push-pull; <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
bias-pull-up; bias-disable;
}; drive-push-pull;
}; slew-rate = <1>;
};
sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
pins1 { pins2 {
pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
<STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ bias-disable;
<STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
<STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
pins2 {
pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
slew-rate = <2>;
drive-push-pull;
bias-pull-up;
};
pins3 {
pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
slew-rate = <1>;
drive-open-drain;
bias-pull-up;
};
};
sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
<STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
<STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */
<STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
<STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
<STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
};
};
spdifrx_pins_a: spdifrx-0 {
pins {
pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
bias-disable;
};
};
spdifrx_sleep_pins_a: spdifrx-1 {
pins {
pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
};
};
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-disable;
};
};
uart4_pins_b: uart4-1 {
pins1 {
pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-disable;
};
};
uart7_pins_a: uart7-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
<STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
<STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
bias-disable;
};
};
};
pinctrl_z: pin-controller-z@54004000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32mp157-z-pinctrl";
ranges = <0 0x54004000 0x400>;
pins-are-numbered;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
gpioz: gpio@54004000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 0x400>;
clocks = <&rcc GPIOZ>;
st,bank-name = "GPIOZ";
st,bank-ioport = <11>;
status = "disabled";
};
i2c2_pins_b2: i2c2-0 {
pins {
pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
i2c2_pins_sleep_b2: i2c2-1 {
pins {
pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
};
};
i2c4_pins_a: i2c4-0 {
pins {
pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
i2c4_pins_sleep_a: i2c4-1 {
pins {
pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
<STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
};
};
spi1_pins_a: spi1-0 {
pins1 {
pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
<STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
bias-disable;
};
};
}; };
}; };
}; };
arch/arm/boot/dts/stm32mp157c.dtsi
View file @ 92d3a35c
...@@ -1572,6 +1572,163 @@ i2c6: i2c@5c009000 { ...@@ -1572,6 +1572,163 @@ i2c6: i2c@5c009000 {
#size-cells = <0>; #size-cells = <0>;
status = "disabled"; status = "disabled";
}; };
/*
* Break node order to solve dependency probe issue between
* pinctrl and exti.
*/
pinctrl: pin-controller@50002000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32mp157-pinctrl";
ranges = <0 0x50002000 0xa400>;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
pins-are-numbered;
gpioa: gpio@50002000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
clocks = <&rcc GPIOA>;
st,bank-name = "GPIOA";
status = "disabled";
};
gpiob: gpio@50003000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1000 0x400>;
clocks = <&rcc GPIOB>;
st,bank-name = "GPIOB";
status = "disabled";
};
gpioc: gpio@50004000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2000 0x400>;
clocks = <&rcc GPIOC>;
st,bank-name = "GPIOC";
status = "disabled";
};
gpiod: gpio@50005000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x3000 0x400>;
clocks = <&rcc GPIOD>;
st,bank-name = "GPIOD";
status = "disabled";
};
gpioe: gpio@50006000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x4000 0x400>;
clocks = <&rcc GPIOE>;
st,bank-name = "GPIOE";
status = "disabled";
};
gpiof: gpio@50007000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000 0x400>;
clocks = <&rcc GPIOF>;
st,bank-name = "GPIOF";
status = "disabled";
};
gpiog: gpio@50008000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x6000 0x400>;
clocks = <&rcc GPIOG>;
st,bank-name = "GPIOG";
status = "disabled";
};
gpioh: gpio@50009000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x7000 0x400>;
clocks = <&rcc GPIOH>;
st,bank-name = "GPIOH";
status = "disabled";
};
gpioi: gpio@5000a000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x8000 0x400>;
clocks = <&rcc GPIOI>;
st,bank-name = "GPIOI";
status = "disabled";
};
gpioj: gpio@5000b000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x9000 0x400>;
clocks = <&rcc GPIOJ>;
st,bank-name = "GPIOJ";
status = "disabled";
};
gpiok: gpio@5000c000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0xa000 0x400>;
clocks = <&rcc GPIOK>;
st,bank-name = "GPIOK";
status = "disabled";
};
};
pinctrl_z: pin-controller-z@54004000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32mp157-z-pinctrl";
ranges = <0 0x54004000 0x400>;
pins-are-numbered;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
gpioz: gpio@54004000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 0x400>;
clocks = <&rcc GPIOZ>;
st,bank-name = "GPIOZ";
st,bank-ioport = <11>;
status = "disabled";
};
};
}; };
mlahb { mlahb {
......
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