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Commit 936d4b41 authored by David S. Miller's avatar David S. Miller
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Merge branch 'mlx5_ifc-updates' 

Saeed Mahameed says:

====================
mlx5_core: mlx5_ifc updates

This series include mlx5_core updates for both net-next and rdma
trees for 4.7 kernel cycle. This is the only shared code planned
for 4.7 between rdma and net trees. Hopefully, this will prevent
future conflicts when merging between ib-next and net-next once
4.7 cycle is over and merge window is opened.

Both Mellanox rdma and net submissions will proceed once this series
is applied into both trees.

Future shared code will be sent to both maintainers as pull requests
from Mellanox's kernel.org tree.

We have included all the maintainers of respective drivers.
Kindly review the change and let us know in case of any review comments.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 993feee9 7d5e1423
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Showing with 179 additions and 74 deletions
include/linux/mlx5/mlx5_ifc.h
View file @ 936d4b41
...@@ -513,7 +513,9 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits { ...@@ -513,7 +513,9 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
u8 max_lso_cap[0x5]; u8 max_lso_cap[0x5];
u8 reserved_at_10[0x4]; u8 reserved_at_10[0x4];
u8 rss_ind_tbl_cap[0x4]; u8 rss_ind_tbl_cap[0x4];
u8 reserved_at_18[0x3]; u8 reg_umr_sq[0x1];
u8 scatter_fcs[0x1];
u8 reserved_at_1a[0x1];
u8 tunnel_lso_const_out_ip_id[0x1]; u8 tunnel_lso_const_out_ip_id[0x1];
u8 reserved_at_1c[0x2]; u8 reserved_at_1c[0x2];
u8 tunnel_statless_gre[0x1]; u8 tunnel_statless_gre[0x1];
...@@ -648,7 +650,7 @@ struct mlx5_ifc_vector_calc_cap_bits { ...@@ -648,7 +650,7 @@ struct mlx5_ifc_vector_calc_cap_bits {
enum { enum {
MLX5_WQ_TYPE_LINKED_LIST = 0x0, MLX5_WQ_TYPE_LINKED_LIST = 0x0,
MLX5_WQ_TYPE_CYCLIC = 0x1, MLX5_WQ_TYPE_CYCLIC = 0x1,
MLX5_WQ_TYPE_STRQ = 0x2, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
}; };
enum { enum {
...@@ -750,21 +752,25 @@ struct mlx5_ifc_cmd_hca_cap_bits { ...@@ -750,21 +752,25 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 ets[0x1]; u8 ets[0x1];
u8 nic_flow_table[0x1]; u8 nic_flow_table[0x1];
u8 eswitch_flow_table[0x1]; u8 eswitch_flow_table[0x1];
u8 early_vf_enable; u8 early_vf_enable[0x1];
u8 reserved_at_1a8[0x2]; u8 reserved_at_1a9[0x2];
u8 local_ca_ack_delay[0x5]; u8 local_ca_ack_delay[0x5];
u8 reserved_at_1af[0x6]; u8 reserved_at_1af[0x2];
u8 ports_check[0x1];
u8 reserved_at_1b2[0x1];
u8 disable_link_up[0x1];
u8 beacon_led[0x1];
u8 port_type[0x2]; u8 port_type[0x2];
u8 num_ports[0x8]; u8 num_ports[0x8];
u8 reserved_at_1bf[0x3]; u8 reserved_at_1c0[0x3];
u8 log_max_msg[0x5]; u8 log_max_msg[0x5];
u8 reserved_at_1c7[0x4]; u8 reserved_at_1c8[0x4];
u8 max_tc[0x4]; u8 max_tc[0x4];
u8 reserved_at_1cf[0x6]; u8 reserved_at_1d0[0x6];
u8 rol_s[0x1]; u8 rol_s[0x1];
u8 rol_g[0x1]; u8 rol_g[0x1];
u8 reserved_at_1d7[0x1]; u8 reserved_at_1d8[0x1];
u8 wol_s[0x1]; u8 wol_s[0x1];
u8 wol_g[0x1]; u8 wol_g[0x1];
u8 wol_a[0x1]; u8 wol_a[0x1];
...@@ -774,47 +780,48 @@ struct mlx5_ifc_cmd_hca_cap_bits { ...@@ -774,47 +780,48 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 wol_p[0x1]; u8 wol_p[0x1];
u8 stat_rate_support[0x10]; u8 stat_rate_support[0x10];
u8 reserved_at_1ef[0xc]; u8 reserved_at_1f0[0xc];
u8 cqe_version[0x4]; u8 cqe_version[0x4];
u8 compact_address_vector[0x1]; u8 compact_address_vector[0x1];
u8 reserved_at_200[0x3]; u8 striding_rq[0x1];
u8 reserved_at_201[0x2];
u8 ipoib_basic_offloads[0x1]; u8 ipoib_basic_offloads[0x1];
u8 reserved_at_204[0xa]; u8 reserved_at_205[0xa];
u8 drain_sigerr[0x1]; u8 drain_sigerr[0x1];
u8 cmdif_checksum[0x2]; u8 cmdif_checksum[0x2];
u8 sigerr_cqe[0x1]; u8 sigerr_cqe[0x1];
u8 reserved_at_212[0x1]; u8 reserved_at_213[0x1];
u8 wq_signature[0x1]; u8 wq_signature[0x1];
u8 sctr_data_cqe[0x1]; u8 sctr_data_cqe[0x1];
u8 reserved_at_215[0x1]; u8 reserved_at_216[0x1];
u8 sho[0x1]; u8 sho[0x1];
u8 tph[0x1]; u8 tph[0x1];
u8 rf[0x1]; u8 rf[0x1];
u8 dct[0x1]; u8 dct[0x1];
u8 reserved_at_21a[0x1]; u8 reserved_at_21b[0x1];
u8 eth_net_offloads[0x1]; u8 eth_net_offloads[0x1];
u8 roce[0x1]; u8 roce[0x1];
u8 atomic[0x1]; u8 atomic[0x1];
u8 reserved_at_21e[0x1]; u8 reserved_at_21f[0x1];
u8 cq_oi[0x1]; u8 cq_oi[0x1];
u8 cq_resize[0x1]; u8 cq_resize[0x1];
u8 cq_moderation[0x1]; u8 cq_moderation[0x1];
u8 reserved_at_222[0x3]; u8 reserved_at_223[0x3];
u8 cq_eq_remap[0x1]; u8 cq_eq_remap[0x1];
u8 pg[0x1]; u8 pg[0x1];
u8 block_lb_mc[0x1]; u8 block_lb_mc[0x1];
u8 reserved_at_228[0x1]; u8 reserved_at_229[0x1];
u8 scqe_break_moderation[0x1]; u8 scqe_break_moderation[0x1];
u8 reserved_at_22a[0x1]; u8 cq_period_start_from_cqe[0x1];
u8 cd[0x1]; u8 cd[0x1];
u8 reserved_at_22c[0x1]; u8 reserved_at_22d[0x1];
u8 apm[0x1]; u8 apm[0x1];
u8 vector_calc[0x1]; u8 vector_calc[0x1];
u8 reserved_at_22f[0x1]; u8 umr_ptr_rlky[0x1];
u8 imaicl[0x1]; u8 imaicl[0x1];
u8 reserved_at_231[0x4]; u8 reserved_at_232[0x4];
u8 qkv[0x1]; u8 qkv[0x1];
u8 pkv[0x1]; u8 pkv[0x1];
u8 set_deth_sqpn[0x1]; u8 set_deth_sqpn[0x1];
...@@ -824,98 +831,101 @@ struct mlx5_ifc_cmd_hca_cap_bits { ...@@ -824,98 +831,101 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 uc[0x1]; u8 uc[0x1];
u8 rc[0x1]; u8 rc[0x1];
u8 reserved_at_23f[0xa]; u8 reserved_at_240[0xa];
u8 uar_sz[0x6]; u8 uar_sz[0x6];
u8 reserved_at_24f[0x8]; u8 reserved_at_250[0x8];
u8 log_pg_sz[0x8]; u8 log_pg_sz[0x8];
u8 bf[0x1]; u8 bf[0x1];
u8 reserved_at_260[0x1]; u8 reserved_at_261[0x1];
u8 pad_tx_eth_packet[0x1]; u8 pad_tx_eth_packet[0x1];
u8 reserved_at_262[0x8]; u8 reserved_at_263[0x8];
u8 log_bf_reg_size[0x5]; u8 log_bf_reg_size[0x5];
u8 reserved_at_26f[0x10]; u8 reserved_at_270[0x10];
u8 reserved_at_27f[0x10]; u8 reserved_at_280[0x10];
u8 max_wqe_sz_sq[0x10]; u8 max_wqe_sz_sq[0x10];
u8 reserved_at_29f[0x10]; u8 reserved_at_2a0[0x10];
u8 max_wqe_sz_rq[0x10]; u8 max_wqe_sz_rq[0x10];
u8 reserved_at_2bf[0x10]; u8 reserved_at_2c0[0x10];
u8 max_wqe_sz_sq_dc[0x10]; u8 max_wqe_sz_sq_dc[0x10];
u8 reserved_at_2df[0x7]; u8 reserved_at_2e0[0x7];
u8 max_qp_mcg[0x19]; u8 max_qp_mcg[0x19];
u8 reserved_at_2ff[0x18]; u8 reserved_at_300[0x18];
u8 log_max_mcg[0x8]; u8 log_max_mcg[0x8];
u8 reserved_at_31f[0x3]; u8 reserved_at_320[0x3];
u8 log_max_transport_domain[0x5]; u8 log_max_transport_domain[0x5];
u8 reserved_at_327[0x3]; u8 reserved_at_328[0x3];
u8 log_max_pd[0x5]; u8 log_max_pd[0x5];
u8 reserved_at_32f[0xb]; u8 reserved_at_330[0xb];
u8 log_max_xrcd[0x5]; u8 log_max_xrcd[0x5];
u8 reserved_at_33f[0x20]; u8 reserved_at_340[0x20];
u8 reserved_at_35f[0x3]; u8 reserved_at_360[0x3];
u8 log_max_rq[0x5]; u8 log_max_rq[0x5];
u8 reserved_at_367[0x3]; u8 reserved_at_368[0x3];
u8 log_max_sq[0x5]; u8 log_max_sq[0x5];
u8 reserved_at_36f[0x3]; u8 reserved_at_370[0x3];
u8 log_max_tir[0x5]; u8 log_max_tir[0x5];
u8 reserved_at_377[0x3]; u8 reserved_at_378[0x3];
u8 log_max_tis[0x5]; u8 log_max_tis[0x5];
u8 basic_cyclic_rcv_wqe[0x1]; u8 basic_cyclic_rcv_wqe[0x1];
u8 reserved_at_380[0x2]; u8 reserved_at_381[0x2];
u8 log_max_rmp[0x5]; u8 log_max_rmp[0x5];
u8 reserved_at_387[0x3]; u8 reserved_at_388[0x3];
u8 log_max_rqt[0x5]; u8 log_max_rqt[0x5];
u8 reserved_at_38f[0x3]; u8 reserved_at_390[0x3];
u8 log_max_rqt_size[0x5]; u8 log_max_rqt_size[0x5];
u8 reserved_at_397[0x3]; u8 reserved_at_398[0x3];
u8 log_max_tis_per_sq[0x5]; u8 log_max_tis_per_sq[0x5];
u8 reserved_at_39f[0x3]; u8 reserved_at_3a0[0x3];
u8 log_max_stride_sz_rq[0x5]; u8 log_max_stride_sz_rq[0x5];
u8 reserved_at_3a7[0x3]; u8 reserved_at_3a8[0x3];
u8 log_min_stride_sz_rq[0x5]; u8 log_min_stride_sz_rq[0x5];
u8 reserved_at_3af[0x3]; u8 reserved_at_3b0[0x3];
u8 log_max_stride_sz_sq[0x5]; u8 log_max_stride_sz_sq[0x5];
u8 reserved_at_3b7[0x3]; u8 reserved_at_3b8[0x3];
u8 log_min_stride_sz_sq[0x5]; u8 log_min_stride_sz_sq[0x5];
u8 reserved_at_3bf[0x1b]; u8 reserved_at_3c0[0x1b];
u8 log_max_wq_sz[0x5]; u8 log_max_wq_sz[0x5];
u8 nic_vport_change_event[0x1]; u8 nic_vport_change_event[0x1];
u8 reserved_at_3e0[0xa]; u8 reserved_at_3e1[0xa];
u8 log_max_vlan_list[0x5]; u8 log_max_vlan_list[0x5];
u8 reserved_at_3ef[0x3]; u8 reserved_at_3f0[0x3];
u8 log_max_current_mc_list[0x5]; u8 log_max_current_mc_list[0x5];
u8 reserved_at_3f7[0x3]; u8 reserved_at_3f8[0x3];
u8 log_max_current_uc_list[0x5]; u8 log_max_current_uc_list[0x5];
u8 reserved_at_3ff[0x80]; u8 reserved_at_400[0x80];
u8 reserved_at_47f[0x3]; u8 reserved_at_480[0x3];
u8 log_max_l2_table[0x5]; u8 log_max_l2_table[0x5];
u8 reserved_at_487[0x8]; u8 reserved_at_488[0x8];
u8 log_uar_page_sz[0x10]; u8 log_uar_page_sz[0x10];
u8 reserved_at_49f[0x20]; u8 reserved_at_4a0[0x20];
u8 device_frequency_mhz[0x20]; u8 device_frequency_mhz[0x20];
u8 device_frequency_khz[0x20]; u8 device_frequency_khz[0x20];
u8 reserved_at_4ff[0x5f];
u8 cqe_zip[0x1];
u8 cqe_zip_timeout[0x10]; u8 reserved_at_500[0x80];
u8 cqe_zip_max_num[0x10];
u8 reserved_at_57f[0x220]; u8 reserved_at_580[0x3f];
u8 cqe_compression[0x1];
u8 cqe_compression_timeout[0x10];
u8 cqe_compression_max_num[0x10];
u8 reserved_at_5e0[0x220];
}; };
enum mlx5_flow_destination_type { enum mlx5_flow_destination_type {
...@@ -997,7 +1007,13 @@ struct mlx5_ifc_wq_bits { ...@@ -997,7 +1007,13 @@ struct mlx5_ifc_wq_bits {
u8 reserved_at_118[0x3]; u8 reserved_at_118[0x3];
u8 log_wq_sz[0x5]; u8 log_wq_sz[0x5];
u8 reserved_at_120[0x4e0]; u8 reserved_at_120[0x15];
u8 log_wqe_num_of_strides[0x3];
u8 two_byte_shift_en[0x1];
u8 reserved_at_139[0x4];
u8 log_wqe_stride_size[0x3];
u8 reserved_at_140[0x4c0];
struct mlx5_ifc_cmd_pas_bits pas[0]; struct mlx5_ifc_cmd_pas_bits pas[0];
}; };
...@@ -2196,7 +2212,8 @@ struct mlx5_ifc_sqc_bits { ...@@ -2196,7 +2212,8 @@ struct mlx5_ifc_sqc_bits {
u8 flush_in_error_en[0x1]; u8 flush_in_error_en[0x1];
u8 reserved_at_4[0x4]; u8 reserved_at_4[0x4];
u8 state[0x4]; u8 state[0x4];
u8 reserved_at_c[0x14]; u8 reg_umr[0x1];
u8 reserved_at_d[0x13];
u8 reserved_at_20[0x8]; u8 reserved_at_20[0x8];
u8 user_index[0x18]; u8 user_index[0x18];
...@@ -2244,7 +2261,8 @@ enum { ...@@ -2244,7 +2261,8 @@ enum {
struct mlx5_ifc_rqc_bits { struct mlx5_ifc_rqc_bits {
u8 rlky[0x1]; u8 rlky[0x1];
u8 reserved_at_1[0x2]; u8 reserved_at_1[0x1];
u8 scatter_fcs[0x1];
u8 vsd[0x1]; u8 vsd[0x1];
u8 mem_rq_type[0x4]; u8 mem_rq_type[0x4];
u8 state[0x4]; u8 state[0x4];
...@@ -2601,6 +2619,11 @@ enum { ...@@ -2601,6 +2619,11 @@ enum {
MLX5_CQC_ST_FIRED = 0xa, MLX5_CQC_ST_FIRED = 0xa,
}; };
enum {
MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
};
struct mlx5_ifc_cqc_bits { struct mlx5_ifc_cqc_bits {
u8 status[0x4]; u8 status[0x4];
u8 reserved_at_4[0x4]; u8 reserved_at_4[0x4];
...@@ -2609,8 +2632,8 @@ struct mlx5_ifc_cqc_bits { ...@@ -2609,8 +2632,8 @@ struct mlx5_ifc_cqc_bits {
u8 reserved_at_c[0x1]; u8 reserved_at_c[0x1];
u8 scqe_break_moderation_en[0x1]; u8 scqe_break_moderation_en[0x1];
u8 oi[0x1]; u8 oi[0x1];
u8 reserved_at_f[0x2]; u8 cq_period_mode[0x2];
u8 cqe_zip_en[0x1]; u8 cqe_comp_en[0x1];
u8 mini_cqe_res_format[0x2]; u8 mini_cqe_res_format[0x2];
u8 st[0x4]; u8 st[0x4];
u8 reserved_at_18[0x8]; u8 reserved_at_18[0x8];
...@@ -2984,7 +3007,11 @@ struct mlx5_ifc_set_fte_in_bits { ...@@ -2984,7 +3007,11 @@ struct mlx5_ifc_set_fte_in_bits {
u8 reserved_at_20[0x10]; u8 reserved_at_20[0x10];
u8 op_mod[0x10]; u8 op_mod[0x10];
u8 reserved_at_40[0x40]; u8 other_vport[0x1];
u8 reserved_at_41[0xf];
u8 vport_number[0x10];
u8 reserved_at_60[0x20];
u8 table_type[0x8]; u8 table_type[0x8];
u8 reserved_at_88[0x18]; u8 reserved_at_88[0x18];
...@@ -5178,7 +5205,11 @@ struct mlx5_ifc_destroy_flow_table_in_bits { ...@@ -5178,7 +5205,11 @@ struct mlx5_ifc_destroy_flow_table_in_bits {
u8 reserved_at_20[0x10]; u8 reserved_at_20[0x10];
u8 op_mod[0x10]; u8 op_mod[0x10];
u8 reserved_at_40[0x40]; u8 other_vport[0x1];
u8 reserved_at_41[0xf];
u8 vport_number[0x10];
u8 reserved_at_60[0x20];
u8 table_type[0x8]; u8 table_type[0x8];
u8 reserved_at_88[0x18]; u8 reserved_at_88[0x18];
...@@ -5205,7 +5236,11 @@ struct mlx5_ifc_destroy_flow_group_in_bits { ...@@ -5205,7 +5236,11 @@ struct mlx5_ifc_destroy_flow_group_in_bits {
u8 reserved_at_20[0x10]; u8 reserved_at_20[0x10];
u8 op_mod[0x10]; u8 op_mod[0x10];
u8 reserved_at_40[0x40]; u8 other_vport[0x1];
u8 reserved_at_41[0xf];
u8 vport_number[0x10];
u8 reserved_at_60[0x20];
u8 table_type[0x8]; u8 table_type[0x8];
u8 reserved_at_88[0x18]; u8 reserved_at_88[0x18];
...@@ -5346,7 +5381,11 @@ struct mlx5_ifc_delete_fte_in_bits { ...@@ -5346,7 +5381,11 @@ struct mlx5_ifc_delete_fte_in_bits {
u8 reserved_at_20[0x10]; u8 reserved_at_20[0x10];
u8 op_mod[0x10]; u8 op_mod[0x10];
u8 reserved_at_40[0x40]; u8 other_vport[0x1];
u8 reserved_at_41[0xf];
u8 vport_number[0x10];
u8 reserved_at_60[0x20];
u8 table_type[0x8]; u8 table_type[0x8];
u8 reserved_at_88[0x18]; u8 reserved_at_88[0x18];
...@@ -5792,7 +5831,11 @@ struct mlx5_ifc_create_flow_table_in_bits { ...@@ -5792,7 +5831,11 @@ struct mlx5_ifc_create_flow_table_in_bits {
u8 reserved_at_20[0x10]; u8 reserved_at_20[0x10];
u8 op_mod[0x10]; u8 op_mod[0x10];
u8 reserved_at_40[0x40]; u8 other_vport[0x1];
u8 reserved_at_41[0xf];
u8 vport_number[0x10];
u8 reserved_at_60[0x20];
u8 table_type[0x8]; u8 table_type[0x8];
u8 reserved_at_88[0x18]; u8 reserved_at_88[0x18];
...@@ -5836,7 +5879,11 @@ struct mlx5_ifc_create_flow_group_in_bits { ...@@ -5836,7 +5879,11 @@ struct mlx5_ifc_create_flow_group_in_bits {
u8 reserved_at_20[0x10]; u8 reserved_at_20[0x10];
u8 op_mod[0x10]; u8 op_mod[0x10];
u8 reserved_at_40[0x40]; u8 other_vport[0x1];
u8 reserved_at_41[0xf];
u8 vport_number[0x10];
u8 reserved_at_60[0x20];
u8 table_type[0x8]; u8 table_type[0x8];
u8 reserved_at_88[0x18]; u8 reserved_at_88[0x18];
...@@ -6369,6 +6416,17 @@ struct mlx5_ifc_ptys_reg_bits { ...@@ -6369,6 +6416,17 @@ struct mlx5_ifc_ptys_reg_bits {
u8 reserved_at_1a0[0x60]; u8 reserved_at_1a0[0x60];
}; };
struct mlx5_ifc_mlcr_reg_bits {
u8 reserved_at_0[0x8];
u8 local_port[0x8];
u8 reserved_at_10[0x20];
u8 beacon_duration[0x10];
u8 reserved_at_40[0x10];
u8 beacon_remain[0x10];
};
struct mlx5_ifc_ptas_reg_bits { struct mlx5_ifc_ptas_reg_bits {
u8 reserved_at_0[0x20]; u8 reserved_at_0[0x20];
...@@ -6778,6 +6836,16 @@ struct mlx5_ifc_pamp_reg_bits { ...@@ -6778,6 +6836,16 @@ struct mlx5_ifc_pamp_reg_bits {
u8 index_data[18][0x10]; u8 index_data[18][0x10];
}; };
struct mlx5_ifc_pcmr_reg_bits {
u8 reserved_at_0[0x8];
u8 local_port[0x8];
u8 reserved_at_10[0x2e];
u8 fcs_cap[0x1];
u8 reserved_at_3f[0x1f];
u8 fcs_chk[0x1];
u8 reserved_at_5f[0x1];
};
struct mlx5_ifc_lane_2_module_mapping_bits { struct mlx5_ifc_lane_2_module_mapping_bits {
u8 reserved_at_0[0x6]; u8 reserved_at_0[0x6];
u8 rx_lane[0x2]; u8 rx_lane[0x2];
...@@ -7114,6 +7182,7 @@ union mlx5_ifc_ports_control_registers_document_bits { ...@@ -7114,6 +7182,7 @@ union mlx5_ifc_ports_control_registers_document_bits {
struct mlx5_ifc_pspa_reg_bits pspa_reg; struct mlx5_ifc_pspa_reg_bits pspa_reg;
struct mlx5_ifc_ptas_reg_bits ptas_reg; struct mlx5_ifc_ptas_reg_bits ptas_reg;
struct mlx5_ifc_ptys_reg_bits ptys_reg; struct mlx5_ifc_ptys_reg_bits ptys_reg;
struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
struct mlx5_ifc_pude_reg_bits pude_reg; struct mlx5_ifc_pude_reg_bits pude_reg;
struct mlx5_ifc_pvlc_reg_bits pvlc_reg; struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
struct mlx5_ifc_slrg_reg_bits slrg_reg; struct mlx5_ifc_slrg_reg_bits slrg_reg;
...@@ -7147,7 +7216,11 @@ struct mlx5_ifc_set_flow_table_root_in_bits { ...@@ -7147,7 +7216,11 @@ struct mlx5_ifc_set_flow_table_root_in_bits {
u8 reserved_at_20[0x10]; u8 reserved_at_20[0x10];
u8 op_mod[0x10]; u8 op_mod[0x10];
u8 reserved_at_40[0x40]; u8 other_vport[0x1];
u8 reserved_at_41[0xf];
u8 vport_number[0x10];
u8 reserved_at_60[0x20];
u8 table_type[0x8]; u8 table_type[0x8];
u8 reserved_at_88[0x18]; u8 reserved_at_88[0x18];
...@@ -7178,7 +7251,9 @@ struct mlx5_ifc_modify_flow_table_in_bits { ...@@ -7178,7 +7251,9 @@ struct mlx5_ifc_modify_flow_table_in_bits {
u8 reserved_at_20[0x10]; u8 reserved_at_20[0x10];
u8 op_mod[0x10]; u8 op_mod[0x10];
u8 reserved_at_40[0x20]; u8 other_vport[0x1];
u8 reserved_at_41[0xf];
u8 vport_number[0x10];
u8 reserved_at_60[0x10]; u8 reserved_at_60[0x10];
u8 modify_field_select[0x10]; u8 modify_field_select[0x10];
...@@ -7244,4 +7319,34 @@ struct mlx5_ifc_qtct_reg_bits { ...@@ -7244,4 +7319,34 @@ struct mlx5_ifc_qtct_reg_bits {
u8 tclass[0x3]; u8 tclass[0x3];
}; };
struct mlx5_ifc_mcia_reg_bits {
u8 l[0x1];
u8 reserved_at_1[0x7];
u8 module[0x8];
u8 reserved_at_10[0x8];
u8 status[0x8];
u8 i2c_device_address[0x8];
u8 page_number[0x8];
u8 device_address[0x10];
u8 reserved_at_40[0x10];
u8 size[0x10];
u8 reserved_at_60[0x20];
u8 dword_0[0x20];
u8 dword_1[0x20];
u8 dword_2[0x20];
u8 dword_3[0x20];
u8 dword_4[0x20];
u8 dword_5[0x20];
u8 dword_6[0x20];
u8 dword_7[0x20];
u8 dword_8[0x20];
u8 dword_9[0x20];
u8 dword_10[0x20];
u8 dword_11[0x20];
};
#endif /* MLX5_IFC_H */ #endif /* MLX5_IFC_H */
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