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Commit 95eb940c authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'samsung-dt-odroid-xu-4.8' of... 

Merge tag 'samsung-dt-odroid-xu-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt

Topic branch for adding Exynos 5410 Odroid XU board for v4.8.

This brings support for Hardkernel's Odroid XU board.  It was the first
design with big.LITTLE SoC from Samsung: Exynos5410.  The board is not
very popular.  Newer XU3 and XU4 got more attention.

Board details:
1. Exynos5410 octa-core (A15+A7, however as of now only one cluster is
   enabled),
2. 2 GB DDR3 RAM,
3. PowerVR SGX544MP3 GPU (not enabled in DTS),
4. USB 3.0 Host x 1, USB 3.0 OTG x 1, USB 2.0 Host x 4,
5. HDMI 1.4a, MIPI DSI and Display Port (Display Port not on all of
   revisions though),
6. eMMC 4.5 and microSD slots.

* tag 'samsung-dt-odroid-xu-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (28 commits)
  ARM: dts: exynos: Add watchdog and Security SubSystem to Exynos5410
  ARM: dts: exynos: Configure PWM, usb3503, PMIC and thermal on Odroid XU board
  ARM: dts: exynos: Add Thermal Management Unit to Exynos5410
  ARM: dts: exynos: Interrupt for USB DWC3-1 differs between Exynos5420 and 5410
  dt-bindings: clock: Add watchdog and SSS clock IDs to Exynos5410
  dt-bindings: clock: Add TMU clock ID to Exynos5410
  ARM: dts: exynos: Add RTC and I2C to Exynos5410
  ARM: dts: exynos: Add I2C, PWM and UART pinctrl to Exynos5410
  ARM: dts: exynos: Move HSI2C nodes to exynos54xx.dtsi
  ARM: dts: exynos: Add initial support for Odroid XU board
  ARM: dts: exynos: Add USB to Exynos5410
  ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI
  ARM: dts: exynos: MCT is not an interrupt controller and extend length of iomap
  ARM: dts: exynos: Enable UART3 on Exynos5410
  ARM: dts: exynos: Include common exynos5 in exynos5410.dtsi
  ARM: dts: exynos: Move Exynos5250 and Exynos5420 nodes under soc
  ARM: dts: exynos: Use phandle to get parent node in exynos5250-snow
  ARM: dts: exynos: Prepare for inclusion of exynos5.dtsi in exynos5410.dtsi
  ARM: dts: exynos: Move common nodes to exynos5.dtsi
  ARM: dts: exynos: Split Odroid XU3 LEDs to separate DTSI
  ...
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents effd7862 b8bd7e23
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Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
View file @ 95eb940c
...@@ -47,6 +47,7 @@ Required root node properties: ...@@ -47,6 +47,7 @@ Required root node properties:
- "hardkernel,odroid-u3" - for Exynos4412-based Hardkernel Odroid U3. - "hardkernel,odroid-u3" - for Exynos4412-based Hardkernel Odroid U3.
- "hardkernel,odroid-x" - for Exynos4412-based Hardkernel Odroid X. - "hardkernel,odroid-x" - for Exynos4412-based Hardkernel Odroid X.
- "hardkernel,odroid-x2" - for Exynos4412-based Hardkernel Odroid X2. - "hardkernel,odroid-x2" - for Exynos4412-based Hardkernel Odroid X2.
- "hardkernel,odroid-xu" - for Exynos5410-based Hardkernel Odroid XU.
- "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3. - "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3.
- "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel - "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel
Odroid XU3 Lite board. Odroid XU3 Lite board.
......
arch/arm/boot/dts/Makefile
View file @ 95eb940c
...@@ -134,6 +134,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \ ...@@ -134,6 +134,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
exynos5250-snow-rev5.dtb \ exynos5250-snow-rev5.dtb \
exynos5250-spring.dtb \ exynos5250-spring.dtb \
exynos5260-xyref5260.dtb \ exynos5260-xyref5260.dtb \
exynos5410-odroidxu.dtb \
exynos5410-smdk5410.dtb \ exynos5410-smdk5410.dtb \
exynos5420-arndale-octa.dtb \ exynos5420-arndale-octa.dtb \
exynos5420-peach-pit.dtb \ exynos5420-peach-pit.dtb \
......
arch/arm/boot/dts/exynos5.dtsi
View file @ 95eb940c
...@@ -20,97 +20,160 @@ / { ...@@ -20,97 +20,160 @@ / {
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
aliases { aliases {
i2c0 = &i2c_0;
i2c1 = &i2c_1;
i2c2 = &i2c_2;
i2c3 = &i2c_3;
serial0 = &serial_0; serial0 = &serial_0;
serial1 = &serial_1; serial1 = &serial_1;
serial2 = &serial_2; serial2 = &serial_2;
serial3 = &serial_3; serial3 = &serial_3;
}; };
chipid@10000000 { soc: soc {
compatible = "samsung,exynos4210-chipid"; compatible = "simple-bus";
reg = <0x10000000 0x100>; #address-cells = <1>;
}; #size-cells = <1>;
ranges;
memory-controller@12250000 { chipid@10000000 {
compatible = "samsung,exynos4210-srom"; compatible = "samsung,exynos4210-chipid";
reg = <0x12250000 0x14>; reg = <0x10000000 0x100>;
}; };
combiner: interrupt-controller@10440000 { sromc: memory-controller@12250000 {
compatible = "samsung,exynos4210-combiner"; compatible = "samsung,exynos4210-srom";
#interrupt-cells = <2>; reg = <0x12250000 0x14>;
interrupt-controller; };
samsung,combiner-nr = <32>;
reg = <0x10440000 0x1000>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
};
gic: interrupt-controller@10481000 { combiner: interrupt-controller@10440000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; compatible = "samsung,exynos4210-combiner";
#interrupt-cells = <3>; #interrupt-cells = <2>;
interrupt-controller; interrupt-controller;
reg = <0x10481000 0x1000>, samsung,combiner-nr = <32>;
<0x10482000 0x1000>, reg = <0x10440000 0x1000>;
<0x10484000 0x2000>, interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0x10486000 0x2000>; <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
interrupts = <1 9 0xf04>; <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
}; <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
};
serial_0: serial@12C00000 { gic: interrupt-controller@10481000 {
compatible = "samsung,exynos4210-uart"; compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
reg = <0x12C00000 0x100>; #interrupt-cells = <3>;
interrupts = <0 51 0>; interrupt-controller;
}; reg = <0x10481000 0x1000>,
<0x10482000 0x1000>,
<0x10484000 0x2000>,
<0x10486000 0x2000>;
interrupts = <1 9 0xf04>;
};
serial_1: serial@12C10000 { sysreg_system_controller: syscon@10050000 {
compatible = "samsung,exynos4210-uart"; compatible = "samsung,exynos5-sysreg", "syscon";
reg = <0x12C10000 0x100>; reg = <0x10050000 0x5000>;
interrupts = <0 52 0>; };
};
serial_2: serial@12C20000 { serial_0: serial@12C00000 {
compatible = "samsung,exynos4210-uart"; compatible = "samsung,exynos4210-uart";
reg = <0x12C20000 0x100>; reg = <0x12C00000 0x100>;
interrupts = <0 53 0>; interrupts = <0 51 0>;
}; };
serial_3: serial@12C30000 { serial_1: serial@12C10000 {
compatible = "samsung,exynos4210-uart"; compatible = "samsung,exynos4210-uart";
reg = <0x12C30000 0x100>; reg = <0x12C10000 0x100>;
interrupts = <0 54 0>; interrupts = <0 52 0>;
}; };
rtc: rtc@101E0000 { serial_2: serial@12C20000 {
compatible = "samsung,s3c6410-rtc"; compatible = "samsung,exynos4210-uart";
reg = <0x101E0000 0x100>; reg = <0x12C20000 0x100>;
interrupts = <0 43 0>, <0 44 0>; interrupts = <0 53 0>;
status = "disabled"; };
};
fimd: fimd@14400000 { serial_3: serial@12C30000 {
compatible = "samsung,exynos5250-fimd"; compatible = "samsung,exynos4210-uart";
interrupt-parent = <&combiner>; reg = <0x12C30000 0x100>;
reg = <0x14400000 0x40000>; interrupts = <0 54 0>;
interrupt-names = "fifo", "vsync", "lcd_sys"; };
interrupts = <18 4>, <18 5>, <18 6>;
samsung,sysreg = <&sysreg_system_controller>;
status = "disabled";
};
dp: dp-controller@145B0000 { i2c_0: i2c@12C60000 {
compatible = "samsung,exynos5-dp"; compatible = "samsung,s3c2440-i2c";
reg = <0x145B0000 0x1000>; reg = <0x12C60000 0x100>;
interrupts = <10 3>; interrupts = <0 56 0>;
interrupt-parent = <&combiner>; #address-cells = <1>;
#address-cells = <1>; #size-cells = <0>;
#size-cells = <0>; samsung,sysreg-phandle = <&sysreg_system_controller>;
status = "disabled"; status = "disabled";
};
i2c_1: i2c@12C70000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C70000 0x100>;
interrupts = <0 57 0>;
#address-cells = <1>;
#size-cells = <0>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
status = "disabled";
};
i2c_2: i2c@12C80000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C80000 0x100>;
interrupts = <0 58 0>;
#address-cells = <1>;
#size-cells = <0>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
status = "disabled";
};
i2c_3: i2c@12C90000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C90000 0x100>;
interrupts = <0 59 0>;
#address-cells = <1>;
#size-cells = <0>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
status = "disabled";
};
pwm: pwm@12DD0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x12DD0000 0x100>;
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
#pwm-cells = <3>;
};
rtc: rtc@101E0000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E0000 0x100>;
interrupts = <0 43 0>, <0 44 0>;
status = "disabled";
};
fimd: fimd@14400000 {
compatible = "samsung,exynos5250-fimd";
interrupt-parent = <&combiner>;
reg = <0x14400000 0x40000>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <18 4>, <18 5>, <18 6>;
samsung,sysreg = <&sysreg_system_controller>;
status = "disabled";
};
dp: dp-controller@145B0000 {
compatible = "samsung,exynos5-dp";
reg = <0x145B0000 0x1000>;
interrupts = <10 3>;
interrupt-parent = <&combiner>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
}; };
}; };
arch/arm/boot/dts/exynos5250-snow-common.dtsi
View file @ 95eb940c
...@@ -61,7 +61,7 @@ i2c-arbitrator { ...@@ -61,7 +61,7 @@ i2c-arbitrator {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
i2c-parent = <&{/i2c@12CA0000}>; i2c-parent = <&i2c_4>;
our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>; our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>;
their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>; their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>;
......
arch/arm/boot/dts/exynos5250.dtsi
View file @ 95eb940c
...@@ -37,10 +37,6 @@ aliases { ...@@ -37,10 +37,6 @@ aliases {
mshc1 = &mmc_1; mshc1 = &mmc_1;
mshc2 = &mmc_2; mshc2 = &mmc_2;
mshc3 = &mmc_3; mshc3 = &mmc_3;
i2c0 = &i2c_0;
i2c1 = &i2c_1;
i2c2 = &i2c_2;
i2c3 = &i2c_3;
i2c4 = &i2c_4; i2c4 = &i2c_4;
i2c5 = &i2c_5; i2c5 = &i2c_5;
i2c6 = &i2c_6; i2c6 = &i2c_6;
...@@ -96,962 +92,896 @@ cpu@1 { ...@@ -96,962 +92,896 @@ cpu@1 {
}; };
}; };
sysram@02020000 { soc: soc {
compatible = "mmio-sram"; sysram@02020000 {
reg = <0x02020000 0x30000>; compatible = "mmio-sram";
#address-cells = <1>; reg = <0x02020000 0x30000>;
#size-cells = <1>; #address-cells = <1>;
ranges = <0 0x02020000 0x30000>; #size-cells = <1>;
ranges = <0 0x02020000 0x30000>;
smp-sysram@0 { smp-sysram@0 {
compatible = "samsung,exynos4210-sysram"; compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>; reg = <0x0 0x1000>;
}; };
smp-sysram@2f000 { smp-sysram@2f000 {
compatible = "samsung,exynos4210-sysram-ns"; compatible = "samsung,exynos4210-sysram-ns";
reg = <0x2f000 0x1000>; reg = <0x2f000 0x1000>;
};
}; };
};
pd_gsc: gsc-power-domain@10044000 { pd_gsc: gsc-power-domain@10044000 {
compatible = "samsung,exynos4210-pd"; compatible = "samsung,exynos4210-pd";
reg = <0x10044000 0x20>; reg = <0x10044000 0x20>;
#power-domain-cells = <0>; #power-domain-cells = <0>;
}; };
pd_mfc: mfc-power-domain@10044040 { pd_mfc: mfc-power-domain@10044040 {
compatible = "samsung,exynos4210-pd"; compatible = "samsung,exynos4210-pd";
reg = <0x10044040 0x20>; reg = <0x10044040 0x20>;
#power-domain-cells = <0>; #power-domain-cells = <0>;
}; };
pd_disp1: disp1-power-domain@100440A0 { pd_disp1: disp1-power-domain@100440A0 {
compatible = "samsung,exynos4210-pd"; compatible = "samsung,exynos4210-pd";
reg = <0x100440A0 0x20>; reg = <0x100440A0 0x20>;
#power-domain-cells = <0>; #power-domain-cells = <0>;
clocks = <&clock CLK_FIN_PLL>, clocks = <&clock CLK_FIN_PLL>,
<&clock CLK_MOUT_ACLK200_DISP1_SUB>, <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
<&clock CLK_MOUT_ACLK300_DISP1_SUB>; <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
clock-names = "oscclk", "clk0", "clk1"; clock-names = "oscclk", "clk0", "clk1";
}; };
clock: clock-controller@10010000 { clock: clock-controller@10010000 {
compatible = "samsung,exynos5250-clock"; compatible = "samsung,exynos5250-clock";
reg = <0x10010000 0x30000>; reg = <0x10010000 0x30000>;
#clock-cells = <1>; #clock-cells = <1>;
}; };
clock_audss: audss-clock-controller@3810000 { clock_audss: audss-clock-controller@3810000 {
compatible = "samsung,exynos5250-audss-clock"; compatible = "samsung,exynos5250-audss-clock";
reg = <0x03810000 0x0C>; reg = <0x03810000 0x0C>;
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
<&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
}; };
timer { timer {
compatible = "arm,armv7-timer"; compatible = "arm,armv7-timer";
interrupts = <1 13 0xf08>, interrupts = <1 13 0xf08>,
<1 14 0xf08>, <1 14 0xf08>,
<1 11 0xf08>, <1 11 0xf08>,
<1 10 0xf08>; <1 10 0xf08>;
/* Unfortunately we need this since some versions of U-Boot /*
* on Exynos don't set the CNTFRQ register, so we need the * Unfortunately we need this since some versions
* value from DT. * of U-Boot on Exynos don't set the CNTFRQ register,
*/ * so we need the value from DT.
clock-frequency = <24000000>; */
}; clock-frequency = <24000000>;
};
mct@101C0000 { mct@101C0000 {
compatible = "samsung,exynos4210-mct"; compatible = "samsung,exynos4210-mct";
reg = <0x101C0000 0x800>; reg = <0x101C0000 0x800>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&mct_map>;
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
mct_map: mct-map {
#interrupt-cells = <2>; #interrupt-cells = <2>;
#address-cells = <0>; interrupt-parent = <&mct_map>;
#size-cells = <0>; interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
interrupt-map = <0x0 0 &combiner 23 3>, <4 0>, <5 0>;
<0x1 0 &combiner 23 4>, clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
<0x2 0 &combiner 25 2>, clock-names = "fin_pll", "mct";
<0x3 0 &combiner 25 3>,
<0x4 0 &gic 0 120 0>, mct_map: mct-map {
<0x5 0 &gic 0 121 0>; #interrupt-cells = <2>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = <0x0 0 &combiner 23 3>,
<0x1 0 &combiner 23 4>,
<0x2 0 &combiner 25 2>,
<0x3 0 &combiner 25 3>,
<0x4 0 &gic 0 120 0>,
<0x5 0 &gic 0 121 0>;
};
}; };
};
pmu {
compatible = "arm,cortex-a15-pmu";
interrupt-parent = <&combiner>;
interrupts = <1 2>, <22 4>;
};
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x11400000 0x1000>;
interrupts = <0 46 0>;
wakup_eint: wakeup-interrupt-controller { pmu {
compatible = "samsung,exynos4210-wakeup-eint"; compatible = "arm,cortex-a15-pmu";
interrupt-parent = <&gic>; interrupt-parent = <&combiner>;
interrupts = <0 32 0>; interrupts = <1 2>, <22 4>;
}; };
};
pinctrl_1: pinctrl@13400000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x13400000 0x1000>;
interrupts = <0 45 0>;
};
pinctrl_2: pinctrl@10d10000 { pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos5250-pinctrl"; compatible = "samsung,exynos5250-pinctrl";
reg = <0x10d10000 0x1000>; reg = <0x11400000 0x1000>;
interrupts = <0 50 0>; interrupts = <0 46 0>;
};
pinctrl_3: pinctrl@03860000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x03860000 0x1000>;
interrupts = <0 47 0>;
};
pmu_system_controller: system-controller@10040000 {
compatible = "samsung,exynos5250-pmu", "syscon";
reg = <0x10040000 0x5000>;
clock-names = "clkout16";
clocks = <&clock CLK_FIN_PLL>;
#clock-cells = <1>;
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
};
sysreg_system_controller: syscon@10050000 { wakup_eint: wakeup-interrupt-controller {
compatible = "samsung,exynos5-sysreg", "syscon"; compatible = "samsung,exynos4210-wakeup-eint";
reg = <0x10050000 0x5000>; interrupt-parent = <&gic>;
}; interrupts = <0 32 0>;
};
};
watchdog@101D0000 { pinctrl_1: pinctrl@13400000 {
compatible = "samsung,exynos5250-wdt"; compatible = "samsung,exynos5250-pinctrl";
reg = <0x101D0000 0x100>; reg = <0x13400000 0x1000>;
interrupts = <0 42 0>; interrupts = <0 45 0>;
clocks = <&clock CLK_WDT>; };
clock-names = "watchdog";
samsung,syscon-phandle = <&pmu_system_controller>;
};
g2d@10850000 { pinctrl_2: pinctrl@10d10000 {
compatible = "samsung,exynos5250-g2d"; compatible = "samsung,exynos5250-pinctrl";
reg = <0x10850000 0x1000>; reg = <0x10d10000 0x1000>;
interrupts = <0 91 0>; interrupts = <0 50 0>;
clocks = <&clock CLK_G2D>; };
clock-names = "fimg2d";
iommus = <&sysmmu_g2d>;
};
mfc: codec@11000000 { pinctrl_3: pinctrl@03860000 {
compatible = "samsung,mfc-v6"; compatible = "samsung,exynos5250-pinctrl";
reg = <0x11000000 0x10000>; reg = <0x03860000 0x1000>;
interrupts = <0 96 0>; interrupts = <0 47 0>;
power-domains = <&pd_mfc>; };
clocks = <&clock CLK_MFC>;
clock-names = "mfc";
iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
iommu-names = "left", "right";
};
rotator: rotator@11C00000 { pmu_system_controller: system-controller@10040000 {
compatible = "samsung,exynos5250-rotator"; compatible = "samsung,exynos5250-pmu", "syscon";
reg = <0x11C00000 0x64>; reg = <0x10040000 0x5000>;
interrupts = <0 84 0>; clock-names = "clkout16";
clocks = <&clock CLK_ROTATOR>; clocks = <&clock CLK_FIN_PLL>;
clock-names = "rotator"; #clock-cells = <1>;
iommus = <&sysmmu_rotator>; interrupt-controller;
}; #interrupt-cells = <3>;
interrupt-parent = <&gic>;
};
tmu: tmu@10060000 { watchdog@101D0000 {
compatible = "samsung,exynos5250-tmu"; compatible = "samsung,exynos5250-wdt";
reg = <0x10060000 0x100>; reg = <0x101D0000 0x100>;
interrupts = <0 65 0>; interrupts = <0 42 0>;
clocks = <&clock CLK_TMU>; clocks = <&clock CLK_WDT>;
clock-names = "tmu_apbif"; clock-names = "watchdog";
#include "exynos4412-tmu-sensor-conf.dtsi" samsung,syscon-phandle = <&pmu_system_controller>;
}; };
thermal-zones { g2d@10850000 {
cpu_thermal: cpu-thermal { compatible = "samsung,exynos5250-g2d";
polling-delay-passive = <0>; reg = <0x10850000 0x1000>;
polling-delay = <0>; interrupts = <0 91 0>;
thermal-sensors = <&tmu 0>; clocks = <&clock CLK_G2D>;
clock-names = "fimg2d";
iommus = <&sysmmu_g2d>;
};
cooling-maps { mfc: codec@11000000 {
map0 { compatible = "samsung,mfc-v6";
/* Corresponds to 800MHz at freq_table */ reg = <0x11000000 0x10000>;
cooling-device = <&cpu0 9 9>; interrupts = <0 96 0>;
}; power-domains = <&pd_mfc>;
map1 { clocks = <&clock CLK_MFC>;
/* Corresponds to 200MHz at freq_table */ clock-names = "mfc";
cooling-device = <&cpu0 15 15>; iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
}; iommu-names = "left", "right";
};
}; };
};
sata: sata@122F0000 { rotator: rotator@11C00000 {
compatible = "snps,dwc-ahci"; compatible = "samsung,exynos5250-rotator";
samsung,sata-freq = <66>; reg = <0x11C00000 0x64>;
reg = <0x122F0000 0x1ff>; interrupts = <0 84 0>;
interrupts = <0 115 0>; clocks = <&clock CLK_ROTATOR>;
clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; clock-names = "rotator";
clock-names = "sata", "sclk_sata"; iommus = <&sysmmu_rotator>;
phys = <&sata_phy>; };
phy-names = "sata-phy";
status = "disabled";
};
sata_phy: sata-phy@12170000 { tmu: tmu@10060000 {
compatible = "samsung,exynos5250-sata-phy"; compatible = "samsung,exynos5250-tmu";
reg = <0x12170000 0x1ff>; reg = <0x10060000 0x100>;
clocks = <&clock CLK_SATA_PHYCTRL>; interrupts = <0 65 0>;
clock-names = "sata_phyctrl"; clocks = <&clock CLK_TMU>;
#phy-cells = <0>; clock-names = "tmu_apbif";
samsung,syscon-phandle = <&pmu_system_controller>; #include "exynos4412-tmu-sensor-conf.dtsi"
status = "disabled"; };
};
i2c_0: i2c@12C60000 { sata: sata@122F0000 {
compatible = "samsung,s3c2440-i2c"; compatible = "snps,dwc-ahci";
reg = <0x12C60000 0x100>; samsung,sata-freq = <66>;
interrupts = <0 56 0>; reg = <0x122F0000 0x1ff>;
#address-cells = <1>; interrupts = <0 115 0>;
#size-cells = <0>; clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
clocks = <&clock CLK_I2C0>; clock-names = "sata", "sclk_sata";
clock-names = "i2c"; phys = <&sata_phy>;
pinctrl-names = "default"; phy-names = "sata-phy";
pinctrl-0 = <&i2c0_bus>; status = "disabled";
samsung,sysreg-phandle = <&sysreg_system_controller>; };
status = "disabled";
};
i2c_1: i2c@12C70000 { sata_phy: sata-phy@12170000 {
compatible = "samsung,s3c2440-i2c"; compatible = "samsung,exynos5250-sata-phy";
reg = <0x12C70000 0x100>; reg = <0x12170000 0x1ff>;
interrupts = <0 57 0>; clocks = <&clock CLK_SATA_PHYCTRL>;
#address-cells = <1>; clock-names = "sata_phyctrl";
#size-cells = <0>; #phy-cells = <0>;
clocks = <&clock CLK_I2C1>; samsung,syscon-phandle = <&pmu_system_controller>;
clock-names = "i2c"; status = "disabled";
pinctrl-names = "default"; };
pinctrl-0 = <&i2c1_bus>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
status = "disabled";
};
i2c_2: i2c@12C80000 { /* i2c_0-3 are defined in exynos5.dtsi */
compatible = "samsung,s3c2440-i2c"; i2c_4: i2c@12CA0000 {
reg = <0x12C80000 0x100>; compatible = "samsung,s3c2440-i2c";
interrupts = <0 58 0>; reg = <0x12CA0000 0x100>;
#address-cells = <1>; interrupts = <0 60 0>;
#size-cells = <0>; #address-cells = <1>;
clocks = <&clock CLK_I2C2>; #size-cells = <0>;
clock-names = "i2c"; clocks = <&clock CLK_I2C4>;
pinctrl-names = "default"; clock-names = "i2c";
pinctrl-0 = <&i2c2_bus>; pinctrl-names = "default";
samsung,sysreg-phandle = <&sysreg_system_controller>; pinctrl-0 = <&i2c4_bus>;
status = "disabled"; status = "disabled";
}; };
i2c_3: i2c@12C90000 { i2c_5: i2c@12CB0000 {
compatible = "samsung,s3c2440-i2c"; compatible = "samsung,s3c2440-i2c";
reg = <0x12C90000 0x100>; reg = <0x12CB0000 0x100>;
interrupts = <0 59 0>; interrupts = <0 61 0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock CLK_I2C3>; clocks = <&clock CLK_I2C5>;
clock-names = "i2c"; clock-names = "i2c";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&i2c3_bus>; pinctrl-0 = <&i2c5_bus>;
samsung,sysreg-phandle = <&sysreg_system_controller>; status = "disabled";
status = "disabled"; };
};
i2c_4: i2c@12CA0000 { i2c_6: i2c@12CC0000 {
compatible = "samsung,s3c2440-i2c"; compatible = "samsung,s3c2440-i2c";
reg = <0x12CA0000 0x100>; reg = <0x12CC0000 0x100>;
interrupts = <0 60 0>; interrupts = <0 62 0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock CLK_I2C4>; clocks = <&clock CLK_I2C6>;
clock-names = "i2c"; clock-names = "i2c";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&i2c4_bus>; pinctrl-0 = <&i2c6_bus>;
status = "disabled"; status = "disabled";
}; };
i2c_5: i2c@12CB0000 { i2c_7: i2c@12CD0000 {
compatible = "samsung,s3c2440-i2c"; compatible = "samsung,s3c2440-i2c";
reg = <0x12CB0000 0x100>; reg = <0x12CD0000 0x100>;
interrupts = <0 61 0>; interrupts = <0 63 0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock CLK_I2C5>; clocks = <&clock CLK_I2C7>;
clock-names = "i2c"; clock-names = "i2c";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&i2c5_bus>; pinctrl-0 = <&i2c7_bus>;
status = "disabled"; status = "disabled";
}; };
i2c_6: i2c@12CC0000 { i2c_8: i2c@12CE0000 {
compatible = "samsung,s3c2440-i2c"; compatible = "samsung,s3c2440-hdmiphy-i2c";
reg = <0x12CC0000 0x100>; reg = <0x12CE0000 0x1000>;
interrupts = <0 62 0>; interrupts = <0 64 0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock CLK_I2C6>; clocks = <&clock CLK_I2C_HDMI>;
clock-names = "i2c"; clock-names = "i2c";
pinctrl-names = "default"; status = "disabled";
pinctrl-0 = <&i2c6_bus>; };
status = "disabled";
};
i2c_7: i2c@12CD0000 { i2c_9: i2c@121D0000 {
compatible = "samsung,s3c2440-i2c"; compatible = "samsung,exynos5-sata-phy-i2c";
reg = <0x12CD0000 0x100>; reg = <0x121D0000 0x100>;
interrupts = <0 63 0>; #address-cells = <1>;
#address-cells = <1>; #size-cells = <0>;
#size-cells = <0>; clocks = <&clock CLK_SATA_PHYI2C>;
clocks = <&clock CLK_I2C7>; clock-names = "i2c";
clock-names = "i2c"; status = "disabled";
pinctrl-names = "default"; };
pinctrl-0 = <&i2c7_bus>;
status = "disabled";
};
i2c_8: i2c@12CE0000 { spi_0: spi@12d20000 {
compatible = "samsung,s3c2440-hdmiphy-i2c"; compatible = "samsung,exynos4210-spi";
reg = <0x12CE0000 0x1000>; status = "disabled";
interrupts = <0 64 0>; reg = <0x12d20000 0x100>;
#address-cells = <1>; interrupts = <0 66 0>;
#size-cells = <0>; dmas = <&pdma0 5
clocks = <&clock CLK_I2C_HDMI>; &pdma0 4>;
clock-names = "i2c"; dma-names = "tx", "rx";
status = "disabled"; #address-cells = <1>;
}; #size-cells = <0>;
clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi0_bus>;
};
i2c_9: i2c@121D0000 { spi_1: spi@12d30000 {
compatible = "samsung,exynos5-sata-phy-i2c"; compatible = "samsung,exynos4210-spi";
reg = <0x121D0000 0x100>; status = "disabled";
#address-cells = <1>; reg = <0x12d30000 0x100>;
#size-cells = <0>; interrupts = <0 67 0>;
clocks = <&clock CLK_SATA_PHYI2C>; dmas = <&pdma1 5
clock-names = "i2c"; &pdma1 4>;
status = "disabled"; dma-names = "tx", "rx";
}; #address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi1_bus>;
};
spi_0: spi@12d20000 { spi_2: spi@12d40000 {
compatible = "samsung,exynos4210-spi"; compatible = "samsung,exynos4210-spi";
status = "disabled"; status = "disabled";
reg = <0x12d20000 0x100>; reg = <0x12d40000 0x100>;
interrupts = <0 66 0>; interrupts = <0 68 0>;
dmas = <&pdma0 5 dmas = <&pdma0 7
&pdma0 4>; &pdma0 6>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
clock-names = "spi", "spi_busclk0"; clock-names = "spi", "spi_busclk0";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&spi0_bus>; pinctrl-0 = <&spi2_bus>;
}; };
spi_1: spi@12d30000 { mmc_0: mmc@12200000 {
compatible = "samsung,exynos4210-spi"; compatible = "samsung,exynos5250-dw-mshc";
status = "disabled"; interrupts = <0 75 0>;
reg = <0x12d30000 0x100>; #address-cells = <1>;
interrupts = <0 67 0>; #size-cells = <0>;
dmas = <&pdma1 5 reg = <0x12200000 0x1000>;
&pdma1 4>; clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
dma-names = "tx", "rx"; clock-names = "biu", "ciu";
#address-cells = <1>; fifo-depth = <0x80>;
#size-cells = <0>; status = "disabled";
clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; };
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi1_bus>;
};
spi_2: spi@12d40000 { mmc_1: mmc@12210000 {
compatible = "samsung,exynos4210-spi"; compatible = "samsung,exynos5250-dw-mshc";
status = "disabled"; interrupts = <0 76 0>;
reg = <0x12d40000 0x100>; #address-cells = <1>;
interrupts = <0 68 0>; #size-cells = <0>;
dmas = <&pdma0 7 reg = <0x12210000 0x1000>;
&pdma0 6>; clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
dma-names = "tx", "rx"; clock-names = "biu", "ciu";
#address-cells = <1>; fifo-depth = <0x80>;
#size-cells = <0>; status = "disabled";
clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; };
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi2_bus>;
};
mmc_0: mmc@12200000 { mmc_2: mmc@12220000 {
compatible = "samsung,exynos5250-dw-mshc"; compatible = "samsung,exynos5250-dw-mshc";
interrupts = <0 75 0>; interrupts = <0 77 0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <0x12200000 0x1000>; reg = <0x12220000 0x1000>;
clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
clock-names = "biu", "ciu"; clock-names = "biu", "ciu";
fifo-depth = <0x80>; fifo-depth = <0x80>;
status = "disabled"; status = "disabled";
}; };
mmc_1: mmc@12210000 { mmc_3: mmc@12230000 {
compatible = "samsung,exynos5250-dw-mshc"; compatible = "samsung,exynos5250-dw-mshc";
interrupts = <0 76 0>; reg = <0x12230000 0x1000>;
#address-cells = <1>; interrupts = <0 78 0>;
#size-cells = <0>; #address-cells = <1>;
reg = <0x12210000 0x1000>; #size-cells = <0>;
clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
clock-names = "biu", "ciu"; clock-names = "biu", "ciu";
fifo-depth = <0x80>; fifo-depth = <0x80>;
status = "disabled"; status = "disabled";
}; };
mmc_2: mmc@12220000 { i2s0: i2s@03830000 {
compatible = "samsung,exynos5250-dw-mshc"; compatible = "samsung,s5pv210-i2s";
interrupts = <0 77 0>; status = "disabled";
#address-cells = <1>; reg = <0x03830000 0x100>;
#size-cells = <0>; dmas = <&pdma0 10
reg = <0x12220000 0x1000>; &pdma0 9
clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; &pdma0 8>;
clock-names = "biu", "ciu"; dma-names = "tx", "rx", "tx-sec";
fifo-depth = <0x80>; clocks = <&clock_audss EXYNOS_I2S_BUS>,
status = "disabled"; <&clock_audss EXYNOS_I2S_BUS>,
}; <&clock_audss EXYNOS_SCLK_I2S>;
clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
samsung,idma-addr = <0x03000000>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
};
mmc_3: mmc@12230000 { i2s1: i2s@12D60000 {
compatible = "samsung,exynos5250-dw-mshc"; compatible = "samsung,s3c6410-i2s";
reg = <0x12230000 0x1000>; status = "disabled";
interrupts = <0 78 0>; reg = <0x12D60000 0x100>;
#address-cells = <1>; dmas = <&pdma1 12
#size-cells = <0>; &pdma1 11>;
clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; dma-names = "tx", "rx";
clock-names = "biu", "ciu"; clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
fifo-depth = <0x80>; clock-names = "iis", "i2s_opclk0";
status = "disabled"; pinctrl-names = "default";
}; pinctrl-0 = <&i2s1_bus>;
};
i2s0: i2s@03830000 { i2s2: i2s@12D70000 {
compatible = "samsung,s5pv210-i2s"; compatible = "samsung,s3c6410-i2s";
status = "disabled"; status = "disabled";
reg = <0x03830000 0x100>; reg = <0x12D70000 0x100>;
dmas = <&pdma0 10 dmas = <&pdma0 12
&pdma0 9 &pdma0 11>;
&pdma0 8>; dma-names = "tx", "rx";
dma-names = "tx", "rx", "tx-sec"; clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
clocks = <&clock_audss EXYNOS_I2S_BUS>, clock-names = "iis", "i2s_opclk0";
<&clock_audss EXYNOS_I2S_BUS>, pinctrl-names = "default";
<&clock_audss EXYNOS_SCLK_I2S>; pinctrl-0 = <&i2s2_bus>;
clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; };
samsung,idma-addr = <0x03000000>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
};
i2s1: i2s@12D60000 { usb_dwc3 {
compatible = "samsung,s3c6410-i2s"; compatible = "samsung,exynos5250-dwusb3";
status = "disabled"; clocks = <&clock CLK_USB3>;
reg = <0x12D60000 0x100>; clock-names = "usbdrd30";
dmas = <&pdma1 12 #address-cells = <1>;
&pdma1 11>; #size-cells = <1>;
dma-names = "tx", "rx"; ranges;
clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
clock-names = "iis", "i2s_opclk0"; usbdrd_dwc3: dwc3@12000000 {
pinctrl-names = "default"; compatible = "synopsys,dwc3";
pinctrl-0 = <&i2s1_bus>; reg = <0x12000000 0x10000>;
}; interrupts = <0 72 0>;
phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
phy-names = "usb2-phy", "usb3-phy";
};
};
i2s2: i2s@12D70000 { usbdrd_phy: phy@12100000 {
compatible = "samsung,s3c6410-i2s"; compatible = "samsung,exynos5250-usbdrd-phy";
status = "disabled"; reg = <0x12100000 0x100>;
reg = <0x12D70000 0x100>; clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
dmas = <&pdma0 12 clock-names = "phy", "ref";
&pdma0 11>; samsung,pmu-syscon = <&pmu_system_controller>;
dma-names = "tx", "rx"; #phy-cells = <1>;
clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; };
clock-names = "iis", "i2s_opclk0";
pinctrl-names = "default";
pinctrl-0 = <&i2s2_bus>;
};
usb_dwc3 { ehci: usb@12110000 {
compatible = "samsung,exynos5250-dwusb3"; compatible = "samsung,exynos4210-ehci";
clocks = <&clock CLK_USB3>; reg = <0x12110000 0x100>;
clock-names = "usbdrd30"; interrupts = <0 71 0>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
usbdrd_dwc3: dwc3@12000000 { clocks = <&clock CLK_USB2>;
compatible = "synopsys,dwc3"; clock-names = "usbhost";
reg = <0x12000000 0x10000>; #address-cells = <1>;
interrupts = <0 72 0>; #size-cells = <0>;
phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; port@0 {
phy-names = "usb2-phy", "usb3-phy"; reg = <0>;
phys = <&usb2_phy_gen 1>;
};
}; };
};
usbdrd_phy: phy@12100000 {
compatible = "samsung,exynos5250-usbdrd-phy";
reg = <0x12100000 0x100>;
clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
clock-names = "phy", "ref";
samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <1>;
};
ehci: usb@12110000 { ohci: usb@12120000 {
compatible = "samsung,exynos4210-ehci"; compatible = "samsung,exynos4210-ohci";
reg = <0x12110000 0x100>; reg = <0x12120000 0x100>;
interrupts = <0 71 0>; interrupts = <0 71 0>;
clocks = <&clock CLK_USB2>; clocks = <&clock CLK_USB2>;
clock-names = "usbhost"; clock-names = "usbhost";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
port@0 { port@0 {
reg = <0>; reg = <0>;
phys = <&usb2_phy_gen 1>; phys = <&usb2_phy_gen 1>;
};
}; };
};
ohci: usb@12120000 { usb2_phy_gen: phy@12130000 {
compatible = "samsung,exynos4210-ohci"; compatible = "samsung,exynos5250-usb2-phy";
reg = <0x12120000 0x100>; reg = <0x12130000 0x100>;
interrupts = <0 71 0>; clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
clock-names = "phy", "ref";
clocks = <&clock CLK_USB2>; #phy-cells = <1>;
clock-names = "usbhost"; samsung,sysreg-phandle = <&sysreg_system_controller>;
#address-cells = <1>; samsung,pmureg-phandle = <&pmu_system_controller>;
#size-cells = <0>;
port@0 {
reg = <0>;
phys = <&usb2_phy_gen 1>;
}; };
};
usb2_phy_gen: phy@12130000 { amba {
compatible = "samsung,exynos5250-usb2-phy"; #address-cells = <1>;
reg = <0x12130000 0x100>; #size-cells = <1>;
clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; compatible = "simple-bus";
clock-names = "phy", "ref"; interrupt-parent = <&gic>;
#phy-cells = <1>; ranges;
samsung,sysreg-phandle = <&sysreg_system_controller>;
samsung,pmureg-phandle = <&pmu_system_controller>; pdma0: pdma@121A0000 {
}; compatible = "arm,pl330", "arm,primecell";
reg = <0x121A0000 0x1000>;
interrupts = <0 34 0>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: pdma@121B0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121B0000 0x1000>;
interrupts = <0 35 0>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
mdma0: mdma@10800000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>;
interrupts = <0 33 0>;
clocks = <&clock CLK_MDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
};
mdma1: mdma@11C10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
interrupts = <0 124 0>;
clocks = <&clock CLK_MDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
};
};
pwm: pwm@12dd0000 { gsc_0: gsc@13e00000 {
compatible = "samsung,exynos4210-pwm"; compatible = "samsung,exynos5-gsc";
reg = <0x12dd0000 0x100>; reg = <0x13e00000 0x1000>;
samsung,pwm-outputs = <0>, <1>, <2>, <3>; interrupts = <0 85 0>;
#pwm-cells = <3>; power-domains = <&pd_gsc>;
clocks = <&clock CLK_PWM>; clocks = <&clock CLK_GSCL0>;
clock-names = "timers"; clock-names = "gscl";
}; iommu = <&sysmmu_gsc0>;
};
amba { gsc_1: gsc@13e10000 {
#address-cells = <1>; compatible = "samsung,exynos5-gsc";
#size-cells = <1>; reg = <0x13e10000 0x1000>;
compatible = "simple-bus"; interrupts = <0 86 0>;
interrupt-parent = <&gic>; power-domains = <&pd_gsc>;
ranges; clocks = <&clock CLK_GSCL1>;
clock-names = "gscl";
pdma0: pdma@121A0000 { iommu = <&sysmmu_gsc1>;
compatible = "arm,pl330", "arm,primecell";
reg = <0x121A0000 0x1000>;
interrupts = <0 34 0>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: pdma@121B0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121B0000 0x1000>;
interrupts = <0 35 0>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
mdma0: mdma@10800000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>;
interrupts = <0 33 0>;
clocks = <&clock CLK_MDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
};
mdma1: mdma@11C10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
interrupts = <0 124 0>;
clocks = <&clock CLK_MDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
}; };
};
gsc_0: gsc@13e00000 { gsc_2: gsc@13e20000 {
compatible = "samsung,exynos5-gsc"; compatible = "samsung,exynos5-gsc";
reg = <0x13e00000 0x1000>; reg = <0x13e20000 0x1000>;
interrupts = <0 85 0>; interrupts = <0 87 0>;
power-domains = <&pd_gsc>; power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL0>; clocks = <&clock CLK_GSCL2>;
clock-names = "gscl"; clock-names = "gscl";
iommu = <&sysmmu_gsc0>; iommu = <&sysmmu_gsc2>;
}; };
gsc_1: gsc@13e10000 { gsc_3: gsc@13e30000 {
compatible = "samsung,exynos5-gsc"; compatible = "samsung,exynos5-gsc";
reg = <0x13e10000 0x1000>; reg = <0x13e30000 0x1000>;
interrupts = <0 86 0>; interrupts = <0 88 0>;
power-domains = <&pd_gsc>; power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL1>; clocks = <&clock CLK_GSCL3>;
clock-names = "gscl"; clock-names = "gscl";
iommu = <&sysmmu_gsc1>; iommu = <&sysmmu_gsc3>;
}; };
gsc_2: gsc@13e20000 { hdmi: hdmi@14530000 {
compatible = "samsung,exynos5-gsc"; compatible = "samsung,exynos4212-hdmi";
reg = <0x13e20000 0x1000>; reg = <0x14530000 0x70000>;
interrupts = <0 87 0>; power-domains = <&pd_disp1>;
power-domains = <&pd_gsc>; interrupts = <0 95 0>;
clocks = <&clock CLK_GSCL2>; clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
clock-names = "gscl"; <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
iommu = <&sysmmu_gsc2>; <&clock CLK_MOUT_HDMI>;
}; clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
"sclk_hdmiphy", "mout_hdmi";
samsung,syscon-phandle = <&pmu_system_controller>;
};
gsc_3: gsc@13e30000 { mixer@14450000 {
compatible = "samsung,exynos5-gsc"; compatible = "samsung,exynos5250-mixer";
reg = <0x13e30000 0x1000>; reg = <0x14450000 0x10000>;
interrupts = <0 88 0>; power-domains = <&pd_disp1>;
power-domains = <&pd_gsc>; interrupts = <0 94 0>;
clocks = <&clock CLK_GSCL3>; clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
clock-names = "gscl"; <&clock CLK_SCLK_HDMI>;
iommu = <&sysmmu_gsc3>; clock-names = "mixer", "hdmi", "sclk_hdmi";
}; iommus = <&sysmmu_tv>;
};
hdmi: hdmi@14530000 { dp_phy: video-phy {
compatible = "samsung,exynos4212-hdmi"; compatible = "samsung,exynos5250-dp-video-phy";
reg = <0x14530000 0x70000>; samsung,pmu-syscon = <&pmu_system_controller>;
power-domains = <&pd_disp1>; #phy-cells = <0>;
interrupts = <0 95 0>; };
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
<&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
<&clock CLK_MOUT_HDMI>;
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
"sclk_hdmiphy", "mout_hdmi";
samsung,syscon-phandle = <&pmu_system_controller>;
};
mixer@14450000 { adc: adc@12D10000 {
compatible = "samsung,exynos5250-mixer"; compatible = "samsung,exynos-adc-v1";
reg = <0x14450000 0x10000>; reg = <0x12D10000 0x100>;
power-domains = <&pd_disp1>; interrupts = <0 106 0>;
interrupts = <0 94 0>; clocks = <&clock CLK_ADC>;
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, clock-names = "adc";
<&clock CLK_SCLK_HDMI>; #io-channel-cells = <1>;
clock-names = "mixer", "hdmi", "sclk_hdmi"; io-channel-ranges;
iommus = <&sysmmu_tv>; samsung,syscon-phandle = <&pmu_system_controller>;
}; status = "disabled";
};
dp_phy: video-phy { sss@10830000 {
compatible = "samsung,exynos5250-dp-video-phy"; compatible = "samsung,exynos4210-secss";
samsung,pmu-syscon = <&pmu_system_controller>; reg = <0x10830000 0x300>;
#phy-cells = <0>; interrupts = <0 112 0>;
}; clocks = <&clock CLK_SSS>;
clock-names = "secss";
};
adc: adc@12D10000 { sysmmu_g2d: sysmmu@10A60000 {
compatible = "samsung,exynos-adc-v1"; compatible = "samsung,exynos-sysmmu";
reg = <0x12D10000 0x100>; reg = <0x10A60000 0x1000>;
interrupts = <0 106 0>; interrupt-parent = <&combiner>;
clocks = <&clock CLK_ADC>; interrupts = <24 5>;
clock-names = "adc"; clock-names = "sysmmu", "master";
#io-channel-cells = <1>; clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
io-channel-ranges; #iommu-cells = <0>;
samsung,syscon-phandle = <&pmu_system_controller>; };
status = "disabled";
};
sss@10830000 { sysmmu_mfc_r: sysmmu@11200000 {
compatible = "samsung,exynos4210-secss"; compatible = "samsung,exynos-sysmmu";
reg = <0x10830000 0x300>; reg = <0x11200000 0x1000>;
interrupts = <0 112 0>; interrupt-parent = <&combiner>;
clocks = <&clock CLK_SSS>; interrupts = <6 2>;
clock-names = "secss"; power-domains = <&pd_mfc>;
}; clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
#iommu-cells = <0>;
};
sysmmu_g2d: sysmmu@10A60000 { sysmmu_mfc_l: sysmmu@11210000 {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x10A60000 0x1000>; reg = <0x11210000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <24 5>; interrupts = <8 5>;
clock-names = "sysmmu", "master"; power-domains = <&pd_mfc>;
clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>; clock-names = "sysmmu", "master";
#iommu-cells = <0>; clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
}; #iommu-cells = <0>;
};
sysmmu_mfc_r: sysmmu@11200000 { sysmmu_rotator: sysmmu@11D40000 {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x11200000 0x1000>; reg = <0x11D40000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <6 2>; interrupts = <4 0>;
power-domains = <&pd_mfc>; clock-names = "sysmmu", "master";
clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; #iommu-cells = <0>;
#iommu-cells = <0>; };
};
sysmmu_mfc_l: sysmmu@11210000 { sysmmu_jpeg: sysmmu@11F20000 {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x11210000 0x1000>; reg = <0x11F20000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <8 5>; interrupts = <4 2>;
power-domains = <&pd_mfc>; power-domains = <&pd_gsc>;
clock-names = "sysmmu", "master"; clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
#iommu-cells = <0>; #iommu-cells = <0>;
}; };
sysmmu_rotator: sysmmu@11D40000 { sysmmu_fimc_isp: sysmmu@13260000 {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x11D40000 0x1000>; reg = <0x13260000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <4 0>; interrupts = <10 6>;
clock-names = "sysmmu", "master"; clock-names = "sysmmu";
clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; clocks = <&clock CLK_SMMU_FIMC_ISP>;
#iommu-cells = <0>; #iommu-cells = <0>;
}; };
sysmmu_jpeg: sysmmu@11F20000 { sysmmu_fimc_drc: sysmmu@13270000 {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x11F20000 0x1000>; reg = <0x13270000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <4 2>; interrupts = <11 6>;
power-domains = <&pd_gsc>; clock-names = "sysmmu";
clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_FIMC_DRC>;
clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; #iommu-cells = <0>;
#iommu-cells = <0>; };
};
sysmmu_fimc_isp: sysmmu@13260000 { sysmmu_fimc_fd: sysmmu@132A0000 {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x13260000 0x1000>; reg = <0x132A0000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <10 6>; interrupts = <5 0>;
clock-names = "sysmmu"; clock-names = "sysmmu";
clocks = <&clock CLK_SMMU_FIMC_ISP>; clocks = <&clock CLK_SMMU_FIMC_FD>;
#iommu-cells = <0>; #iommu-cells = <0>;
}; };
sysmmu_fimc_drc: sysmmu@13270000 { sysmmu_fimc_scc: sysmmu@13280000 {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x13270000 0x1000>; reg = <0x13280000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <11 6>; interrupts = <5 2>;
clock-names = "sysmmu"; clock-names = "sysmmu";
clocks = <&clock CLK_SMMU_FIMC_DRC>; clocks = <&clock CLK_SMMU_FIMC_SCC>;
#iommu-cells = <0>; #iommu-cells = <0>;
}; };
sysmmu_fimc_fd: sysmmu@132A0000 { sysmmu_fimc_scp: sysmmu@13290000 {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x132A0000 0x1000>; reg = <0x13290000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <5 0>; interrupts = <3 6>;
clock-names = "sysmmu"; clock-names = "sysmmu";
clocks = <&clock CLK_SMMU_FIMC_FD>; clocks = <&clock CLK_SMMU_FIMC_SCP>;
#iommu-cells = <0>; #iommu-cells = <0>;
}; };
sysmmu_fimc_scc: sysmmu@13280000 { sysmmu_fimc_mcuctl: sysmmu@132B0000 {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x13280000 0x1000>; reg = <0x132B0000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <5 2>; interrupts = <5 4>;
clock-names = "sysmmu"; clock-names = "sysmmu";
clocks = <&clock CLK_SMMU_FIMC_SCC>; clocks = <&clock CLK_SMMU_FIMC_MCU>;
#iommu-cells = <0>; #iommu-cells = <0>;
}; };
sysmmu_fimc_scp: sysmmu@13290000 { sysmmu_fimc_odc: sysmmu@132C0000 {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x13290000 0x1000>; reg = <0x132C0000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <3 6>; interrupts = <11 0>;
clock-names = "sysmmu"; clock-names = "sysmmu";
clocks = <&clock CLK_SMMU_FIMC_SCP>; clocks = <&clock CLK_SMMU_FIMC_ODC>;
#iommu-cells = <0>; #iommu-cells = <0>;
}; };
sysmmu_fimc_mcuctl: sysmmu@132B0000 { sysmmu_fimc_dis0: sysmmu@132D0000 {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x132B0000 0x1000>; reg = <0x132D0000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <5 4>; interrupts = <10 4>;
clock-names = "sysmmu"; clock-names = "sysmmu";
clocks = <&clock CLK_SMMU_FIMC_MCU>; clocks = <&clock CLK_SMMU_FIMC_DIS0>;
#iommu-cells = <0>; #iommu-cells = <0>;
}; };
sysmmu_fimc_odc: sysmmu@132C0000 { sysmmu_fimc_dis1: sysmmu@132E0000{
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x132C0000 0x1000>; reg = <0x132E0000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <11 0>; interrupts = <9 4>;
clock-names = "sysmmu"; clock-names = "sysmmu";
clocks = <&clock CLK_SMMU_FIMC_ODC>; clocks = <&clock CLK_SMMU_FIMC_DIS1>;
#iommu-cells = <0>; #iommu-cells = <0>;
}; };
sysmmu_fimc_dis0: sysmmu@132D0000 { sysmmu_fimc_3dnr: sysmmu@132F0000 {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x132D0000 0x1000>; reg = <0x132F0000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <10 4>; interrupts = <5 6>;
clock-names = "sysmmu"; clock-names = "sysmmu";
clocks = <&clock CLK_SMMU_FIMC_DIS0>; clocks = <&clock CLK_SMMU_FIMC_3DNR>;
#iommu-cells = <0>; #iommu-cells = <0>;
}; };
sysmmu_fimc_dis1: sysmmu@132E0000{ sysmmu_fimc_lite0: sysmmu@13C40000 {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x132E0000 0x1000>; reg = <0x13C40000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <9 4>; interrupts = <3 4>;
clock-names = "sysmmu"; power-domains = <&pd_gsc>;
clocks = <&clock CLK_SMMU_FIMC_DIS1>; clock-names = "sysmmu", "master";
#iommu-cells = <0>; clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
}; #iommu-cells = <0>;
};
sysmmu_fimc_3dnr: sysmmu@132F0000 { sysmmu_fimc_lite1: sysmmu@13C50000 {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x132F0000 0x1000>; reg = <0x13C50000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <5 6>; interrupts = <24 1>;
clock-names = "sysmmu"; power-domains = <&pd_gsc>;
clocks = <&clock CLK_SMMU_FIMC_3DNR>; clock-names = "sysmmu", "master";
#iommu-cells = <0>; clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
}; #iommu-cells = <0>;
};
sysmmu_fimc_lite0: sysmmu@13C40000 { sysmmu_gsc0: sysmmu@13E80000 {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x13C40000 0x1000>; reg = <0x13E80000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <3 4>; interrupts = <2 0>;
power-domains = <&pd_gsc>; power-domains = <&pd_gsc>;
clock-names = "sysmmu", "master"; clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>; clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
#iommu-cells = <0>; #iommu-cells = <0>;
}; };
sysmmu_fimc_lite1: sysmmu@13C50000 { sysmmu_gsc1: sysmmu@13E90000 {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x13C50000 0x1000>; reg = <0x13E90000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <24 1>; interrupts = <2 2>;
power-domains = <&pd_gsc>; power-domains = <&pd_gsc>;
clock-names = "sysmmu", "master"; clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>; clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
#iommu-cells = <0>; #iommu-cells = <0>;
}; };
sysmmu_gsc0: sysmmu@13E80000 { sysmmu_gsc2: sysmmu@13EA0000 {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x13E80000 0x1000>; reg = <0x13EA0000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <2 0>; interrupts = <2 4>;
power-domains = <&pd_gsc>; power-domains = <&pd_gsc>;
clock-names = "sysmmu", "master"; clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
#iommu-cells = <0>; #iommu-cells = <0>;
}; };
sysmmu_gsc1: sysmmu@13E90000 { sysmmu_gsc3: sysmmu@13EB0000 {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x13E90000 0x1000>; reg = <0x13EB0000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <2 2>; interrupts = <2 6>;
power-domains = <&pd_gsc>; power-domains = <&pd_gsc>;
clock-names = "sysmmu", "master"; clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
#iommu-cells = <0>; #iommu-cells = <0>;
}; };
sysmmu_gsc2: sysmmu@13EA0000 { sysmmu_fimd1: sysmmu@14640000 {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x13EA0000 0x1000>; reg = <0x14640000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <2 4>; interrupts = <3 2>;
power-domains = <&pd_gsc>; power-domains = <&pd_disp1>;
clock-names = "sysmmu", "master"; clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>; clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
#iommu-cells = <0>; #iommu-cells = <0>;
}; };
sysmmu_gsc3: sysmmu@13EB0000 { sysmmu_tv: sysmmu@14650000 {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x13EB0000 0x1000>; reg = <0x14650000 0x1000>;
interrupt-parent = <&combiner>; interrupt-parent = <&combiner>;
interrupts = <2 6>; interrupts = <7 4>;
power-domains = <&pd_gsc>; power-domains = <&pd_disp1>;
clock-names = "sysmmu", "master"; clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>; clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
#iommu-cells = <0>; #iommu-cells = <0>;
};
}; };
sysmmu_fimd1: sysmmu@14640000 { thermal-zones {
compatible = "samsung,exynos-sysmmu"; cpu_thermal: cpu-thermal {
reg = <0x14640000 0x1000>; polling-delay-passive = <0>;
interrupt-parent = <&combiner>; polling-delay = <0>;
interrupts = <3 2>; thermal-sensors = <&tmu 0>;
power-domains = <&pd_disp1>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
#iommu-cells = <0>;
};
sysmmu_tv: sysmmu@14650000 { cooling-maps {
compatible = "samsung,exynos-sysmmu"; map0 {
reg = <0x14650000 0x1000>; /* Corresponds to 800MHz at freq_table */
interrupt-parent = <&combiner>; cooling-device = <&cpu0 9 9>;
interrupts = <7 4>; };
power-domains = <&pd_disp1>; map1 {
clock-names = "sysmmu", "master"; /* Corresponds to 200MHz at freq_table */
clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; cooling-device = <&cpu0 15 15>;
#iommu-cells = <0>; };
};
};
}; };
}; };
...@@ -1070,6 +1000,39 @@ &fimd { ...@@ -1070,6 +1000,39 @@ &fimd {
iommus = <&sysmmu_fimd1>; iommus = <&sysmmu_fimd1>;
}; };
&i2c_0 {
clocks = <&clock CLK_I2C0>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_bus>;
};
&i2c_1 {
clocks = <&clock CLK_I2C1>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_bus>;
};
&i2c_2 {
clocks = <&clock CLK_I2C2>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c2_bus>;
};
&i2c_3 {
clocks = <&clock CLK_I2C3>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c3_bus>;
};
&pwm {
clocks = <&clock CLK_PWM>;
clock-names = "timers";
};
&rtc { &rtc {
clocks = <&clock CLK_RTC>; clocks = <&clock CLK_RTC>;
clock-names = "rtc"; clock-names = "rtc";
......
arch/arm/boot/dts/exynos5410-odroidxu.dts 0 → 100644
View file @ 95eb940c
/*
* Hardkernel Odroid XU board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Copyright (c) 2016 Krzysztof Kozlowski
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "exynos5410.dtsi"
#include <dt-bindings/clock/maxim,max77802.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "exynos54xx-odroidxu-leds.dtsi"
/ {
model = "Hardkernel Odroid XU";
compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5";
memory {
reg = <0x40000000 0x7ea00000>;
};
chosen {
linux,stdout-path = &serial_2;
};
emmc_pwrseq: pwrseq {
pinctrl-0 = <&emmc_nrst_pin>;
pinctrl-names = "default";
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>;
};
fan0: pwm-fan {
compatible = "pwm-fan";
pwms = <&pwm 0 20972 0>;
cooling-min-state = <0>;
cooling-max-state = <3>;
#cooling-cells = <2>;
cooling-levels = <0 130 170 230>;
};
fin_pll: xxti {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "fin_pll";
#clock-cells = <0>;
};
firmware@02073000 {
compatible = "samsung,secure-firmware";
reg = <0x02073000 0x1000>;
};
};
&cpu0_thermal {
thermal-sensors = <&tmu_cpu0 0>;
polling-delay-passive = <0>;
polling-delay = <0>;
trips {
cpu_alert0: cpu-alert-0 {
temperature = <50000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
cpu_alert1: cpu-alert-1 {
temperature = <60000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
cpu_alert2: cpu-alert-2 {
temperature = <70000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "active";
};
cpu_crit0: cpu-crit-0 {
temperature = <120000>; /* millicelsius */
hysteresis = <0>; /* millicelsius */
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device = <&fan0 0 1>;
};
map1 {
trip = <&cpu_alert1>;
cooling-device = <&fan0 1 2>;
};
map2 {
trip = <&cpu_alert2>;
cooling-device = <&fan0 2 3>;
};
};
};
&hsi2c_4 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <400000>;
status = "okay";
usb3503: usb-hub@08 {
compatible = "smsc,usb3503";
reg = <0x08>;
intn-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
connect-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpx1 4 GPIO_ACTIVE_HIGH>;
initial-mode = <1>;
clock-names = "refclk";
clocks = <&pmu_system_controller 0>;
refclk-frequency = <24000000>;
};
max77802: pmic@09 {
compatible = "maxim,max77802";
reg = <0x9>;
interrupt-parent = <&gpx0>;
interrupts = <4 IRQ_TYPE_NONE>;
pinctrl-names = "default";
pinctrl-0 = <&max77802_irq>, <&pmic_dvs_1>, <&pmic_dvs_2>,
<&pmic_dvs_3>;
#clock-cells = <1>;
inl1-supply = <&buck5_reg>;
inl2-supply = <&buck7_reg>;
inl3-supply = <&buck9_reg>;
inl4-supply = <&buck9_reg>;
inl5-supply = <&buck9_reg>;
inl6-supply = <&buck10_reg>;
inl7-supply = <&buck9_reg>;
/* inl9 supply is BOOST, not configured here */
inl10-supply = <&buck7_reg>;
regulators {
buck1_reg: BUCK1 {
regulator-name = "vdd_mif";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-boot-on;
};
buck2_reg: BUCK2 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
};
buck3_reg: BUCK3 {
regulator-name = "vdd_int";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
};
buck4_reg: BUCK4 {
regulator-name = "vdd_g3d";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
};
buck5_reg: BUCK5 {
regulator-name = "vdd_mem";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
};
buck6_reg: BUCK6 {
regulator-name = "vdd_kfc";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
};
buck7_reg: BUCK7 {
regulator-name = "buck7";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-boot-on;
};
buck8_reg: BUCK8 {
/* vdd_mmc0 */
regulator-name = "vddf_2v85";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
regulator-boot-on;
};
buck9_reg: BUCK9 {
regulator-name = "buck9";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
};
buck10_reg: BUCK10 {
regulator-name = "buck10";
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-always-on;
regulator-boot-on;
};
ldo1_reg: LDO1 {
regulator-name = "vdd_alive";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
ldo2_reg: LDO2 {
regulator-name = "vddq_m1_m2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
ldo3_reg: LDO3 {
regulator-name = "vddq_gpio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo4_reg: LDO4 {
regulator-name = "vddq_mmc2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
/* Having it off prevents reboot */
regulator-always-on;
};
ldo5_reg: LDO5 {
regulator-name = "vdd18_hsic";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo6_reg: LDO6 {
regulator-name = "vdd18_bpll";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo7_reg: LDO7 {
regulator-name = "vddq_lcd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo8_reg: LDO8 {
regulator-name = "vdd10_hdmi";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
ldo9_reg: LDO9 {
regulator-name = "ldo9";
};
ldo10_reg: LDO10 {
regulator-name = "vdd18_mipi";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo11_reg: LDO11 {
regulator-name = "vddq_mmc01";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
/*
* Having it off prevents accessing MMC after
* reboot with error:
* MMC Device 1: Clock OFF has been failed.
*/
regulator-always-on;
};
ldo12_reg: LDO12 {
regulator-name = "vdd33_usb3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo13_reg: LDO13 {
regulator-name = "vddq_abbg0";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo14_reg: LDO14 {
regulator-name = "vddq_abbg1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo15_reg: LDO15 {
regulator-name = "vdd10_usb3";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
ldo16_reg: LDO16 {
regulator-name = "ldo16";
};
ldo17_reg: LDO17 {
regulator-name = "cam_sensor_core";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
ldo18_reg: LDO18 {
regulator-name = "ldo18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo19_reg: LDO19 {
regulator-name = "ldo19";
};
ldo20_reg: LDO20 {
regulator-name = "vdd_mmc0";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo21_reg: LDO21 {
/* vdd_mmc2 */
regulator-name = "vddf_2v8";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
ldo22_reg: LDO22 {
regulator-name = "ldo22";
};
ldo23_reg: LDO23 {
regulator-name = "dp_p3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo24_reg: LDO24 {
regulator-name = "cam_af";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo25_reg: LDO25 {
regulator-name = "eth_p3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo26_reg: LDO26 {
regulator-name = "usb30_extclk";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo27_reg: LDO27 {
regulator-name = "ldo27";
};
ldo28_reg: LDO28 {
regulator-name = "ldo28";
};
ldo29_reg: LDO29 {
regulator-name = "ldo29";
};
ldo30_reg: LDO30 {
regulator-name = "vddq_e1_e2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
ldo31_reg: LDO31 {
regulator-name = "ldo31";
};
/* On revisions with ti,ina231 this is sensor VS */
ldo32_reg: LDO32 {
regulator-name = "vs_power_meter";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo33_reg: LDO33 {
regulator-name = "ldo33";
};
ldo34_reg: LDO34 {
regulator-name = "ldo34";
};
ldo35_reg: LDO35 {
regulator-name = "ldo35";
};
};
};
};
&mmc_0 {
status = "okay";
mmc-pwrseq = <&emmc_pwrseq>;
cd-gpios = <&gpc0 2 GPIO_ACTIVE_LOW>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
samsung,dw-mshc-hs400-timing = <0 2>;
samsung,read-strobe-delay = <90>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd>;
bus-width = <8>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
vmmc-supply = <&ldo20_reg>;
vqmmc-supply = <&ldo11_reg>;
};
&mmc_2 {
status = "okay";
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
bus-width = <4>;
cap-sd-highspeed;
vmmc-supply = <&ldo21_reg>;
vqmmc-supply = <&ldo4_reg>;
};
&pinctrl_0 {
emmc_nrst_pin: emmc-nrst {
samsung,pins = "gpd1-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pmic_dvs_3: pmic-dvs-3 {
samsung,pins = "gpx0-0";
samsung,pin-function = <1>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pmic_dvs_2: pmic-dvs-2 {
samsung,pins = "gpx0-1";
samsung,pin-function = <1>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pmic_dvs_1: pmic-dvs-1 {
samsung,pins = "gpx0-2";
samsung,pin-function = <1>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
samsung,pin-val = <1>;
};
max77802_irq: max77802-irq {
samsung,pins = "gpx0-4";
samsung,pin-function = <0xf>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
};
&pwm {
/*
* PWM 0 -- fan
* PWM 1 -- Green LED
* PWM 2 -- Blue LED
* PWM 3 -- on MIPI connector for backlight
*/
pinctrl-0 = <&pwm0_out &pwm1_out &pwm2_out &pwm3_out>;
pinctrl-names = "default";
status = "okay";
};
&rtc {
status = "okay";
clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>;
clock-names = "rtc", "rtc_src";
};
&serial_0 {
status = "okay";
};
&serial_1 {
status = "okay";
};
&serial_2 {
status = "okay";
};
&serial_3 {
status = "okay";
};
&tmu_cpu0 {
vtmu-supply = <&ldo10_reg>;
};
&tmu_cpu1 {
vtmu-supply = <&ldo10_reg>;
};
&tmu_cpu2 {
vtmu-supply = <&ldo10_reg>;
};
&tmu_cpu3 {
vtmu-supply = <&ldo10_reg>;
};
&usbdrd_dwc3_0 {
dr_mode = "host";
};
&usbdrd_dwc3_1 {
dr_mode = "peripheral";
};
&usbdrd3_0 {
vdd33-supply = <&ldo12_reg>;
vdd10-supply = <&ldo15_reg>;
};
&usbdrd3_1 {
vdd33-supply = <&ldo12_reg>;
vdd10-supply = <&ldo15_reg>;
};
arch/arm/boot/dts/exynos5410-pinctrl.dtsi
View file @ 95eb940c
...@@ -277,6 +277,216 @@ gpx3: gpx3 { ...@@ -277,6 +277,216 @@ gpx3: gpx3 {
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
}; };
uart0_data: uart0-data {
samsung,pins = "gpa0-0", "gpa0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart0_fctl: uart0-fctl {
samsung,pins = "gpa0-2", "gpa0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart1_data: uart1-data {
samsung,pins = "gpa0-4", "gpa0-5";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart1_fctl: uart1-fctl {
samsung,pins = "gpa0-6", "gpa0-7";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
i2c2_bus: i2c2-bus {
samsung,pins = "gpa0-6", "gpa0-7";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
uart2_data: uart2-data {
samsung,pins = "gpa1-0", "gpa1-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart2_fctl: uart2-fctl {
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
i2c3_bus: i2c3-bus {
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
uart3_data: uart3-data {
samsung,pins = "gpa1-4", "gpa1-5";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
i2c4_hs_bus: i2c4-hs-bus {
samsung,pins = "gpa2-0", "gpa2-1";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
i2c5_hs_bus: i2c5-hs-bus {
samsung,pins = "gpa2-2", "gpa2-3";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
i2c6_hs_bus: i2c6-hs-bus {
samsung,pins = "gpb1-3", "gpb1-4";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
pwm0_out: pwm0-out {
samsung,pins = "gpb2-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pwm1_out: pwm1-out {
samsung,pins = "gpb2-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pwm2_out: pwm2-out {
samsung,pins = "gpb2-2";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pwm3_out: pwm3-out {
samsung,pins = "gpb2-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
i2c7_hs_bus: i2c7-hs-bus {
samsung,pins = "gpb2-2", "gpb2-3";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
i2c0_bus: i2c0-bus {
samsung,pins = "gpb3-0", "gpb3-1";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
i2c1_bus: i2c1-bus {
samsung,pins = "gpb3-2", "gpb3-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
sd0_clk: sd0-clk {
samsung,pins = "gpc0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd0_cmd: sd0-cmd {
samsung,pins = "gpc0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd0_cd: sd0-cd {
samsung,pins = "gpc0-2";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd0_bus1: sd0-bus-width1 {
samsung,pins = "gpc0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd0_bus4: sd0-bus-width4 {
samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd2_clk: sd2-clk {
samsung,pins = "gpc2-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd2_cmd: sd2-cmd {
samsung,pins = "gpc2-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd2_cd: sd2-cd {
samsung,pins = "gpc2-2";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd2_bus1: sd2-bus-width1 {
samsung,pins = "gpc2-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd2_bus4: sd2-bus-width4 {
samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd0_bus8: sd0-bus-width8 {
samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
}; };
&pinctrl_1 { &pinctrl_1 {
......
arch/arm/boot/dts/exynos5410-smdk5410.dts
View file @ 95eb940c
...@@ -102,14 +102,14 @@ ethernet@3,0 { ...@@ -102,14 +102,14 @@ ethernet@3,0 {
}; };
}; };
&uart0 { &serial_0 {
status = "okay"; status = "okay";
}; };
&uart1 { &serial_1 {
status = "okay"; status = "okay";
}; };
&uart2 { &serial_2 {
status = "okay"; status = "okay";
}; };
arch/arm/boot/dts/exynos5410.dtsi
View file @ 95eb940c
...@@ -13,9 +13,10 @@ ...@@ -13,9 +13,10 @@
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#include "skeleton.dtsi" #include "exynos54xx.dtsi"
#include "exynos-syscon-restart.dtsi" #include "exynos-syscon-restart.dtsi"
#include <dt-bindings/clock/exynos5410.h> #include <dt-bindings/clock/exynos5410.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ { / {
compatible = "samsung,exynos5410", "samsung,exynos5"; compatible = "samsung,exynos5410", "samsung,exynos5";
...@@ -26,37 +27,34 @@ aliases { ...@@ -26,37 +27,34 @@ aliases {
pinctrl1 = &pinctrl_1; pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2; pinctrl2 = &pinctrl_2;
pinctrl3 = &pinctrl_3; pinctrl3 = &pinctrl_3;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
}; };
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
CPU0: cpu@0 { cpu0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a15"; compatible = "arm,cortex-a15";
reg = <0x0>; reg = <0x0>;
clock-frequency = <1600000000>; clock-frequency = <1600000000>;
}; };
CPU1: cpu@1 { cpu1: cpu@1 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a15"; compatible = "arm,cortex-a15";
reg = <0x1>; reg = <0x1>;
clock-frequency = <1600000000>; clock-frequency = <1600000000>;
}; };
CPU2: cpu@2 { cpu2: cpu@2 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a15"; compatible = "arm,cortex-a15";
reg = <0x2>; reg = <0x2>;
clock-frequency = <1600000000>; clock-frequency = <1600000000>;
}; };
CPU3: cpu@3 { cpu3: cpu@3 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a15"; compatible = "arm,cortex-a15";
reg = <0x3>; reg = <0x3>;
...@@ -70,105 +68,54 @@ soc: soc { ...@@ -70,105 +68,54 @@ soc: soc {
#size-cells = <1>; #size-cells = <1>;
ranges; ranges;
combiner: interrupt-controller@10440000 {
compatible = "samsung,exynos4210-combiner";
#interrupt-cells = <2>;
interrupt-controller;
samsung,combiner-nr = <32>;
reg = <0x10440000 0x1000>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
};
gic: interrupt-controller@10481000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x10481000 0x1000>,
<0x10482000 0x1000>,
<0x10484000 0x2000>,
<0x10486000 0x2000>;
interrupts = <1 9 0xf04>;
};
chipid@10000000 {
compatible = "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
};
sromc: memory-controller@12250000 {
compatible = "samsung,exynos4210-srom";
reg = <0x12250000 0x14>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x04000000 0x20000
1 0 0x05000000 0x20000
2 0 0x06000000 0x20000
3 0 0x07000000 0x20000>;
};
pmu_system_controller: system-controller@10040000 { pmu_system_controller: system-controller@10040000 {
compatible = "samsung,exynos5410-pmu", "syscon"; compatible = "samsung,exynos5410-pmu", "syscon";
reg = <0x10040000 0x5000>; reg = <0x10040000 0x5000>;
clock-names = "clkout16";
clocks = <&fin_pll>;
#clock-cells = <1>;
}; };
mct: mct@101C0000 { clock: clock-controller@10010000 {
compatible = "samsung,exynos4210-mct"; compatible = "samsung,exynos5410-clock";
reg = <0x101C0000 0xB00>; reg = <0x10010000 0x30000>;
interrupt-parent = <&interrupt_map>; #clock-cells = <1>;
interrupts = <0>, <1>, <2>, <3>,
<4>, <5>, <6>, <7>,
<8>, <9>, <10>, <11>;
clocks = <&fin_pll>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
interrupt_map: interrupt-map {
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = <0 &combiner 23 3>,
<1 &combiner 23 4>,
<2 &combiner 25 2>,
<3 &combiner 25 3>,
<4 &gic 0 120 0>,
<5 &gic 0 121 0>,
<6 &gic 0 122 0>,
<7 &gic 0 123 0>,
<8 &gic 0 128 0>,
<9 &gic 0 129 0>,
<10 &gic 0 130 0>,
<11 &gic 0 131 0>;
};
}; };
sysram@02020000 { tmu_cpu0: tmu@10060000 {
compatible = "mmio-sram"; compatible = "samsung,exynos5420-tmu";
reg = <0x02020000 0x54000>; reg = <0x10060000 0x100>;
#address-cells = <1>; interrupts = <GIC_SPI 65 0>;
#size-cells = <1>; clocks = <&clock CLK_TMU>;
ranges = <0 0x02020000 0x54000>; clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
};
smp-sysram@0 { tmu_cpu1: tmu@10064000 {
compatible = "samsung,exynos4210-sysram"; compatible = "samsung,exynos5420-tmu";
reg = <0x0 0x1000>; reg = <0x10064000 0x100>;
}; interrupts = <GIC_SPI 183 0>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
};
smp-sysram@53000 { tmu_cpu2: tmu@10068000 {
compatible = "samsung,exynos4210-sysram-ns"; compatible = "samsung,exynos5420-tmu";
reg = <0x53000 0x1000>; reg = <0x10068000 0x100>;
}; interrupts = <GIC_SPI 184 0>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
}; };
clock: clock-controller@10010000 { tmu_cpu3: tmu@1006c000 {
compatible = "samsung,exynos5410-clock"; compatible = "samsung,exynos5420-tmu";
reg = <0x10010000 0x30000>; reg = <0x1006c000 0x100>;
#clock-cells = <1>; interrupts = <GIC_SPI 185 0>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
}; };
mmc_0: mmc@12200000 { mmc_0: mmc@12200000 {
...@@ -236,34 +183,182 @@ pinctrl_3: pinctrl@03860000 { ...@@ -236,34 +183,182 @@ pinctrl_3: pinctrl@03860000 {
reg = <0x03860000 0x1000>; reg = <0x03860000 0x1000>;
interrupts = <0 47 0>; interrupts = <0 47 0>;
}; };
};
uart0: serial@12C00000 { thermal-zones {
compatible = "samsung,exynos4210-uart"; cpu0_thermal: cpu0-thermal {
reg = <0x12C00000 0x100>; thermal-sensors = <&tmu_cpu0>;
interrupts = <0 51 0>; #include "exynos5420-trip-points.dtsi"
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
}; };
cpu1_thermal: cpu1-thermal {
uart1: serial@12C10000 { thermal-sensors = <&tmu_cpu1>;
compatible = "samsung,exynos4210-uart"; #include "exynos5420-trip-points.dtsi"
reg = <0x12C10000 0x100>;
interrupts = <0 52 0>;
clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
}; };
cpu2_thermal: cpu2-thermal {
uart2: serial@12C20000 { thermal-sensors = <&tmu_cpu2>;
compatible = "samsung,exynos4210-uart"; #include "exynos5420-trip-points.dtsi"
reg = <0x12C20000 0x100>; };
interrupts = <0 53 0>; cpu3_thermal: cpu3-thermal {
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; thermal-sensors = <&tmu_cpu3>;
clock-names = "uart", "clk_uart_baud0"; #include "exynos5420-trip-points.dtsi"
status = "disabled";
}; };
}; };
}; };
&i2c_0 {
clocks = <&clock CLK_I2C0>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_bus>;
};
&i2c_1 {
clocks = <&clock CLK_I2C1>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_bus>;
};
&i2c_2 {
clocks = <&clock CLK_I2C2>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c2_bus>;
};
&i2c_3 {
clocks = <&clock CLK_I2C3>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c3_bus>;
};
&hsi2c_4 {
clocks = <&clock CLK_USI0>;
clock-names = "hsi2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c4_hs_bus>;
};
&hsi2c_5 {
clocks = <&clock CLK_USI1>;
clock-names = "hsi2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c5_hs_bus>;
};
&hsi2c_6 {
clocks = <&clock CLK_USI2>;
clock-names = "hsi2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c6_hs_bus>;
};
&hsi2c_7 {
clocks = <&clock CLK_USI3>;
clock-names = "hsi2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c7_hs_bus>;
};
&mct {
clocks = <&fin_pll>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
};
&pwm {
clocks = <&clock CLK_PWM>;
clock-names = "timers";
};
&rtc {
clocks = <&clock CLK_RTC>;
clock-names = "rtc";
interrupt-parent = <&pmu_system_controller>;
status = "disabled";
};
&serial_0 {
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
};
&serial_1 {
clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
};
&serial_2 {
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
};
&serial_3 {
clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
clock-names = "uart", "clk_uart_baud0";
};
&sss {
clocks = <&clock CLK_SSS>;
clock-names = "secss";
};
&sromc {
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x04000000 0x20000
1 0 0x05000000 0x20000
2 0 0x06000000 0x20000
3 0 0x07000000 0x20000>;
};
&usbdrd3_0 {
clocks = <&clock CLK_USBD300>;
clock-names = "usbdrd30";
};
&usbdrd_phy0 {
clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
clock-names = "phy", "ref";
samsung,pmu-syscon = <&pmu_system_controller>;
};
&usbdrd3_1 {
clocks = <&clock CLK_USBD301>;
clock-names = "usbdrd30";
};
&usbdrd_dwc3_1 {
interrupts = <GIC_SPI 200 0>;
};
&usbdrd_phy1 {
clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
clock-names = "phy", "ref";
samsung,pmu-syscon = <&pmu_system_controller>;
};
&usbhost1 {
clocks = <&clock CLK_USBH20>;
clock-names = "usbhost";
};
&usbhost2 {
clocks = <&clock CLK_USBH20>;
clock-names = "usbhost";
};
&usb2_phy {
clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
clock-names = "phy", "ref";
samsung,sysreg-phandle = <&sysreg_system_controller>;
samsung,pmureg-phandle = <&pmu_system_controller>;
};
&watchdog {
clocks = <&clock CLK_WDT>;
clock-names = "watchdog";
samsung,syscon-phandle = <&pmu_system_controller>;
};
#include "exynos5410-pinctrl.dtsi" #include "exynos5410-pinctrl.dtsi"
arch/arm/boot/dts/exynos5420-pinctrl.dtsi
View file @ 95eb940c
...@@ -193,17 +193,17 @@ sd0_bus8: sd0-bus-width8 { ...@@ -193,17 +193,17 @@ sd0_bus8: sd0-bus-width8 {
samsung,pin-drv = <3>; samsung,pin-drv = <3>;
}; };
sd1_clk: sd1-clk { sd0_rclk: sd0-rclk {
samsung,pins = "gpc1-0"; samsung,pins = "gpc0-7";
samsung,pin-function = <2>; samsung,pin-function = <2>;
samsung,pin-pud = <0>; samsung,pin-pud = <1>;
samsung,pin-drv = <3>; samsung,pin-drv = <3>;
}; };
sd0_rclk: sd0-rclk { sd1_clk: sd1-clk {
samsung,pins = "gpc0-7"; samsung,pins = "gpc1-0";
samsung,pin-function = <2>; samsung,pin-function = <2>;
samsung,pin-pud = <1>; samsung,pin-pud = <0>;
samsung,pin-drv = <3>; samsung,pin-drv = <3>;
}; };
......
arch/arm/boot/dts/exynos5420.dtsi
View file @ 95eb940c
...@@ -13,10 +13,10 @@ ...@@ -13,10 +13,10 @@
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#include "exynos54xx.dtsi"
#include <dt-bindings/clock/exynos5420.h> #include <dt-bindings/clock/exynos5420.h>
#include "exynos5.dtsi"
#include <dt-bindings/clock/exynos-audss-clk.h> #include <dt-bindings/clock/exynos-audss-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ { / {
compatible = "samsung,exynos5420", "samsung,exynos5"; compatible = "samsung,exynos5420", "samsung,exynos5";
...@@ -30,14 +30,6 @@ aliases { ...@@ -30,14 +30,6 @@ aliases {
pinctrl2 = &pinctrl_2; pinctrl2 = &pinctrl_2;
pinctrl3 = &pinctrl_3; pinctrl3 = &pinctrl_3;
pinctrl4 = &pinctrl_4; pinctrl4 = &pinctrl_4;
i2c0 = &i2c_0;
i2c1 = &i2c_1;
i2c2 = &i2c_2;
i2c3 = &i2c_3;
i2c4 = &hsi2c_4;
i2c5 = &hsi2c_5;
i2c6 = &hsi2c_6;
i2c7 = &hsi2c_7;
i2c8 = &hsi2c_8; i2c8 = &hsi2c_8;
i2c9 = &hsi2c_9; i2c9 = &hsi2c_9;
i2c10 = &hsi2c_10; i2c10 = &hsi2c_10;
...@@ -46,118 +38,6 @@ aliases { ...@@ -46,118 +38,6 @@ aliases {
spi0 = &spi_0; spi0 = &spi_0;
spi1 = &spi_1; spi1 = &spi_1;
spi2 = &spi_2; spi2 = &spi_2;
usbdrdphy0 = &usbdrd_phy0;
usbdrdphy1 = &usbdrd_phy1;
};
cluster_a15_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp@1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1250000>;
clock-latency-ns = <140000>;
};
opp@1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <1212500>;
clock-latency-ns = <140000>;
};
opp@1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <1175000>;
clock-latency-ns = <140000>;
};
opp@1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <1137500>;
clock-latency-ns = <140000>;
};
opp@1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-microvolt = <1112500>;
clock-latency-ns = <140000>;
};
opp@1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <1062500>;
clock-latency-ns = <140000>;
};
opp@1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1037500>;
clock-latency-ns = <140000>;
};
opp@1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <1012500>;
clock-latency-ns = <140000>;
};
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = < 987500>;
clock-latency-ns = <140000>;
};
opp@900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = < 962500>;
clock-latency-ns = <140000>;
};
opp@800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = < 937500>;
clock-latency-ns = <140000>;
};
opp@700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = < 912500>;
clock-latency-ns = <140000>;
};
};
cluster_a7_opp_table: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
opp@1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <1275000>;
clock-latency-ns = <140000>;
};
opp@1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1212500>;
clock-latency-ns = <140000>;
};
opp@1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <1162500>;
clock-latency-ns = <140000>;
};
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1112500>;
clock-latency-ns = <140000>;
};
opp@900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <1062500>;
clock-latency-ns = <140000>;
};
opp@800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1025000>;
clock-latency-ns = <140000>;
};
opp@700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <975000>;
clock-latency-ns = <140000>;
};
opp@600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <937500>;
clock-latency-ns = <140000>;
};
}; };
/* /*
...@@ -165,1435 +45,1270 @@ opp@600000000 { ...@@ -165,1435 +45,1270 @@ opp@600000000 {
* by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi. * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
*/ */
cci: cci@10d20000 { soc: soc {
compatible = "arm,cci-400"; cluster_a15_opp_table: opp_table0 {
#address-cells = <1>; compatible = "operating-points-v2";
#size-cells = <1>; opp-shared;
reg = <0x10d20000 0x1000>; opp@1800000000 {
ranges = <0x0 0x10d20000 0x6000>; opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1250000>;
cci_control0: slave-if@4000 { clock-latency-ns = <140000>;
compatible = "arm,cci-400-ctrl-if"; };
interface-type = "ace"; opp@1700000000 {
reg = <0x4000 0x1000>; opp-hz = /bits/ 64 <1700000000>;
}; opp-microvolt = <1212500>;
cci_control1: slave-if@5000 { clock-latency-ns = <140000>;
compatible = "arm,cci-400-ctrl-if"; };
interface-type = "ace"; opp@1600000000 {
reg = <0x5000 0x1000>; opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <1175000>;
clock-latency-ns = <140000>;
};
opp@1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <1137500>;
clock-latency-ns = <140000>;
};
opp@1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-microvolt = <1112500>;
clock-latency-ns = <140000>;
};
opp@1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <1062500>;
clock-latency-ns = <140000>;
};
opp@1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1037500>;
clock-latency-ns = <140000>;
};
opp@1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <1012500>;
clock-latency-ns = <140000>;
};
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = < 987500>;
clock-latency-ns = <140000>;
};
opp@900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = < 962500>;
clock-latency-ns = <140000>;
};
opp@800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = < 937500>;
clock-latency-ns = <140000>;
};
opp@700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = < 912500>;
clock-latency-ns = <140000>;
};
};
cluster_a7_opp_table: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
opp@1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <1275000>;
clock-latency-ns = <140000>;
};
opp@1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1212500>;
clock-latency-ns = <140000>;
};
opp@1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <1162500>;
clock-latency-ns = <140000>;
};
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1112500>;
clock-latency-ns = <140000>;
};
opp@900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <1062500>;
clock-latency-ns = <140000>;
};
opp@800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1025000>;
clock-latency-ns = <140000>;
};
opp@700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <975000>;
clock-latency-ns = <140000>;
};
opp@600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <937500>;
clock-latency-ns = <140000>;
};
};
cci: cci@10d20000 {
compatible = "arm,cci-400";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x10d20000 0x1000>;
ranges = <0x0 0x10d20000 0x6000>;
cci_control0: slave-if@4000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x4000 0x1000>;
};
cci_control1: slave-if@5000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x5000 0x1000>;
};
};
clock: clock-controller@10010000 {
compatible = "samsung,exynos5420-clock";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
};
clock_audss: audss-clock-controller@3810000 {
compatible = "samsung,exynos5420-audss-clock";
reg = <0x03810000 0x0C>;
#clock-cells = <1>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
<&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
};
mfc: codec@11000000 {
compatible = "samsung,mfc-v7";
reg = <0x11000000 0x10000>;
interrupts = <0 96 0>;
clocks = <&clock CLK_MFC>;
clock-names = "mfc";
power-domains = <&mfc_pd>;
iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
iommu-names = "left", "right";
};
mmc_0: mmc@12200000 {
compatible = "samsung,exynos5420-dw-mshc-smu";
interrupts = <0 75 0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12200000 0x2000>;
clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
clock-names = "biu", "ciu";
fifo-depth = <0x40>;
status = "disabled";
}; };
};
sysram@02020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x54000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x02020000 0x54000>;
smp-sysram@0 { mmc_1: mmc@12210000 {
compatible = "samsung,exynos4210-sysram"; compatible = "samsung,exynos5420-dw-mshc-smu";
reg = <0x0 0x1000>; interrupts = <0 76 0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12210000 0x2000>;
clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
clock-names = "biu", "ciu";
fifo-depth = <0x40>;
status = "disabled";
}; };
smp-sysram@53000 { mmc_2: mmc@12220000 {
compatible = "samsung,exynos4210-sysram-ns"; compatible = "samsung,exynos5420-dw-mshc";
reg = <0x53000 0x1000>; interrupts = <0 77 0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12220000 0x1000>;
clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
clock-names = "biu", "ciu";
fifo-depth = <0x40>;
status = "disabled";
}; };
};
clock: clock-controller@10010000 {
compatible = "samsung,exynos5420-clock";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
};
clock_audss: audss-clock-controller@3810000 { nocp_mem0_0: nocp@10CA1000 {
compatible = "samsung,exynos5420-audss-clock"; compatible = "samsung,exynos5420-nocp";
reg = <0x03810000 0x0C>; reg = <0x10CA1000 0x200>;
#clock-cells = <1>; status = "disabled";
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, };
<&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
};
mfc: codec@11000000 {
compatible = "samsung,mfc-v7";
reg = <0x11000000 0x10000>;
interrupts = <0 96 0>;
clocks = <&clock CLK_MFC>;
clock-names = "mfc";
power-domains = <&mfc_pd>;
iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
iommu-names = "left", "right";
};
mmc_0: mmc@12200000 { nocp_mem0_1: nocp@10CA1400 {
compatible = "samsung,exynos5420-dw-mshc-smu"; compatible = "samsung,exynos5420-nocp";
interrupts = <0 75 0>; reg = <0x10CA1400 0x200>;
#address-cells = <1>; status = "disabled";
#size-cells = <0>; };
reg = <0x12200000 0x2000>;
clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
clock-names = "biu", "ciu";
fifo-depth = <0x40>;
status = "disabled";
};
mmc_1: mmc@12210000 { nocp_mem1_0: nocp@10CA1800 {
compatible = "samsung,exynos5420-dw-mshc-smu"; compatible = "samsung,exynos5420-nocp";
interrupts = <0 76 0>; reg = <0x10CA1800 0x200>;
#address-cells = <1>; status = "disabled";
#size-cells = <0>; };
reg = <0x12210000 0x2000>;
clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
clock-names = "biu", "ciu";
fifo-depth = <0x40>;
status = "disabled";
};
mmc_2: mmc@12220000 { nocp_mem1_1: nocp@10CA1C00 {
compatible = "samsung,exynos5420-dw-mshc"; compatible = "samsung,exynos5420-nocp";
interrupts = <0 77 0>; reg = <0x10CA1C00 0x200>;
#address-cells = <1>; status = "disabled";
#size-cells = <0>; };
reg = <0x12220000 0x1000>;
clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
clock-names = "biu", "ciu";
fifo-depth = <0x40>;
status = "disabled";
};
mct: mct@101C0000 { nocp_g3d_0: nocp@11A51000 {
compatible = "samsung,exynos4210-mct"; compatible = "samsung,exynos5420-nocp";
reg = <0x101C0000 0x800>; reg = <0x11A51000 0x200>;
interrupt-controller; status = "disabled";
#interrupt-cells = <1>;
interrupt-parent = <&mct_map>;
interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
<8>, <9>, <10>, <11>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
mct_map: mct-map {
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = <0 &combiner 23 3>,
<1 &combiner 23 4>,
<2 &combiner 25 2>,
<3 &combiner 25 3>,
<4 &gic 0 120 0>,
<5 &gic 0 121 0>,
<6 &gic 0 122 0>,
<7 &gic 0 123 0>,
<8 &gic 0 128 0>,
<9 &gic 0 129 0>,
<10 &gic 0 130 0>,
<11 &gic 0 131 0>;
}; };
};
nocp_mem0_0: nocp@10CA1000 { nocp_g3d_1: nocp@11A51400 {
compatible = "samsung,exynos5420-nocp"; compatible = "samsung,exynos5420-nocp";
reg = <0x10CA1000 0x200>; reg = <0x11A51400 0x200>;
status = "disabled"; status = "disabled";
}; };
nocp_mem0_1: nocp@10CA1400 { gsc_pd: power-domain@10044000 {
compatible = "samsung,exynos5420-nocp"; compatible = "samsung,exynos4210-pd";
reg = <0x10CA1400 0x200>; reg = <0x10044000 0x20>;
status = "disabled"; #power-domain-cells = <0>;
}; clocks = <&clock CLK_FIN_PLL>,
<&clock CLK_MOUT_USER_ACLK300_GSCL>,
<&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
clock-names = "oscclk", "clk0", "asb0", "asb1";
};
nocp_mem1_0: nocp@10CA1800 { isp_pd: power-domain@10044020 {
compatible = "samsung,exynos5420-nocp"; compatible = "samsung,exynos4210-pd";
reg = <0x10CA1800 0x200>; reg = <0x10044020 0x20>;
status = "disabled"; #power-domain-cells = <0>;
}; };
nocp_mem1_1: nocp@10CA1C00 { mfc_pd: power-domain@10044060 {
compatible = "samsung,exynos5420-nocp"; compatible = "samsung,exynos4210-pd";
reg = <0x10CA1C00 0x200>; reg = <0x10044060 0x20>;
status = "disabled"; clocks = <&clock CLK_FIN_PLL>,
}; <&clock CLK_MOUT_USER_ACLK333>,
<&clock CLK_ACLK333>;
clock-names = "oscclk", "clk0","asb0";
#power-domain-cells = <0>;
};
nocp_g3d_0: nocp@11A51000 { msc_pd: power-domain@10044120 {
compatible = "samsung,exynos5420-nocp"; compatible = "samsung,exynos4210-pd";
reg = <0x11A51000 0x200>; reg = <0x10044120 0x20>;
status = "disabled"; #power-domain-cells = <0>;
}; };
nocp_g3d_1: nocp@11A51400 { disp_pd: power-domain@100440C0 {
compatible = "samsung,exynos5420-nocp"; compatible = "samsung,exynos4210-pd";
reg = <0x11A51400 0x200>; reg = <0x100440C0 0x20>;
status = "disabled"; #power-domain-cells = <0>;
}; clocks = <&clock CLK_FIN_PLL>,
<&clock CLK_MOUT_USER_ACLK200_DISP1>,
<&clock CLK_MOUT_USER_ACLK300_DISP1>,
<&clock CLK_MOUT_USER_ACLK400_DISP1>,
<&clock CLK_FIMD1>, <&clock CLK_MIXER>;
clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
};
gsc_pd: power-domain@10044000 { pinctrl_0: pinctrl@13400000 {
compatible = "samsung,exynos4210-pd"; compatible = "samsung,exynos5420-pinctrl";
reg = <0x10044000 0x20>; reg = <0x13400000 0x1000>;
#power-domain-cells = <0>; interrupts = <0 45 0>;
clocks = <&clock CLK_FIN_PLL>,
<&clock CLK_MOUT_USER_ACLK300_GSCL>,
<&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
clock-names = "oscclk", "clk0", "asb0", "asb1";
};
isp_pd: power-domain@10044020 { wakeup-interrupt-controller {
compatible = "samsung,exynos4210-pd"; compatible = "samsung,exynos4210-wakeup-eint";
reg = <0x10044020 0x20>; interrupt-parent = <&gic>;
#power-domain-cells = <0>; interrupts = <0 32 0>;
}; };
};
mfc_pd: power-domain@10044060 { pinctrl_1: pinctrl@13410000 {
compatible = "samsung,exynos4210-pd"; compatible = "samsung,exynos5420-pinctrl";
reg = <0x10044060 0x20>; reg = <0x13410000 0x1000>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>, interrupts = <0 78 0>;
<&clock CLK_ACLK333>; };
clock-names = "oscclk", "clk0","asb0";
#power-domain-cells = <0>;
};
msc_pd: power-domain@10044120 { pinctrl_2: pinctrl@14000000 {
compatible = "samsung,exynos4210-pd"; compatible = "samsung,exynos5420-pinctrl";
reg = <0x10044120 0x20>; reg = <0x14000000 0x1000>;
#power-domain-cells = <0>; interrupts = <0 46 0>;
}; };
disp_pd: power-domain@100440C0 { pinctrl_3: pinctrl@14010000 {
compatible = "samsung,exynos4210-pd"; compatible = "samsung,exynos5420-pinctrl";
reg = <0x100440C0 0x20>; reg = <0x14010000 0x1000>;
#power-domain-cells = <0>; interrupts = <0 50 0>;
clocks = <&clock CLK_FIN_PLL>, };
<&clock CLK_MOUT_USER_ACLK200_DISP1>,
<&clock CLK_MOUT_USER_ACLK300_DISP1>,
<&clock CLK_MOUT_USER_ACLK400_DISP1>,
<&clock CLK_FIMD1>, <&clock CLK_MIXER>;
clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
};
pinctrl_0: pinctrl@13400000 { pinctrl_4: pinctrl@03860000 {
compatible = "samsung,exynos5420-pinctrl"; compatible = "samsung,exynos5420-pinctrl";
reg = <0x13400000 0x1000>; reg = <0x03860000 0x1000>;
interrupts = <0 45 0>; interrupts = <0 47 0>;
};
wakeup-interrupt-controller { amba {
compatible = "samsung,exynos4210-wakeup-eint"; #address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
interrupts = <0 32 0>; ranges;
adma: adma@03880000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x03880000 0x1000>;
interrupts = <0 110 0>;
clocks = <&clock_audss EXYNOS_ADMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <6>;
#dma-requests = <16>;
};
pdma0: pdma@121A0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121A0000 0x1000>;
interrupts = <0 34 0>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: pdma@121B0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121B0000 0x1000>;
interrupts = <0 35 0>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
mdma0: mdma@10800000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>;
interrupts = <0 33 0>;
clocks = <&clock CLK_MDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
};
mdma1: mdma@11C10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
interrupts = <0 124 0>;
clocks = <&clock CLK_MDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
/*
* MDMA1 can support both secure and non-secure
* AXI transactions. When this is enabled in
* the kernel for boards that run in secure
* mode, we are getting imprecise external
* aborts causing the kernel to oops.
*/
status = "disabled";
};
};
i2s0: i2s@03830000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x03830000 0x100>;
dmas = <&adma 0
&adma 2
&adma 1>;
dma-names = "tx", "rx", "tx-sec";
clocks = <&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_SCLK_I2S>;
clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
#clock-cells = <1>;
clock-output-names = "i2s_cdclk0";
#sound-dai-cells = <1>;
samsung,idma-addr = <0x03000000>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
status = "disabled";
}; };
};
pinctrl_1: pinctrl@13410000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x13410000 0x1000>;
interrupts = <0 78 0>;
};
pinctrl_2: pinctrl@14000000 { i2s1: i2s@12D60000 {
compatible = "samsung,exynos5420-pinctrl"; compatible = "samsung,exynos5420-i2s";
reg = <0x14000000 0x1000>; reg = <0x12D60000 0x100>;
interrupts = <0 46 0>; dmas = <&pdma1 12
}; &pdma1 11>;
dma-names = "tx", "rx";
pinctrl_3: pinctrl@14010000 { clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
compatible = "samsung,exynos5420-pinctrl"; clock-names = "iis", "i2s_opclk0";
reg = <0x14010000 0x1000>; #clock-cells = <1>;
interrupts = <0 50 0>; clock-output-names = "i2s_cdclk1";
}; #sound-dai-cells = <1>;
pinctrl-names = "default";
pinctrl_4: pinctrl@03860000 { pinctrl-0 = <&i2s1_bus>;
compatible = "samsung,exynos5420-pinctrl";
reg = <0x03860000 0x1000>;
interrupts = <0 47 0>;
};
amba {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
adma: adma@03880000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x03880000 0x1000>;
interrupts = <0 110 0>;
clocks = <&clock_audss EXYNOS_ADMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <6>;
#dma-requests = <16>;
};
pdma0: pdma@121A0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121A0000 0x1000>;
interrupts = <0 34 0>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: pdma@121B0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121B0000 0x1000>;
interrupts = <0 35 0>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
mdma0: mdma@10800000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>;
interrupts = <0 33 0>;
clocks = <&clock CLK_MDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
};
mdma1: mdma@11C10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
interrupts = <0 124 0>;
clocks = <&clock CLK_MDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
/*
* MDMA1 can support both secure and non-secure
* AXI transactions. When this is enabled in the kernel
* for boards that run in secure mode, we are getting
* imprecise external aborts causing the kernel to oops.
*/
status = "disabled"; status = "disabled";
}; };
};
i2s0: i2s@03830000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x03830000 0x100>;
dmas = <&adma 0
&adma 2
&adma 1>;
dma-names = "tx", "rx", "tx-sec";
clocks = <&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_SCLK_I2S>;
clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
#clock-cells = <1>;
clock-output-names = "i2s_cdclk0";
#sound-dai-cells = <1>;
samsung,idma-addr = <0x03000000>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
status = "disabled";
};
i2s1: i2s@12D60000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x12D60000 0x100>;
dmas = <&pdma1 12
&pdma1 11>;
dma-names = "tx", "rx";
clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
clock-names = "iis", "i2s_opclk0";
#clock-cells = <1>;
clock-output-names = "i2s_cdclk1";
#sound-dai-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1_bus>;
status = "disabled";
};
i2s2: i2s@12D70000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x12D70000 0x100>;
dmas = <&pdma0 12
&pdma0 11>;
dma-names = "tx", "rx";
clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
clock-names = "iis", "i2s_opclk0";
#clock-cells = <1>;
clock-output-names = "i2s_cdclk2";
#sound-dai-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&i2s2_bus>;
status = "disabled";
};
spi_0: spi@12d20000 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d20000 0x100>;
interrupts = <0 68 0>;
dmas = <&pdma0 5
&pdma0 4>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi0_bus>;
clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
clock-names = "spi", "spi_busclk0";
status = "disabled";
};
spi_1: spi@12d30000 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d30000 0x100>;
interrupts = <0 69 0>;
dmas = <&pdma1 5
&pdma1 4>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_bus>;
clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
clock-names = "spi", "spi_busclk0";
status = "disabled";
};
spi_2: spi@12d40000 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d40000 0x100>;
interrupts = <0 70 0>;
dmas = <&pdma0 7
&pdma0 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi2_bus>;
clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
clock-names = "spi", "spi_busclk0";
status = "disabled";
};
pwm: pwm@12dd0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x12dd0000 0x100>;
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
#pwm-cells = <3>;
clocks = <&clock CLK_PWM>;
clock-names = "timers";
};
dp_phy: dp-video-phy {
compatible = "samsung,exynos5420-dp-video-phy";
samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <0>;
};
mipi_phy: mipi-video-phy {
compatible = "samsung,s5pv210-mipi-video-phy";
syscon = <&pmu_system_controller>;
#phy-cells = <1>;
};
dsi@14500000 {
compatible = "samsung,exynos5410-mipi-dsi";
reg = <0x14500000 0x10000>;
interrupts = <0 82 0>;
phys = <&mipi_phy 1>;
phy-names = "dsim";
clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
clock-names = "bus_clk", "pll_clk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
adc: adc@12D10000 {
compatible = "samsung,exynos-adc-v2";
reg = <0x12D10000 0x100>;
interrupts = <0 106 0>;
clocks = <&clock CLK_TSADC>;
clock-names = "adc";
#io-channel-cells = <1>;
io-channel-ranges;
samsung,syscon-phandle = <&pmu_system_controller>;
status = "disabled";
};
i2c_0: i2c@12C60000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C60000 0x100>;
interrupts = <0 56 0>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C0>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_bus>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
status = "disabled";
};
i2c_1: i2c@12C70000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C70000 0x100>;
interrupts = <0 57 0>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C1>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_bus>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
status = "disabled";
};
i2c_2: i2c@12C80000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C80000 0x100>;
interrupts = <0 58 0>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C2>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c2_bus>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
status = "disabled";
};
i2c_3: i2c@12C90000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C90000 0x100>;
interrupts = <0 59 0>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C3>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c3_bus>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
status = "disabled";
};
hsi2c_4: i2c@12CA0000 { i2s2: i2s@12D70000 {
compatible = "samsung,exynos5-hsi2c"; compatible = "samsung,exynos5420-i2s";
reg = <0x12CA0000 0x1000>; reg = <0x12D70000 0x100>;
interrupts = <0 60 0>; dmas = <&pdma0 12
#address-cells = <1>; &pdma0 11>;
#size-cells = <0>; dma-names = "tx", "rx";
pinctrl-names = "default"; clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
pinctrl-0 = <&i2c4_hs_bus>; clock-names = "iis", "i2s_opclk0";
clocks = <&clock CLK_USI0>; #clock-cells = <1>;
clock-names = "hsi2c"; clock-output-names = "i2s_cdclk2";
status = "disabled"; #sound-dai-cells = <1>;
}; pinctrl-names = "default";
pinctrl-0 = <&i2s2_bus>;
hsi2c_5: i2c@12CB0000 { status = "disabled";
compatible = "samsung,exynos5-hsi2c";
reg = <0x12CB0000 0x1000>;
interrupts = <0 61 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c5_hs_bus>;
clocks = <&clock CLK_USI1>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_6: i2c@12CC0000 {
compatible = "samsung,exynos5-hsi2c";
reg = <0x12CC0000 0x1000>;
interrupts = <0 62 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c6_hs_bus>;
clocks = <&clock CLK_USI2>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_7: i2c@12CD0000 {
compatible = "samsung,exynos5-hsi2c";
reg = <0x12CD0000 0x1000>;
interrupts = <0 63 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c7_hs_bus>;
clocks = <&clock CLK_USI3>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_8: i2c@12E00000 {
compatible = "samsung,exynos5-hsi2c";
reg = <0x12E00000 0x1000>;
interrupts = <0 87 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c8_hs_bus>;
clocks = <&clock CLK_USI4>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_9: i2c@12E10000 {
compatible = "samsung,exynos5-hsi2c";
reg = <0x12E10000 0x1000>;
interrupts = <0 88 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c9_hs_bus>;
clocks = <&clock CLK_USI5>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_10: i2c@12E20000 {
compatible = "samsung,exynos5-hsi2c";
reg = <0x12E20000 0x1000>;
interrupts = <0 203 0>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c10_hs_bus>;
clocks = <&clock CLK_USI6>;
clock-names = "hsi2c";
status = "disabled";
};
hdmi: hdmi@14530000 {
compatible = "samsung,exynos5420-hdmi";
reg = <0x14530000 0x70000>;
interrupts = <0 95 0>;
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
<&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
<&clock CLK_MOUT_HDMI>;
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
"sclk_hdmiphy", "mout_hdmi";
phy = <&hdmiphy>;
samsung,syscon-phandle = <&pmu_system_controller>;
status = "disabled";
power-domains = <&disp_pd>;
};
hdmiphy: hdmiphy@145D0000 {
reg = <0x145D0000 0x20>;
};
mixer: mixer@14450000 {
compatible = "samsung,exynos5420-mixer";
reg = <0x14450000 0x10000>;
interrupts = <0 94 0>;
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
<&clock CLK_SCLK_HDMI>;
clock-names = "mixer", "hdmi", "sclk_hdmi";
power-domains = <&disp_pd>;
iommus = <&sysmmu_tv>;
};
rotator: rotator@11C00000 {
compatible = "samsung,exynos5250-rotator";
reg = <0x11C00000 0x64>;
interrupts = <0 84 0>;
clocks = <&clock CLK_ROTATOR>;
clock-names = "rotator";
iommus = <&sysmmu_rotator>;
};
gsc_0: video-scaler@13e00000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e00000 0x1000>;
interrupts = <0 85 0>;
clocks = <&clock CLK_GSCL0>;
clock-names = "gscl";
power-domains = <&gsc_pd>;
iommus = <&sysmmu_gscl0>;
};
gsc_1: video-scaler@13e10000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e10000 0x1000>;
interrupts = <0 86 0>;
clocks = <&clock CLK_GSCL1>;
clock-names = "gscl";
power-domains = <&gsc_pd>;
iommus = <&sysmmu_gscl1>;
};
jpeg_0: jpeg@11F50000 {
compatible = "samsung,exynos5420-jpeg";
reg = <0x11F50000 0x1000>;
interrupts = <0 89 0>;
clock-names = "jpeg";
clocks = <&clock CLK_JPEG>;
iommus = <&sysmmu_jpeg0>;
};
jpeg_1: jpeg@11F60000 {
compatible = "samsung,exynos5420-jpeg";
reg = <0x11F60000 0x1000>;
interrupts = <0 168 0>;
clock-names = "jpeg";
clocks = <&clock CLK_JPEG2>;
iommus = <&sysmmu_jpeg1>;
};
pmu_system_controller: system-controller@10040000 {
compatible = "samsung,exynos5420-pmu", "syscon";
reg = <0x10040000 0x5000>;
clock-names = "clkout16";
clocks = <&clock CLK_FIN_PLL>;
#clock-cells = <1>;
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
};
sysreg_system_controller: syscon@10050000 {
compatible = "samsung,exynos5-sysreg", "syscon";
reg = <0x10050000 0x5000>;
};
tmu_cpu0: tmu@10060000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10060000 0x100>;
interrupts = <0 65 0>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
};
tmu_cpu1: tmu@10064000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10064000 0x100>;
interrupts = <0 183 0>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
};
tmu_cpu2: tmu@10068000 {
compatible = "samsung,exynos5420-tmu-ext-triminfo";
reg = <0x10068000 0x100>, <0x1006c000 0x4>;
interrupts = <0 184 0>;
clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
};
tmu_cpu3: tmu@1006c000 {
compatible = "samsung,exynos5420-tmu-ext-triminfo";
reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
interrupts = <0 185 0>;
clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
};
tmu_gpu: tmu@100a0000 {
compatible = "samsung,exynos5420-tmu-ext-triminfo";
reg = <0x100a0000 0x100>, <0x10068000 0x4>;
interrupts = <0 215 0>;
clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
};
thermal-zones {
cpu0_thermal: cpu0-thermal {
thermal-sensors = <&tmu_cpu0>;
#include "exynos5420-trip-points.dtsi"
};
cpu1_thermal: cpu1-thermal {
thermal-sensors = <&tmu_cpu1>;
#include "exynos5420-trip-points.dtsi"
};
cpu2_thermal: cpu2-thermal {
thermal-sensors = <&tmu_cpu2>;
#include "exynos5420-trip-points.dtsi"
};
cpu3_thermal: cpu3-thermal {
thermal-sensors = <&tmu_cpu3>;
#include "exynos5420-trip-points.dtsi"
};
gpu_thermal: gpu-thermal {
thermal-sensors = <&tmu_gpu>;
#include "exynos5420-trip-points.dtsi"
}; };
};
watchdog: watchdog@101D0000 { spi_0: spi@12d20000 {
compatible = "samsung,exynos5420-wdt"; compatible = "samsung,exynos4210-spi";
reg = <0x101D0000 0x100>; reg = <0x12d20000 0x100>;
interrupts = <0 42 0>; interrupts = <0 68 0>;
clocks = <&clock CLK_WDT>; dmas = <&pdma0 5
clock-names = "watchdog"; &pdma0 4>;
samsung,syscon-phandle = <&pmu_system_controller>; dma-names = "tx", "rx";
}; #address-cells = <1>;
#size-cells = <0>;
sss: sss@10830000 { pinctrl-names = "default";
compatible = "samsung,exynos4210-secss"; pinctrl-0 = <&spi0_bus>;
reg = <0x10830000 0x300>; clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
interrupts = <0 112 0>; clock-names = "spi", "spi_busclk0";
clocks = <&clock CLK_SSS>; status = "disabled";
clock-names = "secss";
};
usbdrd3_0: usb3-0 {
compatible = "samsung,exynos5250-dwusb3";
clocks = <&clock CLK_USBD300>;
clock-names = "usbdrd30";
#address-cells = <1>;
#size-cells = <1>;
ranges;
usbdrd_dwc3_0: dwc3@12000000 {
compatible = "snps,dwc3";
reg = <0x12000000 0x10000>;
interrupts = <0 72 0>;
phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
phy-names = "usb2-phy", "usb3-phy";
}; };
};
usbdrd_phy0: phy@12100000 {
compatible = "samsung,exynos5420-usbdrd-phy";
reg = <0x12100000 0x100>;
clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
clock-names = "phy", "ref";
samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <1>;
};
usbdrd3_1: usb3-1 { spi_1: spi@12d30000 {
compatible = "samsung,exynos5250-dwusb3"; compatible = "samsung,exynos4210-spi";
clocks = <&clock CLK_USBD301>; reg = <0x12d30000 0x100>;
clock-names = "usbdrd30"; interrupts = <0 69 0>;
#address-cells = <1>; dmas = <&pdma1 5
#size-cells = <1>; &pdma1 4>;
ranges; dma-names = "tx", "rx";
#address-cells = <1>;
usbdrd_dwc3_1: dwc3@12400000 { #size-cells = <0>;
compatible = "snps,dwc3"; pinctrl-names = "default";
reg = <0x12400000 0x10000>; pinctrl-0 = <&spi1_bus>;
interrupts = <0 73 0>; clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; clock-names = "spi", "spi_busclk0";
phy-names = "usb2-phy", "usb3-phy"; status = "disabled";
}; };
};
usbdrd_phy1: phy@12500000 {
compatible = "samsung,exynos5420-usbdrd-phy";
reg = <0x12500000 0x100>;
clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
clock-names = "phy", "ref";
samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <1>;
};
usbhost2: usb@12110000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12110000 0x100>;
interrupts = <0 71 0>;
clocks = <&clock CLK_USBH20>; spi_2: spi@12d40000 {
clock-names = "usbhost"; compatible = "samsung,exynos4210-spi";
#address-cells = <1>; reg = <0x12d40000 0x100>;
#size-cells = <0>; interrupts = <0 70 0>;
port@0 { dmas = <&pdma0 7
reg = <0>; &pdma0 6>;
phys = <&usb2_phy 1>; dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi2_bus>;
clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
clock-names = "spi", "spi_busclk0";
status = "disabled";
}; };
};
usbhost1: usb@12120000 { dp_phy: dp-video-phy {
compatible = "samsung,exynos4210-ohci"; compatible = "samsung,exynos5420-dp-video-phy";
reg = <0x12120000 0x100>; samsung,pmu-syscon = <&pmu_system_controller>;
interrupts = <0 71 0>; #phy-cells = <0>;
clocks = <&clock CLK_USBH20>;
clock-names = "usbhost";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phys = <&usb2_phy 1>;
}; };
};
usb2_phy: phy@12130000 {
compatible = "samsung,exynos5250-usb2-phy";
reg = <0x12130000 0x100>;
clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
clock-names = "phy", "ref";
#phy-cells = <1>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
samsung,pmureg-phandle = <&pmu_system_controller>;
};
sysmmu_g2dr: sysmmu@0x10A60000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x10A60000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <24 5>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
#iommu-cells = <0>;
};
sysmmu_g2dw: sysmmu@0x10A70000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x10A70000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <22 2>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
#iommu-cells = <0>;
};
sysmmu_tv: sysmmu@0x14650000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x14650000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <7 4>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
power-domains = <&disp_pd>;
#iommu-cells = <0>;
};
sysmmu_gscl0: sysmmu@0x13E80000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13E80000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <2 0>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
power-domains = <&gsc_pd>;
#iommu-cells = <0>;
};
sysmmu_gscl1: sysmmu@0x13E90000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13E90000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <2 2>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
power-domains = <&gsc_pd>;
#iommu-cells = <0>;
};
sysmmu_scaler0r: sysmmu@0x12880000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x12880000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <22 4>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
#iommu-cells = <0>;
};
sysmmu_scaler1r: sysmmu@0x12890000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x12890000 0x1000>;
interrupts = <0 186 0>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
#iommu-cells = <0>;
};
sysmmu_scaler2r: sysmmu@0x128A0000 { mipi_phy: mipi-video-phy {
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,s5pv210-mipi-video-phy";
reg = <0x128A0000 0x1000>; syscon = <&pmu_system_controller>;
interrupts = <0 188 0>; #phy-cells = <1>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
#iommu-cells = <0>;
};
sysmmu_scaler0w: sysmmu@0x128C0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x128C0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <27 2>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
#iommu-cells = <0>;
};
sysmmu_scaler1w: sysmmu@0x128D0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x128D0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <22 6>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
#iommu-cells = <0>;
};
sysmmu_scaler2w: sysmmu@0x128E0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x128E0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <19 6>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
#iommu-cells = <0>;
};
sysmmu_rotator: sysmmu@0x11D40000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11D40000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <4 0>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
#iommu-cells = <0>;
};
sysmmu_jpeg0: sysmmu@0x11F10000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11F10000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <4 2>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
#iommu-cells = <0>;
};
sysmmu_jpeg1: sysmmu@0x11F20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11F20000 0x1000>;
interrupts = <0 169 0>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
#iommu-cells = <0>;
};
sysmmu_mfc_l: sysmmu@0x11200000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11200000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <6 2>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
power-domains = <&mfc_pd>;
#iommu-cells = <0>;
};
sysmmu_mfc_r: sysmmu@0x11210000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11210000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <8 5>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
power-domains = <&mfc_pd>;
#iommu-cells = <0>;
};
sysmmu_fimd1_0: sysmmu@0x14640000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x14640000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <3 2>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
power-domains = <&disp_pd>;
#iommu-cells = <0>;
};
sysmmu_fimd1_1: sysmmu@0x14680000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x14680000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <3 0>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
power-domains = <&disp_pd>;
#iommu-cells = <0>;
};
bus_wcore: bus_wcore {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
clock-names = "bus";
operating-points-v2 = <&bus_wcore_opp_table>;
status = "disabled";
};
bus_noc: bus_noc {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK100_NOC>;
clock-names = "bus";
operating-points-v2 = <&bus_noc_opp_table>;
status = "disabled";
};
bus_fsys_apb: bus_fsys_apb {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
clock-names = "bus";
operating-points-v2 = <&bus_fsys_apb_opp_table>;
status = "disabled";
};
bus_fsys: bus_fsys {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
clock-names = "bus";
operating-points-v2 = <&bus_fsys_apb_opp_table>;
status = "disabled";
};
bus_fsys2: bus_fsys2 {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
clock-names = "bus";
operating-points-v2 = <&bus_fsys2_opp_table>;
status = "disabled";
};
bus_mfc: bus_mfc {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK333>;
clock-names = "bus";
operating-points-v2 = <&bus_mfc_opp_table>;
status = "disabled";
};
bus_gen: bus_gen {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK266>;
clock-names = "bus";
operating-points-v2 = <&bus_gen_opp_table>;
status = "disabled";
};
bus_peri: bus_peri {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK66>;
clock-names = "bus";
operating-points-v2 = <&bus_peri_opp_table>;
status = "disabled";
};
bus_g2d: bus_g2d {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK333_G2D>;
clock-names = "bus";
operating-points-v2 = <&bus_g2d_opp_table>;
status = "disabled";
};
bus_g2d_acp: bus_g2d_acp {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK266_G2D>;
clock-names = "bus";
operating-points-v2 = <&bus_g2d_acp_opp_table>;
status = "disabled";
};
bus_jpeg: bus_jpeg {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
clock-names = "bus";
operating-points-v2 = <&bus_jpeg_opp_table>;
status = "disabled";
};
bus_jpeg_apb: bus_jpeg_apb {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK166>;
clock-names = "bus";
operating-points-v2 = <&bus_jpeg_apb_opp_table>;
status = "disabled";
};
bus_disp1_fimd: bus_disp1_fimd {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
clock-names = "bus";
operating-points-v2 = <&bus_disp1_fimd_opp_table>;
status = "disabled";
};
bus_disp1: bus_disp1 {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
clock-names = "bus";
operating-points-v2 = <&bus_disp1_opp_table>;
status = "disabled";
};
bus_gscl_scaler: bus_gscl_scaler {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
clock-names = "bus";
operating-points-v2 = <&bus_gscl_opp_table>;
status = "disabled";
};
bus_mscl: bus_mscl {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
clock-names = "bus";
operating-points-v2 = <&bus_mscl_opp_table>;
status = "disabled";
};
bus_wcore_opp_table: opp_table2 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <84000000>;
opp-microvolt = <925000>;
};
opp01 {
opp-hz = /bits/ 64 <111000000>;
opp-microvolt = <950000>;
};
opp02 {
opp-hz = /bits/ 64 <222000000>;
opp-microvolt = <950000>;
}; };
opp03 {
opp-hz = /bits/ 64 <333000000>;
opp-microvolt = <950000>;
};
opp04 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <987500>;
};
};
bus_noc_opp_table: opp_table3 { dsi@14500000 {
compatible = "operating-points-v2"; compatible = "samsung,exynos5410-mipi-dsi";
reg = <0x14500000 0x10000>;
opp00 { interrupts = <0 82 0>;
opp-hz = /bits/ 64 <67000000>; phys = <&mipi_phy 1>;
}; phy-names = "dsim";
opp01 { clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
opp-hz = /bits/ 64 <75000000>; clock-names = "bus_clk", "pll_clk";
}; #address-cells = <1>;
opp02 { #size-cells = <0>;
opp-hz = /bits/ 64 <86000000>; status = "disabled";
};
opp03 {
opp-hz = /bits/ 64 <100000000>;
}; };
};
bus_fsys_apb_opp_table: opp_table4 {
compatible = "operating-points-v2";
opp-shared;
opp00 { adc: adc@12D10000 {
opp-hz = /bits/ 64 <100000000>; compatible = "samsung,exynos-adc-v2";
}; reg = <0x12D10000 0x100>;
opp01 { interrupts = <0 106 0>;
opp-hz = /bits/ 64 <200000000>; clocks = <&clock CLK_TSADC>;
clock-names = "adc";
#io-channel-cells = <1>;
io-channel-ranges;
samsung,syscon-phandle = <&pmu_system_controller>;
status = "disabled";
}; };
};
bus_fsys2_opp_table: opp_table5 {
compatible = "operating-points-v2";
opp00 { hsi2c_8: i2c@12E00000 {
opp-hz = /bits/ 64 <75000000>; compatible = "samsung,exynos5250-hsi2c";
}; reg = <0x12E00000 0x1000>;
opp01 { interrupts = <0 87 0>;
opp-hz = /bits/ 64 <100000000>; #address-cells = <1>;
}; #size-cells = <0>;
opp02 { pinctrl-names = "default";
opp-hz = /bits/ 64 <150000000>; pinctrl-0 = <&i2c8_hs_bus>;
clocks = <&clock CLK_USI4>;
clock-names = "hsi2c";
status = "disabled";
}; };
};
bus_mfc_opp_table: opp_table6 { hsi2c_9: i2c@12E10000 {
compatible = "operating-points-v2"; compatible = "samsung,exynos5250-hsi2c";
reg = <0x12E10000 0x1000>;
opp00 { interrupts = <0 88 0>;
opp-hz = /bits/ 64 <96000000>; #address-cells = <1>;
}; #size-cells = <0>;
opp01 { pinctrl-names = "default";
opp-hz = /bits/ 64 <111000000>; pinctrl-0 = <&i2c9_hs_bus>;
}; clocks = <&clock CLK_USI5>;
opp02 { clock-names = "hsi2c";
opp-hz = /bits/ 64 <167000000>; status = "disabled";
};
opp03 {
opp-hz = /bits/ 64 <222000000>;
};
opp04 {
opp-hz = /bits/ 64 <333000000>;
}; };
};
bus_gen_opp_table: opp_table7 { hsi2c_10: i2c@12E20000 {
compatible = "operating-points-v2"; compatible = "samsung,exynos5250-hsi2c";
reg = <0x12E20000 0x1000>;
opp00 { interrupts = <0 203 0>;
opp-hz = /bits/ 64 <89000000>; #address-cells = <1>;
}; #size-cells = <0>;
opp01 { pinctrl-names = "default";
opp-hz = /bits/ 64 <133000000>; pinctrl-0 = <&i2c10_hs_bus>;
}; clocks = <&clock CLK_USI6>;
opp02 { clock-names = "hsi2c";
opp-hz = /bits/ 64 <178000000>; status = "disabled";
};
opp03 {
opp-hz = /bits/ 64 <267000000>;
}; };
};
bus_peri_opp_table: opp_table8 {
compatible = "operating-points-v2";
opp00 { hdmi: hdmi@14530000 {
opp-hz = /bits/ 64 <67000000>; compatible = "samsung,exynos5420-hdmi";
reg = <0x14530000 0x70000>;
interrupts = <0 95 0>;
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
<&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
<&clock CLK_MOUT_HDMI>;
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
"sclk_hdmiphy", "mout_hdmi";
phy = <&hdmiphy>;
samsung,syscon-phandle = <&pmu_system_controller>;
status = "disabled";
power-domains = <&disp_pd>;
};
hdmiphy: hdmiphy@145D0000 {
reg = <0x145D0000 0x20>;
};
mixer: mixer@14450000 {
compatible = "samsung,exynos5420-mixer";
reg = <0x14450000 0x10000>;
interrupts = <0 94 0>;
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
<&clock CLK_SCLK_HDMI>;
clock-names = "mixer", "hdmi", "sclk_hdmi";
power-domains = <&disp_pd>;
iommus = <&sysmmu_tv>;
};
rotator: rotator@11C00000 {
compatible = "samsung,exynos5250-rotator";
reg = <0x11C00000 0x64>;
interrupts = <0 84 0>;
clocks = <&clock CLK_ROTATOR>;
clock-names = "rotator";
iommus = <&sysmmu_rotator>;
};
gsc_0: video-scaler@13e00000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e00000 0x1000>;
interrupts = <0 85 0>;
clocks = <&clock CLK_GSCL0>;
clock-names = "gscl";
power-domains = <&gsc_pd>;
iommus = <&sysmmu_gscl0>;
};
gsc_1: video-scaler@13e10000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e10000 0x1000>;
interrupts = <0 86 0>;
clocks = <&clock CLK_GSCL1>;
clock-names = "gscl";
power-domains = <&gsc_pd>;
iommus = <&sysmmu_gscl1>;
};
jpeg_0: jpeg@11F50000 {
compatible = "samsung,exynos5420-jpeg";
reg = <0x11F50000 0x1000>;
interrupts = <0 89 0>;
clock-names = "jpeg";
clocks = <&clock CLK_JPEG>;
iommus = <&sysmmu_jpeg0>;
};
jpeg_1: jpeg@11F60000 {
compatible = "samsung,exynos5420-jpeg";
reg = <0x11F60000 0x1000>;
interrupts = <0 168 0>;
clock-names = "jpeg";
clocks = <&clock CLK_JPEG2>;
iommus = <&sysmmu_jpeg1>;
};
pmu_system_controller: system-controller@10040000 {
compatible = "samsung,exynos5420-pmu", "syscon";
reg = <0x10040000 0x5000>;
clock-names = "clkout16";
clocks = <&clock CLK_FIN_PLL>;
#clock-cells = <1>;
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
}; };
};
bus_g2d_opp_table: opp_table9 {
compatible = "operating-points-v2";
opp00 { tmu_cpu0: tmu@10060000 {
opp-hz = /bits/ 64 <84000000>; compatible = "samsung,exynos5420-tmu";
}; reg = <0x10060000 0x100>;
opp01 { interrupts = <0 65 0>;
opp-hz = /bits/ 64 <167000000>; clocks = <&clock CLK_TMU>;
}; clock-names = "tmu_apbif";
opp02 { #include "exynos4412-tmu-sensor-conf.dtsi"
opp-hz = /bits/ 64 <222000000>; };
};
opp03 { tmu_cpu1: tmu@10064000 {
opp-hz = /bits/ 64 <300000000>; compatible = "samsung,exynos5420-tmu";
}; reg = <0x10064000 0x100>;
opp04 { interrupts = <0 183 0>;
opp-hz = /bits/ 64 <333000000>; clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
};
tmu_cpu2: tmu@10068000 {
compatible = "samsung,exynos5420-tmu-ext-triminfo";
reg = <0x10068000 0x100>, <0x1006c000 0x4>;
interrupts = <0 184 0>;
clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
};
tmu_cpu3: tmu@1006c000 {
compatible = "samsung,exynos5420-tmu-ext-triminfo";
reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
interrupts = <0 185 0>;
clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
};
tmu_gpu: tmu@100a0000 {
compatible = "samsung,exynos5420-tmu-ext-triminfo";
reg = <0x100a0000 0x100>, <0x10068000 0x4>;
interrupts = <0 215 0>;
clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
};
sysmmu_g2dr: sysmmu@0x10A60000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x10A60000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <24 5>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
#iommu-cells = <0>;
};
sysmmu_g2dw: sysmmu@0x10A70000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x10A70000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <22 2>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
#iommu-cells = <0>;
};
sysmmu_tv: sysmmu@0x14650000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x14650000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <7 4>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
power-domains = <&disp_pd>;
#iommu-cells = <0>;
};
sysmmu_gscl0: sysmmu@0x13E80000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13E80000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <2 0>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
power-domains = <&gsc_pd>;
#iommu-cells = <0>;
};
sysmmu_gscl1: sysmmu@0x13E90000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13E90000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <2 2>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
power-domains = <&gsc_pd>;
#iommu-cells = <0>;
};
sysmmu_scaler0r: sysmmu@0x12880000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x12880000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <22 4>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
#iommu-cells = <0>;
};
sysmmu_scaler1r: sysmmu@0x12890000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x12890000 0x1000>;
interrupts = <0 186 0>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
#iommu-cells = <0>;
};
sysmmu_scaler2r: sysmmu@0x128A0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x128A0000 0x1000>;
interrupts = <0 188 0>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
#iommu-cells = <0>;
};
sysmmu_scaler0w: sysmmu@0x128C0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x128C0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <27 2>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
#iommu-cells = <0>;
};
sysmmu_scaler1w: sysmmu@0x128D0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x128D0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <22 6>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
#iommu-cells = <0>;
};
sysmmu_scaler2w: sysmmu@0x128E0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x128E0000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <19 6>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
#iommu-cells = <0>;
};
sysmmu_rotator: sysmmu@0x11D40000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11D40000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <4 0>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
#iommu-cells = <0>;
};
sysmmu_jpeg0: sysmmu@0x11F10000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11F10000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <4 2>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
#iommu-cells = <0>;
};
sysmmu_jpeg1: sysmmu@0x11F20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11F20000 0x1000>;
interrupts = <0 169 0>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
#iommu-cells = <0>;
};
sysmmu_mfc_l: sysmmu@0x11200000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11200000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <6 2>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
power-domains = <&mfc_pd>;
#iommu-cells = <0>;
};
sysmmu_mfc_r: sysmmu@0x11210000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11210000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <8 5>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
power-domains = <&mfc_pd>;
#iommu-cells = <0>;
};
sysmmu_fimd1_0: sysmmu@0x14640000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x14640000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <3 2>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
power-domains = <&disp_pd>;
#iommu-cells = <0>;
};
sysmmu_fimd1_1: sysmmu@0x14680000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x14680000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <3 0>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
power-domains = <&disp_pd>;
#iommu-cells = <0>;
};
bus_wcore: bus_wcore {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
clock-names = "bus";
operating-points-v2 = <&bus_wcore_opp_table>;
status = "disabled";
}; };
};
bus_g2d_acp_opp_table: opp_table10 {
compatible = "operating-points-v2";
opp00 { bus_noc: bus_noc {
opp-hz = /bits/ 64 <67000000>; compatible = "samsung,exynos-bus";
}; clocks = <&clock CLK_DOUT_ACLK100_NOC>;
opp01 { clock-names = "bus";
opp-hz = /bits/ 64 <133000000>; operating-points-v2 = <&bus_noc_opp_table>;
}; status = "disabled";
opp02 {
opp-hz = /bits/ 64 <178000000>;
};
opp03 {
opp-hz = /bits/ 64 <267000000>;
}; };
};
bus_jpeg_opp_table: opp_table11 {
compatible = "operating-points-v2";
opp00 { bus_fsys_apb: bus_fsys_apb {
opp-hz = /bits/ 64 <75000000>; compatible = "samsung,exynos-bus";
}; clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
opp01 { clock-names = "bus";
opp-hz = /bits/ 64 <150000000>; operating-points-v2 = <&bus_fsys_apb_opp_table>;
}; status = "disabled";
opp02 {
opp-hz = /bits/ 64 <200000000>;
};
opp03 {
opp-hz = /bits/ 64 <300000000>;
}; };
};
bus_jpeg_apb_opp_table: opp_table12 {
compatible = "operating-points-v2";
opp00 { bus_fsys: bus_fsys {
opp-hz = /bits/ 64 <84000000>; compatible = "samsung,exynos-bus";
}; clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
opp01 { clock-names = "bus";
opp-hz = /bits/ 64 <111000000>; operating-points-v2 = <&bus_fsys_apb_opp_table>;
status = "disabled";
}; };
opp02 {
opp-hz = /bits/ 64 <134000000>; bus_fsys2: bus_fsys2 {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
clock-names = "bus";
operating-points-v2 = <&bus_fsys2_opp_table>;
status = "disabled";
}; };
opp03 {
opp-hz = /bits/ 64 <167000000>; bus_mfc: bus_mfc {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK333>;
clock-names = "bus";
operating-points-v2 = <&bus_mfc_opp_table>;
status = "disabled";
}; };
};
bus_disp1_fimd_opp_table: opp_table13 { bus_gen: bus_gen {
compatible = "operating-points-v2"; compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK266>;
clock-names = "bus";
operating-points-v2 = <&bus_gen_opp_table>;
status = "disabled";
};
opp00 { bus_peri: bus_peri {
opp-hz = /bits/ 64 <120000000>; compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK66>;
clock-names = "bus";
operating-points-v2 = <&bus_peri_opp_table>;
status = "disabled";
}; };
opp01 {
opp-hz = /bits/ 64 <200000000>; bus_g2d: bus_g2d {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK333_G2D>;
clock-names = "bus";
operating-points-v2 = <&bus_g2d_opp_table>;
status = "disabled";
}; };
};
bus_disp1_opp_table: opp_table14 { bus_g2d_acp: bus_g2d_acp {
compatible = "operating-points-v2"; compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK266_G2D>;
clock-names = "bus";
operating-points-v2 = <&bus_g2d_acp_opp_table>;
status = "disabled";
};
opp00 { bus_jpeg: bus_jpeg {
opp-hz = /bits/ 64 <120000000>; compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
clock-names = "bus";
operating-points-v2 = <&bus_jpeg_opp_table>;
status = "disabled";
}; };
opp01 {
opp-hz = /bits/ 64 <200000000>; bus_jpeg_apb: bus_jpeg_apb {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK166>;
clock-names = "bus";
operating-points-v2 = <&bus_jpeg_apb_opp_table>;
status = "disabled";
}; };
opp02 {
opp-hz = /bits/ 64 <300000000>; bus_disp1_fimd: bus_disp1_fimd {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
clock-names = "bus";
operating-points-v2 = <&bus_disp1_fimd_opp_table>;
status = "disabled";
}; };
};
bus_gscl_opp_table: opp_table15 { bus_disp1: bus_disp1 {
compatible = "operating-points-v2"; compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
clock-names = "bus";
operating-points-v2 = <&bus_disp1_opp_table>;
status = "disabled";
};
opp00 { bus_gscl_scaler: bus_gscl_scaler {
opp-hz = /bits/ 64 <150000000>; compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
clock-names = "bus";
operating-points-v2 = <&bus_gscl_opp_table>;
status = "disabled";
}; };
opp01 {
opp-hz = /bits/ 64 <200000000>; bus_mscl: bus_mscl {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
clock-names = "bus";
operating-points-v2 = <&bus_mscl_opp_table>;
status = "disabled";
}; };
opp02 {
opp-hz = /bits/ 64 <300000000>; bus_wcore_opp_table: opp_table2 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <84000000>;
opp-microvolt = <925000>;
};
opp01 {
opp-hz = /bits/ 64 <111000000>;
opp-microvolt = <950000>;
};
opp02 {
opp-hz = /bits/ 64 <222000000>;
opp-microvolt = <950000>;
};
opp03 {
opp-hz = /bits/ 64 <333000000>;
opp-microvolt = <950000>;
};
opp04 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <987500>;
};
};
bus_noc_opp_table: opp_table3 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <67000000>;
};
opp01 {
opp-hz = /bits/ 64 <75000000>;
};
opp02 {
opp-hz = /bits/ 64 <86000000>;
};
opp03 {
opp-hz = /bits/ 64 <100000000>;
};
};
bus_fsys_apb_opp_table: opp_table4 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <100000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
};
};
bus_fsys2_opp_table: opp_table5 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <75000000>;
};
opp01 {
opp-hz = /bits/ 64 <100000000>;
};
opp02 {
opp-hz = /bits/ 64 <150000000>;
};
};
bus_mfc_opp_table: opp_table6 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <96000000>;
};
opp01 {
opp-hz = /bits/ 64 <111000000>;
};
opp02 {
opp-hz = /bits/ 64 <167000000>;
};
opp03 {
opp-hz = /bits/ 64 <222000000>;
};
opp04 {
opp-hz = /bits/ 64 <333000000>;
};
};
bus_gen_opp_table: opp_table7 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <89000000>;
};
opp01 {
opp-hz = /bits/ 64 <133000000>;
};
opp02 {
opp-hz = /bits/ 64 <178000000>;
};
opp03 {
opp-hz = /bits/ 64 <267000000>;
};
};
bus_peri_opp_table: opp_table8 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <67000000>;
};
};
bus_g2d_opp_table: opp_table9 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <84000000>;
};
opp01 {
opp-hz = /bits/ 64 <167000000>;
};
opp02 {
opp-hz = /bits/ 64 <222000000>;
};
opp03 {
opp-hz = /bits/ 64 <300000000>;
};
opp04 {
opp-hz = /bits/ 64 <333000000>;
};
};
bus_g2d_acp_opp_table: opp_table10 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <67000000>;
};
opp01 {
opp-hz = /bits/ 64 <133000000>;
};
opp02 {
opp-hz = /bits/ 64 <178000000>;
};
opp03 {
opp-hz = /bits/ 64 <267000000>;
};
};
bus_jpeg_opp_table: opp_table11 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <75000000>;
};
opp01 {
opp-hz = /bits/ 64 <150000000>;
};
opp02 {
opp-hz = /bits/ 64 <200000000>;
};
opp03 {
opp-hz = /bits/ 64 <300000000>;
};
};
bus_jpeg_apb_opp_table: opp_table12 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <84000000>;
};
opp01 {
opp-hz = /bits/ 64 <111000000>;
};
opp02 {
opp-hz = /bits/ 64 <134000000>;
};
opp03 {
opp-hz = /bits/ 64 <167000000>;
};
};
bus_disp1_fimd_opp_table: opp_table13 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <120000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
};
};
bus_disp1_opp_table: opp_table14 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <120000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
};
opp02 {
opp-hz = /bits/ 64 <300000000>;
};
};
bus_gscl_opp_table: opp_table15 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <150000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
};
opp02 {
opp-hz = /bits/ 64 <300000000>;
};
};
bus_mscl_opp_table: opp_table16 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <84000000>;
};
opp01 {
opp-hz = /bits/ 64 <167000000>;
};
opp02 {
opp-hz = /bits/ 64 <222000000>;
};
opp03 {
opp-hz = /bits/ 64 <333000000>;
};
opp04 {
opp-hz = /bits/ 64 <400000000>;
};
}; };
}; };
bus_mscl_opp_table: opp_table16 { thermal-zones {
compatible = "operating-points-v2"; cpu0_thermal: cpu0-thermal {
thermal-sensors = <&tmu_cpu0>;
opp00 { #include "exynos5420-trip-points.dtsi"
opp-hz = /bits/ 64 <84000000>;
}; };
opp01 { cpu1_thermal: cpu1-thermal {
opp-hz = /bits/ 64 <167000000>; thermal-sensors = <&tmu_cpu1>;
#include "exynos5420-trip-points.dtsi"
}; };
opp02 { cpu2_thermal: cpu2-thermal {
opp-hz = /bits/ 64 <222000000>; thermal-sensors = <&tmu_cpu2>;
#include "exynos5420-trip-points.dtsi"
}; };
opp03 { cpu3_thermal: cpu3-thermal {
opp-hz = /bits/ 64 <333000000>; thermal-sensors = <&tmu_cpu3>;
#include "exynos5420-trip-points.dtsi"
}; };
opp04 { gpu_thermal: gpu-thermal {
opp-hz = /bits/ 64 <400000000>; thermal-sensors = <&tmu_gpu>;
#include "exynos5420-trip-points.dtsi"
}; };
}; };
}; };
...@@ -1615,6 +1330,72 @@ &fimd { ...@@ -1615,6 +1330,72 @@ &fimd {
iommu-names = "m0", "m1"; iommu-names = "m0", "m1";
}; };
&i2c_0 {
clocks = <&clock CLK_I2C0>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_bus>;
};
&i2c_1 {
clocks = <&clock CLK_I2C1>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_bus>;
};
&i2c_2 {
clocks = <&clock CLK_I2C2>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c2_bus>;
};
&i2c_3 {
clocks = <&clock CLK_I2C3>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c3_bus>;
};
&hsi2c_4 {
clocks = <&clock CLK_USI0>;
clock-names = "hsi2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c4_hs_bus>;
};
&hsi2c_5 {
clocks = <&clock CLK_USI1>;
clock-names = "hsi2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c5_hs_bus>;
};
&hsi2c_6 {
clocks = <&clock CLK_USI2>;
clock-names = "hsi2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c6_hs_bus>;
};
&hsi2c_7 {
clocks = <&clock CLK_USI3>;
clock-names = "hsi2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c7_hs_bus>;
};
&mct {
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
};
&pwm {
clocks = <&clock CLK_PWM>;
clock-names = "timers";
};
&rtc { &rtc {
clocks = <&clock CLK_RTC>; clocks = <&clock CLK_RTC>;
clock-names = "rtc"; clock-names = "rtc";
...@@ -1642,4 +1423,58 @@ &serial_3 { ...@@ -1642,4 +1423,58 @@ &serial_3 {
clock-names = "uart", "clk_uart_baud0"; clock-names = "uart", "clk_uart_baud0";
}; };
&sss {
clocks = <&clock CLK_SSS>;
clock-names = "secss";
};
&usbdrd3_0 {
clocks = <&clock CLK_USBD300>;
clock-names = "usbdrd30";
};
&usbdrd_phy0 {
clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
clock-names = "phy", "ref";
samsung,pmu-syscon = <&pmu_system_controller>;
};
&usbdrd3_1 {
clocks = <&clock CLK_USBD301>;
clock-names = "usbdrd30";
};
&usbdrd_dwc3_1 {
interrupts = <GIC_SPI 73 0>;
};
&usbdrd_phy1 {
clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
clock-names = "phy", "ref";
samsung,pmu-syscon = <&pmu_system_controller>;
};
&usbhost1 {
clocks = <&clock CLK_USBH20>;
clock-names = "usbhost";
};
&usbhost2 {
clocks = <&clock CLK_USBH20>;
clock-names = "usbhost";
};
&usb2_phy {
clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
clock-names = "phy", "ref";
samsung,sysreg-phandle = <&sysreg_system_controller>;
samsung,pmureg-phandle = <&pmu_system_controller>;
};
&watchdog {
clocks = <&clock CLK_WDT>;
clock-names = "watchdog";
samsung,syscon-phandle = <&pmu_system_controller>;
};
#include "exynos5420-pinctrl.dtsi" #include "exynos5420-pinctrl.dtsi"
arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
View file @ 95eb940c
...@@ -14,44 +14,11 @@ ...@@ -14,44 +14,11 @@
/dts-v1/; /dts-v1/;
#include "exynos5422-odroidxu3-common.dtsi" #include "exynos5422-odroidxu3-common.dtsi"
#include "exynos5422-odroidxu3-audio.dtsi" #include "exynos5422-odroidxu3-audio.dtsi"
#include "exynos54xx-odroidxu-leds.dtsi"
/ { / {
model = "Hardkernel Odroid XU3 Lite"; model = "Hardkernel Odroid XU3 Lite";
compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5"; compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5";
pwmleds {
compatible = "pwm-leds";
greenled {
label = "green:mmc0";
pwms = <&pwm 1 2000000 0>;
pwm-names = "pwm1";
/*
* Green LED is much brighter than the others
* so limit its max brightness
*/
max_brightness = <127>;
linux,default-trigger = "mmc0";
};
blueled {
label = "blue:heartbeat";
pwms = <&pwm 2 2000000 0>;
pwm-names = "pwm2";
max_brightness = <255>;
linux,default-trigger = "heartbeat";
};
};
gpioleds {
compatible = "gpio-leds";
redled {
label = "red:microSD";
gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "mmc1";
};
};
}; };
&pwm { &pwm {
......
arch/arm/boot/dts/exynos5422-odroidxu3.dts
View file @ 95eb940c
...@@ -13,44 +13,11 @@ ...@@ -13,44 +13,11 @@
/dts-v1/; /dts-v1/;
#include "exynos5422-odroidxu3-common.dtsi" #include "exynos5422-odroidxu3-common.dtsi"
#include "exynos5422-odroidxu3-audio.dtsi" #include "exynos5422-odroidxu3-audio.dtsi"
#include "exynos54xx-odroidxu-leds.dtsi"
/ { / {
model = "Hardkernel Odroid XU3"; model = "Hardkernel Odroid XU3";
compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5"; compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5";
pwmleds {
compatible = "pwm-leds";
greenled {
label = "green:mmc0";
pwms = <&pwm 1 2000000 0>;
pwm-names = "pwm1";
/*
* Green LED is much brighter than the others
* so limit its max brightness
*/
max_brightness = <127>;
linux,default-trigger = "mmc0";
};
blueled {
label = "blue:heartbeat";
pwms = <&pwm 2 2000000 0>;
pwm-names = "pwm2";
max_brightness = <255>;
linux,default-trigger = "heartbeat";
};
};
gpioleds {
compatible = "gpio-leds";
redled {
label = "red:microSD";
gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "mmc1";
};
};
}; };
&i2c_0 { &i2c_0 {
......
arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi 0 → 100644
View file @ 95eb940c
/*
* Hardkernel Odroid XU/XU3 LED device tree source
*
* Copyright (c) 2015,2016 Krzysztof Kozlowski
* Copyright (c) 2014 Collabora Ltd.
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/gpio/gpio.h>
/ {
pwmleds {
compatible = "pwm-leds";
greenled {
label = "green:mmc0";
pwms = <&pwm 1 2000000 0>;
pwm-names = "pwm1";
/*
* Green LED is much brighter than the others
* so limit its max brightness
*/
max_brightness = <127>;
linux,default-trigger = "mmc0";
};
blueled {
label = "blue:heartbeat";
pwms = <&pwm 2 2000000 0>;
pwm-names = "pwm2";
max_brightness = <255>;
linux,default-trigger = "heartbeat";
};
};
gpioleds {
compatible = "gpio-leds";
redled {
label = "red:microSD";
gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "mmc1";
};
};
};
arch/arm/boot/dts/exynos54xx.dtsi 0 → 100644
View file @ 95eb940c
/*
* Samsung's Exynos54xx SoC series common device tree source
*
* Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Copyright (c) 2016 Krzysztof Kozlowski
*
* Device nodes common for Samsung Exynos5410/5420/5422/5800. Specific
* Exynos 54xx SoCs should include this file and customize it further
* (e.g. with clocks).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "skeleton.dtsi"
#include "exynos5.dtsi"
/ {
compatible = "samsung,exynos5";
aliases {
i2c4 = &hsi2c_4;
i2c5 = &hsi2c_5;
i2c6 = &hsi2c_6;
i2c7 = &hsi2c_7;
usbdrdphy0 = &usbdrd_phy0;
usbdrdphy1 = &usbdrd_phy1;
};
soc: soc {
sysram@02020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x54000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x02020000 0x54000>;
smp-sysram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
smp-sysram@53000 {
compatible = "samsung,exynos4210-sysram-ns";
reg = <0x53000 0x1000>;
};
};
mct: mct@101c0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x101c0000 0xb00>;
interrupt-parent = <&mct_map>;
interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
<8>, <9>, <10>, <11>;
mct_map: mct-map {
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = <0 &combiner 23 3>,
<1 &combiner 23 4>,
<2 &combiner 25 2>,
<3 &combiner 25 3>,
<4 &gic 0 120 0>,
<5 &gic 0 121 0>,
<6 &gic 0 122 0>,
<7 &gic 0 123 0>,
<8 &gic 0 128 0>,
<9 &gic 0 129 0>,
<10 &gic 0 130 0>,
<11 &gic 0 131 0>;
};
};
watchdog: watchdog@101d0000 {
compatible = "samsung,exynos5420-wdt";
reg = <0x101d0000 0x100>;
interrupts = <0 42 0>;
};
sss: sss@10830000 {
compatible = "samsung,exynos4210-secss";
reg = <0x10830000 0x300>;
interrupts = <0 112 0>;
};
/* i2c_0-3 are defined in exynos5.dtsi */
hsi2c_4: i2c@12ca0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12ca0000 0x1000>;
interrupts = <0 60 0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
hsi2c_5: i2c@12cb0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12cb0000 0x1000>;
interrupts = <0 61 0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
hsi2c_6: i2c@12cc0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12cc0000 0x1000>;
interrupts = <0 62 0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
hsi2c_7: i2c@12cd0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12cd0000 0x1000>;
interrupts = <0 63 0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
usbdrd3_0: usb3-0 {
compatible = "samsung,exynos5250-dwusb3";
#address-cells = <1>;
#size-cells = <1>;
ranges;
usbdrd_dwc3_0: dwc3@12000000 {
compatible = "snps,dwc3";
reg = <0x12000000 0x10000>;
interrupts = <0 72 0>;
phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
phy-names = "usb2-phy", "usb3-phy";
};
};
usbdrd_phy0: phy@12100000 {
compatible = "samsung,exynos5420-usbdrd-phy";
reg = <0x12100000 0x100>;
#phy-cells = <1>;
};
usbdrd3_1: usb3-1 {
compatible = "samsung,exynos5250-dwusb3";
#address-cells = <1>;
#size-cells = <1>;
ranges;
usbdrd_dwc3_1: dwc3@12400000 {
compatible = "snps,dwc3";
reg = <0x12400000 0x10000>;
phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
phy-names = "usb2-phy", "usb3-phy";
};
};
usbdrd_phy1: phy@12500000 {
compatible = "samsung,exynos5420-usbdrd-phy";
reg = <0x12500000 0x100>;
#phy-cells = <1>;
};
usbhost2: usb@12110000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12110000 0x100>;
interrupts = <0 71 0>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phys = <&usb2_phy 1>;
};
};
usbhost1: usb@12120000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12120000 0x100>;
interrupts = <0 71 0>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phys = <&usb2_phy 1>;
};
};
usb2_phy: phy@12130000 {
compatible = "samsung,exynos5250-usb2-phy";
reg = <0x12130000 0x100>;
#phy-cells = <1>;
};
};
};
include/dt-bindings/clock/exynos5410.h
View file @ 95eb940c
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Copyright (c) 2016 Krzysztof Kozlowski
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants for Exynos5421 clock controller.
*/
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H #define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
/* core clocks */ /* core clocks */
#define CLK_FIN_PLL 1 #define CLK_FIN_PLL 1
#define CLK_FOUT_APLL 2 #define CLK_FOUT_APLL 2
#define CLK_FOUT_CPLL 3 #define CLK_FOUT_CPLL 3
#define CLK_FOUT_MPLL 4 #define CLK_FOUT_MPLL 4
#define CLK_FOUT_BPLL 5 #define CLK_FOUT_BPLL 5
#define CLK_FOUT_KPLL 6 #define CLK_FOUT_KPLL 6
/* gate for special clocks (sclk) */ /* gate for special clocks (sclk) */
#define CLK_SCLK_UART0 128 #define CLK_SCLK_UART0 128
#define CLK_SCLK_UART1 129 #define CLK_SCLK_UART1 129
#define CLK_SCLK_UART2 130 #define CLK_SCLK_UART2 130
#define CLK_SCLK_UART3 131 #define CLK_SCLK_UART3 131
#define CLK_SCLK_MMC0 132 #define CLK_SCLK_MMC0 132
#define CLK_SCLK_MMC1 133 #define CLK_SCLK_MMC1 133
#define CLK_SCLK_MMC2 134 #define CLK_SCLK_MMC2 134
#define CLK_SCLK_USBD300 150
#define CLK_SCLK_USBD301 151
#define CLK_SCLK_USBPHY300 152
#define CLK_SCLK_USBPHY301 153
#define CLK_SCLK_PWM 155
/* gate clocks */ /* gate clocks */
#define CLK_UART0 257 #define CLK_UART0 257
#define CLK_UART1 258 #define CLK_UART1 258
#define CLK_UART2 259 #define CLK_UART2 259
#define CLK_UART3 260 #define CLK_I2C0 261
#define CLK_MCT 315 #define CLK_I2C1 262
#define CLK_MMC0 351 #define CLK_I2C2 263
#define CLK_MMC1 352 #define CLK_I2C3 264
#define CLK_MMC2 353 #define CLK_USI0 265
#define CLK_USI1 266
#define CLK_USI2 267
#define CLK_USI3 268
#define CLK_UART3 260
#define CLK_PWM 279
#define CLK_MCT 315
#define CLK_WDT 316
#define CLK_RTC 317
#define CLK_TMU 318
#define CLK_MMC0 351
#define CLK_MMC1 352
#define CLK_MMC2 353
#define CLK_USBH20 365
#define CLK_USBD300 366
#define CLK_USBD301 367
#define CLK_SSS 471
#define CLK_NR_CLKS 512 #define CLK_NR_CLKS 512
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */ #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
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