Commit 96bb2d9e authored by Russell King's avatar Russell King

Merge flint.arm.linux.org.uk:/usr/src/linux-bk-2.5/linux-2.5

into flint.arm.linux.org.uk:/usr/src/linux-bk-2.5/linux-2.5-rmk
parents 88e4bc32 9ed2c5a7
......@@ -836,3 +836,153 @@ CONFIG_DEBUG_BUGVERBOSE
of the BUG call as well as the EIP and oops trace. This aids
debugging but costs about 70-100K of memory.
CONFIG_ZBOOT_ROM
Say Y here if you intend to execute your compressed kernel image (zImage)
directly from ROM or flash. If unsure, say N.
CONFIG_ZBOOT_ROM_TEXT
The base address for zImage. Unless you have special requirements, you
should not change this value.
CONFIG_ZBOOT_ROM_BSS
The base address of 64KiB of read/write memory, which must be available
while the decompressor is running. Unless you have special requirements,
you should not change this value.
CONFIG_CPU_FREQ
CPU clock scaling allows you to change the clock speed of the
running CPU on the fly. This is a nice method to save battery power,
because the lower the clock speed, the less power the CPU
consumes. Note that this driver doesn't automatically change the CPU
clock speed, you need some userland tools (which still have to be
written) to implement the policy. If you don't understand what this
is all about, it's safe to say 'N'.
CONFIG_ARCH_EDB7211
Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211
evaluation board.
CONFIG_SA1100_H3100
Say Y here if you intend to run this kernel on the Compaq iPAQ
H3100 handheld computer. Information about this machine and the
Linux port to this machine can be found at:
<http://www.handhelds.org/Compaq/index.html#iPAQ_H3100>
<http://www.compaq.com/products/handhelds/pocketpc/>
CONFIG_SA1100_H3800
Say Y here if you intend to run this kernel on the Compaq iPAQ H3800
series handheld computer. Information about this machine and the
Linux port to this machine can be found at:
<http://www.handhelds.org/Compaq/index.html#iPAQ_H3800>
<http://www.compaq.com/products/handhelds/pocketpc/>
CONFIG_H3600_SLEEVE
Choose this option to enable support for extension packs (sleeves)
for the Compaq iPAQ H3XXX series of handheld computers. This option
is required for the CF, PCMCIA, Bluetooth and GSM/GPRS extension
packs.
CONFIG_SA1100_GRAPHICSMASTER
Say Y here if you are using an Applied Data Systems Intel(R)
StrongARM(R) SA-1100 based Graphics Master SBC with SA-1111
StrongARM companion chip. See
<http://www.applieddata.net/products_masterSpec.asp> for information
on this system.
CONFIG_SA1100_ADSBITSY
Say Y here if you are using Applied Data Systems Intel(R)
StrongARM(R) 1110 based Bitsy, 3 x 5 inches in size, Compaq - IPAQ -
like platform. See
<http://www.applieddata.net/products_bitsySpec.asp> for more
information.
CONFIG_SA1100_ITSY
Say Y here if you are using the Compaq Itsy experimental pocket
computer. See <http://research.compaq.com/wrl/projects/itsy/> for
more information.
CONFIG_SA1100_HUW_WEBPANEL
Say Y here to support the HuW Webpanel produced by Hoeft & Wessel
AG. English-language website is at
<http://www.hoeft-wessel.de/en.htm>; credits and build instructions
at Documentation/arm/SA1100/HUW_WEBPANEL.
CONFIG_SA1100_PLEB
Say Y here if you are using a Portable Linux Embedded Board
(also known as PLEB). See <http://www.cse.unsw.edu.au/~pleb/>
for more information.
CONFIG_SA1100_SHERMAN
Say Y here to support the Blazie Engineering `Sherman' StrongARM
1110-based SBC, used primarily in assistance products for the
visually impaired. The company is now Freedom Scientific, with
a website at <http://www.freedomscientific.com/index.html>. The
Sherman product, however, appears to have been discontinued.
CONFIG_SA1100_YOPY
Say Y here to support the Yopy PDA. Product information at
<http://www.yopy.com/>. See Documentation/arm/SA110/Yopy
for more.
CONFIG_SA1100_CERF_CPLD
Say Y here to support the Linux CerfPDA development kit from
Intrinsyc. This is a StrongARM-1110-based reference platform for
designing custom PDAs. Product info is at
<http://www.intrinsyc.com/products/referencedesigns/cerfpda.asp>.
CONFIG_SA1100_FREEBIRD
Support the FreeBird board used in Coventive embedded products. See
Documentation/arm/SA1100/Freebird for more.
CONFIG_SA1100_PT_SYSTEM3
Say Y here if you intend to build a kernel suitable to run on
a Pruftechnik Digital Board. For more information see
<http://www.pruftechnik.com>
CONFIG_CPU_ARM926T
This is a variant of the ARM920. It has slightly different
instruction sequences for cache and TLB operations. Curiously,
there is no documentation on it at the ARM corporate website.
Say Y if you want support for the ARM926T processor.
Otherwise, say N.
CONFIG_SA1100_JORNADA720
Say Y here if you want to build a kernel for the HP Jornada 720
handheld computer. See <http://www.hp.com/jornada/products/720>
for details.
CONFIG_SA1100_OMNIMETER
Say Y here if you are using the inhand electronics OmniMeter. See
<http://www.inhandelectronics.com/html/omni1.html> for details.
CONFIG_SA1100_SIMPAD
The SIEMENS webpad SIMpad is based on the StrongARM 1110. There
are two different versions CL4 and SL4. CL4 has 32MB RAM and 16MB
FLASH. The SL4 version got 64 MB RAM and 32 MB FLASH and a
PCMCIA-Slot. The version for the Germany Telecom (DTAG) is the same
like CL4 in additional it has a PCMCIA-Slot. For more information
visit <http://www.my-siemens.com or www.siemens.ch>.
CONFIG_ARCH_CDB89712
This is an evaluation board from Cirrus for the CS89712 processor.
The board includes 2 serial ports, Ethernet, IRDA, and expansion
headers. It comes with 16 MB SDRAM and 8 MB flash ROM.
CONFIG_ARCH_AUTCPU12
Say Y if you intend to run the kernel on the autronix autcpu12
board. This board is based on a Cirrus Logic CS89712.
CONFIG_EP72XX_ROM_BOOT
If you say Y here, your CLPS711x-based kernel will use the bootstrap
mode memory map instead of the normal memory map.
Processors derived from the Cirrus CLPS-711X core support two boot
modes. Normal mode boots from the external memory device at CS0.
Bootstrap mode rearranges parts of the memory map, placing an
internal 128 byte bootstrap ROM at CS0. This option performs the
address map changes required to support booting in this mode.
You almost surely want to say N here.
......@@ -5,31 +5,31 @@
# License. See the file "COPYING" in the main directory of this archive
# for more details.
#
# Copyright (C) 1995-2000 Russell King
# Copyright (C) 1995-2002 Russell King
#
SYSTEM =$(TOPDIR)/vmlinux
ifeq ($(CONFIG_CPU_26),y)
ZTEXTADDR = 0x02080000
ZRELADDR = 0x02080000
PARAMS_PHYS = 0x0207c000
INITRD_PHYS = 0x02180000
INITRD_VIRT = 0x02180000
endif
ifeq ($(CONFIG_ARCH_RPC),y)
ZTEXTADDR = 0x10008000
ZRELADDR = 0x10008000
PARAMS_PHYS = 0x10000100
INITRD_PHYS = 0x18000000
INITRD_VIRT = 0xc8000000
endif
ifeq ($(CONFIG_ARCH_CLPS7500),y)
ZTEXTADDR = 0x10008000
ZRELADDR = 0x10008000
endif
ifeq ($(CONFIG_ARCH_EBSA110),y)
ZTEXTADDR = 0x00008000
ZRELADDR = 0x00008000
PARAMS_PHYS = 0x00000400
INITRD_PHYS = 0x00800000
INITRD_VIRT = 0xc0800000
......@@ -41,41 +41,34 @@ ZRELADDR = 0x08008000
endif
ifeq ($(CONFIG_FOOTBRIDGE),y)
ZTEXTADDR = 0x00008000
ZRELADDR = 0x00008000
PARAMS_PHYS = 0x00000100
INITRD_PHYS = 0x00800000
INITRD_VIRT = 0xc0800000
endif
ifeq ($(CONFIG_ARCH_INTEGRATOR),y)
ZTEXTADDR = 0x00008000
ZRELADDR = 0x00008000
PARAMS_PHYS = 0x00000100
INITRD_PHYS = 0x00800000
INITRD_VIRT = 0xc0800000
endif
ifeq ($(CONFIG_ARCH_CAMELOT),y)
ZTEXTADDR = 0x00008000
ZRELADDR = 0x00008000
endif
ifeq ($(CONFIG_ARCH_NEXUSPCI),y)
ZTEXTADDR = 0x40008000
ZRELADDR = 0x40008000
endif
ifeq ($(CONFIG_ARCH_L7200),y)
# RAM based kernel
#ZTEXTADDR = 0xf0400000
#ZRELADDR = 0xf0008000
# FLASH based kernel
ZTEXTADDR = 0x00010000
ZRELADDR = 0xf0008000
ZBSSADDR = 0xf03e0000
endif
# The standard locations for stuff on CLPS711x type processors
ifeq ($(CONFIG_ARCH_CLPS711X),y)
ZTEXTADDR = 0xc0028000
ZRELADDR = 0xc0028000
PARAMS_PHYS = 0xc0000100
endif
......@@ -90,60 +83,40 @@ INITRD_VIRT = 0xc0300000
endif
ifeq ($(CONFIG_ARCH_SA1100),y)
ZTEXTADDR = 0xc0008000
ZRELADDR = 0xc0008000
ifeq ($(CONFIG_SA1100_VICTOR),y)
ZTEXTADDR = 0x00002000
ZBSSADDR = 0xc0200000
endif
ifeq ($(CONFIG_SA1100_SHERMAN),y)
ZTEXTADDR = 0x00050000
ZBSSADDR = 0xc0200000
endif
ifeq ($(CONFIG_SA1100_GRAPHICSCLIENT),y)
ZTEXTADDR = 0xC0200000
endif
ifeq ($(CONFIG_SA1100_GRAPHICSMASTER),y)
ZTEXTADDR = 0xC0400000
endif
ifeq ($(CONFIG_SA1100_ADSBITSY),y)
ZTEXTADDR = 0xC0400000
endif
ifeq ($(CONFIG_SA1100_YOPY),y)
ZTEXTADDR = 0x00080000
ZBSSADDR = 0xc0200000
endif
# No defconfig file to move this into...
#ifeq ($(CONFIG_SA1100_YOPY),y)
# ZTEXTADDR = 0x00080000
# ZBSSADDR = 0xc0200000
#endif
ifeq ($(CONFIG_SA1111),y)
ZRELADDR = 0xc0208000
endif
endif
ifeq ($(CONFIG_ARCH_ANAKIN),y)
ZTEXTADDR = 0x20008000
ZRELADDR = 0x20008000
endif
ifeq ($(CONFIG_ARCH_IQ80310),y)
ZRELADDR = 0xa0008000
# for serial upload
ZTEXTADDR = 0xa1008000
# for direct flash execution
# ZTEXTADDR = 0x00060000
# ZBSSADDR = 0xa1008000
endif
ifeq ($(CONFIG_ARCH_ADIFCC),y)
ZRELADDR = 0xc0008000
ZTEXTADDR = 0xc1000000
endif
#
# If you don't define ZRELADDR above,
# then it defaults to ZTEXTADDR
# We now have a PIC decompressor implementation. Decompressors running
# from RAM should not define ZTEXTADDR. Decompressors running directly
# from ROM or Flash must define ZTEXTADDR (preferably via the config)
#
ifeq ($(ZRELADDR),)
ZRELADDR = $(ZTEXTADDR)
ifeq ($(CONFIG_ZBOOT_ROM),y)
ZTEXTADDR =0x$(CONFIG_ZBOOT_ROM_TEXT)
ZBSSADDR =0x$(CONFIG_ZBOOT_ROM_BSS)
else
ZTEXTADDR =0
ZBSSADDR =ALIGN(4)
endif
export SYSTEM ZTEXTADDR ZBSSADDR ZRELADDR INITRD_PHYS INITRD_VIRT PARAMS_PHYS
......
......@@ -9,7 +9,7 @@
HEAD = head.o
OBJS = misc.o
CFLAGS = $(CPPFLAGS) -O2 -DSTDC_HEADERS $(CFLAGS_BOOT)
CFLAGS = $(CPPFLAGS) -O2 -DSTDC_HEADERS $(CFLAGS_BOOT) -fpic
FONTC = $(TOPDIR)/drivers/video/font_acorn_8x8.c
ZLDFLAGS = -p -X -T vmlinux.lds
......@@ -65,13 +65,7 @@ ifeq ($(CONFIG_CPU_XSCALE),y)
OBJS += head-xscale.o
endif
SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/LOAD_ADDR/$(ZRELADDR)/;
ifneq ($(ZBSSADDR),)
SEDFLAGS += s/BSS_START/$(ZBSSADDR)/
else
SEDFLAGS += s/BSS_START/ALIGN(4)/
endif
SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/LOAD_ADDR/$(ZRELADDR)/;s/BSS_START/$(ZBSSADDR)/
LIBGCC := $(shell $(CC) $(CFLAGS) --print-libgcc-file-name)
......
......@@ -13,7 +13,7 @@
/* This branch is taken if the CPU memory width matches the
actual device in use. The default at power on is 16 bits
so we must be prepared for a mismatch. */
.section ".start", #alloc, #execinstr
.section ".start", "ax"
2:
b 1f
.word 0xffff
......
#include <asm/mach-types.h>
#include <asm/arch/excalibur.h>
.section ".start", #alloc, #execinstr
.section ".start", "ax"
mov r7, #MACH_TYPE_CAMELOT
......@@ -13,7 +13,7 @@
* 2 of the License, or (at your option) any later version.
*/
.section ".start", #alloc, #execinstr
.section ".start", "ax"
ftv_start:
mcr p15, 0, r0, c7, c5, 0 @ flush I cache
mrc p15, 0, r0, c1, c0
......
#include <asm/mach-types.h>
.section ".start", #alloc, #execinstr
.section ".start", "ax"
mov r7, #MACH_TYPE_INTEGRATOR
......@@ -13,7 +13,7 @@
#error What am I doing here...
#endif
.section ".start", #alloc, #execinstr
.section ".start", "ax"
__L7200_start:
mov r0, #0x00100000 @ FLASH address of initrd
......
/*
* linux/arch/arm/boot/compressed/head-netwinder.S
*
* Copyright (C) 2000 Russell King
* Copyright (C) 2000-2002 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define K(a,b,c) ((a) << 24 | (b) << 12 | (c))
.section ".start", "ax"
.section ".start", #alloc, #execinstr
/*
* check to see if we are running from the correct address.
* If not, we move ourselves in a two stage process. Firstly,
* we copy the start of the kernel (which includes this code)
* to 0x8000, and then jump to this code to continue with the
* rest (since this code will get overwritten).
*/
adr r2, 1f
ldmdb r2, {r9, r10}
and r3, r2, #0xc000
teq r3, #0x8000 @ correctly located?
beq 2f @ skip this code
bic r3, r2, #0xc000
orr r3, r3, #0x8000
mov r0, r3 @ new address if '1'
mov r4, #64 @ number of bytes to copy
sub r5, r10, r9 @ total number of bytes to copy
b 1f
.word _start
.word __bss_start
1:
.rept 4
ldmia r2!, {r6, r9, r10, r11}
stmia r3!, {r6, r9, r10, r11}
.endr
subs r4, r4, #64
bcs 1b
movs r4, r5 @ remaining length
mov r5, #0 @ no more to copy
movne pc, r0 @ jump back to 1 (in the newly copied
@ code)
mov r7, #5 @ only here to fix NeTTroms which dont
mov r8, #2 << 24 @ scheduled for removal in 2.5.xx
orr r8, r8, #5 << 12
2:
mov r7, #5
mov r8, #0
......@@ -11,7 +11,7 @@
#include <linux/linkage.h>
#include <asm/mach-types.h>
.section ".start", #alloc, #execinstr
.section ".start", "ax"
__SA1100_start:
......
......@@ -16,7 +16,7 @@
#include <asm/assembler.h>
.section ".start", #alloc, #execinstr
.section ".start", "ax"
b __beginning
......
......@@ -9,7 +9,7 @@
#include <linux/linkage.h>
#include <asm/mach-types.h>
.section ".start", #alloc, #execinstr
.section ".start", "ax"
__XScale_start:
......
......@@ -132,10 +132,28 @@ not_angel:
*/
.text
1: adr r2, LC0
ldmia r2, {r2, r3, r4, r5, sp}
adr r0, LC0
ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp}
subs r0, r0, r1 @ calculate the delta offset
teq r0, #0 @ if delta is zero, we're
beq not_relocated @ running at the address we
@ were linked at.
add r2, r2, r0 @ different address, so we
add r3, r3, r0 @ need to fix up various
add r5, r5, r0 @ pointers.
add r6, r6, r0
add ip, ip, r0
add sp, sp, r0
1: ldr r1, [r6, #0] @ relocate entries in the GOT
add r1, r1, r0 @ table. This fixes up the
str r1, [r6], #4 @ C references.
cmp r6, ip
blt 1b
mov r0, #0
not_relocated: mov r0, #0
1: str r0, [r2], #4 @ clear bss
str r0, [r2], #4
str r0, [r2], #4
......@@ -149,17 +167,26 @@ not_angel:
mov r1, sp @ malloc space above stack
add r2, sp, #0x10000 @ 64k max
teq r4, r5 @ will we overwrite ourselves?
moveq r5, r2 @ decompress after image
movne r5, r4 @ decompress to final location
/*
* Check to see if we will overwrite ourselves.
* r4 = final kernel address
* r5 = start of this image
* r2 = end of malloc space (and therefore this image)
* We basically want:
* r4 >= r2 -> OK
* r4 + image length <= r5 -> OK
*/
cmp r4, r2
bhs wont_overwrite
add r0, r4, #4096*1024 @ 4MB largest kernel size
cmp r0, r5
bls wont_overwrite
mov r5, r2 @ decompress after malloc space
mov r0, r5
mov r3, r7
bl SYMBOL_NAME(decompress_kernel)
teq r4, r5 @ do we need to relocate
beq call_kernel @ the kernel?
add r0, r0, #127
bic r0, r0, #127 @ align the kernel length
/*
......@@ -184,12 +211,26 @@ not_angel:
bl cache_clean_flush
add pc, r5, r0 @ call relocation code
/*
* We're not in danger of overwriting ourselves. Do this the simple way.
*
* r4 = kernel execution address
* r7 = architecture ID
*/
wont_overwrite: mov r0, r4
mov r3, r7
bl SYMBOL_NAME(decompress_kernel)
b call_kernel
.type LC0, #object
LC0: .word __bss_start
.word _end
.word _load_addr
.word _start
.word user_stack+4096
LC0: .word LC0 @ r1
.word __bss_start @ r2
.word _end @ r3
.word _load_addr @ r4
.word _start @ r5
.word _got_start @ r6
.word _got_end @ r7
.word user_stack+4096 @ r8
.size LC0, . - LC0
/*
......@@ -518,5 +559,5 @@ memdump: mov r12, r0
reloc_end:
.align
.section ".stack"
.section ".stack", "aw"
user_stack: .space 4096
......@@ -35,22 +35,19 @@ SECTIONS
_etext = .;
.data : {
*(.data)
}
_got_start = .;
.got : { *(.got) }
_got_end = .;
.got.plt : { *(.got.plt) }
.data : { *(.data) }
_edata = .;
. = BSS_START;
__bss_start = .;
.bss : {
*(.bss)
}
.bss : { *(.bss) }
_end = .;
.stack : {
*(.stack)
}
.stack (NOLOAD) : { *(.stack) }
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
......
......@@ -433,6 +433,12 @@ else
define_bool CONFIG_FIQ n
fi
# Compressed boot loader in ROM. Yes, we really want to ask about
# TEXT and BSS so we preserve their values in the config files.
bool 'Compressed boot loader in ROM/flash' CONFIG_ZBOOT_ROM
hex 'Compressed ROM boot loader base address' CONFIG_ZBOOT_ROM_TEXT 0
hex 'Compressed ROM boot loader BSS address' CONFIG_ZBOOT_ROM_BSS 0
if [ "$CONFIG_ARCH_SA1100" = "y" -o \
"$CONFIG_ARCH_INTEGRATOR" = "y" ]; then
dep_bool 'Support CPU clock change (EXPERIMENTAL)' CONFIG_CPU_FREQ $CONFIG_EXPERIMENTAL
......
......@@ -139,6 +139,9 @@ CONFIG_ARM_THUMB=y
#
# General setup
#
CONFIG_ZBOOT_ROM=y
CONFIG_ZBOOT_ROM_TEXT=0x00060000
CONFIG_ZBOOT_ROM_BSS=0xa1008000
CONFIG_PCI=y
# CONFIG_ISA is not set
# CONFIG_ISA_DMA is not set
......
......@@ -23,6 +23,9 @@ CONFIG_CPU_32=y
# CONFIG_CPU_26 is not set
CONFIG_CPU_32v4=y
CONFIG_CPU_ARM720=y
CONFIG_ZBOOT_ROM=y
CONFIG_ZBOOT_ROM_TEXT=0x00010000
CONFIG_ZBOOT_ROM_BSS=0xf03e0000
# CONFIG_PCI is not set
# CONFIG_ISA is not set
# CONFIG_ISA_DMA is not set
......
......@@ -47,6 +47,9 @@ CONFIG_MODULES=y
#
# General setup
#
CONFIG_ZBOOT_ROM=y
CONFIG_ZBOOT_ROM_TEXT=0x00050000
CONFIG_ZBOOT_ROM_BSS=0xc0200000
# CONFIG_NET is not set
# CONFIG_SYSVIPC is not set
# CONFIG_BSD_PROCESS_ACCT is not set
......
......@@ -46,6 +46,9 @@ CONFIG_MODULES=y
#
# General setup
#
CONFIG_ZBOOT_ROM=y
CONFIG_ZBOOT_ROM_TEXT=0x00002000
CONFIG_ZBOOT_ROM_BSS=0xc0200000
# CONFIG_NET is not set
# CONFIG_SYSVIPC is not set
# CONFIG_BSD_PROCESS_ACCT is not set
......
......@@ -17,6 +17,7 @@
#include <linux/mman.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <asm/dma.h>
......
......@@ -756,7 +756,6 @@ __irq_svc: sub sp, sp, #S_FRAME_SIZE
#ifdef CONFIG_PREEMPT
ldr r0, [r8, #TI_FLAGS] @ get flags
tst r0, #_TIF_NEED_RESCHED
ldrne r6, .LCirq_stat
blne svc_preempt
preempt_return:
ldr r0, [r8, #TI_PREEMPT] @ read preempt value
......@@ -770,20 +769,20 @@ preempt_return:
#ifdef CONFIG_PREEMPT
svc_preempt: teq r9, #0 @ was preempt count = 0
ldreq r6, .LCirq_stat
movne pc, lr @ no
ldr r0, [r6, #4] @ local_irq_count
ldr r1, [r6, #8] @ local_bh_count
adds r0, r0, r1
movne pc, lr
ldr r1, [r8, #TI_TASK]
set_cpsr_c r2, #MODE_SVC @ enable IRQs
str r0, [r1, #0] @ current->state = TASK_RUNNING
1: bl SYMBOL_NAME(schedule)
mov r7, #PREEMPT_ACTIVE
str r7, [r8, #TI_PREEMPT] @ set PREEMPT_ACTIVE
1: set_cpsr_c r2, #MODE_SVC @ enable IRQs
bl SYMBOL_NAME(schedule)
set_cpsr_c r0, #PSR_I_BIT | MODE_SVC @ disable IRQs
ldr r0, [r8, #TI_FLAGS]
ldr r0, [r8, #TI_FLAGS] @ get new tasks TI_FLAGS
tst r0, #_TIF_NEED_RESCHED
beq preempt_return
set_cpsr_c r0, #MODE_SVC @ enable IRQs
beq preempt_return @ go again
b 1b
#endif
......
......@@ -76,6 +76,9 @@ __do_notify_resume:
* This is how we return from a fork.
*/
ENTRY(ret_from_fork)
#ifdef CONFIG_PREEMPT
bl schedule_tail
#endif
get_thread_info tsk
ldr ip, [tsk, #TI_FLAGS] @ check for syscall tracing
mov why, #1
......
......@@ -29,6 +29,7 @@
#include <linux/smp.h>
#include <linux/init.h>
#include <linux/seq_file.h>
#include <linux/errno.h>
#include <asm/irq.h>
#include <asm/system.h>
......
......@@ -73,7 +73,7 @@ void (*pm_power_off)(void);
* This is our default idle handler. We need to disable
* interrupts here to ensure we don't miss a wakeup call.
*/
static void default_idle(void)
void default_idle(void)
{
__cli();
if (!need_resched() && !hlt_counter)
......
......@@ -13,6 +13,7 @@
*/
#include <linux/config.h>
#include <linux/sched.h>
#include <linux/errno.h>
#include <asm/semaphore.h>
......
......@@ -26,6 +26,7 @@
#include <asm/procinfo.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/tlbflush.h>
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
......@@ -255,7 +256,7 @@ static void __init setup_processor(void)
cpu_user = *list->user;
#endif
printk("Processor: %s %s revision %d\n",
printk("CPU: %s %s revision %d\n",
proc_info.manufacturer, proc_info.cpu_name,
(int)processor_id & 15);
......
......@@ -628,14 +628,12 @@ int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall)
case SIGSTOP: {
struct signal_struct *sig;
current->state = TASK_STOPPED;
current->exit_code = signr;
sig = current->parent->sig;
preempt_disable();
current->state = TASK_STOPPED;
if (sig && !(sig->action[SIGCHLD-1].sa.sa_flags & SA_NOCLDSTOP))
notify_parent(current, SIGCHLD);
schedule();
preempt_enable();
continue;
}
......
......@@ -25,6 +25,7 @@
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/timex.h>
#include <linux/errno.h>
#include <asm/hardware.h>
#include <asm/io.h>
......
......@@ -26,11 +26,10 @@
#include <asm/hardware.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/sizes.h>
#include <asm/mach/map.h>
#define MB1 1048576 /* one megabyte == size of an MMU section */
extern void clps711x_map_io(void);
/*
......@@ -56,12 +55,12 @@ static struct map_desc edb7211_io_desc[] __initdata = {
/* virtual, physical, length, domain, r, w, c, b */
/* memory-mapped extra keyboard row and CS8900A Ethernet chip */
{ EP7211_VIRT_EXTKBD, EP7211_PHYS_EXTKBD, MB1, DOMAIN_IO, 0, 1, 0, 0 },
{ EP7211_VIRT_CS8900A, EP7211_PHYS_CS8900A, MB1, DOMAIN_IO, 0, 1, 0, 0 },
{ EP7211_VIRT_EXTKBD, EP7211_PHYS_EXTKBD, SZ_1M, DOMAIN_IO, 0, 1, 0, 0 },
{ EP7211_VIRT_CS8900A, EP7211_PHYS_CS8900A, SZ_1M, DOMAIN_IO, 0, 1, 0, 0 },
/* flash banks */
{ EP7211_VIRT_FLASH1, EP7211_PHYS_FLASH1, MB1 * 8, DOMAIN_KERNEL, 0, 1, 0, 0 },
{ EP7211_VIRT_FLASH2, EP7211_PHYS_FLASH2, MB1 * 8, DOMAIN_KERNEL, 0, 1, 0, 0 },
{ EP7211_VIRT_FLASH1, EP7211_PHYS_FLASH1, SZ_8M, DOMAIN_KERNEL, 0, 1, 0, 0 },
{ EP7211_VIRT_FLASH2, EP7211_PHYS_FLASH2, SZ_8M, DOMAIN_KERNEL, 0, 1, 0, 0 },
LAST_DESC
};
......
......@@ -44,7 +44,7 @@ static pte_t *minicache_pte;
unsigned long map_page_minicache(unsigned long virt)
{
set_pte(minicache_pte, mk_pte_phys(__pa(virt), minicache_pgprot));
flush_kern_tlb_page(minicache_address);
flush_tlb_kernel_page(minicache_address);
return minicache_address;
}
......
......@@ -723,7 +723,6 @@ ENTRY(xscale_processor_functions)
.word cpu_xscale_set_pgd
.word cpu_xscale_set_pmd
.word cpu_xscale_set_pte
.size xscale_processor_functions, . - xscale_processor_functions
.type cpu_80200_info, #object
......@@ -779,6 +778,5 @@ __pxa250_proc_info:
.long xscale_processor_functions
.long v4wbi_tlb_fns
.long v5te_mc_user_fns
.size __cotulla_proc_info, . - __cotulla_proc_info
.size __pxa250_proc_info, . - __pxa250_proc_info
......@@ -53,6 +53,7 @@ ENTRY(v3_flush_user_tlb_range)
act_mm r3 @ get current->active_mm
teq r2, r3 @ == mm ?
movne pc, lr @ no, we dont do anything
ENTRY(v3_flush_kern_tlb_range)
bic r0, r0, #0x0ff
bic r0, r0, #0xf00
1: mcr p15, 0, r0, c6, c0, 0 @ invalidate TLB entry
......@@ -87,5 +88,6 @@ ENTRY(v3_tlb_fns)
.long v3_flush_user_tlb_mm
.long v3_flush_user_tlb_range
.long v3_flush_user_tlb_page
.long v3_flush_kern_tlb_range
.long v3_flush_kern_tlb_page
.size v3_tlb_fns, . - v3_tlb_fns
......@@ -42,7 +42,7 @@ ENTRY(v4_flush_kern_tlb_all)
/*
* v4_flush_user_tlb_range(start, end, mm)
*
* Invalidate a range of TLB entries in the specified address space.
* Invalidate a range of TLB entries in the specified user address space.
*
* - start - range start address
* - end - range end address
......@@ -85,6 +85,27 @@ ENTRY(v4_flush_user_tlb_page)
mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
mov pc, lr
/*
* v4_flush_kerm_tlb_range(start, end)
*
* Invalidate a range of TLB entries in the specified kernel
* address range.
*
* - start - virtual address (may not be aligned)
* - end - virtual address (may not be aligned)
*/
.align 5
ENTRY(v4_flush_kern_tlb_range)
bic r0, r0, #0x0ff
bic r0, r0, #0xf00
1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
add r0, r0, #PAGE_SZ
cmp r0, r1
blo 1b
mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
mov pc, lr
/*
* v4_flush_kern_tlb_page(kaddr)
*
......@@ -106,5 +127,6 @@ ENTRY(v4_tlb_fns)
.long v4_flush_user_tlb_mm
.long v4_flush_user_tlb_range
.long v4_flush_user_tlb_page
.long v4_flush_kern_tlb_range
.long v4_flush_kern_tlb_page
.size v4_tlb_fns, . - v4_tlb_fns
......@@ -88,7 +88,41 @@ ENTRY(v4wb_flush_user_tlb_page)
mcr p15, 0, r3, c7, c10, 4 @ drain WB
tst r2, #VM_EXEC
mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
mov pc, lr
/*
* v4_flush_kerm_tlb_range(start, end)
*
* Invalidate a range of TLB entries in the specified kernel
* address range.
*
* - start - virtual address (may not be aligned)
* - end - virtual address (may not be aligned)
*/
ENTRY(v4wb_flush_kern_tlb_range)
mov r3, #0
mcr p15, 0, r3, c7, c10, 4 @ drain WB
bic r0, r0, #0x0ff
bic r0, r0, #0xf00
mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
add r0, r0, #PAGE_SZ
cmp r0, r1
blo 1b
mov pc, lr
/*
* v4_flush_kern_tlb_page(kaddr)
*
* Invalidate the TLB entry for the specified page. The address
* will be in the kernels virtual memory space. Current uses
* only require the D-TLB to be invalidated.
*
* - kaddr - Kernel virtual memory address
*/
ENTRY(v4wb_flush_kern_tlb_page)
mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
mov pc, lr
......@@ -107,14 +141,17 @@ ENTRY(v4wb_flush_kern_tlb_page)
*/
.align 5
ENTRY(v4wbi_flush_user_tlb_range)
vma_vm_mm ip, r2
act_mm r3 @ get current->active_mm
teq r2, r3 @ == mm ?
eors r3, ip, r3 @ == mm ?
movne pc, lr @ no, we dont do anything
mov r3, #0
mcr p15, 0, r3, c7, c10, 4 @ drain WB
vma_vm_flags r2, r2
bic r0, r0, #0x0ff
bic r0, r0, #0xf00
1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
1: tst r2, #VM_EXEC
mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
add r0, r0, #PAGE_SZ
cmp r0, r1
......@@ -140,7 +177,23 @@ ENTRY(v4wbi_flush_user_tlb_page)
mcr p15, 0, r3, c7, c10, 4 @ drain WB
tst r2, #VM_EXEC
mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
mov pc, lr
ENTRY(v4wbi_flush_kern_tlb_range)
mov r3, #0
mcr p15, 0, r3, c7, c10, 4 @ drain WB
bic r0, r0, #0x0ff
bic r0, r0, #0xf00
1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
add r0, r0, #PAGE_SZ
cmp r0, r1
blo 1b
mov pc, lr
ENTRY(v4wbi_flush_kern_tlb_page)
mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
mov pc, lr
......@@ -152,6 +205,7 @@ ENTRY(v4wb_tlb_fns)
.long v4wb_flush_user_tlb_mm
.long v4wb_flush_user_tlb_range
.long v4wb_flush_user_tlb_page
.long v4wb_flush_kern_tlb_range
.long v4wb_flush_kern_tlb_page
.size v4wb_tlb_fns, . - v4wb_tlb_fns
......@@ -161,5 +215,6 @@ ENTRY(v4wbi_tlb_fns)
.long v4wbi_flush_user_tlb_mm
.long v4wbi_flush_user_tlb_range
.long v4wbi_flush_user_tlb_page
.long v4wbi_flush_kern_tlb_range
.long v4wbi_flush_kern_tlb_page
.size v4wbi_tlb_fns, . - v4wbi_tlb_fns
......@@ -28,6 +28,7 @@
#include <linux/config.h>
/* XXX */
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/signal.h>
......
......@@ -71,6 +71,7 @@ sa1100_cs-objs-$(CONFIG_SA1100_PT_SYSTEM3) += sa1100_system3.o sa1111_generic.o
sa1100_cs-objs-$(CONFIG_SA1100_SHANNON) += sa1100_shannon.o
sa1100_cs-objs-$(CONFIG_SA1100_SIMPAD) += sa1100_simpad.o
sa1100_cs-objs-$(CONFIG_SA1100_STORK) += sa1100_stork.o
sa1100_cs-objs-$(CONFIG_SA1100_TRIZEPS) += sa1100_trizeps.o
sa1100_cs-objs-$(CONFIG_SA1100_XP860) += sa1100_xp860.o sa1111_generic.o
sa1100_cs-objs-$(CONFIG_SA1100_YOPY) += sa1100_yopy.o
......
......@@ -237,6 +237,9 @@ extern void pcmcia_stork_exit(void);
extern int pcmcia_system3_init(void);
extern void pcmcia_system3_exit(void);
extern int pcmcia_trizeps_init(void);
extern void pcmcia_trizeps_exit(void);
extern int pcmcia_xp860_init(void);
extern void pcmcia_xp860_exit(void);
......
......@@ -1180,6 +1180,9 @@ static int __init sa1100_pcmcia_init(void)
#ifdef CONFIG_SA1100_STORK
pcmcia_stork_init();
#endif
#ifdef CONFIG_SA1100_TRIZEPS
pcmcia_trizeps_init();
#endif
#ifdef CONFIG_SA1100_XP860
pcmcia_xp860_init();
#endif
......
/*
* drivers/pcmcia/sa1100_trizeps.c
*
* PCMCIA implementation routines for Trizeps
*
* Authors:
* Andreas Hofer <ho@dsa-ac.de>,
* Peter Lueg <pl@dsa-ac.de>,
* Guennadi Liakhovetski <gl@dsa-ac.de>
*
*/
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <asm/hardware.h> // included trizeps.h
#include <asm/system.h>
#include <asm/irq.h>
#include "sa1100_generic.h"
#define NUMBER_OF_TRIZEPS_PCMCIA_SLOTS 1
/**
*
*
******************************************************/
static int trizeps_pcmcia_init(struct pcmcia_init *init)
{
int res;
/* Enable CF bus: */
TRIZEPS_BCR_clear(TRIZEPS_BCR1, TRIZEPS_nPCM_ENA_REG);
/* All those are inputs */
GPDR &= ~((GPIO_GPIO(TRIZEPS_GPIO_PCMCIA_CD0))
| (GPIO_GPIO(TRIZEPS_GPIO_PCMCIA_IRQ0)));
/* Set transition detect */
// set_irq_type(SA1100_GPIO_TO_IRQ(GPIO_TRIZEPS_PCMCIA_CD0), IRQT_BOTHEDGE);
set_irq_type(TRIZEPS_IRQ_PCMCIA_IRQ0, IRQT_FALLING);
/* Register SOCKET interrupts */
/* WHY? */
set_irq_type(TRIZEPS_IRQ_PCMCIA_CD0, IRQT_NOEDGE);
res = request_irq( TRIZEPS_IRQ_PCMCIA_CD0, init->handler, SA_INTERRUPT, "PCMCIA_CD0", NULL );
if( res < 0 ) goto irq_err;
//MECR = 0x00060006; // Initialised on trizeps init
// return=sa1100_pcmcia_socket_count (sa1100_generic.c)
// -> number of PCMCIA Slots
// Slot 0 -> Trizeps PCMCIA
// Slot 1 -> Trizeps ISA-Bus
return NUMBER_OF_TRIZEPS_PCMCIA_SLOTS;
irq_err:
printk( KERN_ERR __FUNCTION__ ": PCMCIA Request for IRQ %u failed\n", TRIZEPS_IRQ_PCMCIA_CD0 );
return -1;
}
/**
*
*
******************************************************/
static int trizeps_pcmcia_shutdown(void)
{
printk(">>>>>PCMCIA TRIZEPS shutdown\n");
/* disable IRQs */
free_irq(TRIZEPS_IRQ_PCMCIA_CD0, NULL );
/* Disable CF bus: */
TRIZEPS_BCR_set(TRIZEPS_BCR1, TRIZEPS_nPCM_ENA_REG);
return 0;
}
/**
*
******************************************************/
static int trizeps_pcmcia_socket_state(struct pcmcia_state_array
*state_array){
unsigned long levels;
if (state_array->size < NUMBER_OF_TRIZEPS_PCMCIA_SLOTS) return -1;
memset(state_array->state, 0,
(state_array->size)*sizeof(struct pcmcia_state));
levels = GPLR;
state_array->state[0].detect = ((levels & GPIO_GPIO(TRIZEPS_GPIO_PCMCIA_CD0)) == 0) ? 1 : 0;
state_array->state[0].ready = ((levels & GPIO_GPIO(TRIZEPS_GPIO_PCMCIA_IRQ0)) != 0) ? 1 : 0;
state_array->state[0].bvd1 = ((TRIZEPS_BCR1 & TRIZEPS_PCM_BVD1) !=0 ) ? 1 : 0;
state_array->state[0].bvd2 = ((TRIZEPS_BCR1 & TRIZEPS_PCM_BVD2) != 0) ? 1 : 0;
state_array->state[0].wrprot = 0; // not write protected
state_array->state[0].vs_3v = ((TRIZEPS_BCR1 & TRIZEPS_nPCM_VS1) == 0) ? 1 : 0; //VS1=0 -> vs_3v=1
state_array->state[0].vs_Xv = ((TRIZEPS_BCR1 & TRIZEPS_nPCM_VS2) == 0) ? 1 : 0; //VS2=0 -> vs_Xv=1
return 1; // success
}
/**
*
*
******************************************************/
static int trizeps_pcmcia_get_irq_info(struct pcmcia_irq_info *info){
switch (info->sock) {
case 0:
info->irq=TRIZEPS_IRQ_PCMCIA_IRQ0;
break;
case 1:
// MFTB2 use only one Slot
default:
return -1;
}
return 0;
}
/**
*
*
******************************************************/
static int trizeps_pcmcia_configure_socket(const struct pcmcia_configure *configure)
{
unsigned long flags;
if(configure->sock>1) return -1;
local_irq_save(flags);
switch (configure->vcc) {
case 0:
printk(">>> PCMCIA Power off\n");
TRIZEPS_BCR_clear(TRIZEPS_BCR1, TRIZEPS_PCM_V3_EN_REG);
TRIZEPS_BCR_clear(TRIZEPS_BCR1, TRIZEPS_PCM_V5_EN_REG);
break;
case 33:
// 3.3V Power on
TRIZEPS_BCR_clear(TRIZEPS_BCR1, TRIZEPS_PCM_V3_EN_REG);
TRIZEPS_BCR_set(TRIZEPS_BCR1, TRIZEPS_PCM_V5_EN_REG);
break;
case 50:
// 5.0V Power on
TRIZEPS_BCR_set(TRIZEPS_BCR1, TRIZEPS_PCM_V3_EN_REG);
TRIZEPS_BCR_clear(TRIZEPS_BCR1, TRIZEPS_PCM_V5_EN_REG);
break;
default:
printk(KERN_ERR "%s(): unrecognized Vcc %u\n", __FUNCTION__,
configure->vcc);
local_irq_restore(flags);
return -1;
}
if (configure->reset)
TRIZEPS_BCR_set(TRIZEPS_BCR1, TRIZEPS_nPCM_RESET_DISABLE); // Reset
else
TRIZEPS_BCR_clear(TRIZEPS_BCR1, TRIZEPS_nPCM_RESET_DISABLE); // no Reset
/*
printk(" vcc=%u vpp=%u -->reset=%i\n",
configure->vcc,
configure->vpp,
((BCR_read(1) & nPCM_RESET_DISABLE)? 1:0));
*/
local_irq_restore(flags);
if (configure->irq) {
enable_irq(TRIZEPS_IRQ_PCMCIA_CD0);
enable_irq(TRIZEPS_IRQ_PCMCIA_IRQ0);
} else {
disable_irq(TRIZEPS_IRQ_PCMCIA_IRQ0);
disable_irq(TRIZEPS_IRQ_PCMCIA_CD0);
}
return 0;
}
static int trizeps_pcmcia_socket_init(int sock)
{
return 0;
}
static int trizeps_pcmcia_socket_suspend(int sock)
{
return 0;
}
/**
* low-level PCMCIA interface
*
******************************************************/
struct pcmcia_low_level trizeps_pcmcia_ops = {
init: trizeps_pcmcia_init,
shutdown: trizeps_pcmcia_shutdown,
socket_state: trizeps_pcmcia_socket_state,
get_irq_info: trizeps_pcmcia_get_irq_info,
configure_socket: trizeps_pcmcia_configure_socket,
socket_init: trizeps_pcmcia_socket_init,
socket_suspend: trizeps_pcmcia_socket_suspend,
};
int __init pcmcia_trizeps_init(void)
{
if (machine_is_trizeps()) {
return sa1100_register_pcmcia(&trizeps_pcmcia_ops);
}
return -ENODEV;
}
void __exit pcmcia_trizeps_exit(void)
{
sa1100_unregister_pcmcia(&trizeps_pcmcia_ops);
}
......@@ -180,7 +180,7 @@ anakinfb_init(void)
{
memset(&fb_info, 0, sizeof(struct fb_info));
strcpy(fb_info.modename, "AnakinFB");
fb_info.node = -1;
fb_info.node = NODEV;
fb_info.flags = FBINFO_FLAG_DEFAULT;
fb_info.fbops = &anakinfb_ops;
fb_info.disp = &display;
......@@ -192,7 +192,12 @@ anakinfb_init(void)
memset(&display, 0, sizeof(struct display));
anakinfb_get_var(&display.var, 0, &fb_info);
display.screen_base = ioremap(VGA_START, VGA_SIZE);
if (!(request_mem_region(VGA_START, VGA_SIZE, "vga")))
return -ENOMEM;
if (!(display.screen_base = ioremap(VGA_START, VGA_SIZE))) {
release_mem_region(VGA_START, VGA_SIZE);
return -EIO;
}
display.visual = FB_VISUAL_TRUECOLOR;
display.type = FB_TYPE_PACKED_PIXELS;
display.type_aux = 0;
......@@ -209,8 +214,11 @@ anakinfb_init(void)
display.dispsw = &fbcon_dummy;
#endif
if (register_framebuffer(&fb_info) < 0)
if (register_framebuffer(&fb_info) < 0) {
iounmap(display.screen_base);
release_mem_region(VGA_START, VGA_SIZE);
return -EINVAL;
}
MOD_INC_USE_COUNT;
return 0;
......
/*
* linux/include/asm-arm/cacheflush.h
*
* Copyright (C) 2000-2002 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _ASMARM_CACHEFLUSH_H
#define _ASMARM_CACHEFLUSH_H
#include <asm/proc/cache.h>
#endif
......@@ -272,7 +272,7 @@ extern void consistent_sync(void *vaddr, size_t size, int rw);
/*
* Change "struct page" to physical address.
*/
#ifdef CONFIG_DISCONTIG
#ifdef CONFIG_DISCONTIGMEM
#define page_to_phys(page) \
((((page) - page_zone(page)->zone_mem_map) << PAGE_SHIFT) \
+ page_zone(page)->zone_start_paddr)
......
......@@ -10,11 +10,10 @@
#ifndef _ASMARM_PGALLOC_H
#define _ASMARM_PGALLOC_H
#include <linux/config.h>
#include <asm/processor.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/proc/cache.h>
#include <asm/proc/pgalloc.h>
/*
......
......@@ -27,66 +27,3 @@
/* DAG: ARM3 will flush cache on MEMC updates anyway? so don't bother */
#define clean_cache_area(_start,_size) do { } while (0)
/*
* TLB flushing:
*
* - flush_tlb_all() flushes all processes TLBs
* - flush_tlb_mm(mm) flushes the specified mm context TLB's
* - flush_tlb_page(vma, vmaddr) flushes one page
* - flush_tlb_range(vma, start, end) flushes a range of pages
*/
#define flush_tlb_all() memc_update_all()
#define flush_tlb_mm(mm) memc_update_mm(mm)
#define flush_tlb_range(vma,start,end) \
do { memc_update_mm(vma->vm_mm); (void)(start); (void)(end); } while (0)
#define flush_tlb_page(vma, vmaddr) do { } while (0)
/*
* The following handle the weird MEMC chip
*/
static inline void memc_update_all(void)
{
struct task_struct *p;
cpu_memc_update_all(init_mm.pgd);
for_each_task(p) {
if (!p->mm)
continue;
cpu_memc_update_all(p->mm->pgd);
}
processor._set_pgd(current->active_mm->pgd);
}
static inline void memc_update_mm(struct mm_struct *mm)
{
cpu_memc_update_all(mm->pgd);
if (mm == current->active_mm)
processor._set_pgd(mm->pgd);
}
static inline void
memc_clear(struct mm_struct *mm, struct page *page)
{
cpu_memc_update_entry(mm->pgd, (unsigned long) page_address(page), 0);
if (mm == current->active_mm)
processor._set_pgd(mm->pgd);
}
static inline void
memc_update_addr(struct mm_struct *mm, pte_t pte, unsigned long vaddr)
{
cpu_memc_update_entry(mm->pgd, pte_val(pte), vaddr);
if (mm == current->active_mm)
processor._set_pgd(mm->pgd);
}
static inline void
update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
{
struct mm_struct *mm = vma->vm_mm;
memc_update_addr(mm, pte, addr);
}
/*
* TLB flushing:
*
* - flush_tlb_all() flushes all processes TLBs
* - flush_tlb_mm(mm) flushes the specified mm context TLB's
* - flush_tlb_page(vma, vmaddr) flushes one page
* - flush_tlb_range(vma, start, end) flushes a range of pages
*/
#define flush_tlb_all() memc_update_all()
#define flush_tlb_mm(mm) memc_update_mm(mm)
#define flush_tlb_range(vma,start,end) \
do { memc_update_mm(vma->vm_mm); (void)(start); (void)(end); } while (0)
#define flush_tlb_page(vma, vmaddr) do { } while (0)
/*
* The following handle the weird MEMC chip
*/
static inline void memc_update_all(void)
{
struct task_struct *p;
cpu_memc_update_all(init_mm.pgd);
for_each_task(p) {
if (!p->mm)
continue;
cpu_memc_update_all(p->mm->pgd);
}
processor._set_pgd(current->active_mm->pgd);
}
static inline void memc_update_mm(struct mm_struct *mm)
{
cpu_memc_update_all(mm->pgd);
if (mm == current->active_mm)
processor._set_pgd(mm->pgd);
}
static inline void
memc_clear(struct mm_struct *mm, struct page *page)
{
cpu_memc_update_entry(mm->pgd, (unsigned long) page_address(page), 0);
if (mm == current->active_mm)
processor._set_pgd(mm->pgd);
}
static inline void
memc_update_addr(struct mm_struct *mm, pte_t pte, unsigned long vaddr)
{
cpu_memc_update_entry(mm->pgd, pte_val(pte), vaddr);
if (mm == current->active_mm)
processor._set_pgd(mm->pgd);
}
static inline void
update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
{
struct mm_struct *mm = vma->vm_mm;
memc_update_addr(mm, pte, addr);
}
......@@ -132,108 +132,3 @@ static inline void flush_dcache_page(struct page *page)
do { \
cpu_icache_invalidate_range((_s), (_e)); \
} while (0)
/*
* TLB Management
* ==============
*
* The arch/arm/mm/tlb-*.S files implement these methods.
*
* The TLB specific code is expected to perform whatever tests it
* needs to determine if it should invalidate the TLB for each
* call. Start addresses are inclusive and end addresses are
* exclusive; it is safe to round these addresses down.
*
* flush_tlb_all()
*
* Invalidate the entire TLB.
*
* flush_tlb_mm(mm)
*
* Invalidate all TLB entries in a particular address
* space.
* - mm - mm_struct describing address space
*
* flush_tlb_range(mm,start,end)
*
* Invalidate a range of TLB entries in the specified
* address space.
* - mm - mm_struct describing address space
* - start - start address (may not be aligned)
* - end - end address (exclusive, may not be aligned)
*
* flush_tlb_page(vaddr,vma)
*
* Invalidate the specified page in the specified address range.
* - vaddr - virtual address (may not be aligned)
* - vma - vma_struct describing address range
*
* flush_kern_tlb_page(kaddr)
*
* Invalidate the TLB entry for the specified page. The address
* will be in the kernels virtual memory space. Current uses
* only require the D-TLB to be invalidated.
* - kaddr - Kernel virtual memory address
*/
struct cpu_tlb_fns {
void (*flush_kern_all)(void);
void (*flush_user_mm)(struct mm_struct *);
void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *);
void (*flush_user_page)(unsigned long, struct vm_area_struct *);
void (*flush_kern_page)(unsigned long);
};
/*
* Convert calls to our calling convention.
*/
#define flush_tlb_all() __cpu_flush_kern_tlb_all()
#define flush_tlb_mm(mm) __cpu_flush_user_tlb_mm(mm)
#define flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma)
#define flush_tlb_page(vma,vaddr) __cpu_flush_user_tlb_page(vaddr,vma)
#define flush_kern_tlb_page(kaddr) __cpu_flush_kern_tlb_page(kaddr)
/*
* Now select the calling method
*/
#ifdef MULTI_TLB
extern struct cpu_tlb_fns cpu_tlb;
#define __cpu_flush_kern_tlb_all cpu_tlb.flush_kern_all
#define __cpu_flush_user_tlb_mm cpu_tlb.flush_user_mm
#define __cpu_flush_user_tlb_range cpu_tlb.flush_user_range
#define __cpu_flush_user_tlb_page cpu_tlb.flush_user_page
#define __cpu_flush_kern_tlb_page cpu_tlb.flush_kern_page
#else
#define __cpu_flush_kern_tlb_all __glue(_TLB,_flush_kern_tlb_all)
#define __cpu_flush_user_tlb_mm __glue(_TLB,_flush_user_tlb_mm)
#define __cpu_flush_user_tlb_range __glue(_TLB,_flush_user_tlb_range)
#define __cpu_flush_user_tlb_page __glue(_TLB,_flush_user_tlb_page)
#define __cpu_flush_kern_tlb_page __glue(_TLB,_flush_kern_tlb_page)
extern void __cpu_flush_kern_tlb_all(void);
extern void __cpu_flush_user_tlb_mm(struct mm_struct *);
extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
extern void __cpu_flush_user_tlb_page(unsigned long, struct vm_area_struct *);
extern void __cpu_flush_kern_tlb_page(unsigned long);
#endif
/*
* if PG_dcache_dirty is set for the page, we need to ensure that any
* cache entries for the kernels virtual memory range are written
* back to the page.
*/
extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte);
/*
* Old ARM MEMC stuff. This supports the reversed mapping handling that
* we have on the older 26-bit machines. We don't have a MEMC chip, so...
*/
#define memc_update_all() do { } while (0)
#define memc_update_mm(mm) do { } while (0)
#define memc_update_addr(mm,pte,log) do { } while (0)
#define memc_clear(mm,physaddr) do { } while (0)
/*
* linux/include/asm-arm/proc-armv/tlbflush.h
*
* Copyright (C) 1999-2002 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* TLB Management
* ==============
*
* The arch/arm/mm/tlb-*.S files implement these methods.
*
* The TLB specific code is expected to perform whatever tests it
* needs to determine if it should invalidate the TLB for each
* call. Start addresses are inclusive and end addresses are
* exclusive; it is safe to round these addresses down.
*
* flush_tlb_all()
*
* Invalidate the entire TLB.
*
* flush_tlb_mm(mm)
*
* Invalidate all TLB entries in a particular address
* space.
* - mm - mm_struct describing address space
*
* flush_tlb_range(mm,start,end)
*
* Invalidate a range of TLB entries in the specified
* address space.
* - mm - mm_struct describing address space
* - start - start address (may not be aligned)
* - end - end address (exclusive, may not be aligned)
*
* flush_tlb_page(vaddr,vma)
*
* Invalidate the specified page in the specified address range.
* - vaddr - virtual address (may not be aligned)
* - vma - vma_struct describing address range
*
* flush_kern_tlb_page(kaddr)
*
* Invalidate the TLB entry for the specified page. The address
* will be in the kernels virtual memory space. Current uses
* only require the D-TLB to be invalidated.
* - kaddr - Kernel virtual memory address
*/
struct cpu_tlb_fns {
void (*flush_kern_all)(void);
void (*flush_user_mm)(struct mm_struct *);
void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *);
void (*flush_user_page)(unsigned long, struct vm_area_struct *);
void (*flush_kern_range)(unsigned long, unsigned long);
void (*flush_kern_page)(unsigned long);
};
/*
* Convert calls to our calling convention.
*/
#define flush_tlb_all() __cpu_flush_kern_tlb_all()
#define flush_tlb_mm(mm) __cpu_flush_user_tlb_mm(mm)
#define flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma)
#define flush_tlb_page(vma,vaddr) __cpu_flush_user_tlb_page(vaddr,vma)
#define flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e)
#define flush_tlb_kernel_page(kaddr) __cpu_flush_kern_tlb_page(kaddr)
/*
* Now select the calling method
*/
#ifdef MULTI_TLB
extern struct cpu_tlb_fns cpu_tlb;
#define __cpu_flush_kern_tlb_all cpu_tlb.flush_kern_all
#define __cpu_flush_user_tlb_mm cpu_tlb.flush_user_mm
#define __cpu_flush_user_tlb_range cpu_tlb.flush_user_range
#define __cpu_flush_user_tlb_page cpu_tlb.flush_user_page
#define __cpu_flush_kern_tlb_range cpu_tlb.flush_kern_range
#define __cpu_flush_kern_tlb_page cpu_tlb.flush_kern_page
#else
#define __cpu_flush_kern_tlb_all __glue(_TLB,_flush_kern_tlb_all)
#define __cpu_flush_user_tlb_mm __glue(_TLB,_flush_user_tlb_mm)
#define __cpu_flush_user_tlb_range __glue(_TLB,_flush_user_tlb_range)
#define __cpu_flush_user_tlb_page __glue(_TLB,_flush_user_tlb_page)
#define __cpu_flush_kern_tlb_range __glue(_TLB,_flush_kern_tlb_range)
#define __cpu_flush_kern_tlb_page __glue(_TLB,_flush_kern_tlb_page)
extern void __cpu_flush_kern_tlb_all(void);
extern void __cpu_flush_user_tlb_mm(struct mm_struct *);
extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
extern void __cpu_flush_user_tlb_page(unsigned long, struct vm_area_struct *);
extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
extern void __cpu_flush_kern_tlb_page(unsigned long);
#endif
/*
* if PG_dcache_dirty is set for the page, we need to ensure that any
* cache entries for the kernels virtual memory range are written
* back to the page.
*/
extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte);
/*
* ARM processors do not cache TLB tables in RAM.
*/
#define flush_tlb_pgtables(mm,start,end) do { } while (0)
/*
* Old ARM MEMC stuff. This supports the reversed mapping handling that
* we have on the older 26-bit machines. We don't have a MEMC chip, so...
*/
#define memc_update_all() do { } while (0)
#define memc_update_mm(mm) do { } while (0)
#define memc_update_addr(mm,pte,log) do { } while (0)
#define memc_clear(mm,physaddr) do { } while (0)
......@@ -102,6 +102,8 @@ static inline unsigned long __thread_saved_fp(struct thread_info *thread)
#endif
#define PREEMPT_ACTIVE 0x04000000
/*
* thread information flags:
* TIF_SYSCALL_TRACE - syscall trace active
......
/*
* linux/include/asm-arm/tlbflush.h
*
* Copyright (C) 2000-2002 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _ASMARM_TLBFLUSH_H
#define _ASMARM_TLBFLUSH_H
#include <asm-arm/proc/tlbflush.h>
#endif
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