Commit 976677b5 authored by Dario Binacchi's avatar Dario Binacchi Committed by Jyri Sarha

drm/tilcdc: fix pixel clock setting warning message

The warning message did not printed the LCD pixel clock rate but the LCD
clock divisor input rate. As a consequence, the required and real pixel
clock rates are now passed to the tilcdc_pclk_diff().
Signed-off-by: default avatarDario Binacchi <dariobin@libero.it>
Reviewed-by: default avatarJyri Sarha <jyri.sarha@iki.fi>
Reviewed-by: default avatarTomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Signed-off-by: default avatarJyri Sarha <jyri.sarha@iki.fi>
Link: https://patchwork.freedesktop.org/patch/msgid/20210322213337.26667-4-dariobin@libero.it
parent fd1d9e2d
...@@ -203,7 +203,7 @@ static void tilcdc_crtc_set_clk(struct drm_crtc *crtc) ...@@ -203,7 +203,7 @@ static void tilcdc_crtc_set_clk(struct drm_crtc *crtc)
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct tilcdc_drm_private *priv = dev->dev_private; struct tilcdc_drm_private *priv = dev->dev_private;
struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
unsigned long clk_rate, real_rate, real_pclk_rate, pclk_rate; unsigned long clk_rate, real_pclk_rate, pclk_rate;
unsigned int clkdiv; unsigned int clkdiv;
int ret; int ret;
...@@ -239,12 +239,12 @@ static void tilcdc_crtc_set_clk(struct drm_crtc *crtc) ...@@ -239,12 +239,12 @@ static void tilcdc_crtc_set_clk(struct drm_crtc *crtc)
* 5% is an arbitrary value - LCDs are usually quite tolerant * 5% is an arbitrary value - LCDs are usually quite tolerant
* about pixel clock rates. * about pixel clock rates.
*/ */
real_rate = clkdiv * pclk_rate; real_pclk_rate = clk_rate / clkdiv;
if (tilcdc_pclk_diff(clk_rate, real_rate) > 5) { if (tilcdc_pclk_diff(pclk_rate, real_pclk_rate) > 5) {
dev_warn(dev->dev, dev_warn(dev->dev,
"effective pixel clock rate (%luHz) differs from the calculated rate (%luHz)\n", "effective pixel clock rate (%luHz) differs from the requested rate (%luHz)\n",
clk_rate, real_rate); real_pclk_rate, pclk_rate);
} }
} }
......
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