Commit 9ab5071c authored by Clemens Ladisch's avatar Clemens Ladisch

firewire: add CSR CYCLE_TIME write support

The specification requires that CYCLE_TIME is writable so that it can be
initialized, so we better implement it.
Signed-off-by: default avatarClemens Ladisch <clemens@ladisch.de>
parent 8e4b50f9
...@@ -1097,6 +1097,9 @@ static void handle_registers(struct fw_card *card, struct fw_request *request, ...@@ -1097,6 +1097,9 @@ static void handle_registers(struct fw_card *card, struct fw_request *request,
if (TCODE_IS_READ_REQUEST(tcode) && length == 4) if (TCODE_IS_READ_REQUEST(tcode) && length == 4)
*data = cpu_to_be32(card->driver-> *data = cpu_to_be32(card->driver->
read_csr_reg(card, CSR_CYCLE_TIME)); read_csr_reg(card, CSR_CYCLE_TIME));
else if (tcode == TCODE_WRITE_QUADLET_REQUEST)
card->driver->write_csr_reg(card, CSR_CYCLE_TIME,
be32_to_cpu(*data));
else else
rcode = RCODE_TYPE_ERROR; rcode = RCODE_TYPE_ERROR;
break; break;
......
...@@ -1996,6 +1996,13 @@ static void ohci_write_csr_reg(struct fw_card *card, int csr_offset, u32 value) ...@@ -1996,6 +1996,13 @@ static void ohci_write_csr_reg(struct fw_card *card, int csr_offset, u32 value)
flush_writes(ohci); flush_writes(ohci);
break; break;
case CSR_CYCLE_TIME:
reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
reg_write(ohci, OHCI1394_IntEventSet,
OHCI1394_cycleInconsistent);
flush_writes(ohci);
break;
default: default:
WARN_ON(1); WARN_ON(1);
break; break;
......
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