Commit 9ada9fd5 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp

Pull EDAC fixes from Borislav Petkov:

 - EDAC core error path fix, from Denis Kirjanov.

 - Generalization of AMD MCE bank names and some minor error reporting
   improvements.

 - EDAC core cleanups and simplifications, from Wei Yongjun.

 - amd64_edac fixes for sysfs-reported values, from Josh Hunt.

 - some heavy amd64_edac error reporting path shaving, leading to
   removing a bunch of code.

 - amd64_edac error injection method improvements.

 - EDAC core cleanups and fixes

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: (24 commits)
  EDAC, pci_sysfs: Use for_each_pci_dev to simplify the code
  EDAC: Handle error path in edac_mc_sysfs_init() properly
  MCE, AMD: Dump error status
  MCE, AMD: Report decoded error type first
  MCE, AMD: Dump CPU f/m/s triple with the error
  MCE, AMD: Remove functional unit references
  EDAC: Convert to use simple_open()
  EDAC, Calxeda highbank: Convert to use simple_open()
  EDAC: Fix mc size reported in sysfs
  EDAC: Fix csrow size reported in sysfs
  EDAC: Pass mci parent
  EDAC: Add memory controller flags
  amd64_edac: Fix csrows size and pages computation
  amd64_edac: Use DBAM_DIMM macro
  amd64_edac: Fix K8 chip select reporting
  amd64_edac: Reorganize error reporting path
  amd64_edac: Do not check whether error address is valid
  amd64_edac: Improve error injection
  amd64_edac: Cleanup error injection code
  amd64_edac: Small fixlets and cleanups
  ...
parents c45564e9 3bfe5aae
...@@ -42,10 +42,10 @@ config EDAC_LEGACY_SYSFS ...@@ -42,10 +42,10 @@ config EDAC_LEGACY_SYSFS
config EDAC_DEBUG config EDAC_DEBUG
bool "Debugging" bool "Debugging"
help help
This turns on debugging information for the entire EDAC This turns on debugging information for the entire EDAC subsystem.
sub-system. You can insert module with "debug_level=x", current You do so by inserting edac_module with "edac_debug_level=x." Valid
there're four debug levels (x=0,1,2,3 from low to high). levels are 0-4 (from low to high) and by default it is set to 2.
Usually you should select 'N'. Usually you should select 'N' here.
config EDAC_DECODE_MCE config EDAC_DECODE_MCE
tristate "Decode MCEs in human-readable form (only on AMD for now)" tristate "Decode MCEs in human-readable form (only on AMD for now)"
......
This diff is collapsed.
...@@ -219,7 +219,7 @@ ...@@ -219,7 +219,7 @@
#define DBAM1 0x180 #define DBAM1 0x180
/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */ /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
#define DBAM_DIMM(i, reg) ((((reg) >> (4*i))) & 0xF) #define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF)
#define DBAM_MAX_VALUE 11 #define DBAM_MAX_VALUE 11
...@@ -267,18 +267,20 @@ ...@@ -267,18 +267,20 @@
#define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7) #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
#define F10_NB_ARRAY_ADDR 0xB8 #define F10_NB_ARRAY_ADDR 0xB8
#define F10_NB_ARRAY_DRAM_ECC BIT(31) #define F10_NB_ARRAY_DRAM BIT(31)
/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */ /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
#define SET_NB_ARRAY_ADDRESS(section) (((section) & 0x3) << 1) #define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1)
#define F10_NB_ARRAY_DATA 0xBC #define F10_NB_ARRAY_DATA 0xBC
#define SET_NB_DRAM_INJECTION_WRITE(word, bits) \ #define F10_NB_ARR_ECC_WR_REQ BIT(17)
(BIT(((word) & 0xF) + 20) | \ #define SET_NB_DRAM_INJECTION_WRITE(inj) \
BIT(17) | bits) (BIT(((inj.word) & 0xF) + 20) | \
#define SET_NB_DRAM_INJECTION_READ(word, bits) \ F10_NB_ARR_ECC_WR_REQ | inj.bit_map)
(BIT(((word) & 0xF) + 20) | \ #define SET_NB_DRAM_INJECTION_READ(inj) \
BIT(16) | bits) (BIT(((inj.word) & 0xF) + 20) | \
BIT(16) | inj.bit_map)
#define NBCAP 0xE8 #define NBCAP 0xE8
#define NBCAP_CHIPKILL BIT(4) #define NBCAP_CHIPKILL BIT(4)
...@@ -374,6 +376,23 @@ struct amd64_pvt { ...@@ -374,6 +376,23 @@ struct amd64_pvt {
struct error_injection injection; struct error_injection injection;
}; };
enum err_codes {
DECODE_OK = 0,
ERR_NODE = -1,
ERR_CSROW = -2,
ERR_CHANNEL = -3,
};
struct err_info {
int err_code;
struct mem_ctl_info *src_mci;
int csrow;
int channel;
u16 syndrome;
u32 page;
u32 offset;
};
static inline u64 get_dram_base(struct amd64_pvt *pvt, unsigned i) static inline u64 get_dram_base(struct amd64_pvt *pvt, unsigned i)
{ {
u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8; u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
...@@ -447,7 +466,7 @@ static inline void amd64_remove_sysfs_inject_files(struct mem_ctl_info *mci) ...@@ -447,7 +466,7 @@ static inline void amd64_remove_sysfs_inject_files(struct mem_ctl_info *mci)
struct low_ops { struct low_ops {
int (*early_channel_count) (struct amd64_pvt *pvt); int (*early_channel_count) (struct amd64_pvt *pvt);
void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr, void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr,
u16 syndrome); struct err_info *);
int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct, unsigned cs_mode); int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct, unsigned cs_mode);
int (*read_dct_pci_cfg) (struct amd64_pvt *pvt, int offset, int (*read_dct_pci_cfg) (struct amd64_pvt *pvt, int offset,
u32 *val, const char *func); u32 *val, const char *func);
...@@ -459,6 +478,8 @@ struct amd64_family_type { ...@@ -459,6 +478,8 @@ struct amd64_family_type {
struct low_ops ops; struct low_ops ops;
}; };
int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
u32 *val, const char *func);
int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset, int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
u32 val, const char *func); u32 val, const char *func);
...@@ -475,3 +496,15 @@ int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, ...@@ -475,3 +496,15 @@ int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
u64 *hole_offset, u64 *hole_size); u64 *hole_offset, u64 *hole_size);
#define to_mci(k) container_of(k, struct mem_ctl_info, dev) #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
/* Injection helpers */
static inline void disable_caches(void *dummy)
{
write_cr0(read_cr0() | X86_CR0_CD);
wbinvd();
}
static inline void enable_caches(void *dummy)
{
write_cr0(read_cr0() & ~X86_CR0_CD);
}
...@@ -22,10 +22,11 @@ static ssize_t amd64_inject_section_store(struct device *dev, ...@@ -22,10 +22,11 @@ static ssize_t amd64_inject_section_store(struct device *dev,
struct mem_ctl_info *mci = to_mci(dev); struct mem_ctl_info *mci = to_mci(dev);
struct amd64_pvt *pvt = mci->pvt_info; struct amd64_pvt *pvt = mci->pvt_info;
unsigned long value; unsigned long value;
int ret = 0; int ret;
ret = strict_strtoul(data, 10, &value); ret = strict_strtoul(data, 10, &value);
if (ret != -EINVAL) { if (ret < 0)
return ret;
if (value > 3) { if (value > 3) {
amd64_warn("%s: invalid section 0x%lx\n", __func__, value); amd64_warn("%s: invalid section 0x%lx\n", __func__, value);
...@@ -34,8 +35,6 @@ static ssize_t amd64_inject_section_store(struct device *dev, ...@@ -34,8 +35,6 @@ static ssize_t amd64_inject_section_store(struct device *dev,
pvt->injection.section = (u32) value; pvt->injection.section = (u32) value;
return count; return count;
}
return ret;
} }
static ssize_t amd64_inject_word_show(struct device *dev, static ssize_t amd64_inject_word_show(struct device *dev,
...@@ -60,10 +59,11 @@ static ssize_t amd64_inject_word_store(struct device *dev, ...@@ -60,10 +59,11 @@ static ssize_t amd64_inject_word_store(struct device *dev,
struct mem_ctl_info *mci = to_mci(dev); struct mem_ctl_info *mci = to_mci(dev);
struct amd64_pvt *pvt = mci->pvt_info; struct amd64_pvt *pvt = mci->pvt_info;
unsigned long value; unsigned long value;
int ret = 0; int ret;
ret = strict_strtoul(data, 10, &value); ret = strict_strtoul(data, 10, &value);
if (ret != -EINVAL) { if (ret < 0)
return ret;
if (value > 8) { if (value > 8) {
amd64_warn("%s: invalid word 0x%lx\n", __func__, value); amd64_warn("%s: invalid word 0x%lx\n", __func__, value);
...@@ -72,8 +72,6 @@ static ssize_t amd64_inject_word_store(struct device *dev, ...@@ -72,8 +72,6 @@ static ssize_t amd64_inject_word_store(struct device *dev,
pvt->injection.word = (u32) value; pvt->injection.word = (u32) value;
return count; return count;
}
return ret;
} }
static ssize_t amd64_inject_ecc_vector_show(struct device *dev, static ssize_t amd64_inject_ecc_vector_show(struct device *dev,
...@@ -97,21 +95,19 @@ static ssize_t amd64_inject_ecc_vector_store(struct device *dev, ...@@ -97,21 +95,19 @@ static ssize_t amd64_inject_ecc_vector_store(struct device *dev,
struct mem_ctl_info *mci = to_mci(dev); struct mem_ctl_info *mci = to_mci(dev);
struct amd64_pvt *pvt = mci->pvt_info; struct amd64_pvt *pvt = mci->pvt_info;
unsigned long value; unsigned long value;
int ret = 0; int ret;
ret = strict_strtoul(data, 16, &value); ret = strict_strtoul(data, 16, &value);
if (ret != -EINVAL) { if (ret < 0)
return ret;
if (value & 0xFFFF0000) { if (value & 0xFFFF0000) {
amd64_warn("%s: invalid EccVector: 0x%lx\n", amd64_warn("%s: invalid EccVector: 0x%lx\n", __func__, value);
__func__, value);
return -EINVAL; return -EINVAL;
} }
pvt->injection.bit_map = (u32) value; pvt->injection.bit_map = (u32) value;
return count; return count;
}
return ret;
} }
/* /*
...@@ -126,28 +122,25 @@ static ssize_t amd64_inject_read_store(struct device *dev, ...@@ -126,28 +122,25 @@ static ssize_t amd64_inject_read_store(struct device *dev,
struct amd64_pvt *pvt = mci->pvt_info; struct amd64_pvt *pvt = mci->pvt_info;
unsigned long value; unsigned long value;
u32 section, word_bits; u32 section, word_bits;
int ret = 0; int ret;
ret = strict_strtoul(data, 10, &value); ret = strict_strtoul(data, 10, &value);
if (ret != -EINVAL) { if (ret < 0)
return ret;
/* Form value to choose 16-byte section of cacheline */ /* Form value to choose 16-byte section of cacheline */
section = F10_NB_ARRAY_DRAM_ECC | section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section);
SET_NB_ARRAY_ADDRESS(pvt->injection.section);
amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section); amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection.word, word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection);
pvt->injection.bit_map);
/* Issue 'word' and 'bit' along with the READ request */ /* Issue 'word' and 'bit' along with the READ request */
amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits); amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
edac_dbg(0, "section=0x%x word_bits=0x%x\n", edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);
section, word_bits);
return count; return count;
}
return ret;
} }
/* /*
...@@ -160,30 +153,43 @@ static ssize_t amd64_inject_write_store(struct device *dev, ...@@ -160,30 +153,43 @@ static ssize_t amd64_inject_write_store(struct device *dev,
{ {
struct mem_ctl_info *mci = to_mci(dev); struct mem_ctl_info *mci = to_mci(dev);
struct amd64_pvt *pvt = mci->pvt_info; struct amd64_pvt *pvt = mci->pvt_info;
u32 section, word_bits, tmp;
unsigned long value; unsigned long value;
u32 section, word_bits; int ret;
int ret = 0;
ret = strict_strtoul(data, 10, &value); ret = strict_strtoul(data, 10, &value);
if (ret != -EINVAL) { if (ret < 0)
return ret;
/* Form value to choose 16-byte section of cacheline */ /* Form value to choose 16-byte section of cacheline */
section = F10_NB_ARRAY_DRAM_ECC | section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section);
SET_NB_ARRAY_ADDRESS(pvt->injection.section);
amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section); amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection.word, word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection);
pvt->injection.bit_map);
pr_notice_once("Don't forget to decrease MCE polling interval in\n"
"/sys/bus/machinecheck/devices/machinecheck<CPUNUM>/check_interval\n"
"so that you can get the error report faster.\n");
on_each_cpu(disable_caches, NULL, 1);
/* Issue 'word' and 'bit' along with the READ request */ /* Issue 'word' and 'bit' along with the READ request */
amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits); amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
edac_dbg(0, "section=0x%x word_bits=0x%x\n", retry:
section, word_bits); /* wait until injection happens */
amd64_read_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, &tmp);
if (tmp & F10_NB_ARR_ECC_WR_REQ) {
cpu_relax();
goto retry;
}
on_each_cpu(enable_caches, NULL, 1);
edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);
return count; return count;
}
return ret;
} }
/* /*
......
...@@ -974,20 +974,22 @@ static void edac_ce_error(struct mem_ctl_info *mci, ...@@ -974,20 +974,22 @@ static void edac_ce_error(struct mem_ctl_info *mci,
long grain) long grain)
{ {
unsigned long remapped_page; unsigned long remapped_page;
char *msg_aux = "";
if (*msg)
msg_aux = " ";
if (edac_mc_get_log_ce()) { if (edac_mc_get_log_ce()) {
if (other_detail && *other_detail) if (other_detail && *other_detail)
edac_mc_printk(mci, KERN_WARNING, edac_mc_printk(mci, KERN_WARNING,
"%d CE %s on %s (%s %s - %s)\n", "%d CE %s%son %s (%s %s - %s)\n",
error_count, error_count, msg, msg_aux, label,
msg, label, location, location, detail, other_detail);
detail, other_detail);
else else
edac_mc_printk(mci, KERN_WARNING, edac_mc_printk(mci, KERN_WARNING,
"%d CE %s on %s (%s %s)\n", "%d CE %s%son %s (%s %s)\n",
error_count, error_count, msg, msg_aux, label,
msg, label, location, location, detail);
detail);
} }
edac_inc_ce_error(mci, enable_per_layer_report, pos, error_count); edac_inc_ce_error(mci, enable_per_layer_report, pos, error_count);
...@@ -1022,27 +1024,31 @@ static void edac_ue_error(struct mem_ctl_info *mci, ...@@ -1022,27 +1024,31 @@ static void edac_ue_error(struct mem_ctl_info *mci,
const char *other_detail, const char *other_detail,
const bool enable_per_layer_report) const bool enable_per_layer_report)
{ {
char *msg_aux = "";
if (*msg)
msg_aux = " ";
if (edac_mc_get_log_ue()) { if (edac_mc_get_log_ue()) {
if (other_detail && *other_detail) if (other_detail && *other_detail)
edac_mc_printk(mci, KERN_WARNING, edac_mc_printk(mci, KERN_WARNING,
"%d UE %s on %s (%s %s - %s)\n", "%d UE %s%son %s (%s %s - %s)\n",
error_count, error_count, msg, msg_aux, label,
msg, label, location, detail, location, detail, other_detail);
other_detail);
else else
edac_mc_printk(mci, KERN_WARNING, edac_mc_printk(mci, KERN_WARNING,
"%d UE %s on %s (%s %s)\n", "%d UE %s%son %s (%s %s)\n",
error_count, error_count, msg, msg_aux, label,
msg, label, location, detail); location, detail);
} }
if (edac_mc_get_panic_on_ue()) { if (edac_mc_get_panic_on_ue()) {
if (other_detail && *other_detail) if (other_detail && *other_detail)
panic("UE %s on %s (%s%s - %s)\n", panic("UE %s%son %s (%s%s - %s)\n",
msg, label, location, detail, other_detail); msg, msg_aux, label, location, detail, other_detail);
else else
panic("UE %s on %s (%s%s)\n", panic("UE %s%son %s (%s%s)\n",
msg, label, location, detail); msg, msg_aux, label, location, detail);
} }
edac_inc_ue_error(mci, enable_per_layer_report, pos, error_count); edac_inc_ue_error(mci, enable_per_layer_report, pos, error_count);
...@@ -1101,10 +1107,6 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, ...@@ -1101,10 +1107,6 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type,
*/ */
for (i = 0; i < mci->n_layers; i++) { for (i = 0; i < mci->n_layers; i++) {
if (pos[i] >= (int)mci->layers[i].size) { if (pos[i] >= (int)mci->layers[i].size) {
if (type == HW_EVENT_ERR_CORRECTED)
p = "CE";
else
p = "UE";
edac_mc_printk(mci, KERN_ERR, edac_mc_printk(mci, KERN_ERR,
"INTERNAL ERROR: %s value is out of range (%d >= %d)\n", "INTERNAL ERROR: %s value is out of range (%d >= %d)\n",
...@@ -1136,6 +1138,7 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, ...@@ -1136,6 +1138,7 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type,
grain = 0; grain = 0;
p = label; p = label;
*p = '\0'; *p = '\0';
for (i = 0; i < mci->tot_dimms; i++) { for (i = 0; i < mci->tot_dimms; i++) {
struct dimm_info *dimm = mci->dimms[i]; struct dimm_info *dimm = mci->dimms[i];
...@@ -1203,6 +1206,7 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, ...@@ -1203,6 +1206,7 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type,
/* Fill the RAM location data */ /* Fill the RAM location data */
p = location; p = location;
for (i = 0; i < mci->n_layers; i++) { for (i = 0; i < mci->n_layers; i++) {
if (pos[i] < 0) if (pos[i] < 0)
continue; continue;
...@@ -1215,7 +1219,6 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, ...@@ -1215,7 +1219,6 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type,
*(p - 1) = '\0'; *(p - 1) = '\0';
/* Report the error via the trace interface */ /* Report the error via the trace interface */
grain_bits = fls_long(grain) + 1; grain_bits = fls_long(grain) + 1;
trace_mc_event(type, msg, label, error_count, trace_mc_event(type, msg, label, error_count,
mci->mc_idx, top_layer, mid_layer, low_layer, mci->mc_idx, top_layer, mid_layer, low_layer,
......
...@@ -180,6 +180,9 @@ static ssize_t csrow_size_show(struct device *dev, ...@@ -180,6 +180,9 @@ static ssize_t csrow_size_show(struct device *dev,
int i; int i;
u32 nr_pages = 0; u32 nr_pages = 0;
if (csrow->mci->csbased)
return sprintf(data, "%u\n", PAGES_TO_MiB(csrow->nr_pages));
for (i = 0; i < csrow->nr_channels; i++) for (i = 0; i < csrow->nr_channels; i++)
nr_pages += csrow->channels[i]->dimm->nr_pages; nr_pages += csrow->channels[i]->dimm->nr_pages;
return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages)); return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages));
...@@ -373,6 +376,7 @@ static int edac_create_csrow_object(struct mem_ctl_info *mci, ...@@ -373,6 +376,7 @@ static int edac_create_csrow_object(struct mem_ctl_info *mci,
csrow->dev.bus = &mci->bus; csrow->dev.bus = &mci->bus;
device_initialize(&csrow->dev); device_initialize(&csrow->dev);
csrow->dev.parent = &mci->dev; csrow->dev.parent = &mci->dev;
csrow->mci = mci;
dev_set_name(&csrow->dev, "csrow%d", index); dev_set_name(&csrow->dev, "csrow%d", index);
dev_set_drvdata(&csrow->dev, csrow); dev_set_drvdata(&csrow->dev, csrow);
...@@ -777,12 +781,16 @@ static ssize_t mci_size_mb_show(struct device *dev, ...@@ -777,12 +781,16 @@ static ssize_t mci_size_mb_show(struct device *dev,
for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) { for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) {
struct csrow_info *csrow = mci->csrows[csrow_idx]; struct csrow_info *csrow = mci->csrows[csrow_idx];
if (csrow->mci->csbased) {
total_pages += csrow->nr_pages;
} else {
for (j = 0; j < csrow->nr_channels; j++) { for (j = 0; j < csrow->nr_channels; j++) {
struct dimm_info *dimm = csrow->channels[j]->dimm; struct dimm_info *dimm = csrow->channels[j]->dimm;
total_pages += dimm->nr_pages; total_pages += dimm->nr_pages;
} }
} }
}
return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages)); return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages));
} }
...@@ -838,14 +846,8 @@ static ssize_t edac_fake_inject_write(struct file *file, ...@@ -838,14 +846,8 @@ static ssize_t edac_fake_inject_write(struct file *file,
return count; return count;
} }
static int debugfs_open(struct inode *inode, struct file *file)
{
file->private_data = inode->i_private;
return 0;
}
static const struct file_operations debug_fake_inject_fops = { static const struct file_operations debug_fake_inject_fops = {
.open = debugfs_open, .open = simple_open,
.write = edac_fake_inject_write, .write = edac_fake_inject_write,
.llseek = generic_file_llseek, .llseek = generic_file_llseek,
}; };
...@@ -1124,10 +1126,15 @@ int __init edac_mc_sysfs_init(void) ...@@ -1124,10 +1126,15 @@ int __init edac_mc_sysfs_init(void)
edac_subsys = edac_get_sysfs_subsys(); edac_subsys = edac_get_sysfs_subsys();
if (edac_subsys == NULL) { if (edac_subsys == NULL) {
edac_dbg(1, "no edac_subsys\n"); edac_dbg(1, "no edac_subsys\n");
return -EINVAL; err = -EINVAL;
goto out;
} }
mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL); mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL);
if (!mci_pdev) {
err = -ENOMEM;
goto out_put_sysfs;
}
mci_pdev->bus = edac_subsys; mci_pdev->bus = edac_subsys;
mci_pdev->type = &mc_attr_type; mci_pdev->type = &mc_attr_type;
...@@ -1136,11 +1143,18 @@ int __init edac_mc_sysfs_init(void) ...@@ -1136,11 +1143,18 @@ int __init edac_mc_sysfs_init(void)
err = device_add(mci_pdev); err = device_add(mci_pdev);
if (err < 0) if (err < 0)
return err; goto out_dev_free;
edac_dbg(0, "device %s created\n", dev_name(mci_pdev)); edac_dbg(0, "device %s created\n", dev_name(mci_pdev));
return 0; return 0;
out_dev_free:
kfree(mci_pdev);
out_put_sysfs:
edac_put_sysfs_subsys();
out:
return err;
} }
void __exit edac_mc_sysfs_exit(void) void __exit edac_mc_sysfs_exit(void)
...@@ -1148,4 +1162,5 @@ void __exit edac_mc_sysfs_exit(void) ...@@ -1148,4 +1162,5 @@ void __exit edac_mc_sysfs_exit(void)
put_device(mci_pdev); put_device(mci_pdev);
device_del(mci_pdev); device_del(mci_pdev);
edac_put_sysfs_subsys(); edac_put_sysfs_subsys();
kfree(mci_pdev);
} }
...@@ -18,9 +18,29 @@ ...@@ -18,9 +18,29 @@
#define EDAC_VERSION "Ver: 3.0.0" #define EDAC_VERSION "Ver: 3.0.0"
#ifdef CONFIG_EDAC_DEBUG #ifdef CONFIG_EDAC_DEBUG
static int edac_set_debug_level(const char *buf, struct kernel_param *kp)
{
unsigned long val;
int ret;
ret = kstrtoul(buf, 0, &val);
if (ret)
return ret;
if (val < 0 || val > 4)
return -EINVAL;
return param_set_int(buf, kp);
}
/* Values of 0 to 4 will generate output */ /* Values of 0 to 4 will generate output */
int edac_debug_level = 2; int edac_debug_level = 2;
EXPORT_SYMBOL_GPL(edac_debug_level); EXPORT_SYMBOL_GPL(edac_debug_level);
module_param_call(edac_debug_level, edac_set_debug_level, param_get_int,
&edac_debug_level, 0644);
MODULE_PARM_DESC(edac_debug_level, "EDAC debug level: [0-4], default: 2");
#endif #endif
/* scope is to module level only */ /* scope is to module level only */
...@@ -132,10 +152,3 @@ module_exit(edac_exit); ...@@ -132,10 +152,3 @@ module_exit(edac_exit);
MODULE_LICENSE("GPL"); MODULE_LICENSE("GPL");
MODULE_AUTHOR("Doug Thompson www.softwarebitmaker.com, et al"); MODULE_AUTHOR("Doug Thompson www.softwarebitmaker.com, et al");
MODULE_DESCRIPTION("Core library routines for EDAC reporting"); MODULE_DESCRIPTION("Core library routines for EDAC reporting");
/* refer to *_sysfs.c files for parameters that are exported via sysfs */
#ifdef CONFIG_EDAC_DEBUG
module_param(edac_debug_level, int, 0644);
MODULE_PARM_DESC(edac_debug_level, "Debug level");
#endif
...@@ -470,6 +470,7 @@ struct edac_pci_ctl_info *edac_pci_create_generic_ctl(struct device *dev, ...@@ -470,6 +470,7 @@ struct edac_pci_ctl_info *edac_pci_create_generic_ctl(struct device *dev,
pci->mod_name = mod_name; pci->mod_name = mod_name;
pci->ctl_name = EDAC_PCI_GENCTL_NAME; pci->ctl_name = EDAC_PCI_GENCTL_NAME;
if (edac_op_state == EDAC_OPSTATE_POLL)
pci->edac_check = edac_pci_generic_check; pci->edac_check = edac_pci_generic_check;
pdata->edac_idx = edac_pci_idx++; pdata->edac_idx = edac_pci_idx++;
......
...@@ -645,20 +645,16 @@ typedef void (*pci_parity_check_fn_t) (struct pci_dev *dev); ...@@ -645,20 +645,16 @@ typedef void (*pci_parity_check_fn_t) (struct pci_dev *dev);
/* /*
* pci_dev parity list iterator * pci_dev parity list iterator
* Scan the PCI device list for one pass, looking for SERRORs *
* Master Parity ERRORS or Parity ERRORs on primary or secondary devices * Scan the PCI device list looking for SERRORs, Master Parity ERRORS or
* Parity ERRORs on primary or secondary devices.
*/ */
static inline void edac_pci_dev_parity_iterator(pci_parity_check_fn_t fn) static inline void edac_pci_dev_parity_iterator(pci_parity_check_fn_t fn)
{ {
struct pci_dev *dev = NULL; struct pci_dev *dev = NULL;
/* request for kernel access to the next PCI device, if any, for_each_pci_dev(dev)
* and while we are looking at it have its reference count
* bumped until we are done with it
*/
while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
fn(dev); fn(dev);
}
} }
/* /*
......
...@@ -113,14 +113,8 @@ static ssize_t highbank_mc_err_inject_write(struct file *file, ...@@ -113,14 +113,8 @@ static ssize_t highbank_mc_err_inject_write(struct file *file,
return count; return count;
} }
static int debugfs_open(struct inode *inode, struct file *file)
{
file->private_data = inode->i_private;
return 0;
}
static const struct file_operations highbank_mc_debug_inject_fops = { static const struct file_operations highbank_mc_debug_inject_fops = {
.open = debugfs_open, .open = simple_open,
.write = highbank_mc_err_inject_write, .write = highbank_mc_err_inject_write,
.llseek = generic_file_llseek, .llseek = generic_file_llseek,
}; };
......
This diff is collapsed.
...@@ -29,10 +29,8 @@ ...@@ -29,10 +29,8 @@
#define R4(x) (((x) >> 4) & 0xf) #define R4(x) (((x) >> 4) & 0xf)
#define R4_MSG(x) ((R4(x) < 9) ? rrrr_msgs[R4(x)] : "Wrong R4!") #define R4_MSG(x) ((R4(x) < 9) ? rrrr_msgs[R4(x)] : "Wrong R4!")
/* #define MCI_STATUS_DEFERRED BIT_64(44)
* F3x4C bits (MCi_STATUS' high half) #define MCI_STATUS_POISON BIT_64(43)
*/
#define NBSH_ERR_CPU_VAL BIT(24)
enum tt_ids { enum tt_ids {
TT_INSTR = 0, TT_INSTR = 0,
...@@ -78,14 +76,13 @@ extern const char * const ii_msgs[]; ...@@ -78,14 +76,13 @@ extern const char * const ii_msgs[];
* per-family decoder ops * per-family decoder ops
*/ */
struct amd_decoder_ops { struct amd_decoder_ops {
bool (*dc_mce)(u16, u8); bool (*mc0_mce)(u16, u8);
bool (*ic_mce)(u16, u8); bool (*mc1_mce)(u16, u8);
}; };
void amd_report_gart_errors(bool); void amd_report_gart_errors(bool);
void amd_register_ecc_decoder(void (*f)(int, struct mce *)); void amd_register_ecc_decoder(void (*f)(int, struct mce *));
void amd_unregister_ecc_decoder(void (*f)(int, struct mce *)); void amd_unregister_ecc_decoder(void (*f)(int, struct mce *));
void amd_decode_nb_mce(struct mce *);
int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data); int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data);
#endif /* _EDAC_MCE_AMD_H */ #endif /* _EDAC_MCE_AMD_H */
...@@ -533,6 +533,7 @@ struct csrow_info { ...@@ -533,6 +533,7 @@ struct csrow_info {
u32 ue_count; /* Uncorrectable Errors for this csrow */ u32 ue_count; /* Uncorrectable Errors for this csrow */
u32 ce_count; /* Correctable Errors for this csrow */ u32 ce_count; /* Correctable Errors for this csrow */
u32 nr_pages; /* combined pages count of all channels */
struct mem_ctl_info *mci; /* the parent */ struct mem_ctl_info *mci; /* the parent */
...@@ -667,6 +668,8 @@ struct mem_ctl_info { ...@@ -667,6 +668,8 @@ struct mem_ctl_info {
u32 fake_inject_ue; u32 fake_inject_ue;
u16 fake_inject_count; u16 fake_inject_count;
#endif #endif
__u8 csbased : 1, /* csrow-based memory controller */
__resv : 7;
}; };
#endif #endif
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