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Commit 9c6e72fb authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Bjorn Andersson
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arm64: dts: qcom: add missing cache properties 

Add required cache-level and cache-unified properties to fix warnings
like:

  qdu1000-idp.dtb: l3-cache: 'cache-unified' is a required property
  qdu1000-idp.dtb: l2-cache: 'cache-level' is a required property
Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416101134.95686-3-krzysztof.kozlowski@linaro.org
parent 08465709
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arch/arm64/boot/dts/qcom/ipq5332.dtsi
View file @ 9c6e72fb
......@@ -73,6 +73,7 @@ CPU3: cpu@3 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View file @ 9c6e72fb
......@@ -84,6 +84,7 @@ CPU3: cpu@3 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View file @ 9c6e72fb
......@@ -67,6 +67,7 @@ CPU3: cpu@3 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/ipq9574.dtsi
View file @ 9c6e72fb
......@@ -72,6 +72,7 @@ CPU3: cpu@3 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/msm8916.dtsi
View file @ 9c6e72fb
......@@ -180,6 +180,7 @@ CPU3: cpu@3 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
idle-states {
......
arch/arm64/boot/dts/qcom/msm8953.dtsi
View file @ 9c6e72fb
......@@ -153,11 +153,13 @@ core3 {
L2_0: l2-cache-0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
L2_1: l2-cache-1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/msm8976.dtsi
View file @ 9c6e72fb
......@@ -193,11 +193,13 @@ big_cpu_sleep_1: cpu-sleep-1-1 {
l2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/msm8994.dtsi
View file @ 9c6e72fb
......@@ -52,6 +52,7 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......@@ -88,6 +89,7 @@ CPU4: cpu@100 {
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/msm8996.dtsi
View file @ 9c6e72fb
......@@ -55,6 +55,7 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......@@ -85,6 +86,7 @@ CPU2: cpu@100 {
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/msm8998.dtsi
View file @ 9c6e72fb
......@@ -146,6 +146,7 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......@@ -190,6 +191,7 @@ CPU4: cpu@100 {
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/qcm2290.dtsi
View file @ 9c6e72fb
......@@ -51,6 +51,7 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/qcs404.dtsi
View file @ 9c6e72fb
......@@ -95,6 +95,7 @@ CPU3: cpu@103 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
idle-states {
......
arch/arm64/boot/dts/qcom/qdu1000.dtsi
View file @ 9c6e72fb
......@@ -35,9 +35,13 @@ CPU0: cpu@0 {
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -54,6 +58,8 @@ CPU1: cpu@100 {
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -70,6 +76,8 @@ CPU2: cpu@200 {
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -86,6 +94,8 @@ CPU3: cpu@300 {
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sa8775p.dtsi
View file @ 9c6e72fb
......@@ -42,9 +42,13 @@ CPU0: cpu@0 {
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -58,6 +62,8 @@ CPU1: cpu@100 {
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -71,6 +77,8 @@ CPU2: cpu@200 {
next-level-cache = <&L2_2>;
L2_2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -84,6 +92,8 @@ CPU3: cpu@300 {
next-level-cache = <&L2_3>;
L2_3: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -97,9 +107,13 @@ CPU4: cpu@10000 {
next-level-cache = <&L2_4>;
L2_4: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_1>;
L3_1: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
......@@ -114,6 +128,8 @@ CPU5: cpu@10100 {
next-level-cache = <&L2_5>;
L2_5: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_1>;
};
};
......@@ -127,6 +143,8 @@ CPU6: cpu@10200 {
next-level-cache = <&L2_6>;
L2_6: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_1>;
};
};
......@@ -140,6 +158,8 @@ CPU7: cpu@10300 {
next-level-cache = <&L2_7>;
L2_7: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_1>;
};
};
......
arch/arm64/boot/dts/qcom/sc7180.dtsi
View file @ 9c6e72fb
......@@ -92,10 +92,12 @@ &LITTLE_CPU_SLEEP_1
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -120,6 +122,7 @@ &LITTLE_CPU_SLEEP_1
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -144,6 +147,7 @@ &LITTLE_CPU_SLEEP_1
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -168,6 +172,7 @@ &LITTLE_CPU_SLEEP_1
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -192,6 +197,7 @@ &LITTLE_CPU_SLEEP_1
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -216,6 +222,7 @@ &LITTLE_CPU_SLEEP_1
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -240,6 +247,7 @@ &BIG_CPU_SLEEP_1
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -264,6 +272,7 @@ &BIG_CPU_SLEEP_1
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sc7280.dtsi
View file @ 9c6e72fb
......@@ -182,10 +182,12 @@ &LITTLE_CPU_SLEEP_1
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -208,6 +210,7 @@ &LITTLE_CPU_SLEEP_1
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -230,6 +233,7 @@ &LITTLE_CPU_SLEEP_1
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -252,6 +256,7 @@ &LITTLE_CPU_SLEEP_1
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -274,6 +279,7 @@ &BIG_CPU_SLEEP_1
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -296,6 +302,7 @@ &BIG_CPU_SLEEP_1
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -318,6 +325,7 @@ &BIG_CPU_SLEEP_1
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -340,6 +348,7 @@ &BIG_CPU_SLEEP_1
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View file @ 9c6e72fb
......@@ -58,10 +58,12 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -83,6 +85,7 @@ CPU1: cpu@100 {
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -104,6 +107,7 @@ CPU2: cpu@200 {
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -125,6 +129,7 @@ CPU3: cpu@300 {
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -146,6 +151,7 @@ CPU4: cpu@400 {
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -167,6 +173,7 @@ CPU5: cpu@500 {
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -188,6 +195,7 @@ CPU6: cpu@600 {
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -209,6 +217,7 @@ CPU7: cpu@700 {
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sdm630.dtsi
View file @ 9c6e72fb
......@@ -63,6 +63,7 @@ &PERF_CLUSTER_SLEEP_1
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......@@ -127,6 +128,7 @@ &PWR_CLUSTER_SLEEP_1
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/sdm670.dtsi
View file @ 9c6e72fb
......@@ -41,8 +41,12 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
cache-level = <2>;
cache-unified;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -57,6 +61,8 @@ CPU1: cpu@100 {
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -71,6 +77,8 @@ CPU2: cpu@200 {
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -85,6 +93,8 @@ CPU3: cpu@300 {
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -99,6 +109,8 @@ CPU4: cpu@400 {
next-level-cache = <&L2_400>;
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -113,6 +125,8 @@ CPU5: cpu@500 {
next-level-cache = <&L2_500>;
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -127,6 +141,8 @@ CPU6: cpu@600 {
next-level-cache = <&L2_600>;
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -141,6 +157,8 @@ CPU7: cpu@700 {
next-level-cache = <&L2_700>;
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file @ 9c6e72fb
......@@ -108,10 +108,12 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -135,6 +137,7 @@ CPU1: cpu@100 {
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -158,6 +161,7 @@ CPU2: cpu@200 {
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -181,6 +185,7 @@ CPU3: cpu@300 {
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -204,6 +209,7 @@ CPU4: cpu@400 {
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -227,6 +233,7 @@ CPU5: cpu@500 {
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -250,6 +257,7 @@ CPU6: cpu@600 {
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -273,6 +281,7 @@ CPU7: cpu@700 {
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sm6115.dtsi
View file @ 9c6e72fb
......@@ -50,6 +50,7 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......@@ -102,6 +103,7 @@ CPU4: cpu@100 {
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/sm6125.dtsi
View file @ 9c6e72fb
......@@ -47,6 +47,7 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......@@ -87,6 +88,7 @@ CPU4: cpu@100 {
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/sm6350.dtsi
View file @ 9c6e72fb
......@@ -60,10 +60,12 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -86,6 +88,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -108,6 +111,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -130,6 +134,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -152,6 +157,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -174,6 +180,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -196,6 +203,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -218,6 +226,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sm6375.dtsi
View file @ 9c6e72fb
......@@ -49,9 +49,13 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -69,6 +73,8 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -86,6 +92,8 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -103,6 +111,8 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -120,6 +130,8 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -137,6 +149,8 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -154,6 +168,8 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -171,6 +187,8 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sm8150.dtsi
View file @ 9c6e72fb
......@@ -63,10 +63,12 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -90,6 +92,7 @@ CPU1: cpu@100 {
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -113,6 +116,7 @@ CPU2: cpu@200 {
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -136,6 +140,7 @@ CPU3: cpu@300 {
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -159,6 +164,7 @@ CPU4: cpu@400 {
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -182,6 +188,7 @@ CPU5: cpu@500 {
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -205,6 +212,7 @@ CPU6: cpu@600 {
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -228,6 +236,7 @@ CPU7: cpu@700 {
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sm8350.dtsi
View file @ 9c6e72fb
......@@ -60,10 +60,12 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -82,6 +84,7 @@ CPU1: cpu@100 {
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -100,6 +103,7 @@ CPU2: cpu@200 {
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -118,6 +122,7 @@ CPU3: cpu@300 {
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -136,6 +141,7 @@ CPU4: cpu@400 {
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -154,6 +160,7 @@ CPU5: cpu@500 {
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -172,6 +179,7 @@ CPU6: cpu@600 {
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -190,6 +198,7 @@ CPU7: cpu@700 {
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sm8450.dtsi
View file @ 9c6e72fb
......@@ -59,10 +59,12 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -81,6 +83,7 @@ CPU1: cpu@100 {
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -99,6 +102,7 @@ CPU2: cpu@200 {
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -117,6 +121,7 @@ CPU3: cpu@300 {
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -135,6 +140,7 @@ CPU4: cpu@400 {
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -153,6 +159,7 @@ CPU5: cpu@500 {
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -171,6 +178,7 @@ CPU6: cpu@600 {
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -189,6 +197,7 @@ CPU7: cpu@700 {
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sm8550.dtsi
View file @ 9c6e72fb
......@@ -80,10 +80,12 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -104,6 +106,7 @@ CPU1: cpu@100 {
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -124,6 +127,7 @@ CPU2: cpu@200 {
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -144,6 +148,7 @@ CPU3: cpu@300 {
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -164,6 +169,7 @@ CPU4: cpu@400 {
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -184,6 +190,7 @@ CPU5: cpu@500 {
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -204,6 +211,7 @@ CPU6: cpu@600 {
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -224,6 +232,7 @@ CPU7: cpu@700 {
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
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