Commit 9da96c5e authored by Kevin Lo's avatar Kevin Lo Committed by Kalle Valo

rtlwifi: fix REG_USTIME_TSF register definition

The REG_USTIME_TSF (US Time Tuning for TSF) definition of Realtek chips
should be 0x55C.
Signed-off-by: default avatarKevin Lo <kevlo@kevlo.org>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent 1278bd14
...@@ -248,7 +248,6 @@ ...@@ -248,7 +248,6 @@
#define REG_RD_NAV_NXT 0x0544 #define REG_RD_NAV_NXT 0x0544
#define REG_NAV_PROT_LEN 0x0546 #define REG_NAV_PROT_LEN 0x0546
#define REG_BCN_CTRL 0x0550 #define REG_BCN_CTRL 0x0550
#define REG_USTIME_TSF 0x0551
#define REG_MBID_NUM 0x0552 #define REG_MBID_NUM 0x0552
#define REG_DUAL_TSF_RST 0x0553 #define REG_DUAL_TSF_RST 0x0553
#define REG_BCN_INTERVAL 0x0554 #define REG_BCN_INTERVAL 0x0554
...@@ -256,6 +255,7 @@ ...@@ -256,6 +255,7 @@
#define REG_DRVERLYINT 0x0558 #define REG_DRVERLYINT 0x0558
#define REG_BCNDMATIM 0x0559 #define REG_BCNDMATIM 0x0559
#define REG_ATIMWND 0x055A #define REG_ATIMWND 0x055A
#define REG_USTIME_TSF 0x055C
#define REG_BCN_MAX_ERR 0x055D #define REG_BCN_MAX_ERR 0x055D
#define REG_RXTSF_OFFSET_CCK 0x055E #define REG_RXTSF_OFFSET_CCK 0x055E
#define REG_RXTSF_OFFSET_OFDM 0x055F #define REG_RXTSF_OFFSET_OFDM 0x055F
......
...@@ -227,7 +227,6 @@ ...@@ -227,7 +227,6 @@
#define REG_RD_NAV_NXT 0x0544 #define REG_RD_NAV_NXT 0x0544
#define REG_NAV_PROT_LEN 0x0546 #define REG_NAV_PROT_LEN 0x0546
#define REG_BCN_CTRL 0x0550 #define REG_BCN_CTRL 0x0550
#define REG_USTIME_TSF 0x0551
#define REG_MBID_NUM 0x0552 #define REG_MBID_NUM 0x0552
#define REG_DUAL_TSF_RST 0x0553 #define REG_DUAL_TSF_RST 0x0553
#define REG_BCN_INTERVAL 0x0554 #define REG_BCN_INTERVAL 0x0554
...@@ -235,6 +234,7 @@ ...@@ -235,6 +234,7 @@
#define REG_DRVERLYINT 0x0558 #define REG_DRVERLYINT 0x0558
#define REG_BCNDMATIM 0x0559 #define REG_BCNDMATIM 0x0559
#define REG_ATIMWND 0x055A #define REG_ATIMWND 0x055A
#define REG_USTIME_TSF 0x055C
#define REG_BCN_MAX_ERR 0x055D #define REG_BCN_MAX_ERR 0x055D
#define REG_RXTSF_OFFSET_CCK 0x055E #define REG_RXTSF_OFFSET_CCK 0x055E
#define REG_RXTSF_OFFSET_OFDM 0x055F #define REG_RXTSF_OFFSET_OFDM 0x055F
......
...@@ -255,7 +255,6 @@ ...@@ -255,7 +255,6 @@
#define REG_RD_NAV_NXT 0x0544 #define REG_RD_NAV_NXT 0x0544
#define REG_NAV_PROT_LEN 0x0546 #define REG_NAV_PROT_LEN 0x0546
#define REG_BCN_CTRL 0x0550 #define REG_BCN_CTRL 0x0550
#define REG_USTIME_TSF 0x0551
#define REG_MBID_NUM 0x0552 #define REG_MBID_NUM 0x0552
#define REG_DUAL_TSF_RST 0x0553 #define REG_DUAL_TSF_RST 0x0553
#define REG_BCN_INTERVAL 0x0554 #define REG_BCN_INTERVAL 0x0554
...@@ -263,6 +262,7 @@ ...@@ -263,6 +262,7 @@
#define REG_DRVERLYINT 0x0558 #define REG_DRVERLYINT 0x0558
#define REG_BCNDMATIM 0x0559 #define REG_BCNDMATIM 0x0559
#define REG_ATIMWND 0x055A #define REG_ATIMWND 0x055A
#define REG_USTIME_TSF 0x055C
#define REG_BCN_MAX_ERR 0x055D #define REG_BCN_MAX_ERR 0x055D
#define REG_RXTSF_OFFSET_CCK 0x055E #define REG_RXTSF_OFFSET_CCK 0x055E
#define REG_RXTSF_OFFSET_OFDM 0x055F #define REG_RXTSF_OFFSET_OFDM 0x055F
......
...@@ -217,7 +217,6 @@ ...@@ -217,7 +217,6 @@
#define REG_RD_NAV_NXT 0x0544 #define REG_RD_NAV_NXT 0x0544
#define REG_NAV_PROT_LEN 0x0546 #define REG_NAV_PROT_LEN 0x0546
#define REG_BCN_CTRL 0x0550 #define REG_BCN_CTRL 0x0550
#define REG_USTIME_TSF 0x0551
#define REG_MBID_NUM 0x0552 #define REG_MBID_NUM 0x0552
#define REG_DUAL_TSF_RST 0x0553 #define REG_DUAL_TSF_RST 0x0553
#define REG_BCN_INTERVAL 0x0554 #define REG_BCN_INTERVAL 0x0554
...@@ -225,6 +224,7 @@ ...@@ -225,6 +224,7 @@
#define REG_DRVERLYINT 0x0558 #define REG_DRVERLYINT 0x0558
#define REG_BCNDMATIM 0x0559 #define REG_BCNDMATIM 0x0559
#define REG_ATIMWND 0x055A #define REG_ATIMWND 0x055A
#define REG_USTIME_TSF 0x055C
#define REG_BCN_MAX_ERR 0x055D #define REG_BCN_MAX_ERR 0x055D
#define REG_RXTSF_OFFSET_CCK 0x055E #define REG_RXTSF_OFFSET_CCK 0x055E
#define REG_RXTSF_OFFSET_OFDM 0x055F #define REG_RXTSF_OFFSET_OFDM 0x055F
......
...@@ -261,7 +261,6 @@ ...@@ -261,7 +261,6 @@
#define REG_RD_NAV_NXT 0x0544 #define REG_RD_NAV_NXT 0x0544
#define REG_NAV_PROT_LEN 0x0546 #define REG_NAV_PROT_LEN 0x0546
#define REG_BCN_CTRL 0x0550 #define REG_BCN_CTRL 0x0550
#define REG_USTIME_TSF 0x0551
#define REG_MBID_NUM 0x0552 #define REG_MBID_NUM 0x0552
#define REG_DUAL_TSF_RST 0x0553 #define REG_DUAL_TSF_RST 0x0553
#define REG_BCN_INTERVAL 0x0554 #define REG_BCN_INTERVAL 0x0554
...@@ -269,6 +268,7 @@ ...@@ -269,6 +268,7 @@
#define REG_DRVERLYINT 0x0558 #define REG_DRVERLYINT 0x0558
#define REG_BCNDMATIM 0x0559 #define REG_BCNDMATIM 0x0559
#define REG_ATIMWND 0x055A #define REG_ATIMWND 0x055A
#define REG_USTIME_TSF 0x055C
#define REG_BCN_MAX_ERR 0x055D #define REG_BCN_MAX_ERR 0x055D
#define REG_RXTSF_OFFSET_CCK 0x055E #define REG_RXTSF_OFFSET_CCK 0x055E
#define REG_RXTSF_OFFSET_OFDM 0x055F #define REG_RXTSF_OFFSET_OFDM 0x055F
......
...@@ -267,7 +267,6 @@ ...@@ -267,7 +267,6 @@
#define REG_RD_NAV_NXT 0x0544 #define REG_RD_NAV_NXT 0x0544
#define REG_NAV_PROT_LEN 0x0546 #define REG_NAV_PROT_LEN 0x0546
#define REG_BCN_CTRL 0x0550 #define REG_BCN_CTRL 0x0550
#define REG_USTIME_TSF 0x0551
#define REG_MBID_NUM 0x0552 #define REG_MBID_NUM 0x0552
#define REG_DUAL_TSF_RST 0x0553 #define REG_DUAL_TSF_RST 0x0553
#define REG_BCN_INTERVAL 0x0554 #define REG_BCN_INTERVAL 0x0554
...@@ -275,6 +274,7 @@ ...@@ -275,6 +274,7 @@
#define REG_DRVERLYINT 0x0558 #define REG_DRVERLYINT 0x0558
#define REG_BCNDMATIM 0x0559 #define REG_BCNDMATIM 0x0559
#define REG_ATIMWND 0x055A #define REG_ATIMWND 0x055A
#define REG_USTIME_TSF 0x055C
#define REG_BCN_MAX_ERR 0x055D #define REG_BCN_MAX_ERR 0x055D
#define REG_RXTSF_OFFSET_CCK 0x055E #define REG_RXTSF_OFFSET_CCK 0x055E
#define REG_RXTSF_OFFSET_OFDM 0x055F #define REG_RXTSF_OFFSET_OFDM 0x055F
......
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