Commit 9db4a9c7 authored by Jesse Barnes's avatar Jesse Barnes Committed by Chris Wilson

drm/i915: cleanup per-pipe reg usage

We had some conversions over to the _PIPE macros, but didn't get
everything.  So hide the per-pipe regs with an _ (still used in a few
places for legacy) and add a few _PIPE based macros, then make sure
everyone uses them.

[update: remove usage of non-existent no-op macro]
[update 2: keep modesetting suspend/resume code, update to new reg names]
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
[ickle: stylistic cleanups for checkpatch and taste]
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 8d7e3de1
...@@ -326,21 +326,21 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data) ...@@ -326,21 +326,21 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data)
struct intel_crtc *crtc; struct intel_crtc *crtc;
list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
const char *pipe = crtc->pipe ? "B" : "A"; const char pipe = pipe_name(crtc->pipe);
const char *plane = crtc->plane ? "B" : "A"; const char plane = plane_name(crtc->plane);
struct intel_unpin_work *work; struct intel_unpin_work *work;
spin_lock_irqsave(&dev->event_lock, flags); spin_lock_irqsave(&dev->event_lock, flags);
work = crtc->unpin_work; work = crtc->unpin_work;
if (work == NULL) { if (work == NULL) {
seq_printf(m, "No flip due on pipe %s (plane %s)\n", seq_printf(m, "No flip due on pipe %c (plane %c)\n",
pipe, plane); pipe, plane);
} else { } else {
if (!work->pending) { if (!work->pending) {
seq_printf(m, "Flip queued on pipe %s (plane %s)\n", seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
pipe, plane); pipe, plane);
} else { } else {
seq_printf(m, "Flip pending (waiting for vsync) on pipe %s (plane %s)\n", seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
pipe, plane); pipe, plane);
} }
if (work->enable_stall_check) if (work->enable_stall_check)
...@@ -458,7 +458,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) ...@@ -458,7 +458,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev; struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
int ret, i; int ret, i, pipe;
ret = mutex_lock_interruptible(&dev->struct_mutex); ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret) if (ret)
...@@ -471,10 +471,10 @@ static int i915_interrupt_info(struct seq_file *m, void *data) ...@@ -471,10 +471,10 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
I915_READ(IIR)); I915_READ(IIR));
seq_printf(m, "Interrupt mask: %08x\n", seq_printf(m, "Interrupt mask: %08x\n",
I915_READ(IMR)); I915_READ(IMR));
seq_printf(m, "Pipe A stat: %08x\n", for_each_pipe(pipe)
I915_READ(PIPEASTAT)); seq_printf(m, "Pipe %c stat: %08x\n",
seq_printf(m, "Pipe B stat: %08x\n", pipe_name(pipe),
I915_READ(PIPEBSTAT)); I915_READ(PIPESTAT(pipe)));
} else { } else {
seq_printf(m, "North Display Interrupt enable: %08x\n", seq_printf(m, "North Display Interrupt enable: %08x\n",
I915_READ(DEIER)); I915_READ(DEIER));
......
...@@ -2005,7 +2005,12 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) ...@@ -2005,7 +2005,12 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
spin_lock_init(&dev_priv->irq_lock); spin_lock_init(&dev_priv->irq_lock);
spin_lock_init(&dev_priv->error_lock); spin_lock_init(&dev_priv->error_lock);
ret = drm_vblank_init(dev, I915_NUM_PIPE); if (IS_MOBILE(dev) || !IS_GEN2(dev))
dev_priv->num_pipe = 2;
else
dev_priv->num_pipe = 1;
ret = drm_vblank_init(dev, dev_priv->num_pipe);
if (ret) if (ret)
goto out_gem_unload; goto out_gem_unload;
......
...@@ -50,17 +50,22 @@ ...@@ -50,17 +50,22 @@
enum pipe { enum pipe {
PIPE_A = 0, PIPE_A = 0,
PIPE_B, PIPE_B,
PIPE_C,
I915_MAX_PIPES
}; };
#define pipe_name(p) ((p) + 'A')
enum plane { enum plane {
PLANE_A = 0, PLANE_A = 0,
PLANE_B, PLANE_B,
PLANE_C,
}; };
#define plane_name(p) ((p) + 'A')
#define I915_NUM_PIPE 2
#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
/* Interface history: /* Interface history:
* *
* 1.1: Original. * 1.1: Original.
...@@ -143,8 +148,7 @@ struct intel_display_error_state; ...@@ -143,8 +148,7 @@ struct intel_display_error_state;
struct drm_i915_error_state { struct drm_i915_error_state {
u32 eir; u32 eir;
u32 pgtbl_er; u32 pgtbl_er;
u32 pipeastat; u32 pipestat[I915_MAX_PIPES];
u32 pipebstat;
u32 ipeir; u32 ipeir;
u32 ipehr; u32 ipehr;
u32 instdone; u32 instdone;
......
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
...@@ -129,10 +129,7 @@ static void intel_crt_mode_set(struct drm_encoder *encoder, ...@@ -129,10 +129,7 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
u32 adpa, dpll_md; u32 adpa, dpll_md;
u32 adpa_reg; u32 adpa_reg;
if (intel_crtc->pipe == 0) dpll_md_reg = DPLL_MD(intel_crtc->pipe);
dpll_md_reg = DPLL_A_MD;
else
dpll_md_reg = DPLL_B_MD;
if (HAS_PCH_SPLIT(dev)) if (HAS_PCH_SPLIT(dev))
adpa_reg = PCH_ADPA; adpa_reg = PCH_ADPA;
...@@ -160,17 +157,16 @@ static void intel_crt_mode_set(struct drm_encoder *encoder, ...@@ -160,17 +157,16 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
adpa |= PORT_TRANS_A_SEL_CPT; adpa |= PORT_TRANS_A_SEL_CPT;
else else
adpa |= ADPA_PIPE_A_SELECT; adpa |= ADPA_PIPE_A_SELECT;
if (!HAS_PCH_SPLIT(dev))
I915_WRITE(BCLRPAT_A, 0);
} else { } else {
if (HAS_PCH_CPT(dev)) if (HAS_PCH_CPT(dev))
adpa |= PORT_TRANS_B_SEL_CPT; adpa |= PORT_TRANS_B_SEL_CPT;
else else
adpa |= ADPA_PIPE_B_SELECT; adpa |= ADPA_PIPE_B_SELECT;
if (!HAS_PCH_SPLIT(dev))
I915_WRITE(BCLRPAT_B, 0);
} }
if (!HAS_PCH_SPLIT(dev))
I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
I915_WRITE(adpa_reg, adpa); I915_WRITE(adpa_reg, adpa);
} }
...@@ -353,21 +349,12 @@ intel_crt_load_detect(struct drm_crtc *crtc, struct intel_crt *crt) ...@@ -353,21 +349,12 @@ intel_crt_load_detect(struct drm_crtc *crtc, struct intel_crt *crt)
DRM_DEBUG_KMS("starting load-detect on CRT\n"); DRM_DEBUG_KMS("starting load-detect on CRT\n");
if (pipe == 0) { bclrpat_reg = BCLRPAT(pipe);
bclrpat_reg = BCLRPAT_A; vtotal_reg = VTOTAL(pipe);
vtotal_reg = VTOTAL_A; vblank_reg = VBLANK(pipe);
vblank_reg = VBLANK_A; vsync_reg = VSYNC(pipe);
vsync_reg = VSYNC_A; pipeconf_reg = PIPECONF(pipe);
pipeconf_reg = PIPEACONF; pipe_dsl_reg = PIPEDSL(pipe);
pipe_dsl_reg = PIPEADSL;
} else {
bclrpat_reg = BCLRPAT_B;
vtotal_reg = VTOTAL_B;
vblank_reg = VBLANK_B;
vsync_reg = VSYNC_B;
pipeconf_reg = PIPEBCONF;
pipe_dsl_reg = PIPEBDSL;
}
save_bclrpat = I915_READ(bclrpat_reg); save_bclrpat = I915_READ(bclrpat_reg);
save_vtotal = I915_READ(vtotal_reg); save_vtotal = I915_READ(vtotal_reg);
......
This diff is collapsed.
...@@ -685,6 +685,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, ...@@ -685,6 +685,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int lane_count = 4, bpp = 24; int lane_count = 4, bpp = 24;
struct intel_dp_m_n m_n; struct intel_dp_m_n m_n;
int pipe = intel_crtc->pipe;
/* /*
* Find the lane count in the intel_encoder private * Find the lane count in the intel_encoder private
...@@ -715,39 +716,19 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, ...@@ -715,39 +716,19 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
mode->clock, adjusted_mode->clock, &m_n); mode->clock, adjusted_mode->clock, &m_n);
if (HAS_PCH_SPLIT(dev)) { if (HAS_PCH_SPLIT(dev)) {
if (intel_crtc->pipe == 0) { I915_WRITE(TRANSDATA_M1(pipe),
I915_WRITE(TRANSA_DATA_M1,
((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
m_n.gmch_m); m_n.gmch_m);
I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n); I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m); I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n); I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
} else { } else {
I915_WRITE(TRANSB_DATA_M1, I915_WRITE(PIPE_GMCH_DATA_M(pipe),
((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
m_n.gmch_m); m_n.gmch_m);
I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n); I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m); I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n); I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
}
} else {
if (intel_crtc->pipe == 0) {
I915_WRITE(PIPEA_GMCH_DATA_M,
((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
m_n.gmch_m);
I915_WRITE(PIPEA_GMCH_DATA_N,
m_n.gmch_n);
I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
} else {
I915_WRITE(PIPEB_GMCH_DATA_M,
((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
m_n.gmch_m);
I915_WRITE(PIPEB_GMCH_DATA_N,
m_n.gmch_n);
I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
}
} }
} }
......
...@@ -178,7 +178,7 @@ static void intel_dvo_mode_set(struct drm_encoder *encoder, ...@@ -178,7 +178,7 @@ static void intel_dvo_mode_set(struct drm_encoder *encoder,
int pipe = intel_crtc->pipe; int pipe = intel_crtc->pipe;
u32 dvo_val; u32 dvo_val;
u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg; u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;
int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; int dpll_reg = DPLL(pipe);
switch (dvo_reg) { switch (dvo_reg) {
case DVOA: case DVOA:
......
...@@ -231,6 +231,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, ...@@ -231,6 +231,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
struct intel_lvds *intel_lvds = to_intel_lvds(encoder); struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
struct drm_encoder *tmp_encoder; struct drm_encoder *tmp_encoder;
u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
int pipe;
/* Should never happen!! */ /* Should never happen!! */
if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
...@@ -283,8 +284,8 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, ...@@ -283,8 +284,8 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
* to register description and PRM. * to register description and PRM.
* Change the value here to see the borders for debugging * Change the value here to see the borders for debugging
*/ */
I915_WRITE(BCLRPAT_A, 0); for_each_pipe(pipe)
I915_WRITE(BCLRPAT_B, 0); I915_WRITE(BCLRPAT(pipe), 0);
switch (intel_lvds->fitting_mode) { switch (intel_lvds->fitting_mode) {
case DRM_MODE_SCALE_CENTER: case DRM_MODE_SCALE_CENTER:
......
...@@ -255,7 +255,7 @@ i830_activate_pipe_a(struct drm_device *dev) ...@@ -255,7 +255,7 @@ i830_activate_pipe_a(struct drm_device *dev)
return 0; return 0;
/* most i8xx have pipe a forced on, so don't trust dpms mode */ /* most i8xx have pipe a forced on, so don't trust dpms mode */
if (I915_READ(PIPEACONF) & PIPECONF_ENABLE) if (I915_READ(_PIPEACONF) & PIPECONF_ENABLE)
return 0; return 0;
crtc_funcs = crtc->base.helper_private; crtc_funcs = crtc->base.helper_private;
......
...@@ -1006,6 +1006,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, ...@@ -1006,6 +1006,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
const struct video_levels *video_levels; const struct video_levels *video_levels;
const struct color_conversion *color_conversion; const struct color_conversion *color_conversion;
bool burst_ena; bool burst_ena;
int pipe = intel_crtc->pipe;
if (!tv_mode) if (!tv_mode)
return; /* can't happen (mode_prepare prevents this) */ return; /* can't happen (mode_prepare prevents this) */
...@@ -1149,14 +1150,11 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, ...@@ -1149,14 +1150,11 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
((video_levels->black << TV_BLACK_LEVEL_SHIFT) | ((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
(video_levels->blank << TV_BLANK_LEVEL_SHIFT))); (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
{ {
int pipeconf_reg = (intel_crtc->pipe == 0) ? int pipeconf_reg = PIPECONF(pipe);
PIPEACONF : PIPEBCONF; int dspcntr_reg = DSPCNTR(pipe);
int dspcntr_reg = (intel_crtc->plane == 0) ?
DSPACNTR : DSPBCNTR;
int pipeconf = I915_READ(pipeconf_reg); int pipeconf = I915_READ(pipeconf_reg);
int dspcntr = I915_READ(dspcntr_reg); int dspcntr = I915_READ(dspcntr_reg);
int dspbase_reg = (intel_crtc->plane == 0) ? int dspbase_reg = DSPADDR(pipe);
DSPAADDR : DSPBADDR;
int xpos = 0x0, ypos = 0x0; int xpos = 0x0, ypos = 0x0;
unsigned int xsize, ysize; unsigned int xsize, ysize;
/* Pipe must be off here */ /* Pipe must be off here */
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment