Commit 9e14d4f1 authored by hersen wu's avatar hersen wu Committed by Alex Deucher

drm/amd/display: skip dsc config for navi10 bring up

[why] we meet a bug when program dsc register even dsc mode is not
enabled. disable dsc config for now. we will re-visit this issue.
Signed-off-by: default avatarhersen wu <hersenxs.wu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0fcf90d1
...@@ -191,6 +191,15 @@ void optc2_set_dsc_config(struct timing_generator *optc, ...@@ -191,6 +191,15 @@ void optc2_set_dsc_config(struct timing_generator *optc,
uint32_t dsc_slice_width) uint32_t dsc_slice_width)
{ {
struct optc *optc1 = DCN10TG_FROM_TG(optc); struct optc *optc1 = DCN10TG_FROM_TG(optc);
uint32_t data_format = 0;
/* skip if dsc mode is not changed */
data_format = dm_read_reg(CTX, REG(OPTC_DATA_FORMAT_CONTROL));
data_format = data_format & 0x30; /* bit5:4 */
data_format = data_format >> 4;
if (data_format == dsc_mode)
return;
REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,
OPTC_DSC_MODE, dsc_mode); OPTC_DSC_MODE, dsc_mode);
......
...@@ -670,7 +670,7 @@ static const struct dc_debug_options debug_defaults_drv = { ...@@ -670,7 +670,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.max_downscale_src_width = 5120,/*upto 5K*/ .max_downscale_src_width = 5120,/*upto 5K*/
.disable_pplib_wm_range = false, .disable_pplib_wm_range = false,
.scl_reset_length10 = true, .scl_reset_length10 = true,
.sanity_checks = true, .sanity_checks = false,
.disable_tri_buf = true, .disable_tri_buf = true,
}; };
......
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