Commit 9ef9edb9 authored by Chia-Yuan Li's avatar Chia-Yuan Li Committed by Kalle Valo

wifi: rtw89: set response rate selection

With suitable response rate, it can acknowledge peer packets are received.
Otherwise, peer could re-transmit again due to missing of ACK frames.
To achieve this, refer to RX rate and CMAC table to choose the smaller
as initial response rate.
Signed-off-by: default avatarChia-Yuan Li <leo.li@realtek.com>
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220908051257.25353-6-pkshih@realtek.com
parent 755fda37
......@@ -2553,6 +2553,11 @@ struct rtw89_imr_info {
u32 tmac_imr_set;
};
struct rtw89_rrsr_cfgs {
struct rtw89_reg3_def ref_rate;
struct rtw89_reg3_def rsc;
};
struct rtw89_dig_regs {
u32 seg0_pd_reg;
u32 pd_lower_bound_mask;
......@@ -2677,6 +2682,7 @@ struct rtw89_chip_info {
const struct rtw89_reg_def *dcfo_comp;
u8 dcfo_comp_sft;
const struct rtw89_imr_info *imr_info;
const struct rtw89_rrsr_cfgs *rrsr_cfgs;
};
union rtw89_bus_info {
......
......@@ -1979,6 +1979,8 @@ static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs;
u32 reg, val, sifs;
int ret;
......@@ -2009,6 +2011,11 @@ static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx);
rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN);
reg = rtw89_mac_reg_by_idx(rrsr->ref_rate.addr, mac_idx);
rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data);
reg = rtw89_mac_reg_by_idx(rrsr->rsc.addr, mac_idx);
rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data);
return 0;
}
......@@ -2087,6 +2094,7 @@ static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx)
{
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
u32 val, reg;
int ret;
......@@ -2101,6 +2109,11 @@ static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx)
val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK);
rtw89_write32(rtwdev, reg, val);
if (chip_id == RTL8852A || chip_id == RTL8852B) {
reg = rtw89_mac_reg_by_idx(R_AX_PTCL_RRSR1, mac_idx);
rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN);
}
return 0;
}
......
......@@ -1833,6 +1833,13 @@
#define B_AX_TXSC_40M_MASK GENMASK(7, 4)
#define B_AX_TXSC_20M_MASK GENMASK(3, 0)
#define R_AX_PTCL_RRSR1 0xC090
#define R_AX_PTCL_RRSR1_C1 0xE090
#define B_AX_RRSR_RATE_EN_MASK GENMASK(11, 8)
#define RRSR_OFDM_CCK_EN 3
#define B_AX_RSC_MASK GENMASK(7, 6)
#define B_AX_RRSR_CCK_MASK GENMASK(3, 0)
#define R_AX_CMAC_ERR_IMR 0xC160
#define R_AX_CMAC_ERR_IMR_C1 0xE160
#define B_AX_WMAC_TX_ERR_IND_EN BIT(7)
......@@ -2563,6 +2570,20 @@
#define WMAC_SPEC_SIFS_OFDM_52C 0x11
#define WMAC_SPEC_SIFS_CCK 0xA
#define R_AX_TRXPTCL_RRSR_CTL_0 0xCC08
#define R_AX_TRXPTCL_RRSR_CTL_0_C1 0xEC08
#define B_AX_RESP_TX_MACID_CCA_TH_EN BIT(31)
#define B_AX_RESP_TX_PWRMODE_MASK GENMASK(30, 28)
#define B_AX_FTM_RRSR_RATE_EN_MASK GENMASK(27, 24)
#define B_AX_NESS_MASK GENMASK(23, 22)
#define B_AX_WMAC_RESP_DOPPLEB_AX_EN BIT(21)
#define B_AX_WMAC_RESP_DCM_EN BIT(20)
#define B_AX_WMAC_RRSB_AX_CCK_MASK GENMASK(19, 16)
#define B_AX_WMAC_RESP_RATE_EN_MASK GENMASK(15, 12)
#define B_AX_WMAC_RESP_RSC_MASK GENMASK(11, 10)
#define B_AX_WMAC_RESP_REF_RATE_SEL BIT(9)
#define B_AX_WMAC_RESP_REF_RATE_MASK GENMASK(8, 0)
#define R_AX_MAC_LOOPBACK 0xCC20
#define R_AX_MAC_LOOPBACK_C1 0xEC20
#define B_AX_MACLBK_EN BIT(0)
......
......@@ -453,6 +453,11 @@ static const struct rtw89_imr_info rtw8852a_imr_info = {
.tmac_imr_set = B_AX_TMAC_IMR_SET,
};
static const struct rtw89_rrsr_cfgs rtw8852a_rrsr_cfgs = {
.ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
.rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
};
static const struct rtw89_dig_regs rtw8852a_dig_regs = {
.seg0_pd_reg = R_SEG0R_PD,
.pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
......@@ -2224,7 +2229,8 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
.page_regs = &rtw8852a_page_regs,
.dcfo_comp = &rtw8852a_dcfo_comp,
.dcfo_comp_sft = 3,
.imr_info = &rtw8852a_imr_info
.imr_info = &rtw8852a_imr_info,
.rrsr_cfgs = &rtw8852a_rrsr_cfgs,
};
EXPORT_SYMBOL(rtw8852a_chip_info);
......
......@@ -131,6 +131,11 @@ static const struct rtw89_imr_info rtw8852c_imr_info = {
.tmac_imr_set = B_AX_TMAC_IMR_SET_V1,
};
static const struct rtw89_rrsr_cfgs rtw8852c_rrsr_cfgs = {
.ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
.rsc = {R_AX_PTCL_RRSR1, B_AX_RSC_MASK, 2},
};
static const struct rtw89_dig_regs rtw8852c_dig_regs = {
.seg0_pd_reg = R_SEG0R_PD,
.pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
......@@ -3068,7 +3073,8 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
.page_regs = &rtw8852c_page_regs,
.dcfo_comp = &rtw8852c_dcfo_comp,
.dcfo_comp_sft = 5,
.imr_info = &rtw8852c_imr_info
.imr_info = &rtw8852c_imr_info,
.rrsr_cfgs = &rtw8852c_rrsr_cfgs,
};
EXPORT_SYMBOL(rtw8852c_chip_info);
......
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