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Commit 9f1a2068 authored by Russell King's avatar Russell King
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Convert ARM92x/ARM1020 specific configuration symbols to generic CPU 

symbols.  Remove unused flush_page_to_ram in ARM code.
parent 1b00b832
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Showing with 141 additions and 425 deletions
arch/arm/Config.help
View file @ 9f1a2068
......@@ -678,23 +678,6 @@ CONFIG_CPU_ARM922T
Say Y if you want support for the ARM922T processor.
Otherwise, say N.
CONFIG_CPU_ARM922_CPU_IDLE
Saying Y here will allow the processor to enter a low power
mode whilst waiting for an interrupt in idle. If you're unsure
say Y.
CONFIG_CPU_ARM922_I_CACHE_ON
Say Y here to enable the processor instruction cache. Unless
you have a reason not to, say Y.
CONFIG_CPU_ARM922_D_CACHE_ON
Say Y here to enable the processor data cache. Unless
you have a reason not to, say Y.
CONFIG_CPU_ARM922_WRITETHROUGH
Say Y here to use the data cache in writethough mode. Unless you
specifically require this, say N.
CONFIG_CPU_ARM1020
The ARM1020 is the cached version of the ARM10 processor,
with an addition of a floating-point unit.
......@@ -711,6 +694,25 @@ CONFIG_CPU_SA110
Say Y if you want support for the SA-110 processor.
Otherwise, say N.
CONFIG_CPU_ICACHE_DISABLE
Say Y here to disable the processor instruction cache. Unless
you have a reason not to or are unsure, say N.
CONFIG_CPU_DCACHE_DISABLE
Say Y here to disable the processor data cache. Unless
you have a reason not to or are unsure, say N.
CONFIG_CPU_DCACHE_WRITETHROUGH
Say Y here to use the data cache in writethough mode. Unless you
specifically require this or are unsure, say N.
CONFIG_CPU_CACHE_ROUND_ROBIN
Say Y here to use the predictable round-robin cache replacement
policy. Unless you specifically require this or are unsure, say N.
CONFIG_CPU_BPREDICT_DISABLE
Say Y here to disable branch prediction. If unsure, say N.
CONFIG_FPE_NWFPE
Say Y to include the NWFPE floating point emulator in the kernel.
This is necessary to run most binaries. Linux does not currently
......
arch/arm/config.in
View file @ 9f1a2068
......@@ -218,7 +218,7 @@ fi
comment 'Processor Type'
# Firstly, figure out what processor architecture version we should be using.
# This depends more on the machine type than anything else.
# This defines the compiler instruction set which depends on the machine type.
if [ "$CONFIG_ARCH_RPC" = "y" -o "$CONFIG_ARCH_CLPS7500" = "y" ]; then
define_bool CONFIG_CPU_32v3 y
......@@ -235,10 +235,15 @@ if [ "$CONFIG_ARCH_EBSA110" = "y" -o "$CONFIG_FOOTBRIDGE" = "y" -o \
else
define_bool CONFIG_CPU_32v4 n
fi
if [ "$CONFIG_ARCH_IOP310" = "y" -o "$CONFIG_ARCH_ADIFCC" = "y" ]; then
define_bool CONFIG_CPU_32v5 y
else
define_bool CONFIG_CPU_32v5 n
fi
# Select CPU types depending on the architecture selected.
# We use this to select which CPUs are supported, and to select
# the compiler tuning options.
# Select CPU types depending on the architecture selected. This selects
# which CPUs we support in the kernel image, and the compiler instruction
# optimiser behaviour.
# ARM610
if [ "$CONFIG_ARCH_RPC" = "y" ]; then
......@@ -277,14 +282,6 @@ if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then
else
define_bool CONFIG_CPU_ARM920T n
fi
if [ "$CONFIG_CPU_ARM920T" = "y" ]; then
bool ' ARM920T CPU idle' CONFIG_CPU_ARM920_CPU_IDLE
bool ' ARM920T I-Cache on' CONFIG_CPU_ARM920_I_CACHE_ON
bool ' ARM920T D-Cache on' CONFIG_CPU_ARM920_D_CACHE_ON
if [ "$CONFIG_CPU_ARM920_D_CACHE_ON" = "y" ] ; then
bool ' Force write through caches on ARM920T' CONFIG_CPU_ARM920_WRITETHROUGH
fi
fi
# ARM922T
if [ "$CONFIG_ARCH_CAMELOT" = "y" ]; then
......@@ -292,14 +289,6 @@ if [ "$CONFIG_ARCH_CAMELOT" = "y" ]; then
else
define_bool CONFIG_CPU_ARM922T n
fi
if [ "$CONFIG_CPU_ARM922T" = "y" ]; then
bool ' ARM922T CPU idle' CONFIG_CPU_ARM922_CPU_IDLE
bool ' ARM922T I-Cache on' CONFIG_CPU_ARM922_I_CACHE_ON
bool ' ARM922T D-Cache on' CONFIG_CPU_ARM922_D_CACHE_ON
if [ "$CONFIG_CPU_ARM922_D_CACHE_ON" = "y" ] ; then
bool ' Force write through caches on ARM922T' CONFIG_CPU_ARM922_WRITETHROUGH
fi
fi
# ARM926T
if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then
......@@ -307,18 +296,6 @@ if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then
else
define_bool CONFIG_CPU_ARM926T n
fi
if [ "$CONFIG_CPU_ARM926T" = "y" ]; then
bool ' ARM926T CPU idle' CONFIG_CPU_ARM926_CPU_IDLE
bool ' ARM926T I-Cache on' CONFIG_CPU_ARM926_I_CACHE_ON
bool ' ARM926T D-Cache on' CONFIG_CPU_ARM926_D_CACHE_ON
if [ "$CONFIG_CPU_ARM926_D_CACHE_ON" = "y" ] ; then
bool ' Force write through caches on ARM926T' CONFIG_CPU_ARM926_WRITETHROUGH
fi
if [ "$CONFIG_CPU_ARM926_I_CACHE_ON" = "y" -o \
"$CONFIG_CPU_ARM926_D_CACHE_ON" = "y" ]; then
bool ' Round robin I and D cache replacement algorithm' CONFIG_CPU_ARM926_ROUND_ROBIN
fi
fi
# ARM1020
if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then
......@@ -326,17 +303,6 @@ if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then
else
define_bool CONFIG_CPU_ARM1020 n
fi
if [ "$CONFIG_CPU_ARM1020" = "y" ]; then
bool ' ARM1020 I-Cache on' CONFIG_CPU_ARM1020_I_CACHE_ON
bool ' ARM10 D-Cache on' CONFIG_CPU_ARM1020_D_CACHE_ON
if [ "$CONFIG_CPU_ARM1020_D_CACHE_ON" = "y" ] ; then
bool ' Force write through caches on ARM1020' CONFIG_CPU_ARM1020_FORCE_WRITE_THROUGH
fi
if [ "$CONFIG_CPU_ARM1020_I_CACHE_ON" = "y" -o \
"$CONFIG_CPU_ARM1020_D_CACHE_ON" = "y" ]; then
bool ' Round robin I and D cache replacement algorithm' CONFIG_CPU_ARM1020_ROUND_ROBIN
fi
fi
# SA110
if [ "$CONFIG_ARCH_EBSA110" = "y" -o "$CONFIG_FOOTBRIDGE" = "y" -o \
......@@ -360,8 +326,9 @@ fi
# XScale
if [ "$CONFIG_ARCH_IOP310" = "y" -o "$CONFIG_ARCH_ADIFCC" = "y" ]; then
define_bool CONFIG_CPU_32v5 y
define_bool CONFIG_CPU_XSCALE y
else
define_bool CONFIG_CPU_XSCALE n
fi
#if [ "$CONFIG_CPU_XSCALE" = "y" ]; then
......@@ -374,9 +341,34 @@ else
define_bool CONFIG_XSCALE_PMU n
fi
if [ "$CONFIG_CPU_32" = "y" ]; then
comment 'Processor Features'
if [ "$CONFIG_CPU_ARM720T" = "y" -o "$CONFIG_CPU_ARM920T" = "y" -o \
"$CONFIG_CPU_ARM922T" = "y" -o "$CONFIG_CPU_ARM926T" = "y" -o \
"$CONFIG_CPU_ARM1020" = "y" -o "$CONFIG_CPU_XSCALE" = "y" ]; then
dep_bool 'Support Thumb instructions (experimental)' CONFIG_ARM_THUMB $CONFIG_EXPERIMENTAL
fi
if [ "$CONFIG_CPU_ARM920T" = "y" -o "$CONFIG_CPU_ARM922T" = "y" -o \
"$CONFIG_CPU_ARM926T" = "y" -o "$CONFIG_CPU_ARM1020" = "y" ]; then
bool 'Disable I-Cache' CONFIG_CPU_ICACHE_DISABLE
bool 'Disable D-Cache' CONFIG_CPU_DCACHE_DISABLE
if [ "$CONFIG_CPU_DISABLE_DCACHE" = "n" ]; then
bool 'Force write through D-cache' CONFIG_CPU_DCACHE_WRITETHROUGH
fi
fi
if [ "$CONFIG_CPU_ARM926T" = "y" -o "$CONFIG_CPU_ARM1020" = "y" ]; then
if [ "$CONFIG_CPU_ICACHE_DISABLE" = "n" -o "$CONFIG_CPU_DCACHE_DISABLE" = "n" ]; then
bool 'Round robin I and D cache replacement algorithm' CONFIG_CPU_CACHE_ROUND_ROBIN
fi
fi
if [ "$CONFIG_CPU_ARM1020" = "y" ]; then
bool 'Disable branch prediction' CONFIG_CPU_BPREDICT_DISABLE
fi
endmenu
mainmenu_option next_comment
comment 'General setup'
# Select various configuration options depending on the machine type
if [ "$CONFIG_ARCH_EDB7211" = "y" -o \
......@@ -386,11 +378,6 @@ else
define_bool CONFIG_DISCONTIGMEM n
fi
endmenu
mainmenu_option next_comment
comment 'General setup'
# Now handle the bus types
if [ "$CONFIG_ARCH_FTVPCI" = "y" -o \
"$CONFIG_ARCH_SHARK" = "y" -o \
......
arch/arm/mm/proc-arm1020.S
View file @ 9f1a2068
......@@ -21,6 +21,8 @@
*
* These are the low level assembler for performing cache and TLB
* functions on the arm1020.
*
* CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
*/
#include <linux/linkage.h>
#include <linux/config.h>
......@@ -107,10 +109,6 @@ ENTRY(cpu_arm1020_reset)
.align 5
ENTRY(cpu_arm1020_do_idle)
mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov r0, r0
mov r0, r0
#endif
mov pc, lr
/* ================================= CACHE ================================ */
......@@ -128,7 +126,7 @@ ENTRY(cpu_arm1020_do_idle)
ENTRY(cpu_arm1020_cache_clean_invalidate_all)
mov r2, #1
cpu_arm1020_cache_clean_invalidate_all_r2:
#ifdef CONFIG_CPU_ARM1020_D_CACHE_ON
#ifndef CONFIG_CPU_DCACHE_DISABLE
mcr p15, 0, ip, c7, c10, 4
mov r1, #0xf @ 16 segments
......@@ -137,9 +135,6 @@ cpu_arm1020_cache_clean_invalidate_all_r2:
orr ip, ip, r1, LSL #5 @ shift in/up index
mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
mcr p15, 0, ip, c7, c10, 4 @ drain WB
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov ip, ip
#endif
subs r3, r3, #1
cmp r3, #0
bge 2b @ entries 3F to 0
......@@ -147,16 +142,11 @@ cpu_arm1020_cache_clean_invalidate_all_r2:
cmp r1, #0
bge 1b @ segments 7 to 0
#endif
#ifdef CONFIG_CPU_ARM1020_I_CACHE_ON
#ifndef CONFIG_CPU_ICACHE_DISABLE
teq r2, #0
mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
#endif
mcr p15, 0, ip, c7, c10, 4 @ drain WB
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov ip, ip
mov ip, ip
#endif
mov pc, lr
/*
......@@ -175,60 +165,21 @@ ENTRY(cpu_arm1020_cache_clean_invalidate_range)
cmp r3, #MAX_AREA_SIZE
bgt cpu_arm1020_cache_clean_invalidate_all_r2
mcr p15, 0, r3, c7, c10, 4
#ifdef CONFIG_CPU_ARM1020_D_CACHE_ON
#ifndef CONFIG_CPU_DCACHE_DISABLE
1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
mcr p15, 0, r3, c7, c10, 4 @ drain WB
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
mcr p15, 0, r3, c7, c10, 4 @ drain WB
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov r0, r0
#endif
add r0, r0, #DCACHELINESIZE
cmp r0, r1
blt 1b
#endif
#ifdef CONFIG_CPU_ARM1020_I_CACHE_ON
#ifndef CONFIG_CPU_ICACHE_DISABLE
teq r2, #0
movne r0, #0
mcrne p15, 0, r0, c7, c5, 0 @ invalidate I cache
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov r0, r0
mov r0, r0
#endif
#endif
mov pc, lr
/*
* cpu_arm1020_flush_ram_page(page)
*
* clean and invalidate all cache lines associated with this area of memory
*
* page: page to clean and invalidate
*/
.align 5
ENTRY(cpu_arm1020_flush_ram_page)
mcr p15, 0, r1, c7, c10, 4
#ifdef CONFIG_CPU_ARM1020_D_CACHE_ON
mov r1, #PAGESIZE
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
mcr p15, 0, r0, c7, c10, 4 @ drain WB
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
mcr p15, 0, r0, c7, c10, 4 @ drain WB
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov r0, r0
mov r0, r0
#endif
subs r1, r1, #2 * DCACHELINESIZE
bne 1b
mov r0, #0
#endif
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov r0, r0
mov r0, r0
#endif
mov pc, lr
......@@ -247,41 +198,25 @@ ENTRY(cpu_arm1020_flush_ram_page)
*/
.align 5
ENTRY(cpu_arm1020_dcache_invalidate_range)
#ifdef CONFIG_CPU_ARM1020_D_CACHE_ON
#ifndef CONFIG_CPU_DCACHE_DISABLE
/* D cache are on */
tst r0, #DCACHELINESIZE - 1
bic r0, r0, #DCACHELINESIZE - 1
mcrne p15, 0, r0, c7, c10, 4
mcrne p15, 0, r0, c7, c10, 1 @ clean D entry at start
mcrne p15, 0, r0, c7, c10, 4 @ drain WB
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov r0, r0
mov r0, r0
#endif
tst r1, #DCACHELINESIZE - 1
mcrne p15, 0, r1, c7, c10, 4
mcrne p15, 0, r1, c7, c10, 1 @ clean D entry at end
mcrne p15, 0, r1, c7, c10, 4 @ drain WB
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov r1, r1
mov r1, r1
mov r1, r1
#endif
1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov r0, r0
#endif
add r0, r0, #DCACHELINESIZE
cmp r0, r1
blt 1b
#else
/* D cache off, but still drain the write buffer */
mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov r0, r0
mov r0, r0
#endif
#endif
mov pc, lr
......@@ -302,24 +237,16 @@ ENTRY(cpu_arm1020_dcache_clean_range)
cmp r3, #MAX_AREA_SIZE
bgt cpu_arm1020_cache_clean_invalidate_all_r2
mcr p15, 0, r3, c7, c10, 4
#ifdef CONFIG_CPU_ARM1020_D_CACHE_ON
#ifndef CONFIG_CPU_DCACHE_DISABLE
1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
mcr p15, 0, r3, c7, c10, 4 @ drain WB
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
mcr p15, 0, r3, c7, c10, 4 @ drain WB
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov r0, r0
#endif
add r0, r0, #DCACHELINESIZE
cmp r0, r1
blt 1b
#endif
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov r0, r0
mov r0, r0
#endif
mov pc, lr
/*
......@@ -339,25 +266,15 @@ ENTRY(cpu_arm1020_dcache_clean_range)
ENTRY(cpu_arm1020_dcache_clean_page)
mov r1, #PAGESIZE
mcr p15, 0, r0, c7, c10, 4
#ifdef CONFIG_CPU_ARM1020_D_CACHE_ON
#ifndef CONFIG_CPU_DCACHE_DISABLE
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry (drain is done by TLB fns)
mcr p15, 0, r0, c7, c10, 4 @ drain WB
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov r0, r0
#endif
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
mcr p15, 0, r0, c7, c10, 4 @ drain WB
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov r0, r0
#endif
add r0, r0, #DCACHELINESIZE
subs r1, r1, #2 * DCACHELINESIZE
bhi 1b
#endif
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov r0, r0
mov r0, r0
#endif
mov pc, lr
......@@ -373,16 +290,12 @@ ENTRY(cpu_arm1020_dcache_clean_page)
ENTRY(cpu_arm1020_dcache_clean_entry)
mov r1, #0
mcr p15, 0, r1, c7, c10, 4
#ifdef CONFIG_CPU_ARM1020_D_CACHE_ON
#ifndef CONFIG_CPU_DCACHE_DISABLE
mcr p15, 0, r0, c7, c10, 1 @ clean single D entry
mcr p15, 0, r1, c7, c10, 4 @ drain WB
#endif
#ifdef CONFIG_CPU_ARM1020_I_CACHE_ON
#ifndef CONFIG_CPU_ICACHE_DISABLE
mcr p15, 0, r1, c7, c5, 1 @ invalidate I entry
#endif
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov r1, r1
mov r1, r1
#endif
mov pc, lr
......@@ -399,25 +312,18 @@ ENTRY(cpu_arm1020_dcache_clean_entry)
.align 5
ENTRY(cpu_arm1020_icache_invalidate_range)
1: mcr p15, 0, r0, c7, c10, 4
#ifdef CONFIG_CPU_ARM1020_D_CACHE_ON
#ifndef CONFIG_CPU_DCACHE_DISABLE
mcr p15, 0, r0, c7, c10, 1 @ Clean D entry
mcr p15, 0, r0, c7, c10, 4 @ drain WB
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c10, 1 @ Clean D entry
mcr p15, 0, r0, c7, c10, 4 @ drain WB
#endif
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov r0, r0
#endif
add r0, r0, #DCACHELINESIZE
cmp r0, r1
blo 1b
ENTRY(cpu_arm1020_icache_invalidate_page)
mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov r0, r0
mov r0, r0
#endif
mov pc, lr
/* =============================== PageTable ============================== */
......@@ -431,7 +337,7 @@ ENTRY(cpu_arm1020_icache_invalidate_page)
*/
.align 5
ENTRY(cpu_arm1020_set_pgd)
#ifdef CONFIG_CPU_ARM1020_D_CACHE_ON
#ifndef CONFIG_CPU_DCACHE_DISABLE
mcr p15, 0, r3, c7, c10, 4
mov r1, #0xF @ 16 segments
1: mov r3, #0x3F @ 64 entries
......@@ -440,9 +346,6 @@ ENTRY(cpu_arm1020_set_pgd)
mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
mov ip, #0
mcr p15, 0, ip, c7, c10, 4
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov ip, ip
#endif
subs r3, r3, #1
cmp r3, #0
bge 2b @ entries 3F to 0
......@@ -452,16 +355,12 @@ ENTRY(cpu_arm1020_set_pgd)
#endif
mov r1, #0
#ifdef CONFIG_CPU_ARM1020_I_CACHE_ON
#ifndef CONFIG_CPU_ICACHE_DISABLE
mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
#endif
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov ip, ip
mov ip, ip
#endif
mov pc, lr
/*
......@@ -475,21 +374,17 @@ ENTRY(cpu_arm1020_set_pgd)
*/
.align 5
ENTRY(cpu_arm1020_set_pmd)
#ifdef CONFIG_CPU_ARM1020_FORCE_WRITE_THROUGH
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
eor r2, r1, #0x0a @ C & Section
tst r2, #0x0b
biceq r1, r1, #4 @ clear bufferable bit
#endif
str r1, [r0]
#ifdef CONFIG_CPU_ARM1020_D_CACHE_ON
#ifndef CONFIG_CPU_DCACHE_DISABLE
mcr p15, 0, r0, c7, c10, 4
mcr p15, 0, r0, c7, c10, 1 @ clean D entry (drain is done by TLB fns)
#endif
mcr p15, 0, r0, c7, c10, 4 @ drain WB
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov r0, r0
mov r0, r0
#endif
mov pc, lr
/*
......@@ -518,22 +413,18 @@ ENTRY(cpu_arm1020_set_pte)
tst r1, #LPTE_PRESENT | LPTE_YOUNG @ Present and Young?
movne r2, #0
#ifdef CONFIG_CPU_ARM1020_FORCE_WRITE_THROUGH
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
eor r3, r1, #0x0a @ C & small page?
tst r3, #0x0b
biceq r2, r2, #4
#endif
str r2, [r0] @ hardware version
mov r0, r0
#ifdef CONFIG_CPU_ARM1020_D_CACHE_ON
#ifndef CONFIG_CPU_DCACHE_DISABLE
mcr p15, 0, r0, c7, c10, 4
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
#endif
mcr p15, 0, r0, c7, c10, 4 @ drain WB
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
mov r0, r0
mov r0, r0
#endif
mov pc, lr
......@@ -541,24 +432,21 @@ cpu_manu_name:
.asciz "ARM/VLSI"
ENTRY(cpu_arm1020_name)
.ascii "Arm1020"
#if defined(CONFIG_CPU_ARM1020_CPU_IDLE)
.ascii "s"
#endif
#if defined(CONFIG_CPU_ARM1020_I_CACHE_ON)
#ifndef CONFIG_CPU_ICACHE_DISABLE
.ascii "i"
#endif
#if defined(CONFIG_CPU_ARM1020_D_CACHE_ON)
#ifndef CONFIG_CPU_DCACHE_DISABLE
.ascii "d"
#if defined(CONFIG_CPU_ARM1020_FORCE_WRITE_THROUGH)
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
.ascii "(wt)"
#else
.ascii "(wb)"
#endif
#endif
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
#ifndef CONFIG_CPU_BPREDICT_DISABLE
.ascii "B"
#endif
#ifdef CONFIG_CPU_ARM1020_ROUND_ROBIN
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
.ascii "RR"
#endif
.ascii "\0"
......@@ -588,16 +476,16 @@ __arm1020_setup:
orr r0, r0, #0x0031 @ ..........DP...M
orr r0, r0, #0x0100 @ .......S........
#ifdef CONFIG_CPU_ARM1020_ROUND_ROBIN
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .R..............
#endif
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
#ifndef CONFIG_CPU_BPREDICT_DISABLE
orr r0, r0, #0x0800 @ ....Z...........
#endif
#ifdef CONFIG_CPU_ARM1020_D_CACHE_ON
#ifndef CONFIG_CPU_DCACHE_DISABLE
orr r0, r0, #0x0004 @ Enable D cache
#endif
#ifdef CONFIG_CPU_ARM1020_I_CACHE_ON
#ifndef CONFIG_CPU_ICACHE_DISABLE
orr r0, r0, #0x1000 @ I Cache on
#endif
mov pc, lr
......@@ -620,7 +508,6 @@ arm1020_processor_functions:
/* cache */
.word cpu_arm1020_cache_clean_invalidate_all
.word cpu_arm1020_cache_clean_invalidate_range
.word cpu_arm1020_flush_ram_page
/* dcache */
.word cpu_arm1020_dcache_invalidate_range
......
arch/arm/mm/proc-arm6,7.S
View file @ 9f1a2068
......@@ -43,8 +43,6 @@ ENTRY(cpu_arm6_dcache_clean_page)
ENTRY(cpu_arm7_dcache_clean_page)
ENTRY(cpu_arm6_dcache_clean_entry)
ENTRY(cpu_arm7_dcache_clean_entry)
ENTRY(cpu_arm6_flush_ram_page)
ENTRY(cpu_arm7_flush_ram_page)
mov pc, lr
/*
......@@ -358,7 +356,6 @@ ENTRY(arm6_processor_functions)
/* cache */
.word cpu_arm6_cache_clean_invalidate_all
.word cpu_arm6_cache_clean_invalidate_range
.word cpu_arm6_flush_ram_page
/* dcache */
.word cpu_arm6_dcache_invalidate_range
......@@ -393,7 +390,6 @@ ENTRY(arm7_processor_functions)
/* cache */
.word cpu_arm7_cache_clean_invalidate_all
.word cpu_arm7_cache_clean_invalidate_range
.word cpu_arm7_flush_ram_page
/* dcache */
.word cpu_arm7_dcache_invalidate_range
......
arch/arm/mm/proc-arm720.S
View file @ 9f1a2068
......@@ -63,7 +63,6 @@ ENTRY(cpu_arm720_dcache_invalidate_range)
ENTRY(cpu_arm720_dcache_clean_range)
ENTRY(cpu_arm720_dcache_clean_page)
ENTRY(cpu_arm720_dcache_clean_entry)
ENTRY(cpu_arm720_flush_ram_page)
mov pc, lr
/*
......@@ -211,7 +210,6 @@ ENTRY(arm720_processor_functions)
/* cache */
.word cpu_arm720_cache_clean_invalidate_all
.word cpu_arm720_cache_clean_invalidate_range
.word cpu_arm720_flush_ram_page
/* dcache */
.word cpu_arm720_dcache_invalidate_range
......
arch/arm/mm/proc-arm920.S
View file @ 9f1a2068
......@@ -21,6 +21,8 @@
*
* These are the low level assembler for performing cache and TLB
* functions on the arm920.
*
* CONFIG_CPU_ARM920_CPU_IDLE -> nohlt
*/
#include <linux/linkage.h>
#include <linux/config.h>
......@@ -106,9 +108,7 @@ ENTRY(cpu_arm920_reset)
*/
.align 5
ENTRY(cpu_arm920_do_idle)
#if defined(CONFIG_CPU_ARM920_CPU_IDLE)
mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
#endif
mov pc, lr
/* ================================= CACHE ================================ */
......@@ -127,7 +127,7 @@ ENTRY(cpu_arm920_cache_clean_invalidate_all)
mov r2, #1
cpu_arm920_cache_clean_invalidate_all_r2:
mov ip, #0
#ifdef CONFIG_CPU_ARM920_WRITETHROUGH
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
#else
/*
......@@ -165,7 +165,7 @@ ENTRY(cpu_arm920_cache_clean_invalidate_range)
cmp r3, #MAX_AREA_SIZE
bgt cpu_arm920_cache_clean_invalidate_all_r2
1: teq r2, #0
#ifdef CONFIG_CPU_ARM920_WRITETHROUGH
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
add r0, r0, #DCACHELINESIZE
......@@ -186,32 +186,6 @@ ENTRY(cpu_arm920_cache_clean_invalidate_range)
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr
/*
* cpu_arm920_flush_ram_page(page)
*
* clean and invalidate all cache lines associated with this area of memory
*
* page: page to clean and invalidate
*/
.align 5
ENTRY(cpu_arm920_flush_ram_page)
mov r1, #PAGESIZE
#ifdef CONFIG_CPU_ARM920_WRITETHROUGH
1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
add r0, r0, #DCACHELINESIZE
#else
1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
add r0, r0, #DCACHELINESIZE
#endif
subs r1, r1, #2 * DCACHELINESIZE
bne 1b
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr
/* ================================ D-CACHE =============================== */
/*
......@@ -227,7 +201,7 @@ ENTRY(cpu_arm920_flush_ram_page)
*/
.align 5
ENTRY(cpu_arm920_dcache_invalidate_range)
#ifndef CONFIG_CPU_ARM920_WRITETHROUGH
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
tst r0, #DCACHELINESIZE - 1
mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
tst r1, #DCACHELINESIZE - 1
......@@ -253,7 +227,7 @@ ENTRY(cpu_arm920_dcache_invalidate_range)
*/
.align 5
ENTRY(cpu_arm920_dcache_clean_range)
#ifndef CONFIG_CPU_ARM920_WRITETHROUGH
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
bic r0, r0, #DCACHELINESIZE - 1
sub r1, r1, r0
cmp r1, #MAX_AREA_SIZE
......@@ -286,7 +260,7 @@ ENTRY(cpu_arm920_dcache_clean_range)
*/
.align 5
ENTRY(cpu_arm920_dcache_clean_page)
#ifndef CONFIG_CPU_ARM920_WRITETHROUGH
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mov r1, #PAGESIZE
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, #DCACHELINESIZE
......@@ -307,7 +281,7 @@ ENTRY(cpu_arm920_dcache_clean_page)
*/
.align 5
ENTRY(cpu_arm920_dcache_clean_entry)
#ifndef CONFIG_CPU_ARM920_WRITETHROUGH
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
#endif
mcr p15, 0, r0, c7, c10, 4 @ drain WB
......@@ -370,7 +344,7 @@ ENTRY(cpu_arm920_icache_invalidate_page)
.align 5
ENTRY(cpu_arm920_set_pgd)
mov ip, #0
#ifdef CONFIG_CPU_ARM920_WRITETHROUGH
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
/* Any reason why we don't use mcr p15, 0, r0, c7, c7, 0 here? --rmk */
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
#else
......@@ -403,7 +377,7 @@ ENTRY(cpu_arm920_set_pgd)
*/
.align 5
ENTRY(cpu_arm920_set_pmd)
#ifdef CONFIG_CPU_ARM920_WRITETHROUGH
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
eor r2, r1, #0x0a @ C & Section
tst r2, #0x0b
biceq r1, r1, #4 @ clear bufferable bit
......@@ -439,7 +413,7 @@ ENTRY(cpu_arm920_set_pte)
tst r1, #LPTE_PRESENT | LPTE_YOUNG @ Present and Young?
movne r2, #0
#ifdef CONFIG_CPU_ARM920_WRITETHROUGH
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
eor r3, r2, #0x0a @ C & small page?
tst r3, #0x0b
biceq r2, r2, #4
......@@ -455,15 +429,12 @@ cpu_manu_name:
.asciz "ARM/CIRRUS"
ENTRY(cpu_arm920_name)
.ascii "Arm920T"
#if defined(CONFIG_CPU_ARM920_CPU_IDLE)
.ascii "s"
#endif
#if defined(CONFIG_CPU_ARM920_I_CACHE_ON)
#ifndef CONFIG_CPU_ICACHE_DISABLE
.ascii "i"
#endif
#if defined(CONFIG_CPU_ARM920_D_CACHE_ON)
#ifndef CONFIG_CPU_DCACHE_DISABLE
.ascii "d"
#if defined(CONFIG_CPU_ARM920_WRITETHROUGH)
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
.ascii "(wt)"
#else
.ascii "(wb)"
......@@ -497,10 +468,10 @@ __arm920_setup:
orr r0, r0, #0x0031
orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1
#ifdef CONFIG_CPU_ARM920_D_CACHE_ON
#ifndef CONFIG_CPU_DCACHE_DISABLE
orr r0, r0, #0x0004 @ .... .... .... .1..
#endif
#ifdef CONFIG_CPU_ARM920_I_CACHE_ON
#ifndef CONFIG_CPU_ICACHE_DISABLE
orr r0, r0, #0x1000 @ ...1 .... .... ....
#endif
mov pc, lr
......@@ -523,7 +494,6 @@ arm920_processor_functions:
/* cache */
.word cpu_arm920_cache_clean_invalidate_all
.word cpu_arm920_cache_clean_invalidate_range
.word cpu_arm920_flush_ram_page
/* dcache */
.word cpu_arm920_dcache_invalidate_range
......
arch/arm/mm/proc-arm922.S
View file @ 9f1a2068
......@@ -22,6 +22,8 @@
*
* These are the low level assembler for performing cache and TLB
* functions on the arm922.
*
* CONFIG_CPU_ARM922_CPU_IDLE -> nohlt
*/
#include <linux/linkage.h>
#include <linux/config.h>
......@@ -107,9 +109,7 @@ ENTRY(cpu_arm922_reset)
*/
.align 5
ENTRY(cpu_arm922_do_idle)
#if defined(CONFIG_CPU_ARM922_CPU_IDLE)
mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
#endif
mov pc, lr
/* ================================= CACHE ================================ */
......@@ -128,7 +128,7 @@ ENTRY(cpu_arm922_cache_clean_invalidate_all)
mov r2, #1
cpu_arm922_cache_clean_invalidate_all_r2:
mov ip, #0
#ifdef CONFIG_CPU_ARM922_WRITETHROUGH
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
#else
/*
......@@ -166,7 +166,7 @@ ENTRY(cpu_arm922_cache_clean_invalidate_range)
cmp r3, #MAX_AREA_SIZE
bgt cpu_arm922_cache_clean_invalidate_all_r2
1: teq r2, #0
#ifdef CONFIG_CPU_ARM922_WRITETHROUGH
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
add r0, r0, #DCACHELINESIZE
......@@ -187,32 +187,6 @@ ENTRY(cpu_arm922_cache_clean_invalidate_range)
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr
/*
* cpu_arm922_flush_ram_page(page)
*
* clean and invalidate all cache lines associated with this area of memory
*
* page: page to clean and invalidate
*/
.align 5
ENTRY(cpu_arm922_flush_ram_page)
mov r1, #PAGESIZE
#ifdef CONFIG_CPU_ARM922_WRITETHROUGH
1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
add r0, r0, #DCACHELINESIZE
#else
1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
add r0, r0, #DCACHELINESIZE
#endif
subs r1, r1, #2 * DCACHELINESIZE
bne 1b
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr
/* ================================ D-CACHE =============================== */
/*
......@@ -228,7 +202,7 @@ ENTRY(cpu_arm922_flush_ram_page)
*/
.align 5
ENTRY(cpu_arm922_dcache_invalidate_range)
#ifndef CONFIG_CPU_ARM922_WRITETHROUGH
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
tst r0, #DCACHELINESIZE - 1
mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
tst r1, #DCACHELINESIZE - 1
......@@ -254,7 +228,7 @@ ENTRY(cpu_arm922_dcache_invalidate_range)
*/
.align 5
ENTRY(cpu_arm922_dcache_clean_range)
#ifndef CONFIG_CPU_ARM922_WRITETHROUGH
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
bic r0, r0, #DCACHELINESIZE - 1
sub r1, r1, r0
cmp r1, #MAX_AREA_SIZE
......@@ -287,7 +261,7 @@ ENTRY(cpu_arm922_dcache_clean_range)
*/
.align 5
ENTRY(cpu_arm922_dcache_clean_page)
#ifndef CONFIG_CPU_ARM922_WRITETHROUGH
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mov r1, #PAGESIZE
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, #DCACHELINESIZE
......@@ -308,7 +282,7 @@ ENTRY(cpu_arm922_dcache_clean_page)
*/
.align 5
ENTRY(cpu_arm922_dcache_clean_entry)
#ifndef CONFIG_CPU_ARM922_WRITETHROUGH
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
#endif
mcr p15, 0, r0, c7, c10, 4 @ drain WB
......@@ -371,7 +345,7 @@ ENTRY(cpu_arm922_icache_invalidate_page)
.align 5
ENTRY(cpu_arm922_set_pgd)
mov ip, #0
#ifdef CONFIG_CPU_ARM922_WRITETHROUGH
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
/* Any reason why we don't use mcr p15, 0, r0, c7, c7, 0 here? --rmk */
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
#else
......@@ -404,7 +378,7 @@ ENTRY(cpu_arm922_set_pgd)
*/
.align 5
ENTRY(cpu_arm922_set_pmd)
#ifdef CONFIG_CPU_ARM922_WRITETHROUGH
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
eor r2, r1, #0x0a @ C & Section
tst r2, #0x0b
biceq r1, r1, #4 @ clear bufferable bit
......@@ -440,7 +414,7 @@ ENTRY(cpu_arm922_set_pte)
tst r1, #LPTE_PRESENT | LPTE_YOUNG @ Present and Young?
movne r2, #0
#ifdef CONFIG_CPU_ARM922_WRITETHROUGH
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
eor r3, r2, #0x0a @ C & small page?
tst r3, #0x0b
biceq r2, r2, #4
......@@ -456,15 +430,12 @@ cpu_manu_name:
.asciz "ARM/ALTERA"
ENTRY(cpu_arm922_name)
.ascii "Arm922T"
#if defined(CONFIG_CPU_ARM922_CPU_IDLE)
.ascii "s"
#endif
#if defined(CONFIG_CPU_ARM922_I_CACHE_ON)
#ifndef CONFIG_CPU_ICACHE_DISABLE
.ascii "i"
#endif
#if defined(CONFIG_CPU_ARM922_D_CACHE_ON)
#ifndef CONFIG_CPU_DCACHE_DISABLE
.ascii "d"
#if defined(CONFIG_CPU_ARM922_WRITETHROUGH)
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
.ascii "(wt)"
#else
.ascii "(wb)"
......@@ -498,10 +469,10 @@ __arm922_setup:
orr r0, r0, #0x0031
orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1
#ifdef CONFIG_CPU_ARM922_D_CACHE_ON
#ifndef CONFIG_CPU_DCACHE_DISABLE
orr r0, r0, #0x0004 @ .... .... .... .1..
#endif
#ifdef CONFIG_CPU_ARM922_I_CACHE_ON
#ifndef CONFIG_CPU_ICACHE_DISABLE
orr r0, r0, #0x1000 @ ...1 .... .... ....
#endif
mov pc, lr
......@@ -524,7 +495,6 @@ arm922_processor_functions:
/* cache */
.word cpu_arm922_cache_clean_invalidate_all
.word cpu_arm922_cache_clean_invalidate_range
.word cpu_arm922_flush_ram_page
/* dcache */
.word cpu_arm922_dcache_invalidate_range
......
arch/arm/mm/proc-arm926.S
View file @ 9f1a2068
......@@ -21,6 +21,8 @@
*
* These are the low level assembler for performing cache and TLB
* functions on the arm926.
*
* CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
*/
#include <linux/linkage.h>
#include <linux/config.h>
......@@ -52,45 +54,6 @@
.text
/*
* cpu_arm926_data_abort()
*
* obtain information about current aborted instruction
* Note: we read user space. This means we might cause a data
* abort here if the I-TLB and D-TLB aren't seeing the same
* picture. Unfortunately, this does happen. We live with it.
*
* Inputs:
* r2 = address of abort
* r3 = cpsr of abort
*
* Returns:
* r0 = address of abort
* r1 != 0 if writing
* r3 = FSR
* r4 = corrupted
*/
.align 5
ENTRY(cpu_arm926_data_abort)
mrc p15, 0, r0, c6, c0, 0 @ get FAR
mrc p15, 0, r4, c5, c0, 0 @ get FSR
tst r1, #1<<24 @ Check for Jbit (NE -> found)
movne r1, #-1 @ Mark as writing
bne 2f
tst r3, #1<<5 @ Check for Thumb-bit (NE -> found)
ldrneh r1, [r2] @ Read aborted Thumb instruction
tstne r1, r1, lsr #12 @ C = bit 11
ldreq r1, [r2] @ Read aborted ARM instruction
tsteq r1, r1, lsr #21 @ C = bit 20
sbc r1, r1, r1 @ r1 = C - 1
2:
and r3, r4, #255
mov pc, lr
/*
* cpu_arm926_check_bugs()
*/
......@@ -146,9 +109,7 @@ ENTRY(cpu_arm926_reset)
*/
.align 5
ENTRY(cpu_arm926_do_idle)
#if defined(CONFIG_CPU_ARM926_CPU_IDLE)
mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
#endif
mov pc, lr
/* ================================= CACHE ================================ */
......@@ -167,7 +128,7 @@ ENTRY(cpu_arm926_cache_clean_invalidate_all)
mov r2, #1
cpu_arm926_cache_clean_invalidate_all_r2:
mov ip, #0
#ifdef CONFIG_CPU_ARM926_WRITETHROUGH
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
#else
1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
......@@ -203,7 +164,7 @@ ENTRY(cpu_arm926_cache_clean_invalidate_range)
bgt cpu_arm926_cache_clean_invalidate_all_r2
1: teq r2, #0
#ifdef CONFIG_CPU_ARM926_WRITETHROUGH
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
add r0, r0, #DCACHELINESIZE
......@@ -226,32 +187,6 @@ ENTRY(cpu_arm926_cache_clean_invalidate_range)
mov pc, lr
/*
* cpu_arm926_flush_ram_page(page)
*
* clean and invalidate all cache lines associated with this area of memory
*
* page: page to clean and invalidate
*/
.align 5
ENTRY(cpu_arm926_flush_ram_page)
mov r1, #PAGESIZE
#ifdef CONFIG_CPU_ARM926_WRITETHROUGH
1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
add r0, r0, #DCACHELINESIZE
#else
1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
add r0, r0, #DCACHELINESIZE
#endif
subs r1, r1, #2 * DCACHELINESIZE
bne 1b
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr
/* ================================ D-CACHE =============================== */
/*
......@@ -267,7 +202,7 @@ ENTRY(cpu_arm926_flush_ram_page)
*/
.align 5
ENTRY(cpu_arm926_dcache_invalidate_range)
#ifndef CONFIG_CPU_ARM926_WRITETHROUGH
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
tst r0, #DCACHELINESIZE - 1
mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
tst r1, #DCACHELINESIZE - 1
......@@ -293,7 +228,7 @@ ENTRY(cpu_arm926_dcache_invalidate_range)
*/
.align 5
ENTRY(cpu_arm926_dcache_clean_range)
#ifndef CONFIG_CPU_ARM926_WRITETHROUGH
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
bic r0, r0, #DCACHELINESIZE - 1
sub r1, r1, r0
cmp r1, #MAX_AREA_SIZE
......@@ -326,7 +261,7 @@ ENTRY(cpu_arm926_dcache_clean_range)
*/
.align 5
ENTRY(cpu_arm926_dcache_clean_page)
#ifndef CONFIG_CPU_ARM926_WRITETHROUGH
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mov r1, #PAGESIZE
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, #DCACHELINESIZE
......@@ -347,7 +282,7 @@ ENTRY(cpu_arm926_dcache_clean_page)
*/
.align 5
ENTRY(cpu_arm926_dcache_clean_entry)
#ifndef CONFIG_CPU_ARM926_WRITETHROUGH
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
#endif
mcr p15, 0, r0, c7, c10, 4 @ drain WB
......@@ -399,7 +334,7 @@ ENTRY(cpu_arm926_icache_invalidate_page)
.align 5
ENTRY(cpu_arm926_set_pgd)
mov ip, #0
#ifdef CONFIG_CPU_ARM926_WRITETHROUGH
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
/* Any reason why we don't use mcr p15, 0, r0, c7, c7, 0 here? --rmk */
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
#else
......@@ -424,13 +359,13 @@ ENTRY(cpu_arm926_set_pgd)
*/
.align 5
ENTRY(cpu_arm926_set_pmd)
#ifdef CONFIG_CPU_ARM926_WRITETHROUGH
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
eor r2, r1, #0x0a @ C & Section
tst r2, #0x0b
biceq r1, r1, #4 @ clear bufferable bit
#endif
str r1, [r0]
#ifndef CONFIG_CPU_ARM926_WRITETHROUGH
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
#endif
mcr p15, 0, r0, c7, c10, 4 @ drain WB
......@@ -462,14 +397,14 @@ ENTRY(cpu_arm926_set_pte)
tst r1, #LPTE_PRESENT | LPTE_YOUNG @ Present and Young?
movne r2, #0
#ifdef CONFIG_CPU_ARM926_WRITETHROUGH
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
eor r3, r2, #0x0a @ C & small page?
tst r3, #0x0b
biceq r2, r2, #4
#endif
str r2, [r0] @ hardware version
mov r0, r0
#ifndef CONFIG_CPU_ARM926_WRITETHROUGH
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
#endif
mcr p15, 0, r0, c7, c10, 4 @ drain WB
......@@ -480,20 +415,17 @@ cpu_manu_name:
.asciz "ARM"
ENTRY(cpu_arm926_name)
.ascii "ARM926EJ-S"
#if defined(CONFIG_CPU_ARM926_CPU_IDLE)
.ascii "s"
#endif
#if defined(CONFIG_CPU_ARM926_I_CACHE_ON)
#ifndef CONFIG_CPU_ICACHE_DISABLE
.ascii "i"
#endif
#if defined(CONFIG_CPU_ARM926_D_CACHE_ON)
#ifndef CONFIG_CPU_DCACHE_DISABLE
.ascii "d"
#if defined(CONFIG_CPU_ARM926_WRITETHROUGH)
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
.ascii "(wt)"
#else
.ascii "(wb)"
#endif
#ifdef CONFIG_CPU_ARM926_ROUND_ROBIN
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
.ascii "RR"
#endif
#endif
......@@ -510,7 +442,7 @@ __arm926_setup:
mcr p15, 0, r4, c2, c0 @ load page table pointer
#if defined(CONFIG_CPU_ARM926_WRITETHROUGH)
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mov r0, #4 @ disable write-back on caches explicitly
mcr p15, 7, r0, c15, c0, 0
#endif
......@@ -532,13 +464,13 @@ __arm926_setup:
orr r0, r0, #0x0031
orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1
#ifdef CONFIG_CPU_ARM926_ROUND_ROBIN
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
orr r0, r0, #0x4000 @ .1.. .... .... ....
#endif
#ifdef CONFIG_CPU_ARM926_D_CACHE_ON
#ifndef CONFIG_CPU_DCACHE_DISABLE
orr r0, r0, #0x0004 @ .... .... .... .1..
#endif
#ifdef CONFIG_CPU_ARM926_I_CACHE_ON
#ifndef CONFIG_CPU_ICACHE_DISABLE
orr r0, r0, #0x1000 @ ...1 .... .... ....
#endif
mov pc, lr
......@@ -561,7 +493,6 @@ arm926_processor_functions:
/* cache */
.word cpu_arm926_cache_clean_invalidate_all
.word cpu_arm926_cache_clean_invalidate_range
.word cpu_arm926_flush_ram_page
/* dcache */
.word cpu_arm926_dcache_invalidate_range
......
arch/arm/mm/proc-macros.S
View file @ 9f1a2068
......@@ -21,6 +21,11 @@
ldr \rd, [\rn, #VMA_VM_FLAGS]
.endm
.macro tsk_mm, rd, rn
ldr \rd, [\rn, #TI_TASK]
ldr \rd, [\rd, #TSK_ACTIVE_MM]
.endm
/*
* act_mm - get current->active_mm
*/
......
arch/arm/mm/proc-sa110.S
View file @ 9f1a2068
......@@ -262,26 +262,6 @@ ENTRY(cpu_sa1100_cache_clean_invalidate_range)
bhi cpu_sa1100_cache_clean_invalidate_all_r2
b 1b
/*
* cpu_sa110_flush_ram_page(page)
*
* clean and invalidate all cache lines associated with this area of memory
*
* page: page to clean and invalidate
*/
.align 5
ENTRY(cpu_sa110_flush_ram_page)
ENTRY(cpu_sa1100_flush_ram_page)
mov r1, #PAGESIZE
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, #DCACHELINESIZE
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, #DCACHELINESIZE
subs r1, r1, #2 * DCACHELINESIZE
bne 1b
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr
/* ================================ D-CACHE =============================== */
/*
......@@ -550,7 +530,6 @@ ENTRY(sa110_processor_functions)
/* cache */
.word cpu_sa110_cache_clean_invalidate_all
.word cpu_sa110_cache_clean_invalidate_range
.word cpu_sa110_flush_ram_page
/* dcache */
.word cpu_sa110_dcache_invalidate_range
......@@ -591,7 +570,6 @@ ENTRY(sa1100_processor_functions)
/* cache */
.word cpu_sa1100_cache_clean_invalidate_all
.word cpu_sa1100_cache_clean_invalidate_range
.word cpu_sa1100_flush_ram_page
/* dcache */
.word cpu_sa1100_dcache_invalidate_range
......
arch/arm/mm/proc-syms.c
View file @ 9f1a2068
......@@ -16,7 +16,6 @@
#ifndef MULTI_CPU
EXPORT_SYMBOL(cpu_cache_clean_invalidate_all);
EXPORT_SYMBOL(cpu_cache_clean_invalidate_range);
EXPORT_SYMBOL(cpu_flush_ram_page);
EXPORT_SYMBOL(cpu_dcache_clean_page);
EXPORT_SYMBOL(cpu_dcache_clean_entry);
EXPORT_SYMBOL(cpu_dcache_clean_range);
......
include/asm-arm/cpu-multi32.h
View file @ 9f1a2068
......@@ -56,10 +56,6 @@ extern struct processor {
* flush a specific page or pages
*/
void (*clean_invalidate_range)(unsigned long address, unsigned long end, int flags);
/*
* flush a page to RAM
*/
void (*_flush_ram_page)(void *virt_page);
} cache;
struct { /* D-cache */
......@@ -121,7 +117,6 @@ extern const struct processor sa110_processor_functions;
#define cpu_cache_clean_invalidate_all() processor.cache.clean_invalidate_all()
#define cpu_cache_clean_invalidate_range(s,e,f) processor.cache.clean_invalidate_range(s,e,f)
#define cpu_flush_ram_page(vp) processor.cache._flush_ram_page(vp)
#define cpu_dcache_clean_page(vp) processor.dcache.clean_page(vp)
#define cpu_dcache_clean_entry(addr) processor.dcache.clean_entry(addr)
......
include/asm-arm/cpu-single.h
View file @ 9f1a2068
......@@ -29,7 +29,6 @@
#define cpu_do_idle __cpu_fn(CPU_NAME,_do_idle)
#define cpu_cache_clean_invalidate_all __cpu_fn(CPU_NAME,_cache_clean_invalidate_all)
#define cpu_cache_clean_invalidate_range __cpu_fn(CPU_NAME,_cache_clean_invalidate_range)
#define cpu_flush_ram_page __cpu_fn(CPU_NAME,_flush_ram_page)
#define cpu_dcache_invalidate_range __cpu_fn(CPU_NAME,_dcache_invalidate_range)
#define cpu_dcache_clean_range __cpu_fn(CPU_NAME,_dcache_clean_range)
#define cpu_dcache_clean_page __cpu_fn(CPU_NAME,_dcache_clean_page)
......@@ -57,7 +56,6 @@ extern int cpu_do_idle(int mode);
extern void cpu_cache_clean_invalidate_all(void);
extern void cpu_cache_clean_invalidate_range(unsigned long address, unsigned long end, int flags);
extern void cpu_flush_ram_page(void *virt_page);
extern void cpu_dcache_invalidate_range(unsigned long start, unsigned long end);
extern void cpu_dcache_clean_range(unsigned long start, unsigned long end);
......
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