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Commit a16a0d2f authored by Alexander Duyck's avatar Alexander Duyck Committed by Jeff Kirsher
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ixgbe: Cleanup holes in flags after removing several of them 

This change is just meant to defragment the flags as there are several hole
that have been introduced since several features, or the flags for them,
have been removed.
Signed-off-by: default avatarAlexander Duyck <alexander.h.duyck@intel.com>
Tested-by: default avatarPhil Schmitt <phillip.j.schmitt@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent fbe7ca7f
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Showing with 25 additions and 25 deletions
drivers/net/ethernet/intel/ixgbe/ixgbe.h
View file @ a16a0d2f
...@@ -433,33 +433,33 @@ struct ixgbe_adapter { ...@@ -433,33 +433,33 @@ struct ixgbe_adapter {
* thus the additional *_CAPABLE flags. * thus the additional *_CAPABLE flags.
*/ */
u32 flags; u32 flags;
#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1) #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 0)
#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2) #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1)
#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3) #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 2)
#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4) #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3)
#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6) #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4)
#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7) #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5)
#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8) #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6)
#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9) #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 7)
#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10) #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8)
#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11) #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9)
#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12) #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10)
#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13) #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11)
#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14) #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12)
#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18) #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13)
#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19) #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14)
#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20) #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15)
#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22) #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16)
#define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 23) #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17)
#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 24) #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18)
#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 25) #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19)
#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 26) #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20)
#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 27) #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21)
#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 28) #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22)
#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 29) #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23)
u32 flags2; u32 flags2;
#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1) #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0)
#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
#define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3) #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
......
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