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Commit a29ca894 authored by David S. Miller's avatar David S. Miller
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Merge branch 'bcm_sf2-utilize-b53_common' 

Florian Fainelli says:

====================
net: dsa: Make bcm_sf2 utilize b53_common

This patch series makes the bcm_sf2 driver utilize a large number of the core
functions offered by the b53_common driver since the SWITCH_CORE registers are
mostly register compatible with the switches driven by b53_common.

In order to accomplish that, we just override the dsa_driver_ops callbacks that
we need to. There are still integration specific logic from the bcm_sf2 that we
cannot absorb into b53_common because it is just not there, mostly in the area
of link management and power management, but most of the features are within
b53_common now: VLAN, FDB, bridge

Along the process, we also improve support for the BCM58xx SoCs, since those
also have the same version of the switching IP that 7445 has (for which bcm_sf2
was developed).

Changes in v3:

- rebase against 145dd5f9 ("net: flush the
  softnet backlog in process context")

Changes in v2:

- rebased against "net: dsa: rename switch operations structure"
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents ed35ca99 de0b9d3b
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Inline Side-by-side
Showing with 288 additions and 967 deletions
drivers/net/dsa/Kconfig
View file @ a29ca894
...@@ -16,6 +16,7 @@ config NET_DSA_BCM_SF2 ...@@ -16,6 +16,7 @@ config NET_DSA_BCM_SF2
select FIXED_PHY select FIXED_PHY
select BCM7XXX_PHY select BCM7XXX_PHY
select MDIO_BCM_UNIMAC select MDIO_BCM_UNIMAC
select B53
---help--- ---help---
This enables support for the Broadcom Starfighter 2 Ethernet This enables support for the Broadcom Starfighter 2 Ethernet
switch chips. switch chips.
......
drivers/net/dsa/b53/b53_common.c
View file @ a29ca894
...@@ -167,6 +167,65 @@ static const struct b53_mib_desc b53_mibs[] = { ...@@ -167,6 +167,65 @@ static const struct b53_mib_desc b53_mibs[] = {
#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs) #define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
static const struct b53_mib_desc b53_mibs_58xx[] = {
{ 8, 0x00, "TxOctets" },
{ 4, 0x08, "TxDropPkts" },
{ 4, 0x0c, "TxQPKTQ0" },
{ 4, 0x10, "TxBroadcastPkts" },
{ 4, 0x14, "TxMulticastPkts" },
{ 4, 0x18, "TxUnicastPKts" },
{ 4, 0x1c, "TxCollisions" },
{ 4, 0x20, "TxSingleCollision" },
{ 4, 0x24, "TxMultipleCollision" },
{ 4, 0x28, "TxDeferredCollision" },
{ 4, 0x2c, "TxLateCollision" },
{ 4, 0x30, "TxExcessiveCollision" },
{ 4, 0x34, "TxFrameInDisc" },
{ 4, 0x38, "TxPausePkts" },
{ 4, 0x3c, "TxQPKTQ1" },
{ 4, 0x40, "TxQPKTQ2" },
{ 4, 0x44, "TxQPKTQ3" },
{ 4, 0x48, "TxQPKTQ4" },
{ 4, 0x4c, "TxQPKTQ5" },
{ 8, 0x50, "RxOctets" },
{ 4, 0x58, "RxUndersizePkts" },
{ 4, 0x5c, "RxPausePkts" },
{ 4, 0x60, "RxPkts64Octets" },
{ 4, 0x64, "RxPkts65to127Octets" },
{ 4, 0x68, "RxPkts128to255Octets" },
{ 4, 0x6c, "RxPkts256to511Octets" },
{ 4, 0x70, "RxPkts512to1023Octets" },
{ 4, 0x74, "RxPkts1024toMaxPktsOctets" },
{ 4, 0x78, "RxOversizePkts" },
{ 4, 0x7c, "RxJabbers" },
{ 4, 0x80, "RxAlignmentErrors" },
{ 4, 0x84, "RxFCSErrors" },
{ 8, 0x88, "RxGoodOctets" },
{ 4, 0x90, "RxDropPkts" },
{ 4, 0x94, "RxUnicastPkts" },
{ 4, 0x98, "RxMulticastPkts" },
{ 4, 0x9c, "RxBroadcastPkts" },
{ 4, 0xa0, "RxSAChanges" },
{ 4, 0xa4, "RxFragments" },
{ 4, 0xa8, "RxJumboPkt" },
{ 4, 0xac, "RxSymblErr" },
{ 4, 0xb0, "InRangeErrCount" },
{ 4, 0xb4, "OutRangeErrCount" },
{ 4, 0xb8, "EEELpiEvent" },
{ 4, 0xbc, "EEELpiDuration" },
{ 4, 0xc0, "RxDiscard" },
{ 4, 0xc8, "TxQPKTQ6" },
{ 4, 0xcc, "TxQPKTQ7" },
{ 4, 0xd0, "TxPkts64Octets" },
{ 4, 0xd4, "TxPkts65to127Octets" },
{ 4, 0xd8, "TxPkts128to255Octets" },
{ 4, 0xdc, "TxPkts256to511Ocets" },
{ 4, 0xe0, "TxPkts512to1023Ocets" },
{ 4, 0xe4, "TxPkts1024toMaxPktOcets" },
};
#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
static int b53_do_vlan_op(struct b53_device *dev, u8 op) static int b53_do_vlan_op(struct b53_device *dev, u8 op)
{ {
unsigned int i; unsigned int i;
...@@ -635,6 +694,8 @@ static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev) ...@@ -635,6 +694,8 @@ static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
return b53_mibs_65; return b53_mibs_65;
else if (is63xx(dev)) else if (is63xx(dev))
return b53_mibs_63xx; return b53_mibs_63xx;
else if (is58xx(dev))
return b53_mibs_58xx;
else else
return b53_mibs; return b53_mibs;
} }
...@@ -645,6 +706,8 @@ static unsigned int b53_get_mib_size(struct b53_device *dev) ...@@ -645,6 +706,8 @@ static unsigned int b53_get_mib_size(struct b53_device *dev)
return B53_MIBS_65_SIZE; return B53_MIBS_65_SIZE;
else if (is63xx(dev)) else if (is63xx(dev))
return B53_MIBS_63XX_SIZE; return B53_MIBS_63XX_SIZE;
else if (is58xx(dev))
return B53_MIBS_58XX_SIZE;
else else
return B53_MIBS_SIZE; return B53_MIBS_SIZE;
} }
...@@ -1252,9 +1315,21 @@ static int b53_br_join(struct dsa_switch *ds, int port, ...@@ -1252,9 +1315,21 @@ static int b53_br_join(struct dsa_switch *ds, int port,
struct net_device *bridge) struct net_device *bridge)
{ {
struct b53_device *dev = ds_to_priv(ds); struct b53_device *dev = ds_to_priv(ds);
s8 cpu_port = ds->dst->cpu_port;
u16 pvlan, reg; u16 pvlan, reg;
unsigned int i; unsigned int i;
/* Make this port leave the all VLANs join since we will have proper
* VLAN entries from now on
*/
if (is58xx(dev)) {
b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
reg &= ~BIT(port);
if ((reg & BIT(cpu_port)) == BIT(cpu_port))
reg &= ~BIT(cpu_port);
b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
}
dev->ports[port].bridge_dev = bridge; dev->ports[port].bridge_dev = bridge;
b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan); b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
...@@ -1287,6 +1362,7 @@ static void b53_br_leave(struct dsa_switch *ds, int port) ...@@ -1287,6 +1362,7 @@ static void b53_br_leave(struct dsa_switch *ds, int port)
struct b53_device *dev = ds_to_priv(ds); struct b53_device *dev = ds_to_priv(ds);
struct net_device *bridge = dev->ports[port].bridge_dev; struct net_device *bridge = dev->ports[port].bridge_dev;
struct b53_vlan *vl = &dev->vlans[0]; struct b53_vlan *vl = &dev->vlans[0];
s8 cpu_port = ds->dst->cpu_port;
unsigned int i; unsigned int i;
u16 pvlan, reg, pvid; u16 pvlan, reg, pvid;
...@@ -1316,10 +1392,19 @@ static void b53_br_leave(struct dsa_switch *ds, int port) ...@@ -1316,10 +1392,19 @@ static void b53_br_leave(struct dsa_switch *ds, int port)
else else
pvid = 0; pvid = 0;
/* Make this port join all VLANs without VLAN entries */
if (is58xx(dev)) {
b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
reg |= BIT(port);
if (!(reg & BIT(cpu_port)))
reg |= BIT(cpu_port);
b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
} else {
b53_get_vlan_entry(dev, pvid, vl); b53_get_vlan_entry(dev, pvid, vl);
vl->members |= BIT(port) | BIT(dev->cpu_port); vl->members |= BIT(port) | BIT(dev->cpu_port);
vl->untag |= BIT(port) | BIT(dev->cpu_port); vl->untag |= BIT(port) | BIT(dev->cpu_port);
b53_set_vlan_entry(dev, pvid, vl); b53_set_vlan_entry(dev, pvid, vl);
}
} }
static void b53_br_set_stp_state(struct dsa_switch *ds, int port, static void b53_br_set_stp_state(struct dsa_switch *ds, int port,
...@@ -1598,11 +1683,22 @@ static const struct b53_chip_data b53_switch_chips[] = { ...@@ -1598,11 +1683,22 @@ static const struct b53_chip_data b53_switch_chips[] = {
.jumbo_pm_reg = B53_JUMBO_PORT_MASK, .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
.jumbo_size_reg = B53_JUMBO_MAX_SIZE, .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
}, },
{
.chip_id = BCM7445_DEVICE_ID,
.dev_name = "BCM7445",
.vlans = 4096,
.enabled_ports = 0x1ff,
.arl_entries = 4,
.cpu_port = B53_CPU_PORT,
.vta_regs = B53_VTA_REGS,
.duplex_reg = B53_DUPLEX_STAT_GE,
.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
},
}; };
static int b53_switch_init(struct b53_device *dev) static int b53_switch_init(struct b53_device *dev)
{ {
struct dsa_switch *ds = dev->ds;
unsigned int i; unsigned int i;
int ret; int ret;
...@@ -1618,7 +1714,6 @@ static int b53_switch_init(struct b53_device *dev) ...@@ -1618,7 +1714,6 @@ static int b53_switch_init(struct b53_device *dev)
dev->vta_regs[1] = chip->vta_regs[1]; dev->vta_regs[1] = chip->vta_regs[1];
dev->vta_regs[2] = chip->vta_regs[2]; dev->vta_regs[2] = chip->vta_regs[2];
dev->jumbo_pm_reg = chip->jumbo_pm_reg; dev->jumbo_pm_reg = chip->jumbo_pm_reg;
ds->ops = &b53_switch_ops;
dev->cpu_port = chip->cpu_port; dev->cpu_port = chip->cpu_port;
dev->num_vlans = chip->vlans; dev->num_vlans = chip->vlans;
dev->num_arl_entries = chip->arl_entries; dev->num_arl_entries = chip->arl_entries;
...@@ -1706,6 +1801,7 @@ struct b53_device *b53_switch_alloc(struct device *base, ...@@ -1706,6 +1801,7 @@ struct b53_device *b53_switch_alloc(struct device *base,
dev->ds = ds; dev->ds = ds;
dev->priv = priv; dev->priv = priv;
dev->ops = ops; dev->ops = ops;
ds->ops = &b53_switch_ops;
mutex_init(&dev->reg_mutex); mutex_init(&dev->reg_mutex);
mutex_init(&dev->stats_mutex); mutex_init(&dev->stats_mutex);
......
drivers/net/dsa/b53/b53_priv.h
View file @ a29ca894
...@@ -60,6 +60,7 @@ enum { ...@@ -60,6 +60,7 @@ enum {
BCM53018_DEVICE_ID = 0x53018, BCM53018_DEVICE_ID = 0x53018,
BCM53019_DEVICE_ID = 0x53019, BCM53019_DEVICE_ID = 0x53019,
BCM58XX_DEVICE_ID = 0x5800, BCM58XX_DEVICE_ID = 0x5800,
BCM7445_DEVICE_ID = 0x7445,
}; };
#define B53_N_PORTS 9 #define B53_N_PORTS 9
...@@ -174,6 +175,12 @@ static inline int is5301x(struct b53_device *dev) ...@@ -174,6 +175,12 @@ static inline int is5301x(struct b53_device *dev)
dev->chip_id == BCM53019_DEVICE_ID; dev->chip_id == BCM53019_DEVICE_ID;
} }
static inline int is58xx(struct b53_device *dev)
{
return dev->chip_id == BCM58XX_DEVICE_ID ||
dev->chip_id == BCM7445_DEVICE_ID;
}
#define B53_CPU_PORT_25 5 #define B53_CPU_PORT_25 5
#define B53_CPU_PORT 8 #define B53_CPU_PORT 8
......
drivers/net/dsa/b53/b53_regs.h
View file @ a29ca894
...@@ -309,6 +309,9 @@ ...@@ -309,6 +309,9 @@
/* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */ /* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */
#define B53_PVLAN_PORT_MASK(i) ((i) * 2) #define B53_PVLAN_PORT_MASK(i) ((i) * 2)
/* Join all VLANs register (16 bit) */
#define B53_JOIN_ALL_VLAN_EN 0x50
/************************************************************************* /*************************************************************************
* 802.1Q Page Registers * 802.1Q Page Registers
*************************************************************************/ *************************************************************************/
......
drivers/net/dsa/bcm_sf2.c
View file @ a29ca894
This diff is collapsed.
drivers/net/dsa/bcm_sf2.h
View file @ a29ca894
...@@ -26,6 +26,7 @@ ...@@ -26,6 +26,7 @@
#include <net/dsa.h> #include <net/dsa.h>
#include "bcm_sf2_regs.h" #include "bcm_sf2_regs.h"
#include "b53/b53_priv.h"
struct bcm_sf2_hw_params { struct bcm_sf2_hw_params {
u16 top_rev; u16 top_rev;
...@@ -50,71 +51,9 @@ struct bcm_sf2_port_status { ...@@ -50,71 +51,9 @@ struct bcm_sf2_port_status {
struct ethtool_eee eee; struct ethtool_eee eee;
u32 vlan_ctl_mask; u16 vlan_ctl_mask;
u16 pvid;
struct net_device *bridge_dev;
};
struct bcm_sf2_arl_entry {
u8 port;
u8 mac[ETH_ALEN];
u16 vid;
u8 is_valid:1;
u8 is_age:1;
u8 is_static:1;
}; };
struct bcm_sf2_vlan {
u16 members;
u16 untag;
};
static inline void bcm_sf2_mac_from_u64(u64 src, u8 *dst)
{
unsigned int i;
for (i = 0; i < ETH_ALEN; i++)
dst[ETH_ALEN - 1 - i] = (src >> (8 * i)) & 0xff;
}
static inline u64 bcm_sf2_mac_to_u64(const u8 *src)
{
unsigned int i;
u64 dst = 0;
for (i = 0; i < ETH_ALEN; i++)
dst |= (u64)src[ETH_ALEN - 1 - i] << (8 * i);
return dst;
}
static inline void bcm_sf2_arl_to_entry(struct bcm_sf2_arl_entry *ent,
u64 mac_vid, u32 fwd_entry)
{
memset(ent, 0, sizeof(*ent));
ent->port = fwd_entry & PORTID_MASK;
ent->is_valid = !!(fwd_entry & ARL_VALID);
ent->is_age = !!(fwd_entry & ARL_AGE);
ent->is_static = !!(fwd_entry & ARL_STATIC);
bcm_sf2_mac_from_u64(mac_vid, ent->mac);
ent->vid = mac_vid >> VID_SHIFT;
}
static inline void bcm_sf2_arl_from_entry(u64 *mac_vid, u32 *fwd_entry,
const struct bcm_sf2_arl_entry *ent)
{
*mac_vid = bcm_sf2_mac_to_u64(ent->mac);
*mac_vid |= (u64)(ent->vid & VID_MASK) << VID_SHIFT;
*fwd_entry = ent->port & PORTID_MASK;
if (ent->is_valid)
*fwd_entry |= ARL_VALID;
if (ent->is_static)
*fwd_entry |= ARL_STATIC;
if (ent->is_age)
*fwd_entry |= ARL_AGE;
}
struct bcm_sf2_priv { struct bcm_sf2_priv {
/* Base registers, keep those in order with BCM_SF2_REGS_NAME */ /* Base registers, keep those in order with BCM_SF2_REGS_NAME */
void __iomem *core; void __iomem *core;
...@@ -134,6 +73,9 @@ struct bcm_sf2_priv { ...@@ -134,6 +73,9 @@ struct bcm_sf2_priv {
u32 irq1_stat; u32 irq1_stat;
u32 irq1_mask; u32 irq1_mask;
/* Backing b53_device */
struct b53_device *dev;
/* Mutex protecting access to the MIB counters */ /* Mutex protecting access to the MIB counters */
struct mutex stats_mutex; struct mutex stats_mutex;
...@@ -155,16 +97,14 @@ struct bcm_sf2_priv { ...@@ -155,16 +97,14 @@ struct bcm_sf2_priv {
struct device_node *master_mii_dn; struct device_node *master_mii_dn;
struct mii_bus *slave_mii_bus; struct mii_bus *slave_mii_bus;
struct mii_bus *master_mii_bus; struct mii_bus *master_mii_bus;
/* Cache of programmed VLANs */
struct bcm_sf2_vlan vlans[VLAN_N_VID];
}; };
struct bcm_sf2_hw_stats { static inline struct bcm_sf2_priv *bcm_sf2_to_priv(struct dsa_switch *ds)
const char *string; {
u16 reg; struct b53_device *dev = ds_to_priv(ds);
u8 sizeof_stat;
}; return dev->priv;
}
#define SF2_IO_MACRO(name) \ #define SF2_IO_MACRO(name) \
static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off) \ static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off) \
......
drivers/net/dsa/bcm_sf2_regs.h
View file @ a29ca894
...@@ -115,14 +115,6 @@ ...@@ -115,14 +115,6 @@
#define RX_BCST_EN (1 << 2) #define RX_BCST_EN (1 << 2)
#define RX_MCST_EN (1 << 3) #define RX_MCST_EN (1 << 3)
#define RX_UCST_EN (1 << 4) #define RX_UCST_EN (1 << 4)
#define G_MISTP_STATE_SHIFT 5
#define G_MISTP_NO_STP (0 << G_MISTP_STATE_SHIFT)
#define G_MISTP_DIS_STATE (1 << G_MISTP_STATE_SHIFT)
#define G_MISTP_BLOCK_STATE (2 << G_MISTP_STATE_SHIFT)
#define G_MISTP_LISTEN_STATE (3 << G_MISTP_STATE_SHIFT)
#define G_MISTP_LEARN_STATE (4 << G_MISTP_STATE_SHIFT)
#define G_MISTP_FWD_STATE (5 << G_MISTP_STATE_SHIFT)
#define G_MISTP_STATE_MASK 0x7
#define CORE_SWMODE 0x0002c #define CORE_SWMODE 0x0002c
#define SW_FWDG_MODE (1 << 0) #define SW_FWDG_MODE (1 << 0)
...@@ -205,75 +197,11 @@ ...@@ -205,75 +197,11 @@
#define BRCM_HDR_EN_P5 (1 << 1) #define BRCM_HDR_EN_P5 (1 << 1)
#define BRCM_HDR_EN_P7 (1 << 2) #define BRCM_HDR_EN_P7 (1 << 2)
#define CORE_BRCM_HDR_CTRL2 0x0828
#define CORE_HL_PRTC_CTRL 0x0940
#define ARP_EN (1 << 0)
#define RARP_EN (1 << 1)
#define DHCP_EN (1 << 2)
#define ICMPV4_EN (1 << 3)
#define ICMPV6_EN (1 << 4)
#define ICMPV6_FWD_MODE (1 << 5)
#define IGMP_DIP_EN (1 << 8)
#define IGMP_RPTLVE_EN (1 << 9)
#define IGMP_RTPLVE_FWD_MODE (1 << 10)
#define IGMP_QRY_EN (1 << 11)
#define IGMP_QRY_FWD_MODE (1 << 12)
#define IGMP_UKN_EN (1 << 13)
#define IGMP_UKN_FWD_MODE (1 << 14)
#define MLD_RPTDONE_EN (1 << 15)
#define MLD_RPTDONE_FWD_MODE (1 << 16)
#define MLD_QRY_EN (1 << 17)
#define MLD_QRY_FWD_MODE (1 << 18)
#define CORE_RST_MIB_CNT_EN 0x0950 #define CORE_RST_MIB_CNT_EN 0x0950
#define CORE_BRCM_HDR_RX_DIS 0x0980 #define CORE_BRCM_HDR_RX_DIS 0x0980
#define CORE_BRCM_HDR_TX_DIS 0x0988 #define CORE_BRCM_HDR_TX_DIS 0x0988
#define CORE_ARLA_NUM_ENTRIES 1024
#define CORE_ARLA_RWCTL 0x1400
#define ARL_RW (1 << 0)
#define IVL_SVL_SELECT (1 << 6)
#define ARL_STRTDN (1 << 7)
#define CORE_ARLA_MAC 0x1408
#define CORE_ARLA_VID 0x1420
#define ARLA_VIDTAB_INDX_MASK 0x1fff
#define CORE_ARLA_MACVID0 0x1440
#define MAC_MASK 0xffffffffff
#define VID_SHIFT 48
#define VID_MASK 0xfff
#define CORE_ARLA_FWD_ENTRY0 0x1460
#define PORTID_MASK 0x1ff
#define ARL_CON_SHIFT 9
#define ARL_CON_MASK 0x3
#define ARL_PRI_SHIFT 11
#define ARL_PRI_MASK 0x7
#define ARL_AGE (1 << 14)
#define ARL_STATIC (1 << 15)
#define ARL_VALID (1 << 16)
#define CORE_ARLA_MACVID_ENTRY(x) (CORE_ARLA_MACVID0 + ((x) * 0x40))
#define CORE_ARLA_FWD_ENTRY(x) (CORE_ARLA_FWD_ENTRY0 + ((x) * 0x40))
#define CORE_ARLA_SRCH_CTL 0x1540
#define ARLA_SRCH_VLID (1 << 0)
#define IVL_SVL_SELECT (1 << 6)
#define ARLA_SRCH_STDN (1 << 7)
#define CORE_ARLA_SRCH_ADR 0x1544
#define ARLA_SRCH_ADR_VALID (1 << 15)
#define CORE_ARLA_SRCH_RSLT_0_MACVID 0x1580
#define CORE_ARLA_SRCH_RSLT_0 0x15a0
#define CORE_ARLA_SRCH_RSLT_MACVID(x) (CORE_ARLA_SRCH_RSLT_0_MACVID + ((x) * 0x40))
#define CORE_ARLA_SRCH_RSLT(x) (CORE_ARLA_SRCH_RSLT_0 + ((x) * 0x40))
#define CORE_ARLA_VTBL_RWCTRL 0x1600 #define CORE_ARLA_VTBL_RWCTRL 0x1600
#define ARLA_VTBL_CMD_WRITE 0 #define ARLA_VTBL_CMD_WRITE 0
#define ARLA_VTBL_CMD_READ 1 #define ARLA_VTBL_CMD_READ 1
...@@ -297,59 +225,9 @@ ...@@ -297,59 +225,9 @@
#define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \ #define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \
((x) * P_TXQ_PSM_VDD_SHIFT)) ((x) * P_TXQ_PSM_VDD_SHIFT))
#define CORE_P0_MIB_OFFSET 0x8000
#define P_MIB_SIZE 0x400
#define CORE_P_MIB_OFFSET(x) (CORE_P0_MIB_OFFSET + (x) * P_MIB_SIZE)
#define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8)) #define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8))
#define PORT_VLAN_CTRL_MASK 0x1ff #define PORT_VLAN_CTRL_MASK 0x1ff
#define CORE_VLAN_CTRL0 0xd000
#define CHANGE_1P_VID_INNER (1 << 0)
#define CHANGE_1P_VID_OUTER (1 << 1)
#define CHANGE_1Q_VID (1 << 3)
#define VLAN_LEARN_MODE_SVL (0 << 5)
#define VLAN_LEARN_MODE_IVL (3 << 5)
#define VLAN_EN (1 << 7)
#define CORE_VLAN_CTRL1 0xd004
#define EN_RSV_MCAST_FWDMAP (1 << 2)
#define EN_RSV_MCAST_UNTAG (1 << 3)
#define EN_IPMC_BYPASS_FWDMAP (1 << 5)
#define EN_IPMC_BYPASS_UNTAG (1 << 6)
#define CORE_VLAN_CTRL2 0xd008
#define EN_MIIM_BYPASS_V_FWDMAP (1 << 2)
#define EN_GMRP_GVRP_V_FWDMAP (1 << 5)
#define EN_GMRP_GVRP_UNTAG_MAP (1 << 6)
#define CORE_VLAN_CTRL3 0xd00c
#define EN_DROP_NON1Q_MASK 0x1ff
#define CORE_VLAN_CTRL4 0xd014
#define RESV_MCAST_FLOOD (1 << 1)
#define EN_DOUBLE_TAG_MASK 0x3
#define EN_DOUBLE_TAG_SHIFT 2
#define EN_MGE_REV_GMRP (1 << 4)
#define EN_MGE_REV_GVRP (1 << 5)
#define INGR_VID_CHK_SHIFT 6
#define INGR_VID_CHK_MASK 0x3
#define INGR_VID_CHK_FWD (0 << INGR_VID_CHK_SHIFT)
#define INGR_VID_CHK_DROP (1 << INGR_VID_CHK_SHIFT)
#define INGR_VID_CHK_NO_CHK (2 << INGR_VID_CHK_SHIFT)
#define INGR_VID_CHK_VID_VIOL_IMP (3 << INGR_VID_CHK_SHIFT)
#define CORE_VLAN_CTRL5 0xd018
#define EN_CPU_RX_BYP_INNER_CRCCHCK (1 << 0)
#define EN_VID_FFF_FWD (1 << 2)
#define DROP_VTABLE_MISS (1 << 3)
#define EGRESS_DIR_FRM_BYP_TRUNK_EN (1 << 4)
#define PRESV_NON1Q (1 << 6)
#define CORE_VLAN_CTRL6 0xd01c
#define STRICT_SFD_DETECT (1 << 0)
#define DIS_ARL_BUST_LMIT (1 << 4)
#define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8)) #define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8))
#define CFI_SHIFT 12 #define CFI_SHIFT 12
#define PRI_SHIFT 13 #define PRI_SHIFT 13
......
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