Commit a3102faf authored by Arnd Bergmann's avatar Arnd Bergmann

ARM: iop32x: enable multiplatform support

After iop32x was converted to the generic multi-irq entry
code, nothing really stops us from building it into a
generic kernel.

The two last headers can simply be removed, the mach/irqs.h
gets replaced with the sparse-irq intiialization from the
board specific .nr_irqs value, and the decompressor debug
output can use the debug_ll hack that all other platforms
use.
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 8c1fb11b
...@@ -356,17 +356,6 @@ config ARCH_FOOTBRIDGE ...@@ -356,17 +356,6 @@ config ARCH_FOOTBRIDGE
Support for systems based on the DC21285 companion chip Support for systems based on the DC21285 companion chip
("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
config ARCH_IOP32X
bool "IOP32x-based"
select CPU_XSCALE
select GPIO_IOP
select GPIOLIB
select FORCE_PCI
select PLAT_IOP
help
Support for Intel's 80219 and IOP32X (XScale) family of
processors.
config ARCH_IXP4XX config ARCH_IXP4XX
bool "IXP4xx-based" bool "IXP4xx-based"
select ARCH_SUPPORTS_BIG_ENDIAN select ARCH_SUPPORTS_BIG_ENDIAN
...@@ -688,9 +677,6 @@ config ARCH_MPS2 ...@@ -688,9 +677,6 @@ config ARCH_MPS2
config ARCH_ACORN config ARCH_ACORN
bool bool
config PLAT_IOP
bool
config PLAT_ORION config PLAT_ORION
bool bool
select CLKSRC_MMIO select CLKSRC_MMIO
......
...@@ -7,6 +7,7 @@ CONFIG_SLAB=y ...@@ -7,6 +7,7 @@ CONFIG_SLAB=y
CONFIG_MODULES=y CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_BSG is not set
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_IOP32X=y CONFIG_ARCH_IOP32X=y
CONFIG_MACH_GLANTANK=y CONFIG_MACH_GLANTANK=y
CONFIG_ARCH_IQ80321=y CONFIG_ARCH_IQ80321=y
......
# SPDX-License-Identifier: GPL-2.0 # SPDX-License-Identifier: GPL-2.0
if ARCH_IOP32X menuconfig ARCH_IOP32X
bool "IOP32x-based platforms"
menu "IOP32x Implementation Options" depends on ARCH_MULTI_V5
select CPU_XSCALE
select GPIO_IOP
select GPIOLIB
select FORCE_PCI
help
Support for Intel's 80219 and IOP32X (XScale) family of
processors.
comment "IOP32x Platform Types" if ARCH_IOP32X
config MACH_EP80219 config MACH_EP80219
bool bool
...@@ -42,6 +49,4 @@ config MACH_EM7210 ...@@ -42,6 +49,4 @@ config MACH_EM7210
board. Say also Y here if you have a SS4000e Baxter Creek NAS board. Say also Y here if you have a SS4000e Baxter Creek NAS
appliance." appliance."
endmenu
endif endif
...@@ -223,6 +223,7 @@ static void __init em7210_init_machine(void) ...@@ -223,6 +223,7 @@ static void __init em7210_init_machine(void)
MACHINE_START(EM7210, "Lanner EM7210") MACHINE_START(EM7210, "Lanner EM7210")
.atag_offset = 0x100, .atag_offset = 0x100,
.nr_irqs = IOP32X_NR_IRQS,
.map_io = em7210_map_io, .map_io = em7210_map_io,
.init_irq = iop32x_init_irq, .init_irq = iop32x_init_irq,
.init_time = em7210_timer_init, .init_time = em7210_timer_init,
......
...@@ -205,6 +205,7 @@ static void __init glantank_init_machine(void) ...@@ -205,6 +205,7 @@ static void __init glantank_init_machine(void)
MACHINE_START(GLANTANK, "GLAN Tank") MACHINE_START(GLANTANK, "GLAN Tank")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
.atag_offset = 0x100, .atag_offset = 0x100,
.nr_irqs = IOP32X_NR_IRQS,
.map_io = glantank_map_io, .map_io = glantank_map_io,
.init_irq = iop32x_init_irq, .init_irq = iop32x_init_irq,
.init_time = glantank_timer_init, .init_time = glantank_timer_init,
......
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/arm/mach-iop32x/include/mach/irqs.h
*
* Author: Rory Bolt <rorybolt@pacbell.net>
* Copyright: (C) 2002 Rory Bolt
*/
#ifndef __IRQS_H
#define __IRQS_H
#define NR_IRQS 33
#endif
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/mach-iop32x/include/mach/uncompress.h
*/
#include <asm/types.h>
#include <asm/mach-types.h>
#include <linux/serial_reg.h>
#define uart_base ((volatile u8 *)0xfe800000)
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
static inline void putc(char c)
{
while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
barrier();
uart_base[UART_TX] = c;
}
static inline void flush(void)
{
}
#define arch_decomp_setup() do { } while (0)
...@@ -324,6 +324,7 @@ MACHINE_END ...@@ -324,6 +324,7 @@ MACHINE_END
MACHINE_START(EP80219, "Intel EP80219") MACHINE_START(EP80219, "Intel EP80219")
/* Maintainer: Intel Corp. */ /* Maintainer: Intel Corp. */
.atag_offset = 0x100, .atag_offset = 0x100,
.nr_irqs = IOP32X_NR_IRQS,
.map_io = iq31244_map_io, .map_io = iq31244_map_io,
.init_irq = iop32x_init_irq, .init_irq = iop32x_init_irq,
.init_time = iq31244_timer_init, .init_time = iq31244_timer_init,
......
...@@ -183,6 +183,7 @@ static void __init iq80321_init_machine(void) ...@@ -183,6 +183,7 @@ static void __init iq80321_init_machine(void)
MACHINE_START(IQ80321, "Intel IQ80321") MACHINE_START(IQ80321, "Intel IQ80321")
/* Maintainer: Intel Corp. */ /* Maintainer: Intel Corp. */
.atag_offset = 0x100, .atag_offset = 0x100,
.nr_irqs = IOP32X_NR_IRQS,
.map_io = iq80321_map_io, .map_io = iq80321_map_io,
.init_irq = iop32x_init_irq, .init_irq = iop32x_init_irq,
.init_time = iq80321_timer_init, .init_time = iq80321_timer_init,
......
...@@ -43,4 +43,6 @@ ...@@ -43,4 +43,6 @@
#define IRQ_IOP32X_XINT3 IOP_IRQ(30) #define IRQ_IOP32X_XINT3 IOP_IRQ(30)
#define IRQ_IOP32X_HPI IOP_IRQ(31) #define IRQ_IOP32X_HPI IOP_IRQ(31)
#define IOP32X_NR_IRQS (IRQ_IOP32X_HPI + 1)
#endif #endif
...@@ -358,6 +358,7 @@ static void __init n2100_init_machine(void) ...@@ -358,6 +358,7 @@ static void __init n2100_init_machine(void)
MACHINE_START(N2100, "Thecus N2100") MACHINE_START(N2100, "Thecus N2100")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
.atag_offset = 0x100, .atag_offset = 0x100,
.nr_irqs = IOP32X_NR_IRQS,
.map_io = n2100_map_io, .map_io = n2100_map_io,
.init_irq = iop32x_init_irq, .init_irq = iop32x_init_irq,
.init_time = n2100_timer_init, .init_time = n2100_timer_init,
......
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