Commit a552b73f authored by Daniel Vetter's avatar Daniel Vetter

Merge tag 'drm-intel-fixes-2023-04-13' of...

Merge tag 'drm-intel-fixes-2023-04-13' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes

drm/i915 fixes for v6.3-rc7:
- Fix dual link DSI for TGL+
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/877cugckzu.fsf@intel.com
parents 62b92afd 6b844685
...@@ -300,9 +300,21 @@ static void configure_dual_link_mode(struct intel_encoder *encoder, ...@@ -300,9 +300,21 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
{ {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
u32 dss_ctl1; u32 dss_ctl1;
dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1); /* FIXME: Move all DSS handling to intel_vdsc.c */
if (DISPLAY_VER(dev_priv) >= 12) {
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe);
} else {
dss_ctl1_reg = DSS_CTL1;
dss_ctl2_reg = DSS_CTL2;
}
dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg);
dss_ctl1 |= SPLITTER_ENABLE; dss_ctl1 |= SPLITTER_ENABLE;
dss_ctl1 &= ~OVERLAP_PIXELS_MASK; dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
...@@ -323,16 +335,16 @@ static void configure_dual_link_mode(struct intel_encoder *encoder, ...@@ -323,16 +335,16 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2); dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg);
dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK; dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK;
dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
intel_de_write(dev_priv, DSS_CTL2, dss_ctl2); intel_de_write(dev_priv, dss_ctl2_reg, dss_ctl2);
} else { } else {
/* Interleave */ /* Interleave */
dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
} }
intel_de_write(dev_priv, DSS_CTL1, dss_ctl1); intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1);
} }
/* aka DSI 8X clock */ /* aka DSI 8X clock */
......
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