Commit a5c1bf7e authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Krzysztof Wilczyński

dt-bindings: PCI: socionext,uniphier-pcie-ep: Add top-level constraints

Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:".

Add missing top-level constraints for clock-names and reset-names.

Link: https://lore.kernel.org/linux-pci/20240818172843.121787-3-krzysztof.kozlowski@linaro.orgSigned-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarKrzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: default avatarKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
parent c62a0b8f
......@@ -38,13 +38,17 @@ properties:
minItems: 1
maxItems: 2
clock-names: true
clock-names:
minItems: 1
maxItems: 2
resets:
minItems: 1
maxItems: 2
reset-names: true
reset-names:
minItems: 1
maxItems: 2
num-ib-windows:
const: 16
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment