ppc64: add dabr and iabr cpu features

arch/ppc64/kernel/cputable.c

@@ -37,7 +37,8 @@ extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec);
 struct cpu_spec	cpu_specs[] = {
     {	/* Power3 */
 	    0xffff0000, 0x00400000, "Power3 (630)",
-	    CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+	    CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+		    CPU_FTR_DABR | CPU_FTR_IABR,
 	    COMMON_USER_PPC64,
 	    128, 128,
 	    __setup_cpu_power3,
@@ -45,7 +46,8 @@ struct cpu_spec	cpu_specs[] = {
     },
     {	/* Power3+ */
 	    0xffff0000, 0x00410000, "Power3 (630+)",
-	    CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+	    CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+		    CPU_FTR_DABR | CPU_FTR_IABR,
 	    COMMON_USER_PPC64,
 	    128, 128,
 	    __setup_cpu_power3,
@@ -53,7 +55,8 @@ struct cpu_spec	cpu_specs[] = {
     },
     {	/* Northstar */
 	    0xffff0000, 0x00330000, "Northstar",
-	    CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+	    CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+		    CPU_FTR_DABR | CPU_FTR_IABR,
 	    COMMON_USER_PPC64,
 	    128, 128,
 	    __setup_cpu_power3,
@@ -61,7 +64,8 @@ struct cpu_spec	cpu_specs[] = {
     },
     {	/* Pulsar */
 	    0xffff0000, 0x00340000, "Pulsar",
-	    CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+	    CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+		    CPU_FTR_DABR | CPU_FTR_IABR,
 	    COMMON_USER_PPC64,
 	    128, 128,
 	    __setup_cpu_power3,
@@ -69,7 +73,8 @@ struct cpu_spec	cpu_specs[] = {
     },
     {	/* I-star */
 	    0xffff0000, 0x00360000, "I-star",
-	    CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+	    CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+		    CPU_FTR_DABR | CPU_FTR_IABR,
 	    COMMON_USER_PPC64,
 	    128, 128,
 	    __setup_cpu_power3,
@@ -77,7 +82,8 @@ struct cpu_spec	cpu_specs[] = {
     },
     {	/* S-star */
 	    0xffff0000, 0x00370000, "S-star",
-	    CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+	    CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
+		    CPU_FTR_DABR | CPU_FTR_IABR,
 	    COMMON_USER_PPC64,
 	    128, 128,
 	    __setup_cpu_power3,
@@ -86,7 +92,7 @@ struct cpu_spec	cpu_specs[] = {
     {	/* Power4 */
 	    0xffff0000, 0x00350000, "Power4",
 	    CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-	    CPU_FTR_PPCAS_ARCH_V2,
+	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_DABR,
 	    COMMON_USER_PPC64,
 	    128, 128,
 	    __setup_cpu_power4,
@@ -95,7 +101,7 @@ struct cpu_spec	cpu_specs[] = {
     {	/* Power4+ */
 	    0xffff0000, 0x00380000, "Power4+",
 	    CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-	    CPU_FTR_PPCAS_ARCH_V2,
+	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_DABR,
 	    COMMON_USER_PPC64,
 	    128, 128,
 	    __setup_cpu_power4,
@@ -104,7 +110,7 @@ struct cpu_spec	cpu_specs[] = {
     {	/* default match */
 	    0x00000000, 0x00000000, "(Power4-Compatible)",
   	    CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
-	    CPU_FTR_PPCAS_ARCH_V2,
+	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_DABR,
 	    COMMON_USER_PPC64,
 	    128, 128,
 	    __setup_cpu_power4,

arch/ppc64/xmon/xmon.c

@@ -26,6 +26,7 @@
 #include <asm/naca.h>
 #include <asm/paca.h>
 #include <asm/ppcdebug.h>
+#include <asm/cputable.h>
 #include "nonstdio.h"
 #include "privinst.h"
 
@@ -469,9 +470,9 @@ insert_bpts()
 		}
 	}
 
-	if (cpu_has_dabr() && dabr.enabled)
+	if ((cur_cpu_spec->cpu_features & CPU_FTR_DABR) && dabr.enabled)
 		set_dabr(dabr.address);
-	if (cpu_has_iabr() && iabr.enabled)
+	if ((cur_cpu_spec->cpu_features & CPU_FTR_IABR) && iabr.enabled)
 		set_iabr(iabr.address);
 }
 
@@ -485,9 +486,9 @@ remove_bpts()
 	if (systemcfg->platform != PLATFORM_PSERIES)
 		return;
 
-	if (cpu_has_dabr())
+	if ((cur_cpu_spec->cpu_features & CPU_FTR_DABR))
 		set_dabr(0);
-	if (cpu_has_iabr())
+	if ((cur_cpu_spec->cpu_features & CPU_FTR_IABR))
 		set_iabr(0);
 
 	bp = bpts;
@@ -777,7 +778,7 @@ bpt_cmds(void)
 	cmd = inchar();
 	switch (cmd) {
 	case 'd':	/* bd - hardware data breakpoint */
-		if (cpu_has_dabr()) {
+		if (!(cur_cpu_spec->cpu_features & CPU_FTR_DABR)) {
 			printf("Not implemented on this cpu\n");
 			break;
 		}
@@ -797,7 +798,7 @@ bpt_cmds(void)
 			dabr.address = (dabr.address & ~7) | mode;
 		break;
 	case 'i':	/* bi - hardware instr breakpoint */
-		if (cpu_has_iabr()) {
+		if (!(cur_cpu_spec->cpu_features & CPU_FTR_IABR)) {
 			printf("Not implemented on POWER4\n");
 			break;
 		}

include/asm-ppc64/cputable.h

@@ -113,6 +113,8 @@ extern firmware_feature_t firmware_features_table[];
 #define CPU_FTR_TLBIEL         		0x0000000400000000
 #define CPU_FTR_NOEXECUTE     		0x0000000800000000
 #define CPU_FTR_NODSISRALIGN  		0x0000001000000000
+#define CPU_FTR_DABR  			0x0000002000000000
+#define CPU_FTR_IABR  			0x0000004000000000
 
 /* Platform firmware features */
 #define FW_FTR_                         0x0000000000000001

include/asm-ppc64/processor.h

@@ -730,15 +730,6 @@ static inline void prefetchw(const void *x)
 
 #define spin_lock_prefetch(x)	prefetchw(x)
 
-/* XXX we have to call HV to set when in LPAR */
-#define cpu_has_dabr()		(1)
-
-#define cpu_has_iabr()		(processor_type() != PV_POWER4 && \
-				 processor_type() != PV_POWER4p)
-
-#define cpu_alignexc_sets_dsisr() (processor_type() != PV_POWER4 && \
-				 processor_type() != PV_POWER4p)
-
 #endif /* ASSEMBLY */
 
 #endif /* __ASM_PPC64_PROCESSOR_H */

include/asm-ppc64/system.h

@@ -115,13 +115,6 @@ static inline int __is_processor(unsigned long pv)
 	return(PVR_VER(pvr) == pv);
 }
 
-static inline int processor_type(void)
-{
-	unsigned long pvr;
-	asm ("mfspr %0, 0x11F" : "=r" (pvr)); 
-	return(PVR_VER(pvr));
-}
-
 /*
  * Atomic exchange
  *