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Commit a80c69fc authored by Daniel Vetter's avatar Daniel Vetter
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Merge branch 'topic/atomic-conversion' into drm-intel-next-queued 

The i915 atomic conversion is a real beast and it's not getting easier
wrangling in a separate branch. I'm might be regretting this, but
right after vacation nothing can burst my little bubble here!
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@intel.com>
parents 49e4d842 c0165304
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Showing with 513 additions and 583 deletions
drivers/gpu/drm/i915/i915_debugfs.c
View file @ a80c69fc
......@@ -2783,13 +2783,16 @@ static int i915_display_info(struct seq_file *m, void *unused)
seq_printf(m, "---------\n");
for_each_intel_crtc(dev, crtc) {
bool active;
struct intel_crtc_state *pipe_config;
int x, y;
pipe_config = to_intel_crtc_state(crtc->base.state);
seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
crtc->base.base.id, pipe_name(crtc->pipe),
yesno(crtc->active), crtc->config->pipe_src_w,
crtc->config->pipe_src_h);
if (crtc->active) {
yesno(pipe_config->base.active),
pipe_config->pipe_src_w, pipe_config->pipe_src_h);
if (pipe_config->base.active) {
intel_crtc_info(m, crtc);
active = cursor_position(dev, crtc->pipe, &x, &y);
......@@ -3030,7 +3033,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
seq_puts(m, "\n\n");
if (intel_crtc->config->has_drrs) {
if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
struct intel_panel *panel;
mutex_lock(&drrs->mutex);
......@@ -3082,7 +3085,7 @@ static int i915_drrs_status(struct seq_file *m, void *unused)
for_each_intel_crtc(dev, intel_crtc) {
drm_modeset_lock(&intel_crtc->base.mutex, NULL);
if (intel_crtc->active) {
if (intel_crtc->base.state->active) {
active_crtc_cnt++;
seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
......@@ -3624,22 +3627,33 @@ static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *crtc =
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
struct intel_crtc_state *pipe_config;
drm_modeset_lock_all(dev);
pipe_config = to_intel_crtc_state(crtc->base.state);
/*
* If we use the eDP transcoder we need to make sure that we don't
* bypass the pfit, since otherwise the pipe CRC source won't work. Only
* relevant on hsw with pipe A when using the always-on power well
* routing.
*/
if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
!crtc->config->pch_pfit.enabled) {
crtc->config->pch_pfit.force_thru = true;
if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
!pipe_config->pch_pfit.enabled) {
bool active = pipe_config->base.active;
if (active) {
intel_crtc_control(&crtc->base, false);
pipe_config = to_intel_crtc_state(crtc->base.state);
}
pipe_config->pch_pfit.force_thru = true;
intel_display_power_get(dev_priv,
POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
intel_crtc_reset(crtc);
if (active)
intel_crtc_control(&crtc->base, true);
}
drm_modeset_unlock_all(dev);
}
......@@ -3649,6 +3663,7 @@ static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *crtc =
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
struct intel_crtc_state *pipe_config;
drm_modeset_lock_all(dev);
/*
......@@ -3657,13 +3672,22 @@ static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
* relevant on hsw with pipe A when using the always-on power well
* routing.
*/
if (crtc->config->pch_pfit.force_thru) {
crtc->config->pch_pfit.force_thru = false;
pipe_config = to_intel_crtc_state(crtc->base.state);
if (pipe_config->pch_pfit.force_thru) {
bool active = pipe_config->base.active;
if (active) {
intel_crtc_control(&crtc->base, false);
pipe_config = to_intel_crtc_state(crtc->base.state);
}
intel_crtc_reset(crtc);
pipe_config->pch_pfit.force_thru = false;
intel_display_power_put(dev_priv,
POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
if (active)
intel_crtc_control(&crtc->base, true);
}
drm_modeset_unlock_all(dev);
}
......@@ -3779,7 +3803,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
pipe_name(pipe));
drm_modeset_lock(&crtc->base.mutex, NULL);
if (crtc->active)
if (crtc->base.state->active)
intel_wait_for_vblank(dev, pipe);
drm_modeset_unlock(&crtc->base.mutex);
......
drivers/gpu/drm/i915/i915_drv.c
View file @ a80c69fc
......@@ -601,7 +601,6 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
static int i915_drm_suspend(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_crtc *crtc;
pci_power_t opregion_target_state;
int error;
......@@ -632,8 +631,7 @@ static int i915_drm_suspend(struct drm_device *dev)
* for _thaw. Also, power gate the CRTC power wells.
*/
drm_modeset_lock_all(dev);
for_each_crtc(dev, crtc)
intel_crtc_control(crtc, false);
intel_display_suspend(dev);
drm_modeset_unlock_all(dev);
intel_dp_mst_suspend(dev);
......
drivers/gpu/drm/i915/i915_drv.h
View file @ a80c69fc
......@@ -376,7 +376,6 @@ struct intel_shared_dpll_config {
struct intel_shared_dpll {
struct intel_shared_dpll_config config;
struct intel_shared_dpll_config *new_config;
int active; /* count of number of active CRTCs (i.e. DPMS on) */
bool on; /* is the PLL actually active? Disabled during modeset */
......@@ -631,7 +630,6 @@ struct drm_i915_display_funcs {
struct intel_crtc_state *crtc_state);
void (*crtc_enable)(struct drm_crtc *crtc);
void (*crtc_disable)(struct drm_crtc *crtc);
void (*off)(struct drm_crtc *crtc);
void (*audio_codec_enable)(struct drm_connector *connector,
struct intel_encoder *encoder,
struct drm_display_mode *mode);
......
drivers/gpu/drm/i915/i915_irq.c
View file @ a80c69fc
......@@ -564,8 +564,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
struct intel_crtc *intel_crtc =
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
const struct drm_display_mode *mode =
&intel_crtc->config->base.adjusted_mode;
const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
htotal = mode->crtc_htotal;
hsync_start = mode->crtc_hsync_start;
......@@ -620,7 +619,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
const struct drm_display_mode *mode = &crtc->base.hwmode;
enum pipe pipe = crtc->pipe;
int position, vtotal;
......@@ -647,14 +646,14 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
const struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
int position;
int vbl_start, vbl_end, hsync_start, htotal, vtotal;
bool in_vbl = true;
int ret = 0;
unsigned long irqflags;
if (!intel_crtc->active) {
if (WARN_ON(!mode->crtc_clock)) {
DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
"pipe %c\n", pipe_name(pipe));
return 0;
......@@ -796,7 +795,7 @@ static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
return -EINVAL;
}
if (!crtc->state->enable) {
if (!crtc->hwmode.crtc_clock) {
DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
return -EBUSY;
}
......@@ -805,7 +804,7 @@ static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
vblank_time, flags,
crtc,
&to_intel_crtc(crtc)->config->base.adjusted_mode);
&crtc->hwmode);
}
static bool intel_hpd_irq_event(struct drm_device *dev,
......
drivers/gpu/drm/i915/intel_atomic.c
View file @ a80c69fc
......@@ -129,6 +129,8 @@ int intel_atomic_commit(struct drm_device *dev,
struct drm_atomic_state *state,
bool async)
{
struct drm_crtc_state *crtc_state;
struct drm_crtc *crtc;
int ret;
int i;
......@@ -142,48 +144,19 @@ int intel_atomic_commit(struct drm_device *dev,
return ret;
/* Point of no return */
drm_atomic_helper_swap_state(dev, state);
/*
* FIXME: The proper sequence here will eventually be:
*
* drm_atomic_helper_swap_state(dev, state)
* drm_atomic_helper_commit_modeset_disables(dev, state);
* drm_atomic_helper_commit_planes(dev, state);
* drm_atomic_helper_commit_modeset_enables(dev, state);
* drm_atomic_helper_wait_for_vblanks(dev, state);
* drm_atomic_helper_cleanup_planes(dev, state);
* drm_atomic_state_free(state);
*
* once we have full atomic modeset. For now, just manually update
* plane states to avoid clobbering good states with dummy states
* while nuclear pageflipping.
*/
for (i = 0; i < dev->mode_config.num_total_plane; i++) {
struct drm_plane *plane = state->planes[i];
if (!plane)
continue;
plane->state->state = state;
swap(state->plane_states[i], plane->state);
plane->state->state = NULL;
}
/* swap crtc_scaler_state */
for (i = 0; i < dev->mode_config.num_crtc; i++) {
struct drm_crtc *crtc = state->crtcs[i];
if (!crtc) {
continue;
}
to_intel_crtc(crtc)->config->scaler_state =
to_intel_crtc_state(state->crtc_states[i])->scaler_state;
for_each_crtc_in_state(state, crtc, crtc_state, i) {
to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
if (INTEL_INFO(dev)->gen >= 9)
skl_detach_scalers(to_intel_crtc(crtc));
drm_atomic_helper_commit_planes_on_crtc(crtc_state);
}
drm_atomic_helper_commit_planes(dev, state);
/* FIXME: This function should eventually call __intel_set_mode when needed */
drm_atomic_helper_wait_for_vblanks(dev, state);
drm_atomic_helper_cleanup_planes(dev, state);
drm_atomic_state_free(state);
......@@ -421,3 +394,54 @@ int intel_atomic_setup_scalers(struct drm_device *dev,
return 0;
}
static void
intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
struct intel_shared_dpll_config *shared_dpll)
{
enum intel_dpll_id i;
/* Copy shared dpll state */
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
shared_dpll[i] = pll->config;
}
}
struct intel_shared_dpll_config *
intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
{
struct intel_atomic_state *state = to_intel_atomic_state(s);
WARN_ON(!drm_modeset_is_locked(&s->dev->mode_config.connection_mutex));
if (!state->dpll_set) {
state->dpll_set = true;
intel_atomic_duplicate_dpll_state(to_i915(s->dev),
state->shared_dpll);
}
return state->shared_dpll;
}
struct drm_atomic_state *
intel_atomic_state_alloc(struct drm_device *dev)
{
struct intel_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state || drm_atomic_state_init(dev, &state->base) < 0) {
kfree(state);
return NULL;
}
return &state->base;
}
void intel_atomic_state_clear(struct drm_atomic_state *s)
{
struct intel_atomic_state *state = to_intel_atomic_state(s);
drm_atomic_state_default_clear(&state->base);
state->dpll_set = false;
}
drivers/gpu/drm/i915/intel_display.c
View file @ a80c69fc
......@@ -86,8 +86,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
static void ironlake_pch_clock_get(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config);
static int intel_set_mode(struct drm_crtc *crtc,
struct drm_atomic_state *state);
static int intel_set_mode(struct drm_atomic_state *state);
static int intel_framebuffer_init(struct drm_device *dev,
struct intel_framebuffer *ifb,
struct drm_mode_fb_cmd2 *mode_cmd,
......@@ -431,6 +430,12 @@ static void vlv_clock(int refclk, intel_clock_t *clock)
clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
}
static bool
needs_modeset(struct drm_crtc_state *state)
{
return state->mode_changed || state->active_changed;
}
/**
* Returns whether any output on the specified pipe is of the specified type
*/
......@@ -1693,7 +1698,7 @@ static int intel_num_dvo_pipes(struct drm_device *dev)
int count = 0;
for_each_intel_crtc(dev, crtc)
count += crtc->active &&
count += crtc->base.state->active &&
intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
return count;
......@@ -1774,7 +1779,7 @@ static void i9xx_disable_pll(struct intel_crtc *crtc)
/* Disable DVO 2x clock on both PLLs if necessary */
if (IS_I830(dev) &&
intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
intel_num_dvo_pipes(dev) == 1) {
!intel_num_dvo_pipes(dev)) {
I915_WRITE(DPLL(PIPE_B),
I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
I915_WRITE(DPLL(PIPE_A),
......@@ -2630,9 +2635,9 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
dev_priv->preserve_bios_swizzle = true;
primary->fb = fb;
primary->state->crtc = &intel_crtc->base;
primary->crtc = &intel_crtc->base;
primary->crtc = primary->state->crtc = &intel_crtc->base;
update_state_fb(primary);
intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
}
......@@ -3179,24 +3184,8 @@ static void intel_update_primary_planes(struct drm_device *dev)
}
}
void intel_crtc_reset(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
if (!crtc->active)
return;
intel_crtc_disable_planes(&crtc->base);
dev_priv->display.crtc_disable(&crtc->base);
dev_priv->display.crtc_enable(&crtc->base);
intel_crtc_enable_planes(&crtc->base);
}
void intel_prepare_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *crtc;
/* no reset support for gen2 */
if (IS_GEN2(dev))
return;
......@@ -3206,18 +3195,11 @@ void intel_prepare_reset(struct drm_device *dev)
return;
drm_modeset_lock_all(dev);
/*
* Disabling the crtcs gracefully seems nicer. Also the
* g33 docs say we should at least disable all the planes.
*/
for_each_intel_crtc(dev, crtc) {
if (!crtc->active)
continue;
intel_crtc_disable_planes(&crtc->base);
dev_priv->display.crtc_disable(&crtc->base);
}
intel_display_suspend(dev);
}
void intel_finish_reset(struct drm_device *dev)
......@@ -4203,34 +4185,16 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
}
void intel_put_shared_dpll(struct intel_crtc *crtc)
{
struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
if (pll == NULL)
return;
if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
WARN(1, "bad %s crtc mask\n", pll->name);
return;
}
pll->config.crtc_mask &= ~(1 << crtc->pipe);
if (pll->config.crtc_mask == 0) {
WARN_ON(pll->on);
WARN_ON(pll->active);
}
crtc->config->shared_dpll = DPLL_ID_PRIVATE;
}
struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
struct intel_shared_dpll *pll;
struct intel_shared_dpll_config *shared_dpll;
enum intel_dpll_id i;
shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
if (HAS_PCH_IBX(dev_priv->dev)) {
/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
i = (enum intel_dpll_id) crtc->pipe;
......@@ -4239,7 +4203,7 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
crtc->base.base.id, pll->name);
WARN_ON(pll->new_config->crtc_mask);
WARN_ON(shared_dpll[i].crtc_mask);
goto found;
}
......@@ -4259,7 +4223,7 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
pll = &dev_priv->shared_dplls[i];
DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
crtc->base.base.id, pll->name);
WARN_ON(pll->new_config->crtc_mask);
WARN_ON(shared_dpll[i].crtc_mask);
goto found;
}
......@@ -4268,15 +4232,15 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
pll = &dev_priv->shared_dplls[i];
/* Only want to check enabled timings first */
if (pll->new_config->crtc_mask == 0)
if (shared_dpll[i].crtc_mask == 0)
continue;
if (memcmp(&crtc_state->dpll_hw_state,
&pll->new_config->hw_state,
sizeof(pll->new_config->hw_state)) == 0) {
&shared_dpll[i].hw_state,
sizeof(crtc_state->dpll_hw_state)) == 0) {
DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
crtc->base.base.id, pll->name,
pll->new_config->crtc_mask,
shared_dpll[i].crtc_mask,
pll->active);
goto found;
}
......@@ -4285,7 +4249,7 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
/* Ok no matching timings, maybe there's a free one? */
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
pll = &dev_priv->shared_dplls[i];
if (pll->new_config->crtc_mask == 0) {
if (shared_dpll[i].crtc_mask == 0) {
DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
crtc->base.base.id, pll->name);
goto found;
......@@ -4295,83 +4259,33 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
return NULL;
found:
if (pll->new_config->crtc_mask == 0)
pll->new_config->hw_state = crtc_state->dpll_hw_state;
if (shared_dpll[i].crtc_mask == 0)
shared_dpll[i].hw_state =
crtc_state->dpll_hw_state;
crtc_state->shared_dpll = i;
DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
pipe_name(crtc->pipe));
pll->new_config->crtc_mask |= 1 << crtc->pipe;
shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
return pll;
}
/**
* intel_shared_dpll_start_config - start a new PLL staged config
* @dev_priv: DRM device
* @clear_pipes: mask of pipes that will have their PLLs freed
*
* Starts a new PLL staged config, copying the current config but
* releasing the references of pipes specified in clear_pipes.
*/
static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
unsigned clear_pipes)
{
struct intel_shared_dpll *pll;
enum intel_dpll_id i;
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
pll = &dev_priv->shared_dplls[i];
pll->new_config = kmemdup(&pll->config, sizeof pll->config,
GFP_KERNEL);
if (!pll->new_config)
goto cleanup;
pll->new_config->crtc_mask &= ~clear_pipes;
}
return 0;
cleanup:
while (--i >= 0) {
pll = &dev_priv->shared_dplls[i];
kfree(pll->new_config);
pll->new_config = NULL;
}
return -ENOMEM;
}
static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
static void intel_shared_dpll_commit(struct drm_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->dev);
struct intel_shared_dpll_config *shared_dpll;
struct intel_shared_dpll *pll;
enum intel_dpll_id i;
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
pll = &dev_priv->shared_dplls[i];
WARN_ON(pll->new_config == &pll->config);
pll->config = *pll->new_config;
kfree(pll->new_config);
pll->new_config = NULL;
}
}
static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
{
struct intel_shared_dpll *pll;
enum intel_dpll_id i;
if (!to_intel_atomic_state(state)->dpll_set)
return;
shared_dpll = to_intel_atomic_state(state)->shared_dpll;
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
pll = &dev_priv->shared_dplls[i];
WARN_ON(pll->new_config == &pll->config);
kfree(pll->new_config);
pll->new_config = NULL;
pll->config = shared_dpll[i];
}
}
......@@ -4671,7 +4585,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
bool reenable_ips = false;
/* The clocks have to be on to load the palette. */
if (!crtc->state->enable || !intel_crtc->active)
if (!crtc->state->active)
return;
if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
......@@ -4838,6 +4752,7 @@ static void intel_crtc_enable_planes(struct drm_crtc *crtc)
intel_enable_primary_hw_plane(crtc->primary, crtc);
intel_enable_sprite_planes(crtc);
if (to_intel_plane_state(crtc->cursor->state)->visible)
intel_crtc_update_cursor(crtc, true);
intel_post_enable_primary(crtc);
......@@ -4887,9 +4802,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
struct intel_encoder *encoder;
int pipe = intel_crtc->pipe;
WARN_ON(!crtc->state->enable);
if (intel_crtc->active)
if (WARN_ON(intel_crtc->active))
return;
if (intel_crtc->config->has_pch_encoder)
......@@ -4956,46 +4869,17 @@ static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
}
/*
* This implements the workaround described in the "notes" section of the mode
* set sequence documentation. When going from no pipes or single pipe to
* multiple pipes, and planes are enabled after the pipe, we need to wait at
* least 2 vblanks on the first pipe before enabling planes on the second pipe.
*/
static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
struct intel_crtc *crtc_it, *other_active_crtc = NULL;
/* We want to get the other_active_crtc only if there's only 1 other
* active crtc. */
for_each_intel_crtc(dev, crtc_it) {
if (!crtc_it->active || crtc_it == crtc)
continue;
if (other_active_crtc)
return;
other_active_crtc = crtc_it;
}
if (!other_active_crtc)
return;
intel_wait_for_vblank(dev, other_active_crtc->pipe);
intel_wait_for_vblank(dev, other_active_crtc->pipe);
}
static void haswell_crtc_enable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_encoder *encoder;
int pipe = intel_crtc->pipe;
int pipe = intel_crtc->pipe, hsw_workaround_pipe;
struct intel_crtc_state *pipe_config =
to_intel_crtc_state(crtc->state);
WARN_ON(!crtc->state->enable);
if (intel_crtc->active)
if (WARN_ON(intel_crtc->active))
return;
if (intel_crtc_to_shared_dpll(intel_crtc))
......@@ -5070,7 +4954,11 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
/* If we change the relative order between pipe/planes enabling, we need
* to change the workaround. */
haswell_mode_set_planes_workaround(intel_crtc);
hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
intel_wait_for_vblank(dev, hsw_workaround_pipe);
intel_wait_for_vblank(dev, hsw_workaround_pipe);
}
}
static void ironlake_pfit_disable(struct intel_crtc *crtc)
......@@ -5097,7 +4985,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
int pipe = intel_crtc->pipe;
u32 reg, temp;
if (!intel_crtc->active)
if (WARN_ON(!intel_crtc->active))
return;
for_each_encoder_on_crtc(dev, crtc, encoder)
......@@ -5160,7 +5048,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
struct intel_encoder *encoder;
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
if (!intel_crtc->active)
if (WARN_ON(!intel_crtc->active))
return;
for_each_encoder_on_crtc(dev, crtc, encoder) {
......@@ -5210,13 +5098,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
intel_disable_shared_dpll(intel_crtc);
}
static void ironlake_crtc_off(struct drm_crtc *crtc)
{
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
intel_put_shared_dpll(intel_crtc);
}
static void i9xx_pfit_enable(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
......@@ -6012,7 +5893,7 @@ static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
int max_pixclk = intel_mode_max_pixclk(state->dev, state);
int cdclk, i;
int cdclk, ret = 0;
if (max_pixclk < 0)
return max_pixclk;
......@@ -6027,20 +5908,25 @@ static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
/* add all active pipes to the state */
for_each_crtc(state->dev, crtc) {
if (!crtc->state->enable)
continue;
crtc_state = drm_atomic_get_crtc_state(state, crtc);
if (IS_ERR(crtc_state))
return PTR_ERR(crtc_state);
}
/* disable/enable all currently active pipes while we change cdclk */
for_each_crtc_in_state(state, crtc, crtc_state, i)
if (crtc_state->enable)
if (!crtc_state->active || needs_modeset(crtc_state))
continue;
crtc_state->mode_changed = true;
return 0;
ret = drm_atomic_add_affected_connectors(state, crtc);
if (ret)
break;
ret = drm_atomic_add_affected_planes(state, crtc);
if (ret)
break;
}
return ret;
}
static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
......@@ -6125,9 +6011,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
int pipe = intel_crtc->pipe;
bool is_dsi;
WARN_ON(!crtc->state->enable);
if (intel_crtc->active)
if (WARN_ON(intel_crtc->active))
return;
is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
......@@ -6203,9 +6087,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
struct intel_encoder *encoder;
int pipe = intel_crtc->pipe;
WARN_ON(!crtc->state->enable);
if (intel_crtc->active)
if (WARN_ON(intel_crtc->active))
return;
i9xx_set_pll_dividers(intel_crtc);
......@@ -6265,7 +6147,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
struct intel_encoder *encoder;
int pipe = intel_crtc->pipe;
if (!intel_crtc->active)
if (WARN_ON(!intel_crtc->active))
return;
/*
......@@ -6310,31 +6192,16 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
mutex_unlock(&dev->struct_mutex);
}
static void i9xx_crtc_off(struct drm_crtc *crtc)
static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
{
}
/* Master function to enable/disable CRTC and corresponding power wells */
void intel_crtc_control(struct drm_crtc *crtc, bool enable)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
enum intel_display_power_domain domain;
unsigned long domains;
if (enable) {
if (!intel_crtc->active) {
domains = get_crtc_power_domains(crtc);
for_each_power_domain(domain, domains)
intel_display_power_get(dev_priv, domain);
intel_crtc->enabled_power_domains = domains;
if (!intel_crtc->active)
return;
dev_priv->display.crtc_enable(crtc);
intel_crtc_enable_planes(crtc);
}
} else {
if (intel_crtc->active) {
intel_crtc_disable_planes(crtc);
dev_priv->display.crtc_disable(crtc);
......@@ -6342,53 +6209,79 @@ void intel_crtc_control(struct drm_crtc *crtc, bool enable)
for_each_power_domain(domain, domains)
intel_display_power_put(dev_priv, domain);
intel_crtc->enabled_power_domains = 0;
}
}
}
/**
* Sets the power management mode of the pipe and plane.
/*
* turn all crtc's off, but do not adjust state
* This has to be paired with a call to intel_modeset_setup_hw_state.
*/
void intel_crtc_update_dpms(struct drm_crtc *crtc)
void intel_display_suspend(struct drm_device *dev)
{
struct drm_device *dev = crtc->dev;
struct intel_encoder *intel_encoder;
bool enable = false;
for_each_encoder_on_crtc(dev, crtc, intel_encoder)
enable |= intel_encoder->connectors_active;
intel_crtc_control(crtc, enable);
struct drm_crtc *crtc;
crtc->state->active = enable;
for_each_crtc(dev, crtc)
intel_crtc_disable_noatomic(crtc);
}
static void intel_crtc_disable(struct drm_crtc *crtc)
/* Master function to enable/disable CRTC and corresponding power wells */
int intel_crtc_control(struct drm_crtc *crtc, bool enable)
{
struct drm_device *dev = crtc->dev;
struct drm_connector *connector;
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_mode_config *config = &dev->mode_config;
struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_crtc_state *pipe_config;
struct drm_atomic_state *state;
int ret;
/* crtc should still be enabled when we disable it. */
WARN_ON(!crtc->state->enable);
if (enable == intel_crtc->active)
return 0;
intel_crtc_disable_planes(crtc);
dev_priv->display.crtc_disable(crtc);
dev_priv->display.off(crtc);
if (enable && !crtc->state->enable)
return 0;
drm_plane_helper_disable(crtc->primary);
/* this function should be called with drm_modeset_lock_all for now */
if (WARN_ON(!ctx))
return -EIO;
lockdep_assert_held(&ctx->ww_ctx);
/* Update computed state. */
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
if (!connector->encoder || !connector->encoder->crtc)
continue;
state = drm_atomic_state_alloc(dev);
if (WARN_ON(!state))
return -ENOMEM;
if (connector->encoder->crtc != crtc)
continue;
state->acquire_ctx = ctx;
state->allow_modeset = true;
connector->dpms = DRM_MODE_DPMS_OFF;
to_intel_encoder(connector->encoder)->connectors_active = false;
pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
if (IS_ERR(pipe_config)) {
ret = PTR_ERR(pipe_config);
goto err;
}
pipe_config->base.active = enable;
ret = intel_set_mode(state);
if (!ret)
return ret;
err:
DRM_ERROR("Updating crtc active failed with %i\n", ret);
drm_atomic_state_free(state);
return ret;
}
/**
* Sets the power management mode of the pipe and plane.
*/
void intel_crtc_update_dpms(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
struct intel_encoder *intel_encoder;
bool enable = false;
for_each_encoder_on_crtc(dev, crtc, intel_encoder)
enable |= intel_encoder->connectors_active;
intel_crtc_control(crtc, enable);
}
void intel_encoder_destroy(struct drm_encoder *encoder)
......@@ -10538,7 +10431,7 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector,
drm_mode_copy(&crtc_state->base.mode, mode);
if (intel_set_mode(crtc, state)) {
if (intel_set_mode(state)) {
DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
if (old->release_fb)
old->release_fb->funcs->destroy(old->release_fb);
......@@ -10612,7 +10505,7 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
if (ret)
goto fail;
ret = intel_set_mode(crtc, state);
ret = intel_set_mode(state);
if (ret)
goto fail;
......@@ -11730,8 +11623,35 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
kfree(work);
if (ret == -EIO) {
struct drm_atomic_state *state;
struct drm_plane_state *plane_state;
out_hang:
ret = intel_plane_restore(primary);
state = drm_atomic_state_alloc(dev);
if (!state)
return -ENOMEM;
state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
retry:
plane_state = drm_atomic_get_plane_state(state, primary);
ret = PTR_ERR_OR_ZERO(plane_state);
if (!ret) {
drm_atomic_set_fb_for_plane(plane_state, fb);
ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
if (!ret)
ret = drm_atomic_commit(state);
}
if (ret == -EDEADLK) {
drm_modeset_backoff(state->acquire_ctx);
drm_atomic_state_clear(state);
goto retry;
}
if (ret)
drm_atomic_state_free(state);
if (ret == 0 && event) {
spin_lock_irq(&dev->event_lock);
drm_send_vblank_event(dev, pipe, event);
......@@ -11796,43 +11716,6 @@ static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
}
}
/* Fixup legacy state after an atomic state swap.
*/
static void intel_modeset_fixup_state(struct drm_atomic_state *state)
{
struct intel_crtc *crtc;
struct intel_encoder *encoder;
struct intel_connector *connector;
for_each_intel_connector(state->dev, connector) {
connector->base.encoder = connector->base.state->best_encoder;
if (connector->base.encoder)
connector->base.encoder->crtc =
connector->base.state->crtc;
}
/* Update crtc of disabled encoders */
for_each_intel_encoder(state->dev, encoder) {
int num_connectors = 0;
for_each_intel_connector(state->dev, connector)
if (connector->base.encoder == &encoder->base)
num_connectors++;
if (num_connectors == 0)
encoder->base.crtc = NULL;
}
for_each_intel_crtc(state->dev, crtc) {
crtc->base.enabled = crtc->base.state->enable;
crtc->config = to_intel_crtc_state(crtc->base.state);
}
/* Copy the new configuration to the staged state, to keep the few
* pieces of code that haven't been converted yet happy */
intel_modeset_update_staged_output_state(state->dev);
}
static void
connected_sink_compute_bpp(struct intel_connector *connector,
struct intel_crtc_state *pipe_config)
......@@ -12161,9 +12044,10 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
static int
intel_modeset_pipe_config(struct drm_crtc *crtc,
struct drm_atomic_state *state,
struct intel_crtc_state *pipe_config)
struct drm_atomic_state *state)
{
struct drm_crtc_state *crtc_state;
struct intel_crtc_state *pipe_config;
struct intel_encoder *encoder;
struct drm_connector *connector;
struct drm_connector_state *connector_state;
......@@ -12181,6 +12065,21 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
return -EINVAL;
}
crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
if (WARN_ON(!crtc_state))
return -EINVAL;
pipe_config = to_intel_crtc_state(crtc_state);
/*
* XXX: Add all connectors to make the crtc state match the encoders.
*/
if (!needs_modeset(&pipe_config->base)) {
ret = drm_atomic_add_affected_connectors(state, crtc);
if (ret)
return ret;
}
clear_intel_crtc_state(pipe_config);
pipe_config->cpu_transcoder =
......@@ -12272,7 +12171,19 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
return 0;
/* Check if we need to force a modeset */
if (pipe_config->has_audio !=
to_intel_crtc_state(crtc->state)->has_audio) {
pipe_config->base.mode_changed = true;
ret = drm_atomic_add_affected_planes(state, crtc);
}
/*
* Note we have an issue here with infoframes: current code
* only updates them on the full mode set path per hw
* requirements. So here we should be checking for any
* required changes and forcing a mode set.
*/
fail:
return ret;
}
......@@ -12289,73 +12200,66 @@ static bool intel_crtc_in_use(struct drm_crtc *crtc)
return false;
}
static bool
needs_modeset(struct drm_crtc_state *state)
{
return state->mode_changed || state->active_changed;
}
static void
intel_modeset_update_state(struct drm_atomic_state *state)
{
struct drm_device *dev = state->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_encoder *intel_encoder;
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
struct drm_connector *connector;
int i;
intel_shared_dpll_commit(dev_priv);
intel_shared_dpll_commit(state);
for_each_intel_encoder(dev, intel_encoder) {
if (!intel_encoder->base.crtc)
continue;
for_each_crtc_in_state(state, crtc, crtc_state, i) {
if (crtc != intel_encoder->base.crtc)
crtc = intel_encoder->base.crtc;
crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
if (!crtc_state || !needs_modeset(crtc->state))
continue;
if (crtc_state->enable && needs_modeset(crtc_state))
intel_encoder->connectors_active = false;
break;
}
}
drm_atomic_helper_swap_state(state->dev, state);
intel_modeset_fixup_state(state);
drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
intel_modeset_update_staged_output_state(state->dev);
/* Double check state. */
for_each_crtc(dev, crtc) {
WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
/* Update hwmode for vblank functions */
if (crtc->state->active)
crtc->hwmode = crtc->state->adjusted_mode;
else
crtc->hwmode.crtc_clock = 0;
}
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
if (!connector->encoder || !connector->encoder->crtc)
continue;
for_each_crtc_in_state(state, crtc, crtc_state, i) {
if (crtc != connector->encoder->crtc)
crtc = connector->encoder->crtc;
crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
if (!crtc_state || !needs_modeset(crtc->state))
continue;
if (crtc->state->enable && needs_modeset(crtc->state)) {
if (crtc->state->active) {
struct drm_property *dpms_property =
dev->mode_config.dpms_property;
connector->dpms = DRM_MODE_DPMS_ON;
drm_object_property_set_value(&connector->base,
dpms_property,
DRM_MODE_DPMS_ON);
drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
intel_encoder = to_intel_encoder(connector->encoder);
intel_encoder->connectors_active = true;
} else
connector->dpms = DRM_MODE_DPMS_OFF;
}
break;
}
}
}
static bool intel_fuzzy_clock_check(int clock1, int clock2)
......@@ -12759,6 +12663,10 @@ check_crtc_state(struct drm_device *dev)
"crtc active state doesn't match with hw state "
"(expected %i, found %i)\n", crtc->active, active);
I915_STATE_WARN(crtc->active != crtc->base.state->active,
"transitional active state does not match atomic hw state "
"(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
if (active &&
!intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
I915_STATE_WARN(1, "pipe state doesn't match!\n");
......@@ -12879,60 +12787,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
crtc->scanline_offset = 1;
}
static struct intel_crtc_state *
intel_modeset_compute_config(struct drm_crtc *crtc,
struct drm_atomic_state *state)
{
struct intel_crtc_state *pipe_config;
int ret = 0;
ret = drm_atomic_add_affected_connectors(state, crtc);
if (ret)
return ERR_PTR(ret);
ret = drm_atomic_helper_check_modeset(state->dev, state);
if (ret)
return ERR_PTR(ret);
/*
* Note this needs changes when we start tracking multiple modes
* and crtcs. At that point we'll need to compute the whole config
* (i.e. one pipe_config for each crtc) rather than just the one
* for this crtc.
*/
pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
if (IS_ERR(pipe_config))
return pipe_config;
if (!pipe_config->base.enable)
return pipe_config;
ret = intel_modeset_pipe_config(crtc, state, pipe_config);
if (ret)
return ERR_PTR(ret);
/* Check things that can only be changed through modeset */
if (pipe_config->has_audio !=
to_intel_crtc(crtc)->config->has_audio)
pipe_config->base.mode_changed = true;
/*
* Note we have an issue here with infoframes: current code
* only updates them on the full mode set path per hw
* requirements. So here we should be checking for any
* required changes and forcing a mode set.
*/
intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
ret = drm_atomic_helper_check_planes(state->dev, state);
if (ret)
return ERR_PTR(ret);
return pipe_config;
}
static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
static int intel_modeset_setup_plls(struct drm_atomic_state *state)
{
struct drm_device *dev = state->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
......@@ -12957,9 +12812,13 @@ static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
}
}
ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
if (ret)
goto done;
if (clear_pipes) {
struct intel_shared_dpll_config *shared_dpll =
intel_atomic_get_shared_dpll_state(state);
for (i = 0; i < dev_priv->num_shared_dpll; i++)
shared_dpll[i].crtc_mask &= ~clear_pipes;
}
for_each_crtc_in_state(state, crtc, crtc_state, i) {
if (!needs_modeset(crtc_state) || !crtc_state->enable)
......@@ -12970,18 +12829,80 @@ static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
ret = dev_priv->display.crtc_compute_clock(intel_crtc,
intel_crtc_state);
if (ret) {
intel_shared_dpll_abort_config(dev_priv);
goto done;
}
if (ret)
return ret;
}
done:
return ret;
}
/*
* This implements the workaround described in the "notes" section of the mode
* set sequence documentation. When going from no pipes or single pipe to
* multiple pipes, and planes are enabled after the pipe, we need to wait at
* least 2 vblanks on the first pipe before enabling planes on the second pipe.
*/
static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
{
struct drm_crtc_state *crtc_state;
struct intel_crtc *intel_crtc;
struct drm_crtc *crtc;
struct intel_crtc_state *first_crtc_state = NULL;
struct intel_crtc_state *other_crtc_state = NULL;
enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
int i;
/* look at all crtc's that are going to be enabled in during modeset */
for_each_crtc_in_state(state, crtc, crtc_state, i) {
intel_crtc = to_intel_crtc(crtc);
if (!crtc_state->active || !needs_modeset(crtc_state))
continue;
if (first_crtc_state) {
other_crtc_state = to_intel_crtc_state(crtc_state);
break;
} else {
first_crtc_state = to_intel_crtc_state(crtc_state);
first_pipe = intel_crtc->pipe;
}
}
/* No workaround needed? */
if (!first_crtc_state)
return 0;
/* w/a possibly needed, check how many crtc's are already enabled. */
for_each_intel_crtc(state->dev, intel_crtc) {
struct intel_crtc_state *pipe_config;
pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
if (IS_ERR(pipe_config))
return PTR_ERR(pipe_config);
pipe_config->hsw_workaround_pipe = INVALID_PIPE;
if (!pipe_config->base.active ||
needs_modeset(&pipe_config->base))
continue;
/* 2 or more enabled crtcs means no need for w/a */
if (enabled_pipe != INVALID_PIPE)
return 0;
enabled_pipe = intel_crtc->pipe;
}
if (enabled_pipe != INVALID_PIPE)
first_crtc_state->hsw_workaround_pipe = enabled_pipe;
else if (other_crtc_state)
other_crtc_state->hsw_workaround_pipe = first_pipe;
return 0;
}
/* Code that should eventually be part of atomic_check() */
static int __intel_set_mode_checks(struct drm_atomic_state *state)
static int intel_modeset_checks(struct drm_atomic_state *state)
{
struct drm_device *dev = state->dev;
int ret;
......@@ -13003,62 +12924,73 @@ static int __intel_set_mode_checks(struct drm_atomic_state *state)
return ret;
}
ret = __intel_set_mode_setup_plls(state);
ret = intel_modeset_setup_plls(state);
if (ret)
return ret;
return 0;
if (IS_HASWELL(dev))
ret = haswell_mode_set_planes_workaround(state);
return ret;
}
static int __intel_set_mode(struct drm_crtc *modeset_crtc,
struct intel_crtc_state *pipe_config)
static int
intel_modeset_compute_config(struct drm_atomic_state *state)
{
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
int ret, i;
ret = drm_atomic_helper_check_modeset(state->dev, state);
if (ret)
return ret;
for_each_crtc_in_state(state, crtc, crtc_state, i) {
if (!crtc_state->enable &&
WARN_ON(crtc_state->active))
crtc_state->active = false;
if (!crtc_state->enable)
continue;
ret = intel_modeset_pipe_config(crtc, state);
if (ret)
return ret;
intel_dump_pipe_config(to_intel_crtc(crtc),
to_intel_crtc_state(crtc_state),
"[modeset]");
}
ret = intel_modeset_checks(state);
if (ret)
return ret;
return drm_atomic_helper_check_planes(state->dev, state);
}
static int __intel_set_mode(struct drm_atomic_state *state)
{
struct drm_device *dev = modeset_crtc->dev;
struct drm_device *dev = state->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_atomic_state *state = pipe_config->base.state;
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
int ret = 0;
int i;
ret = __intel_set_mode_checks(state);
if (ret < 0)
return ret;
ret = drm_atomic_helper_prepare_planes(dev, state);
if (ret)
return ret;
drm_atomic_helper_swap_state(dev, state);
for_each_crtc_in_state(state, crtc, crtc_state, i) {
if (!needs_modeset(crtc_state))
if (!needs_modeset(crtc->state) || !crtc_state->active)
continue;
if (!crtc_state->enable) {
intel_crtc_disable(crtc);
} else if (crtc->state->enable) {
intel_crtc_disable_planes(crtc);
dev_priv->display.crtc_disable(crtc);
}
}
/* crtc->mode is already used by the ->mode_set callbacks, hence we need
* to set it here already despite that we pass it down the callchain.
*
* Note we'll need to fix this up when we start tracking multiple
* pipes; here we assume a single modeset_pipe and only track the
* single crtc and mode.
*/
if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
modeset_crtc->mode = pipe_config->base.mode;
/*
* Calculate and store various constants which
* are later needed by vblank and swap-completion
* timestamping. They are derived from true hwmode.
*/
drm_calc_timestamping_constants(modeset_crtc,
&pipe_config->base.adjusted_mode);
}
/* Only after disabling all output pipelines that will be changed can we
* update the the output configuration. */
......@@ -13069,11 +13001,11 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc,
modeset_update_crtc_power_domains(state);
drm_atomic_helper_commit_planes(dev, state);
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
for_each_crtc_in_state(state, crtc, crtc_state, i) {
if (!needs_modeset(crtc->state) || !crtc->state->enable)
drm_atomic_helper_commit_planes_on_crtc(crtc_state);
if (!needs_modeset(crtc->state) || !crtc->state->active)
continue;
update_scanline_offset(to_intel_crtc(crtc));
......@@ -13091,37 +13023,27 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc,
return 0;
}
static int intel_set_mode_with_config(struct drm_crtc *crtc,
struct intel_crtc_state *pipe_config)
static int intel_set_mode_checked(struct drm_atomic_state *state)
{
struct drm_device *dev = state->dev;
int ret;
ret = __intel_set_mode(crtc, pipe_config);
ret = __intel_set_mode(state);
if (ret == 0)
intel_modeset_check_state(crtc->dev);
intel_modeset_check_state(dev);
return ret;
}
static int intel_set_mode(struct drm_crtc *crtc,
struct drm_atomic_state *state)
static int intel_set_mode(struct drm_atomic_state *state)
{
struct intel_crtc_state *pipe_config;
int ret = 0;
pipe_config = intel_modeset_compute_config(crtc, state);
if (IS_ERR(pipe_config)) {
ret = PTR_ERR(pipe_config);
goto out;
}
int ret;
ret = intel_set_mode_with_config(crtc, pipe_config);
ret = intel_modeset_compute_config(state);
if (ret)
goto out;
out:
return ret;
return intel_set_mode_checked(state);
}
void intel_crtc_restore_mode(struct drm_crtc *crtc)
......@@ -13193,7 +13115,7 @@ void intel_crtc_restore_mode(struct drm_crtc *crtc)
intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
crtc->primary->fb, crtc->x, crtc->y);
ret = intel_set_mode(crtc, state);
ret = intel_set_mode(state);
if (ret)
drm_atomic_state_free(state);
}
......@@ -13339,20 +13261,10 @@ intel_modeset_stage_output_state(struct drm_device *dev,
return 0;
}
static bool primary_plane_visible(struct drm_crtc *crtc)
{
struct intel_plane_state *plane_state =
to_intel_plane_state(crtc->primary->state);
return plane_state->visible;
}
static int intel_crtc_set_config(struct drm_mode_set *set)
{
struct drm_device *dev;
struct drm_atomic_state *state = NULL;
struct intel_crtc_state *pipe_config;
bool primary_plane_was_visible;
int ret;
BUG_ON(!set);
......@@ -13383,46 +13295,13 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
if (ret)
goto out;
pipe_config = intel_modeset_compute_config(set->crtc, state);
if (IS_ERR(pipe_config)) {
ret = PTR_ERR(pipe_config);
ret = intel_modeset_compute_config(state);
if (ret)
goto out;
}
intel_update_pipe_size(to_intel_crtc(set->crtc));
primary_plane_was_visible = primary_plane_visible(set->crtc);
ret = intel_set_mode_with_config(set->crtc, pipe_config);
if (ret == 0 &&
pipe_config->base.enable &&
pipe_config->base.planes_changed &&
!needs_modeset(&pipe_config->base)) {
struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
/*
* We need to make sure the primary plane is re-enabled if it
* has previously been turned off.
*/
if (ret == 0 && !primary_plane_was_visible &&
primary_plane_visible(set->crtc)) {
WARN_ON(!intel_crtc->active);
intel_post_enable_primary(set->crtc);
}
/*
* In the fastboot case this may be our only check of the
* state after boot. It would be better to only do it on
* the first update, but we don't have a nice way of doing that
* (and really, set_config isn't used much for high freq page
* flipping, so increasing its cost here shouldn't be a big
* deal).
*/
if (i915.fastboot && ret == 0)
intel_modeset_check_state(set->crtc->dev);
}
ret = intel_set_mode_checked(state);
if (ret) {
DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
set->crtc->base.id, ret);
......@@ -13755,8 +13634,15 @@ intel_check_primary_plane(struct drm_plane *plane,
*/
if (IS_BROADWELL(dev))
intel_crtc->atomic.wait_vblank = true;
if (crtc_state && !needs_modeset(&crtc_state->base))
intel_crtc->atomic.post_enable_primary = true;
}
if (!state->visible && old_state->visible &&
crtc_state && !needs_modeset(&crtc_state->base))
intel_crtc->atomic.pre_disable_primary = true;
intel_crtc->atomic.fb_bits |=
INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
......@@ -13820,6 +13706,7 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc)
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct drm_crtc_state *crtc_state = intel_crtc->base.state;
struct intel_plane *intel_plane;
struct drm_plane *p;
unsigned fb_bits = 0;
......@@ -13863,7 +13750,7 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc)
intel_runtime_pm_get(dev_priv);
/* Perform vblank evasion around commit operation */
if (intel_crtc->active)
if (crtc_state->active && !needs_modeset(crtc_state))
intel_crtc->atomic.evade =
intel_pipe_update_start(intel_crtc,
&intel_crtc->atomic.start_vbl_count);
......@@ -13882,7 +13769,7 @@ static void intel_finish_crtc_commit(struct drm_crtc *crtc)
intel_runtime_pm_put(dev_priv);
if (intel_crtc->atomic.wait_vblank)
if (intel_crtc->atomic.wait_vblank && intel_crtc->active)
intel_wait_for_vblank(dev, intel_crtc->pipe);
intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
......@@ -14748,6 +14635,8 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
.output_poll_changed = intel_fbdev_output_poll_changed,
.atomic_check = intel_atomic_check,
.atomic_commit = intel_atomic_commit,
.atomic_state_alloc = intel_atomic_state_alloc,
.atomic_state_clear = intel_atomic_state_clear,
};
/* Set up chip specific display functions */
......@@ -14774,7 +14663,6 @@ static void intel_init_display(struct drm_device *dev)
haswell_crtc_compute_clock;
dev_priv->display.crtc_enable = haswell_crtc_enable;
dev_priv->display.crtc_disable = haswell_crtc_disable;
dev_priv->display.off = ironlake_crtc_off;
dev_priv->display.update_primary_plane =
skylake_update_primary_plane;
} else if (HAS_DDI(dev)) {
......@@ -14785,7 +14673,6 @@ static void intel_init_display(struct drm_device *dev)
haswell_crtc_compute_clock;
dev_priv->display.crtc_enable = haswell_crtc_enable;
dev_priv->display.crtc_disable = haswell_crtc_disable;
dev_priv->display.off = ironlake_crtc_off;
dev_priv->display.update_primary_plane =
ironlake_update_primary_plane;
} else if (HAS_PCH_SPLIT(dev)) {
......@@ -14796,7 +14683,6 @@ static void intel_init_display(struct drm_device *dev)
ironlake_crtc_compute_clock;
dev_priv->display.crtc_enable = ironlake_crtc_enable;
dev_priv->display.crtc_disable = ironlake_crtc_disable;
dev_priv->display.off = ironlake_crtc_off;
dev_priv->display.update_primary_plane =
ironlake_update_primary_plane;
} else if (IS_VALLEYVIEW(dev)) {
......@@ -14806,7 +14692,6 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
dev_priv->display.crtc_enable = valleyview_crtc_enable;
dev_priv->display.crtc_disable = i9xx_crtc_disable;
dev_priv->display.off = i9xx_crtc_off;
dev_priv->display.update_primary_plane =
i9xx_update_primary_plane;
} else {
......@@ -14816,7 +14701,6 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
dev_priv->display.crtc_enable = i9xx_crtc_enable;
dev_priv->display.crtc_disable = i9xx_crtc_disable;
dev_priv->display.off = i9xx_crtc_off;
dev_priv->display.update_primary_plane =
i9xx_update_primary_plane;
}
......@@ -15272,7 +15156,9 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_encoder *encoder;
u32 reg;
bool enable;
/* Clear any frame start delays used for debugging left by the BIOS */
reg = PIPECONF(crtc->config->cpu_transcoder);
......@@ -15289,7 +15175,6 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
* disable the crtc (and hence change the state) if it is wrong. Note
* that gen4+ has a fixed plane -> pipe mapping. */
if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
struct intel_connector *connector;
bool plane;
DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
......@@ -15301,30 +15186,8 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
plane = crtc->plane;
to_intel_plane_state(crtc->base.primary->state)->visible = true;
crtc->plane = !plane;
intel_crtc_disable_planes(&crtc->base);
dev_priv->display.crtc_disable(&crtc->base);
intel_crtc_disable_noatomic(&crtc->base);
crtc->plane = plane;
/* ... and break all links. */
for_each_intel_connector(dev, connector) {
if (connector->encoder->base.crtc != &crtc->base)
continue;
connector->base.dpms = DRM_MODE_DPMS_OFF;
connector->base.encoder = NULL;
}
/* multiple connectors may have the same encoder:
* handle them and break crtc link separately */
for_each_intel_connector(dev, connector)
if (connector->encoder->base.crtc == &crtc->base) {
connector->encoder->base.crtc = NULL;
connector->encoder->connectors_active = false;
}
WARN_ON(crtc->active);
crtc->base.state->enable = false;
crtc->base.state->active = false;
crtc->base.enabled = false;
}
if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
......@@ -15338,13 +15201,18 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
/* Adjust the state of the output pipe according to whether we
* have active connectors/encoders. */
intel_crtc_update_dpms(&crtc->base);
enable = false;
for_each_encoder_on_crtc(dev, &crtc->base, encoder)
enable |= encoder->connectors_active;
if (crtc->active != crtc->base.state->enable) {
struct intel_encoder *encoder;
if (!enable)
intel_crtc_disable_noatomic(&crtc->base);
if (crtc->active != crtc->base.state->active) {
/* This can happen either due to bugs in the get_hw_state
* functions or because the pipe is force-enabled due to the
* functions or because of calls to intel_crtc_disable_noatomic,
* or because the pipe is force-enabled due to the
* pipe A quirk. */
DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
crtc->base.base.id,
......@@ -15484,6 +15352,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
struct intel_plane_state *plane_state;
memset(crtc->config, 0, sizeof(*crtc->config));
crtc->config->base.crtc = &crtc->base;
crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
......@@ -15493,6 +15362,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
crtc->base.state->enable = crtc->active;
crtc->base.state->active = crtc->active;
crtc->base.enabled = crtc->active;
crtc->base.hwmode = crtc->config->base.adjusted_mode;
plane_state = to_intel_plane_state(primary->state);
plane_state->visible = primary_get_hw_state(crtc);
......@@ -15683,7 +15553,9 @@ void intel_modeset_gem_init(struct drm_device *dev)
to_intel_crtc(c)->pipe);
drm_framebuffer_unreference(c->primary->fb);
c->primary->fb = NULL;
c->primary->crtc = c->primary->state->crtc = NULL;
update_state_fb(c->primary);
c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
}
}
......
drivers/gpu/drm/i915/intel_drv.h
View file @ a80c69fc
......@@ -241,6 +241,13 @@ typedef struct dpll {
int p;
} intel_clock_t;
struct intel_atomic_state {
struct drm_atomic_state base;
bool dpll_set;
struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
};
struct intel_plane_state {
struct drm_plane_state base;
struct drm_rect src;
......@@ -447,6 +454,9 @@ struct intel_crtc_state {
int pbn;
struct intel_crtc_scaler_state scaler_state;
/* w/a for waiting 2 vblanks during crtc enable */
enum pipe hsw_workaround_pipe;
};
struct intel_pipe_wm {
......@@ -628,6 +638,7 @@ struct cxsr_latency {
unsigned long cursor_hpll_disable;
};
#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
#define to_intel_connector(x) container_of(x, struct intel_connector, base)
......@@ -993,8 +1004,8 @@ int intel_pch_rawclk(struct drm_device *dev);
void intel_mark_busy(struct drm_device *dev);
void intel_mark_idle(struct drm_device *dev);
void intel_crtc_restore_mode(struct drm_crtc *crtc);
void intel_crtc_control(struct drm_crtc *crtc, bool enable);
void intel_crtc_reset(struct intel_crtc *crtc);
void intel_display_suspend(struct drm_device *dev);
int intel_crtc_control(struct drm_crtc *crtc, bool enable);
void intel_crtc_update_dpms(struct drm_crtc *crtc);
void intel_encoder_destroy(struct drm_encoder *encoder);
int intel_connector_init(struct intel_connector *);
......@@ -1083,7 +1094,6 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
struct intel_crtc_state *state);
void intel_put_shared_dpll(struct intel_crtc *crtc);
void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
const struct dpll *dpll);
......@@ -1405,6 +1415,11 @@ int intel_connector_atomic_get_property(struct drm_connector *connector,
struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
void intel_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state);
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
void intel_atomic_state_clear(struct drm_atomic_state *);
struct intel_shared_dpll_config *
intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
static inline struct intel_crtc_state *
intel_atomic_get_crtc_state(struct drm_atomic_state *state,
struct intel_crtc *crtc)
......
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