Commit ac67a3b9 authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman

staging: comedi: adv_pci_dio: cleanup "disable and clear interrupts" comments

For aesthetics, use a common comment for the switch() that disables and clears
interrupts.
Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: default avatarIan Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent c94a5991
...@@ -307,62 +307,50 @@ static int pci_dio_reset(struct comedi_device *dev) ...@@ -307,62 +307,50 @@ static int pci_dio_reset(struct comedi_device *dev)
if (board->cardtype == TYPE_PCI1752 || board->cardtype == TYPE_PCI1756) if (board->cardtype == TYPE_PCI1752 || board->cardtype == TYPE_PCI1756)
outw(0, dev->iobase + PCI1752_6_CFC); outw(0, dev->iobase + PCI1752_6_CFC);
/* disable and clear interrupts */
switch (board->cardtype) { switch (board->cardtype) {
case TYPE_PCI1730: case TYPE_PCI1730:
case TYPE_PCI1733: case TYPE_PCI1733:
/* disable interrupts */
outb(0, dev->iobase + PCI1730_3_INT_EN); outb(0, dev->iobase + PCI1730_3_INT_EN);
/* clear interrupts */
outb(0x0f, dev->iobase + PCI1730_3_INT_CLR); outb(0x0f, dev->iobase + PCI1730_3_INT_CLR);
/* set rising edge trigger */
outb(0, dev->iobase + PCI1730_3_INT_RF); outb(0, dev->iobase + PCI1730_3_INT_RF);
break; break;
case TYPE_PCI1736: case TYPE_PCI1736:
/* disable interrupts */
outb(0, dev->iobase + PCI1736_3_INT_EN); outb(0, dev->iobase + PCI1736_3_INT_EN);
/* clear interrupts */
outb(0x0f, dev->iobase + PCI1736_3_INT_CLR); outb(0x0f, dev->iobase + PCI1736_3_INT_CLR);
/* set rising edge trigger */
outb(0, dev->iobase + PCI1736_3_INT_RF); outb(0, dev->iobase + PCI1736_3_INT_RF);
break; break;
case TYPE_PCI1739: case TYPE_PCI1739:
/* disable & clear interrupts */
outb(0x88, dev->iobase + PCI1739_ICR); outb(0x88, dev->iobase + PCI1739_ICR);
break; break;
case TYPE_PCI1750: case TYPE_PCI1750:
case TYPE_PCI1751: case TYPE_PCI1751:
/* disable & clear interrupts */
outb(0x88, dev->iobase + PCI1750_ICR); outb(0x88, dev->iobase + PCI1750_ICR);
break; break;
case TYPE_PCI1753E: case TYPE_PCI1753E:
outb(0x88, dev->iobase + PCI1753E_ICR0); /* disable & clear outb(0x88, dev->iobase + PCI1753E_ICR0);
* interrupts */
outb(0x80, dev->iobase + PCI1753E_ICR1); outb(0x80, dev->iobase + PCI1753E_ICR1);
outb(0x80, dev->iobase + PCI1753E_ICR2); outb(0x80, dev->iobase + PCI1753E_ICR2);
outb(0x80, dev->iobase + PCI1753E_ICR3); outb(0x80, dev->iobase + PCI1753E_ICR3);
/* fallthrough */ /* fallthrough */
case TYPE_PCI1753: case TYPE_PCI1753:
outb(0x88, dev->iobase + PCI1753_ICR0); /* disable & clear outb(0x88, dev->iobase + PCI1753_ICR0);
* interrupts */
outb(0x80, dev->iobase + PCI1753_ICR1); outb(0x80, dev->iobase + PCI1753_ICR1);
outb(0x80, dev->iobase + PCI1753_ICR2); outb(0x80, dev->iobase + PCI1753_ICR2);
outb(0x80, dev->iobase + PCI1753_ICR3); outb(0x80, dev->iobase + PCI1753_ICR3);
break; break;
case TYPE_PCI1754: case TYPE_PCI1754:
outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear outw(0x08, dev->iobase + PCI1754_6_ICR0);
* interrupts */
outw(0x08, dev->iobase + PCI1754_6_ICR1); outw(0x08, dev->iobase + PCI1754_6_ICR1);
outw(0x08, dev->iobase + PCI1754_ICR2); outw(0x08, dev->iobase + PCI1754_ICR2);
outw(0x08, dev->iobase + PCI1754_ICR3); outw(0x08, dev->iobase + PCI1754_ICR3);
break; break;
case TYPE_PCI1756: case TYPE_PCI1756:
outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear outw(0x08, dev->iobase + PCI1754_6_ICR0);
* interrupts */
outw(0x08, dev->iobase + PCI1754_6_ICR1); outw(0x08, dev->iobase + PCI1754_6_ICR1);
break; break;
case TYPE_PCI1762: case TYPE_PCI1762:
outw(0x0101, dev->iobase + PCI1762_ICR); /* disable & clear outw(0x0101, dev->iobase + PCI1762_ICR);
* interrupts */
break; break;
default: default:
break; break;
......
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