Commit ac9219d9 authored by Oswald Buddenhagen's avatar Oswald Buddenhagen Committed by Takashi Iwai

ALSA: emu10k1: remove some bogus defines

Firstly, remove the FXWC_* defines - the comment on FXWC implies that
the relevant defines are the (A_)EXTOUT_* ones. It's unclear where this
came from - it was in the initial ALSA import, but neither the driver
from Creative nor kX-project have these defines.

Secondly, remove A_HR, which made plain no sense (was unused, and
clashed with FXRT). Amends commit cbb7d8f9 ("emu10k1: Update
registers defines for the Audigy 2/emu10k2.5").
Signed-off-by: default avatarOswald Buddenhagen <oswald.buddenhagen@gmx.de>
Link: https://lore.kernel.org/r/20230422161021.1143903-5-oswald.buddenhagen@gmx.deSigned-off-by: default avatarTakashi Iwai <tiwai@suse.de>
parent a062b103
...@@ -471,7 +471,6 @@ ...@@ -471,7 +471,6 @@
#define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */ #define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
#define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */ #define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
#define A_HR 0x0b /* High Resolution. 24bit playback from host to DSP. */
#define MAPA 0x0c /* Cache map A */ #define MAPA 0x0c /* Cache map A */
#define MAPB 0x0d /* Cache map B */ #define MAPB 0x0d /* Cache map B */
...@@ -626,20 +625,6 @@ ...@@ -626,20 +625,6 @@
/* is 16bit, 48KHz only. All 32 channels can be enabled */ /* is 16bit, 48KHz only. All 32 channels can be enabled */
/* simultaneously. */ /* simultaneously. */
#define FXWC_DEFAULTROUTE_C (1<<0) /* left emu out? */
#define FXWC_DEFAULTROUTE_B (1<<1) /* right emu out? */
#define FXWC_DEFAULTROUTE_A (1<<12)
#define FXWC_DEFAULTROUTE_D (1<<13)
#define FXWC_ADCLEFT (1<<18)
#define FXWC_CDROMSPDIFLEFT (1<<18)
#define FXWC_ADCRIGHT (1<<19)
#define FXWC_CDROMSPDIFRIGHT (1<<19)
#define FXWC_MIC (1<<20)
#define FXWC_ZOOMLEFT (1<<20)
#define FXWC_ZOOMRIGHT (1<<21)
#define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */
#define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */
#define A_TBLSZ 0x43 /* Effects Tank Internal Table Size. Only low byte or register used */ #define A_TBLSZ 0x43 /* Effects Tank Internal Table Size. Only low byte or register used */
#define TCBS 0x44 /* Tank cache buffer size register */ #define TCBS 0x44 /* Tank cache buffer size register */
......
...@@ -1745,7 +1745,6 @@ int snd_emu10k1_pcm_efx(struct snd_emu10k1 *emu, int device) ...@@ -1745,7 +1745,6 @@ int snd_emu10k1_pcm_efx(struct snd_emu10k1 *emu, int device)
* to these * to these
*/ */
/* emu->efx_voices_mask[0] = FXWC_DEFAULTROUTE_C | FXWC_DEFAULTROUTE_A; */
if (emu->audigy) { if (emu->audigy) {
emu->efx_voices_mask[0] = 0; emu->efx_voices_mask[0] = 0;
if (emu->card_capabilities->emu_model) if (emu->card_capabilities->emu_model)
......
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