Commit ae1b1a48 authored by Michel Dänzer's avatar Michel Dänzer Committed by Dave Airlie

drm: radeon: fix up bus mastering when writeback is disabled

When writeback isn't used, actually disable it in the hardware.

Not doing this might waste bus bandwidth or even cause memory corruption or
system crashes on systems that check bus transfers. No such incident has been
reported though.
Signed-off-by: default avatarDave Airlie <airlied@linux.ie>
parent 8624ecbf
...@@ -1258,6 +1258,13 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv) ...@@ -1258,6 +1258,13 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
dev_priv->writeback_works = 0; dev_priv->writeback_works = 0;
DRM_INFO("writeback forced off\n"); DRM_INFO("writeback forced off\n");
} }
if (!dev_priv->writeback_works) {
/* Disable writeback to avoid unnecessary bus master transfer */
RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
RADEON_RB_NO_UPDATE);
RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
}
} }
/* Enable or disable PCI-E GART on the chip */ /* Enable or disable PCI-E GART on the chip */
......
...@@ -681,6 +681,7 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp, ...@@ -681,6 +681,7 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
#define RADEON_CP_RB_BASE 0x0700 #define RADEON_CP_RB_BASE 0x0700
#define RADEON_CP_RB_CNTL 0x0704 #define RADEON_CP_RB_CNTL 0x0704
# define RADEON_BUF_SWAP_32BIT (2 << 16) # define RADEON_BUF_SWAP_32BIT (2 << 16)
# define RADEON_RB_NO_UPDATE (1 << 27)
#define RADEON_CP_RB_RPTR_ADDR 0x070c #define RADEON_CP_RB_RPTR_ADDR 0x070c
#define RADEON_CP_RB_RPTR 0x0710 #define RADEON_CP_RB_RPTR 0x0710
#define RADEON_CP_RB_WPTR 0x0714 #define RADEON_CP_RB_WPTR 0x0714
......
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