ppc64: dont allow tlbiel on large pages.

add power4 flag for assembler, needed for tlbiel.

arch/ppc64/Makefile

@@ -18,7 +18,8 @@ KERNELLOAD	=0xc000000000000000
 LINKFLAGS	= -T arch/ppc64/vmlinux.lds -Bstatic \
 		-e $(KERNELLOAD) -Ttext $(KERNELLOAD)
 CFLAGS		:= $(CFLAGS) -fsigned-char -msoft-float -pipe \
-		-Wno-uninitialized -mminimal-toc -mtraceback=full
+		-Wno-uninitialized -mminimal-toc -mtraceback=full \
+		-Wa,-mpower4
 CPP		= $(CC) -E $(CFLAGS)
 
 

arch/ppc64/kernel/pSeries_htab.c

@@ -359,7 +359,7 @@ static void pSeries_hpte_invalidate(unsigned long slot, unsigned long va,
 
 	/* Invalidate the tlb */
 	if (!large && local && __is_processor(PV_POWER4)) {
-		_tlbiel(va, large);
+		_tlbiel(va);
 	} else {
 		spin_lock_irqsave(&pSeries_tlbie_lock, flags);
 		_tlbie(va, large);

include/asm-ppc64/mmu.h

@@ -211,18 +211,11 @@ static inline void _tlbie(unsigned long va, int large)
 	asm volatile("eieio; tlbsync; ptesync": : :"memory");
 }
 
-static inline void _tlbiel(unsigned long va, int large)
+static inline void _tlbiel(unsigned long va)
 {
 	asm volatile("ptesync": : :"memory");
-
-	if (large) {
-		asm volatile("clrldi	%0,%0,16\n\
-			      tlbiel	%0,1" : : "r"(va) : "memory");
-	} else {
 	asm volatile("clrldi	%0,%0,16\n\
-			      tlbiel	%0,0" : : "r"(va) : "memory");
-	}
-
+		      tlbiel	%0" : : "r"(va) : "memory");
 	asm volatile("ptesync": : :"memory");
 }