Commit ae8578c0 authored by Paul Walmsley's avatar Paul Walmsley Committed by Russell King

[ARM] OMAP: Make dpll4_m4_ck programmable with clk_set_rate()

Filling the set_rate and round_rate fields of dpll4_m4_ck makes
this clock programmable through clk_set_rate().  This is needed
to give omapfb control over the dss1_alwon_fck rate.

This patch includes a fix from Tomi Valkeinen <tomi.valkeinen@nokia.com>.

linux-omap source commits are e42218d45afbc3e654e289e021e6b80c657b16c2 and
9d211b761b3cdf7736602ecf7e68f8a298c13278.
Signed-off-by: default avatarMåns Rullgård <mans@mansr.com>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@nokia.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 6c8fe0b9
......@@ -811,6 +811,8 @@ static struct clk dpll4_m4_ck = {
.clksel = div16_dpll4_clksel,
.flags = RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
.set_rate = &omap2_clksel_set_rate,
.round_rate = &omap2_clksel_round_rate,
};
/* The PWRDN bit is apparently only available on 3430ES2 and above */
......
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